1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (C) 2022 Marek Vasut <marex@denx.de> 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/net/qca-ar803x.h> 9#include <dt-bindings/phy/phy-imx8-pcie.h> 10#include "imx8mp.dtsi" 11 12/ { 13 model = "Data Modul i.MX8M Plus eDM SBC"; 14 compatible = "dmo,imx8mp-data-modul-edm-sbc", "fsl,imx8mp"; 15 16 aliases { 17 rtc0 = &rtc; 18 rtc1 = &snvs_rtc; 19 }; 20 21 chosen { 22 stdout-path = &uart3; 23 }; 24 25 memory@40000000 { 26 device_type = "memory"; 27 /* There are 1/2/4 GiB options, adjusted by bootloader. */ 28 reg = <0x0 0x40000000 0 0x40000000>; 29 }; 30 31 backlight: backlight { 32 compatible = "pwm-backlight"; 33 pinctrl-names = "default"; 34 pinctrl-0 = <&pinctrl_panel_backlight>; 35 brightness-levels = <0 1 10 20 30 40 50 60 70 75 80 90 100>; 36 default-brightness-level = <7>; 37 enable-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; 38 pwms = <&pwm1 0 5000000 0>; 39 /* Disabled by default, unless display board plugged in. */ 40 status = "disabled"; 41 }; 42 43 clk_xtal25: clock-xtal25 { 44 compatible = "fixed-clock"; 45 #clock-cells = <0>; 46 clock-frequency = <25000000>; 47 }; 48 49 clk_pwm4: clock-pwm4 { 50 compatible = "pwm-clock"; 51 #clock-cells = <0>; 52 clock-frequency = <12000000>; 53 clock-output-names = "codec-pwm4"; 54 /* 55 * 1 / 83 ns ~= 12 MHz , but since the PWM input clock is 24 MHz 56 * and the calculated PWM period is 1 and duty cycle is 50%, the 57 * result is exactly 12 MHz, which is fine for SGTL5000 MCLK. 58 */ 59 pwms = <&pwm4 0 83 0>; 60 }; 61 62 panel: panel { 63 /* Compatible string is filled in by panel board DT Overlay. */ 64 backlight = <&backlight>; 65 power-supply = <®_panel_vcc>; 66 /* Disabled by default, unless display board plugged in. */ 67 status = "disabled"; 68 }; 69 70 reg_panel_vcc: regulator-panel-vcc { 71 compatible = "regulator-fixed"; 72 pinctrl-names = "default"; 73 pinctrl-0 = <&pinctrl_panel_vcc_reg>; 74 regulator-min-microvolt = <5000000>; 75 regulator-max-microvolt = <5000000>; 76 regulator-name = "PANEL_VCC"; 77 /* GPIO flags are ignored, enable-active-high applies. */ 78 gpio = <&gpio3 6 GPIO_ACTIVE_HIGH>; 79 enable-active-high; 80 /* Disabled by default, unless display board plugged in. */ 81 status = "disabled"; 82 }; 83 84 reg_usdhc2_vmmc: regulator-usdhc2-vmmc { 85 compatible = "regulator-fixed"; 86 pinctrl-names = "default"; 87 pinctrl-0 = <&pinctrl_usdhc2_vmmc>; 88 regulator-max-microvolt = <3300000>; 89 regulator-min-microvolt = <3300000>; 90 regulator-name = "VDD_3V3_SD"; 91 /* GPIO flags are ignored, enable-active-high applies. */ 92 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; /* SD2_RESET */ 93 enable-active-high; 94 off-on-delay-us = <12000>; 95 startup-delay-us = <100>; 96 vin-supply = <&buck4>; 97 }; 98 99 sound { 100 compatible = "simple-audio-card"; 101 simple-audio-card,name = "SGTL5000-Card"; 102 simple-audio-card,format = "i2s"; 103 simple-audio-card,bitclock-master = <&codec_dai>; 104 simple-audio-card,frame-master = <&codec_dai>; 105 simple-audio-card,widgets = "Headphone", "Headphone Jack"; 106 simple-audio-card,routing = "Headphone Jack", "HP_OUT"; 107 108 cpu_dai: simple-audio-card,cpu { 109 sound-dai = <&sai3>; 110 }; 111 112 codec_dai: simple-audio-card,codec { 113 sound-dai = <&sgtl5000>; 114 }; 115 }; 116 117 watchdog { /* TPS3813 */ 118 compatible = "linux,wdt-gpio"; 119 pinctrl-names = "default"; 120 pinctrl-0 = <&pinctrl_watchdog_gpio>; 121 always-running; 122 gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; 123 hw_algo = "level"; 124 /* Reset triggers in 2..3 seconds */ 125 hw_margin_ms = <1500>; 126 /* Disabled by default */ 127 status = "disabled"; 128 }; 129}; 130 131&A53_0 { 132 cpu-supply = <&buck2>; 133}; 134 135&A53_1 { 136 cpu-supply = <&buck2>; 137}; 138 139&A53_2 { 140 cpu-supply = <&buck2>; 141}; 142 143&A53_3 { 144 cpu-supply = <&buck2>; 145}; 146 147&ecspi1 { 148 pinctrl-names = "default"; 149 pinctrl-0 = <&pinctrl_ecspi1>; 150 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 151 status = "okay"; 152 153 flash@0 { /* W25Q128JVEI */ 154 compatible = "jedec,spi-nor"; 155 reg = <0>; 156 spi-max-frequency = <40000000>; 157 spi-tx-bus-width = <1>; 158 spi-rx-bus-width = <1>; 159 }; 160}; 161 162&ecspi2 { /* Feature connector SPI */ 163 pinctrl-names = "default"; 164 pinctrl-0 = <&pinctrl_ecspi2>; 165 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 166 /* Disabled by default, unless feature board plugged in. */ 167 status = "disabled"; 168}; 169 170&ecspi3 { /* Display connector SPI */ 171 pinctrl-names = "default"; 172 pinctrl-0 = <&pinctrl_ecspi3>; 173 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; 174 /* Disabled by default, unless display board plugged in. */ 175 status = "disabled"; 176}; 177 178&eqos { /* First ethernet */ 179 pinctrl-names = "default"; 180 pinctrl-0 = <&pinctrl_eqos>; 181 phy-handle = <&phy_eqos>; 182 phy-mode = "rgmii-id"; 183 status = "okay"; 184 185 mdio { 186 compatible = "snps,dwmac-mdio"; 187 #address-cells = <1>; 188 #size-cells = <0>; 189 190 /* Atheros AR8031 PHY */ 191 phy_eqos: ethernet-phy@0 { 192 compatible = "ethernet-phy-ieee802.3-c22"; 193 reg = <0>; 194 /* 195 * Dedicated ENET_WOL# signal is unused, the PHY 196 * can wake the SoC up via INT signal as well. 197 */ 198 interrupts-extended = <&gpio1 11 IRQ_TYPE_LEVEL_LOW>; 199 reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; 200 reset-assert-us = <10000>; 201 reset-deassert-us = <10000>; 202 qca,keep-pll-enabled; 203 vddio-supply = <&vddio_eqos>; 204 205 vddio_eqos: vddio-regulator { 206 regulator-name = "VDDIO_EQOS"; 207 regulator-min-microvolt = <1800000>; 208 regulator-max-microvolt = <1800000>; 209 }; 210 211 vddh_eqos: vddh-regulator { 212 regulator-name = "VDDH_EQOS"; 213 }; 214 }; 215 }; 216}; 217 218&fec { /* Second ethernet */ 219 pinctrl-names = "default"; 220 pinctrl-0 = <&pinctrl_fec>; 221 phy-handle = <&phy_fec>; 222 phy-mode = "rgmii-id"; 223 fsl,magic-packet; 224 status = "okay"; 225 226 mdio { 227 #address-cells = <1>; 228 #size-cells = <0>; 229 230 /* Atheros AR8031 PHY */ 231 phy_fec: ethernet-phy@0 { 232 compatible = "ethernet-phy-ieee802.3-c22"; 233 reg = <0>; 234 /* 235 * Dedicated ENET_WOL# signal is unused, the PHY 236 * can wake the SoC up via INT signal as well. 237 */ 238 interrupts-extended = <&gpio2 2 IRQ_TYPE_LEVEL_LOW>; 239 reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; 240 reset-assert-us = <10000>; 241 reset-deassert-us = <10000>; 242 qca,keep-pll-enabled; 243 vddio-supply = <&vddio_fec>; 244 245 vddio_fec: vddio-regulator { 246 regulator-name = "VDDIO_FEC"; 247 regulator-min-microvolt = <1800000>; 248 regulator-max-microvolt = <1800000>; 249 }; 250 251 vddh_fec: vddh-regulator { 252 regulator-name = "VDDH_FEC"; 253 }; 254 }; 255 }; 256}; 257 258&flexcan1 { 259 pinctrl-names = "default"; 260 pinctrl-0 = <&pinctrl_flexcan1>; 261 status = "okay"; 262}; 263 264&gpio1 { 265 gpio-line-names = 266 "", "USBHUB_RESET#", "WDOG_B#", "PMIC_INT#", 267 "", "M2_PCIE_RST#", "M2_PCIE_WAKE#", "GPIO5_IO03", 268 "GPIO5_IO04", "PDM_SEL", "ENET_WOL#", "ENET_INT#", 269 "", "", "", "ENET_RST#", 270 "", "", "", "", "", "", "", "", 271 "", "", "", "", "", "", "", ""; 272}; 273 274&gpio2 { 275 gpio-line-names = 276 "", "", "ENET2_INT#", "", "", "", "", "", 277 "WDOG_KICK#", "ENET2_RST#", "CAN_INT#", "RTC_IRQ#", 278 "", "", "", "", 279 "", "", "", "SD2_RESET#", "", "", "", "", 280 "", "", "", "", "", "", "", ""; 281}; 282 283&gpio3 { 284 gpio-line-names = 285 "BL_ENABLE_1V8", "PG_V_IN_VAR#", "", "", 286 "", "", "TFT_ENABLE_1V8", "GRAPHICS_GPIO0_1V8", 287 "CSI2_PD_1V8", "CSI2_RESET_1V8#", "", "", 288 "", "", "EEPROM_WP_1V8#", "", "", "", "", "", 289 "MEMCFG0", "PCIE_CLK_GEN_CLKPWRGD_PD_1V8#", 290 "", "M2_W_DISABLE1_1V8#", 291 "M2_W_DISABLE2_1V8#", "", "I2C5_SCL_3V3", "I2C5_SDA_3V3", 292 "", "", "", ""; 293}; 294 295&gpio4 { 296 gpio-line-names = 297 "DSI_RESET_1V8#", "MEMCFG2", "", "MEMCFG1", "", "", "", "", 298 "", "", "", "", "", "", "", "", 299 "", "", "GRAPHICS_PRSNT_1V8#", "DSI_IRQ_1V8#", 300 "", "DIS_USB_DN1", "DIS_USB_DN2", "", 301 "", "", "", "", "", "", "", ""; 302}; 303 304&gpio5 { 305 gpio-line-names = 306 "", "", "", "", "", "WDOG_EN", "", "", 307 "", "SPI1_CS#", "", "", 308 "", "SPI2_CS#", "I2C1_SCL_3V3", "I2C1_SDA_3V3", 309 "I2C2_SCL_3V3", "I2C2_SDA_3V3", "I2C3_SCL_3V3", "I2C3_SDA_3V3", 310 "", "", "", "", 311 "", "SPI3_CS#", "", "", "", "", "", ""; 312}; 313 314&i2c1 { 315 clock-frequency = <100000>; 316 pinctrl-names = "default", "gpio"; 317 pinctrl-0 = <&pinctrl_i2c1>; 318 pinctrl-1 = <&pinctrl_i2c1_gpio>; 319 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 320 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 321 status = "okay"; 322 323 sgtl5000: audio-codec@a { 324 compatible = "fsl,sgtl5000"; 325 reg = <0x0a>; 326 #sound-dai-cells = <0>; 327 clocks = <&clk_pwm4>; 328 VDDA-supply = <&buck4>; 329 VDDIO-supply = <&buck4>; 330 }; 331 332 usb-hub@2c { 333 compatible = "microchip,usb2514bi"; 334 reg = <0x2c>; 335 pinctrl-names = "default"; 336 pinctrl-0 = <&pinctrl_usb_hub>; 337 individual-port-switching; 338 reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; 339 self-powered; 340 }; 341 342 eeprom: eeprom@50 { 343 compatible = "atmel,24c32"; 344 reg = <0x50>; 345 pagesize = <32>; 346 }; 347 348 rtc: rtc@68 { 349 compatible = "st,m41t62"; 350 reg = <0x68>; 351 pinctrl-names = "default"; 352 pinctrl-0 = <&pinctrl_rtc>; 353 interrupts-extended = <&gpio2 11 IRQ_TYPE_LEVEL_LOW>; 354 }; 355 356 pcieclk: clk@6a { 357 compatible = "renesas,9fgv0241"; 358 reg = <0x6a>; 359 clocks = <&clk_xtal25>; 360 #clock-cells = <1>; 361 }; 362}; 363 364&i2c2 { 365 clock-frequency = <100000>; 366 pinctrl-names = "default", "gpio"; 367 pinctrl-0 = <&pinctrl_i2c2>; 368 pinctrl-1 = <&pinctrl_i2c2_gpio>; 369 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 370 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 371 status = "okay"; 372}; 373 374&i2c3 { 375 clock-frequency = <100000>; 376 pinctrl-names = "default", "gpio"; 377 pinctrl-0 = <&pinctrl_i2c3>; 378 pinctrl-1 = <&pinctrl_i2c3_gpio>; 379 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 380 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 381 status = "okay"; 382 383 pmic: pmic@25 { 384 compatible = "nxp,pca9450c"; 385 reg = <0x25>; 386 pinctrl-names = "default"; 387 pinctrl-0 = <&pinctrl_pmic>; 388 interrupt-parent = <&gpio1>; 389 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 390 391 /* 392 * i.MX 8M Plus Data Sheet for Consumer Products 393 * 3.1.4 Operating ranges 394 * MIMX8ML8CVNKZAB 395 */ 396 regulators { 397 buck1: BUCK1 { /* VDD_SOC (dual-phase with BUCK3) */ 398 regulator-min-microvolt = <850000>; 399 regulator-max-microvolt = <1000000>; 400 regulator-ramp-delay = <3125>; 401 regulator-always-on; 402 regulator-boot-on; 403 }; 404 405 buck2: BUCK2 { /* VDD_ARM */ 406 nxp,dvs-run-voltage = <950000>; 407 nxp,dvs-standby-voltage = <850000>; 408 regulator-min-microvolt = <850000>; 409 regulator-max-microvolt = <1000000>; 410 regulator-ramp-delay = <3125>; 411 regulator-always-on; 412 regulator-boot-on; 413 }; 414 415 buck4: BUCK4 { /* VDD_3V3 */ 416 regulator-min-microvolt = <3300000>; 417 regulator-max-microvolt = <3300000>; 418 regulator-always-on; 419 regulator-boot-on; 420 }; 421 422 buck5: BUCK5 { /* VDD_1V8 */ 423 regulator-min-microvolt = <1800000>; 424 regulator-max-microvolt = <1800000>; 425 regulator-always-on; 426 regulator-boot-on; 427 }; 428 429 buck6: BUCK6 { /* NVCC_DRAM_1V1 */ 430 regulator-min-microvolt = <1100000>; 431 regulator-max-microvolt = <1100000>; 432 regulator-always-on; 433 regulator-boot-on; 434 }; 435 436 ldo1: LDO1 { /* NVCC_SNVS_1V8 */ 437 regulator-min-microvolt = <1800000>; 438 regulator-max-microvolt = <1800000>; 439 regulator-always-on; 440 regulator-boot-on; 441 }; 442 443 ldo3: LDO3 { /* VDDA_1V8 */ 444 regulator-min-microvolt = <1800000>; 445 regulator-max-microvolt = <1800000>; 446 regulator-always-on; 447 regulator-boot-on; 448 }; 449 450 ldo4: LDO4 { /* PMIC_LDO4 */ 451 regulator-min-microvolt = <3300000>; 452 regulator-max-microvolt = <3300000>; 453 }; 454 455 ldo5: LDO5 { /* NVCC_SD2 */ 456 regulator-min-microvolt = <1800000>; 457 regulator-max-microvolt = <3300000>; 458 }; 459 }; 460 }; 461}; 462 463&i2c5 { /* HDMI EDID bus */ 464 clock-frequency = <100000>; 465 pinctrl-names = "default", "gpio"; 466 pinctrl-0 = <&pinctrl_i2c5>; 467 pinctrl-1 = <&pinctrl_i2c5_gpio>; 468 scl-gpios = <&gpio3 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 469 sda-gpios = <&gpio3 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 470 status = "okay"; 471}; 472 473&pcie_phy { 474 clocks = <&pcieclk 0>; 475 clock-names = "ref"; 476 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; 477 status = "okay"; 478}; 479 480&pcie { 481 pinctrl-names = "default"; 482 pinctrl-0 = <&pinctrl_pcie0>; 483 fsl,max-link-speed = <3>; 484 reset-gpio = <&gpio1 5 GPIO_ACTIVE_LOW>; 485 status = "okay"; 486}; 487 488&pwm1 { 489 pinctrl-names = "default"; 490 pinctrl-0 = <&pinctrl_panel_pwm>; 491 /* Disabled by default, unless display board plugged in. */ 492 status = "disabled"; 493}; 494 495&pwm4 { 496 pinctrl-names = "default"; 497 pinctrl-0 = <&pinctrl_pwm4>; 498 status = "okay"; 499}; 500 501&sai3 { 502 #clock-cells = <0>; 503 #sound-dai-cells = <0>; 504 assigned-clocks = <&clk IMX8MP_CLK_SAI3>; 505 assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; 506 assigned-clock-rates = <12288000>; 507 pinctrl-names = "default"; 508 pinctrl-0 = <&pinctrl_sai3>; 509 status = "okay"; 510}; 511 512/* SD slot */ 513&usdhc2 { 514 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 515 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 516 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 517 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 518 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 519 vmmc-supply = <®_usdhc2_vmmc>; 520 bus-width = <4>; 521 status = "okay"; 522}; 523 524/* eMMC */ 525&usdhc3 { 526 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 527 pinctrl-0 = <&pinctrl_usdhc3>; 528 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 529 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 530 vmmc-supply = <&buck4>; 531 vqmmc-supply = <&buck5>; 532 bus-width = <8>; 533 no-sd; 534 no-sdio; 535 non-removable; 536 status = "okay"; 537}; 538 539&uart1 { /* RS485 */ 540 pinctrl-names = "default"; 541 pinctrl-0 = <&pinctrl_uart1>; 542 uart-has-rtscts; 543 status = "disabled"; /* Optional */ 544}; 545 546&uart2 { 547 pinctrl-names = "default"; 548 pinctrl-0 = <&pinctrl_uart2>; 549 uart-has-rtscts; 550 status = "okay"; 551}; 552 553&uart3 { /* A53 Debug */ 554 pinctrl-names = "default"; 555 pinctrl-0 = <&pinctrl_uart3>; 556 status = "okay"; 557}; 558 559&uart4 { 560 pinctrl-names = "default"; 561 pinctrl-0 = <&pinctrl_uart4>; 562 status = "disabled"; 563}; 564 565&usb3_phy0 { 566 status = "okay"; 567}; 568 569&usb3_0 { 570 fsl,over-current-active-low; 571 status = "okay"; 572}; 573 574&usb_dwc3_0 { /* Lower plug direct */ 575 pinctrl-names = "default"; 576 pinctrl-0 = <&pinctrl_usb1>; 577 dr_mode = "host"; 578 status = "okay"; 579}; 580 581&usb3_phy1 { 582 status = "okay"; 583}; 584 585&usb3_1 { 586 status = "okay"; 587}; 588 589&usb_dwc3_1 { /* Upper plug via HUB */ 590 dr_mode = "host"; 591 status = "okay"; 592}; 593 594&wdog1 { 595 status = "okay"; 596}; 597 598/* IOMUXC node should be at the end of DT to improve readability. */ 599&iomuxc { 600 pinctrl-names = "default"; 601 pinctrl-0 = <&pinctrl_hog_feature>, <&pinctrl_hog_misc>, 602 <&pinctrl_hog_panel>, <&pinctrl_hog_sbc>, 603 <&pinctrl_panel_expansion>; 604 605 pinctrl_ecspi1: ecspi1-grp { 606 fsl,pins = < 607 MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x44 608 MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x44 609 MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x44 610 MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x40 611 >; 612 }; 613 614 pinctrl_ecspi2: ecspi2-grp { 615 fsl,pins = < 616 MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x44 617 MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x44 618 MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x44 619 MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40 620 >; 621 }; 622 623 pinctrl_ecspi3: ecspi3-grp { 624 fsl,pins = < 625 MX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK 0x44 626 MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI 0x44 627 MX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO 0x44 628 MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 0x40 629 >; 630 }; 631 632 pinctrl_eqos: eqos-grp { 633 fsl,pins = < 634 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 635 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 636 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f 637 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f 638 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f 639 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f 640 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f 641 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f 642 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 643 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 644 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 645 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 646 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 647 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 648 /* ENET_RST# */ 649 MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x6 650 /* ENET_INT# */ 651 MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000090 652 >; 653 }; 654 655 pinctrl_fec: fec-grp { 656 fsl,pins = < 657 MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 658 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 659 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 660 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 661 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 662 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 663 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 664 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 665 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f 666 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f 667 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f 668 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f 669 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f 670 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f 671 /* ENET2_RST# */ 672 MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x6 673 /* ENET2_INT# */ 674 MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 0x40000090 675 >; 676 }; 677 678 pinctrl_flexcan1: flexcan1-grp { 679 fsl,pins = < 680 MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 681 MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 682 >; 683 }; 684 685 pinctrl_hog_feature: hog-feature-grp { 686 fsl,pins = < 687 /* GPIO5_IO03 */ 688 MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x40000006 689 /* GPIO5_IO04 */ 690 MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x40000006 691 692 /* CAN_INT# */ 693 MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x40000090 694 >; 695 }; 696 697 pinctrl_hog_panel: hog-panel-grp { 698 fsl,pins = < 699 /* GRAPHICS_GPIO0_1V8 */ 700 MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x26 701 >; 702 }; 703 704 pinctrl_hog_misc: hog-misc-grp { 705 fsl,pins = < 706 /* ENET_WOL# -- shared by both PHYs */ 707 MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x40000090 708 709 /* PG_V_IN_VAR# */ 710 MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x40000000 711 /* CSI2_PD_1V8 */ 712 MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x0 713 /* CSI2_RESET_1V8# */ 714 MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x0 715 716 /* DIS_USB_DN1 */ 717 MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x0 718 /* DIS_USB_DN2 */ 719 MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x0 720 721 /* EEPROM_WP_1V8# */ 722 MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x100 723 /* PCIE_CLK_GEN_CLKPWRGD_PD_1V8# */ 724 MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x0 725 /* GRAPHICS_PRSNT_1V8# */ 726 MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x40000000 727 728 /* CLK_CCM_CLKO1_3V3 */ 729 MX8MP_IOMUXC_GPIO1_IO14__CCM_CLKO1 0x10 730 >; 731 }; 732 733 pinctrl_hog_sbc: hog-sbc-grp { 734 fsl,pins = < 735 /* MEMCFG[0..2] straps */ 736 MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x40000140 737 MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x40000140 738 MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x40000140 739 >; 740 }; 741 742 pinctrl_i2c1: i2c1-grp { 743 fsl,pins = < 744 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x40000084 745 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x40000084 746 >; 747 }; 748 749 pinctrl_i2c1_gpio: i2c1-gpio-grp { 750 fsl,pins = < 751 MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x84 752 MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x84 753 >; 754 }; 755 756 pinctrl_i2c2: i2c2-grp { 757 fsl,pins = < 758 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x40000084 759 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x40000084 760 >; 761 }; 762 763 pinctrl_i2c2_gpio: i2c2-gpio-grp { 764 fsl,pins = < 765 MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x84 766 MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x84 767 >; 768 }; 769 770 pinctrl_i2c3: i2c3-grp { 771 fsl,pins = < 772 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x40000084 773 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x40000084 774 >; 775 }; 776 777 pinctrl_i2c3_gpio: i2c3-gpio-grp { 778 fsl,pins = < 779 MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x84 780 MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x84 781 >; 782 }; 783 784 pinctrl_i2c5: i2c5-grp { 785 fsl,pins = < 786 MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL 0x40000084 787 MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA 0x40000084 788 >; 789 }; 790 791 pinctrl_i2c5_gpio: i2c5-gpio-grp { 792 fsl,pins = < 793 MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26 0x84 794 MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27 0x84 795 >; 796 }; 797 798 pinctrl_panel_backlight: panel-backlight-grp { 799 fsl,pins = < 800 /* BL_ENABLE_1V8 */ 801 MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x104 802 >; 803 }; 804 805 pinctrl_panel_expansion: panel-expansion-grp { 806 fsl,pins = < 807 /* DSI_RESET_1V8# */ 808 MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x2 809 /* DSI_IRQ_1V8# */ 810 MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x40000090 811 >; 812 }; 813 814 pinctrl_panel_pwm: panel-pwm-grp { 815 fsl,pins = < 816 /* BL_PWM_3V3 */ 817 MX8MP_IOMUXC_I2C4_SDA__PWM1_OUT 0x12 818 >; 819 }; 820 821 pinctrl_panel_vcc_reg: panel-vcc-grp { 822 fsl,pins = < 823 /* TFT_ENABLE_1V8 */ 824 MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x104 825 >; 826 }; 827 828 pinctrl_pcie0: pcie-grp { 829 fsl,pins = < 830 /* M2_PCIE_RST# */ 831 MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x2 832 /* M2_W_DISABLE1_1V8# */ 833 MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x2 834 /* M2_W_DISABLE2_1V8# */ 835 MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x2 836 /* CLK_M2_32K768 */ 837 MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x14 838 /* M2_PCIE_WAKE# */ 839 MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x40000140 840 /* M2_PCIE_CLKREQ# */ 841 MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x61 842 >; 843 }; 844 845 pinctrl_pdm: pdm-grp { 846 fsl,pins = < 847 /* PDM_SEL */ 848 MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x0 849 MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_PDM_CLK 0x0 850 MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_PDM_BIT_STREAM00 0x0 851 >; 852 }; 853 854 pinctrl_pmic: pmic-grp { 855 fsl,pins = < 856 /* PMIC_nINT */ 857 MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x40000090 858 >; 859 }; 860 861 pinctrl_pwm4: pwm4-grp { 862 fsl,pins = < 863 MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT 0xd6 864 >; 865 }; 866 867 pinctrl_rtc: rtc-grp { 868 fsl,pins = < 869 /* RTC_IRQ# */ 870 MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x40000090 871 >; 872 }; 873 874 pinctrl_sai1: sai1-grp { 875 fsl,pins = < 876 MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC 0xd6 877 MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00 0xd6 878 MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI1_TX_BCLK 0xd6 879 MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK 0xd6 880 MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00 0xd6 881 >; 882 }; 883 884 pinctrl_sai2: sai2-grp { 885 fsl,pins = < 886 MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0xd6 887 MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6 888 MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0xd6 889 MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK 0xd6 890 >; 891 }; 892 893 pinctrl_sai3: sai3-grp { 894 fsl,pins = < 895 MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6 896 MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6 897 MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6 898 MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 899 >; 900 }; 901 902 pinctrl_uart1: uart1-grp { 903 fsl,pins = < 904 MX8MP_IOMUXC_SD1_CLK__UART1_DCE_TX 0x49 905 MX8MP_IOMUXC_SD1_CMD__UART1_DCE_RX 0x49 906 MX8MP_IOMUXC_SD1_DATA1__UART1_DCE_CTS 0x49 907 MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x49 908 >; 909 }; 910 911 pinctrl_uart2: uart2-grp { 912 fsl,pins = < 913 MX8MP_IOMUXC_SD1_DATA2__UART2_DCE_TX 0x49 914 MX8MP_IOMUXC_SD1_DATA3__UART2_DCE_RX 0x49 915 MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 0x49 916 MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x49 917 >; 918 }; 919 920 pinctrl_uart3: uart3-grp { 921 fsl,pins = < 922 MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x49 923 MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x49 924 >; 925 }; 926 927 pinctrl_uart4: uart4-grp { 928 fsl,pins = < 929 MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49 930 MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49 931 >; 932 }; 933 934 pinctrl_usdhc2: usdhc2-grp { 935 fsl,pins = < 936 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 937 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 938 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 939 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 940 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 941 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 942 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 943 >; 944 }; 945 946 pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp { 947 fsl,pins = < 948 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 949 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 950 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 951 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 952 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 953 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 954 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 955 >; 956 }; 957 958 pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp { 959 fsl,pins = < 960 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 961 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 962 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 963 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 964 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 965 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 966 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 967 >; 968 }; 969 970 pinctrl_usdhc2_vmmc: usdhc2-vmmc-grp { 971 fsl,pins = < 972 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x20 973 >; 974 }; 975 976 pinctrl_usdhc2_gpio: usdhc2-gpio-grp { 977 fsl,pins = < 978 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x40000080 979 >; 980 }; 981 982 pinctrl_usdhc3: usdhc3-grp { 983 fsl,pins = < 984 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 985 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 986 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 987 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 988 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 989 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 990 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 991 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 992 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 993 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 994 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 995 MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141 996 >; 997 }; 998 999 pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp { 1000 fsl,pins = < 1001 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 1002 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 1003 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 1004 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 1005 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 1006 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 1007 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 1008 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 1009 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 1010 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 1011 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 1012 MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141 1013 >; 1014 }; 1015 1016 pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp { 1017 fsl,pins = < 1018 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 1019 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 1020 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 1021 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 1022 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 1023 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 1024 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 1025 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 1026 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 1027 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 1028 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 1029 MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141 1030 >; 1031 }; 1032 1033 pinctrl_usb_hub: usb-hub-grp { 1034 fsl,pins = < 1035 /* USBHUB_RESET# */ 1036 MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x4 1037 >; 1038 }; 1039 1040 pinctrl_usb1: usb1-grp { 1041 fsl,pins = < 1042 MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR 0x6 1043 MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x80 1044 >; 1045 }; 1046 1047 pinctrl_watchdog_gpio: watchdog-gpio-grp { 1048 fsl,pins = < 1049 /* WDOG_B# */ 1050 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x26 1051 /* WDOG_EN -- ungate WDT RESET# signal propagation */ 1052 MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x6 1053 /* WDOG_KICK# / WDI */ 1054 MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x26 1055 >; 1056 }; 1057}; 1058