1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2// 3// Device Tree Include file for Layerscape-LX2160A family SoC. 4// 5// Copyright 2018-2020 NXP 6 7#include <dt-bindings/clock/fsl,qoriq-clockgen.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/thermal/thermal.h> 11 12/memreserve/ 0x80000000 0x00010000; 13 14/ { 15 compatible = "fsl,lx2160a"; 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 rtc1 = &ftm_alarm0; 22 }; 23 24 cpus { 25 #address-cells = <1>; 26 #size-cells = <0>; 27 28 // 8 clusters having 2 Cortex-A72 cores each 29 cpu0: cpu@0 { 30 device_type = "cpu"; 31 compatible = "arm,cortex-a72"; 32 enable-method = "psci"; 33 reg = <0x0>; 34 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 35 d-cache-size = <0x8000>; 36 d-cache-line-size = <64>; 37 d-cache-sets = <128>; 38 i-cache-size = <0xC000>; 39 i-cache-line-size = <64>; 40 i-cache-sets = <192>; 41 next-level-cache = <&cluster0_l2>; 42 cpu-idle-states = <&cpu_pw15>; 43 #cooling-cells = <2>; 44 }; 45 46 cpu1: cpu@1 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a72"; 49 enable-method = "psci"; 50 reg = <0x1>; 51 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 52 d-cache-size = <0x8000>; 53 d-cache-line-size = <64>; 54 d-cache-sets = <128>; 55 i-cache-size = <0xC000>; 56 i-cache-line-size = <64>; 57 i-cache-sets = <192>; 58 next-level-cache = <&cluster0_l2>; 59 cpu-idle-states = <&cpu_pw15>; 60 #cooling-cells = <2>; 61 }; 62 63 cpu100: cpu@100 { 64 device_type = "cpu"; 65 compatible = "arm,cortex-a72"; 66 enable-method = "psci"; 67 reg = <0x100>; 68 clocks = <&clockgen QORIQ_CLK_CMUX 1>; 69 d-cache-size = <0x8000>; 70 d-cache-line-size = <64>; 71 d-cache-sets = <128>; 72 i-cache-size = <0xC000>; 73 i-cache-line-size = <64>; 74 i-cache-sets = <192>; 75 next-level-cache = <&cluster1_l2>; 76 cpu-idle-states = <&cpu_pw15>; 77 #cooling-cells = <2>; 78 }; 79 80 cpu101: cpu@101 { 81 device_type = "cpu"; 82 compatible = "arm,cortex-a72"; 83 enable-method = "psci"; 84 reg = <0x101>; 85 clocks = <&clockgen QORIQ_CLK_CMUX 1>; 86 d-cache-size = <0x8000>; 87 d-cache-line-size = <64>; 88 d-cache-sets = <128>; 89 i-cache-size = <0xC000>; 90 i-cache-line-size = <64>; 91 i-cache-sets = <192>; 92 next-level-cache = <&cluster1_l2>; 93 cpu-idle-states = <&cpu_pw15>; 94 #cooling-cells = <2>; 95 }; 96 97 cpu200: cpu@200 { 98 device_type = "cpu"; 99 compatible = "arm,cortex-a72"; 100 enable-method = "psci"; 101 reg = <0x200>; 102 clocks = <&clockgen QORIQ_CLK_CMUX 2>; 103 d-cache-size = <0x8000>; 104 d-cache-line-size = <64>; 105 d-cache-sets = <128>; 106 i-cache-size = <0xC000>; 107 i-cache-line-size = <64>; 108 i-cache-sets = <192>; 109 next-level-cache = <&cluster2_l2>; 110 cpu-idle-states = <&cpu_pw15>; 111 #cooling-cells = <2>; 112 }; 113 114 cpu201: cpu@201 { 115 device_type = "cpu"; 116 compatible = "arm,cortex-a72"; 117 enable-method = "psci"; 118 reg = <0x201>; 119 clocks = <&clockgen QORIQ_CLK_CMUX 2>; 120 d-cache-size = <0x8000>; 121 d-cache-line-size = <64>; 122 d-cache-sets = <128>; 123 i-cache-size = <0xC000>; 124 i-cache-line-size = <64>; 125 i-cache-sets = <192>; 126 next-level-cache = <&cluster2_l2>; 127 cpu-idle-states = <&cpu_pw15>; 128 #cooling-cells = <2>; 129 }; 130 131 cpu300: cpu@300 { 132 device_type = "cpu"; 133 compatible = "arm,cortex-a72"; 134 enable-method = "psci"; 135 reg = <0x300>; 136 clocks = <&clockgen QORIQ_CLK_CMUX 3>; 137 d-cache-size = <0x8000>; 138 d-cache-line-size = <64>; 139 d-cache-sets = <128>; 140 i-cache-size = <0xC000>; 141 i-cache-line-size = <64>; 142 i-cache-sets = <192>; 143 next-level-cache = <&cluster3_l2>; 144 cpu-idle-states = <&cpu_pw15>; 145 #cooling-cells = <2>; 146 }; 147 148 cpu301: cpu@301 { 149 device_type = "cpu"; 150 compatible = "arm,cortex-a72"; 151 enable-method = "psci"; 152 reg = <0x301>; 153 clocks = <&clockgen QORIQ_CLK_CMUX 3>; 154 d-cache-size = <0x8000>; 155 d-cache-line-size = <64>; 156 d-cache-sets = <128>; 157 i-cache-size = <0xC000>; 158 i-cache-line-size = <64>; 159 i-cache-sets = <192>; 160 next-level-cache = <&cluster3_l2>; 161 cpu-idle-states = <&cpu_pw15>; 162 #cooling-cells = <2>; 163 }; 164 165 cpu400: cpu@400 { 166 device_type = "cpu"; 167 compatible = "arm,cortex-a72"; 168 enable-method = "psci"; 169 reg = <0x400>; 170 clocks = <&clockgen QORIQ_CLK_CMUX 4>; 171 d-cache-size = <0x8000>; 172 d-cache-line-size = <64>; 173 d-cache-sets = <128>; 174 i-cache-size = <0xC000>; 175 i-cache-line-size = <64>; 176 i-cache-sets = <192>; 177 next-level-cache = <&cluster4_l2>; 178 cpu-idle-states = <&cpu_pw15>; 179 #cooling-cells = <2>; 180 }; 181 182 cpu401: cpu@401 { 183 device_type = "cpu"; 184 compatible = "arm,cortex-a72"; 185 enable-method = "psci"; 186 reg = <0x401>; 187 clocks = <&clockgen QORIQ_CLK_CMUX 4>; 188 d-cache-size = <0x8000>; 189 d-cache-line-size = <64>; 190 d-cache-sets = <128>; 191 i-cache-size = <0xC000>; 192 i-cache-line-size = <64>; 193 i-cache-sets = <192>; 194 next-level-cache = <&cluster4_l2>; 195 cpu-idle-states = <&cpu_pw15>; 196 #cooling-cells = <2>; 197 }; 198 199 cpu500: cpu@500 { 200 device_type = "cpu"; 201 compatible = "arm,cortex-a72"; 202 enable-method = "psci"; 203 reg = <0x500>; 204 clocks = <&clockgen QORIQ_CLK_CMUX 5>; 205 d-cache-size = <0x8000>; 206 d-cache-line-size = <64>; 207 d-cache-sets = <128>; 208 i-cache-size = <0xC000>; 209 i-cache-line-size = <64>; 210 i-cache-sets = <192>; 211 next-level-cache = <&cluster5_l2>; 212 cpu-idle-states = <&cpu_pw15>; 213 #cooling-cells = <2>; 214 }; 215 216 cpu501: cpu@501 { 217 device_type = "cpu"; 218 compatible = "arm,cortex-a72"; 219 enable-method = "psci"; 220 reg = <0x501>; 221 clocks = <&clockgen QORIQ_CLK_CMUX 5>; 222 d-cache-size = <0x8000>; 223 d-cache-line-size = <64>; 224 d-cache-sets = <128>; 225 i-cache-size = <0xC000>; 226 i-cache-line-size = <64>; 227 i-cache-sets = <192>; 228 next-level-cache = <&cluster5_l2>; 229 cpu-idle-states = <&cpu_pw15>; 230 #cooling-cells = <2>; 231 }; 232 233 cpu600: cpu@600 { 234 device_type = "cpu"; 235 compatible = "arm,cortex-a72"; 236 enable-method = "psci"; 237 reg = <0x600>; 238 clocks = <&clockgen QORIQ_CLK_CMUX 6>; 239 d-cache-size = <0x8000>; 240 d-cache-line-size = <64>; 241 d-cache-sets = <128>; 242 i-cache-size = <0xC000>; 243 i-cache-line-size = <64>; 244 i-cache-sets = <192>; 245 next-level-cache = <&cluster6_l2>; 246 cpu-idle-states = <&cpu_pw15>; 247 #cooling-cells = <2>; 248 }; 249 250 cpu601: cpu@601 { 251 device_type = "cpu"; 252 compatible = "arm,cortex-a72"; 253 enable-method = "psci"; 254 reg = <0x601>; 255 clocks = <&clockgen QORIQ_CLK_CMUX 6>; 256 d-cache-size = <0x8000>; 257 d-cache-line-size = <64>; 258 d-cache-sets = <128>; 259 i-cache-size = <0xC000>; 260 i-cache-line-size = <64>; 261 i-cache-sets = <192>; 262 next-level-cache = <&cluster6_l2>; 263 cpu-idle-states = <&cpu_pw15>; 264 #cooling-cells = <2>; 265 }; 266 267 cpu700: cpu@700 { 268 device_type = "cpu"; 269 compatible = "arm,cortex-a72"; 270 enable-method = "psci"; 271 reg = <0x700>; 272 clocks = <&clockgen QORIQ_CLK_CMUX 7>; 273 d-cache-size = <0x8000>; 274 d-cache-line-size = <64>; 275 d-cache-sets = <128>; 276 i-cache-size = <0xC000>; 277 i-cache-line-size = <64>; 278 i-cache-sets = <192>; 279 next-level-cache = <&cluster7_l2>; 280 cpu-idle-states = <&cpu_pw15>; 281 #cooling-cells = <2>; 282 }; 283 284 cpu701: cpu@701 { 285 device_type = "cpu"; 286 compatible = "arm,cortex-a72"; 287 enable-method = "psci"; 288 reg = <0x701>; 289 clocks = <&clockgen QORIQ_CLK_CMUX 7>; 290 d-cache-size = <0x8000>; 291 d-cache-line-size = <64>; 292 d-cache-sets = <128>; 293 i-cache-size = <0xC000>; 294 i-cache-line-size = <64>; 295 i-cache-sets = <192>; 296 next-level-cache = <&cluster7_l2>; 297 cpu-idle-states = <&cpu_pw15>; 298 #cooling-cells = <2>; 299 }; 300 301 cluster0_l2: l2-cache0 { 302 compatible = "cache"; 303 cache-unified; 304 cache-size = <0x100000>; 305 cache-line-size = <64>; 306 cache-sets = <1024>; 307 cache-level = <2>; 308 }; 309 310 cluster1_l2: l2-cache1 { 311 compatible = "cache"; 312 cache-unified; 313 cache-size = <0x100000>; 314 cache-line-size = <64>; 315 cache-sets = <1024>; 316 cache-level = <2>; 317 }; 318 319 cluster2_l2: l2-cache2 { 320 compatible = "cache"; 321 cache-unified; 322 cache-size = <0x100000>; 323 cache-line-size = <64>; 324 cache-sets = <1024>; 325 cache-level = <2>; 326 }; 327 328 cluster3_l2: l2-cache3 { 329 compatible = "cache"; 330 cache-unified; 331 cache-size = <0x100000>; 332 cache-line-size = <64>; 333 cache-sets = <1024>; 334 cache-level = <2>; 335 }; 336 337 cluster4_l2: l2-cache4 { 338 compatible = "cache"; 339 cache-unified; 340 cache-size = <0x100000>; 341 cache-line-size = <64>; 342 cache-sets = <1024>; 343 cache-level = <2>; 344 }; 345 346 cluster5_l2: l2-cache5 { 347 compatible = "cache"; 348 cache-unified; 349 cache-size = <0x100000>; 350 cache-line-size = <64>; 351 cache-sets = <1024>; 352 cache-level = <2>; 353 }; 354 355 cluster6_l2: l2-cache6 { 356 compatible = "cache"; 357 cache-unified; 358 cache-size = <0x100000>; 359 cache-line-size = <64>; 360 cache-sets = <1024>; 361 cache-level = <2>; 362 }; 363 364 cluster7_l2: l2-cache7 { 365 compatible = "cache"; 366 cache-unified; 367 cache-size = <0x100000>; 368 cache-line-size = <64>; 369 cache-sets = <1024>; 370 cache-level = <2>; 371 }; 372 373 cpu_pw15: cpu-pw15 { 374 compatible = "arm,idle-state"; 375 idle-state-name = "PW15"; 376 arm,psci-suspend-param = <0x0>; 377 entry-latency-us = <2000>; 378 exit-latency-us = <2000>; 379 min-residency-us = <6000>; 380 }; 381 }; 382 383 gic: interrupt-controller@6000000 { 384 compatible = "arm,gic-v3"; 385 reg = <0x0 0x06000000 0 0x10000>, // GIC Dist 386 <0x0 0x06200000 0 0x200000>, // GICR (RD_base + 387 // SGI_base) 388 <0x0 0x0c0c0000 0 0x2000>, // GICC 389 <0x0 0x0c0d0000 0 0x1000>, // GICH 390 <0x0 0x0c0e0000 0 0x20000>; // GICV 391 #interrupt-cells = <3>; 392 #address-cells = <2>; 393 #size-cells = <2>; 394 ranges; 395 interrupt-controller; 396 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 397 398 its: msi-controller@6020000 { 399 compatible = "arm,gic-v3-its"; 400 msi-controller; 401 reg = <0x0 0x6020000 0 0x20000>; 402 }; 403 }; 404 405 timer { 406 compatible = "arm,armv8-timer"; 407 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 408 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 409 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 410 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 411 }; 412 413 pmu { 414 compatible = "arm,cortex-a72-pmu"; 415 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 416 }; 417 418 psci { 419 compatible = "arm,psci-0.2"; 420 method = "smc"; 421 }; 422 423 memory@80000000 { 424 // DRAM space - 1, size : 2 GB DRAM 425 device_type = "memory"; 426 reg = <0x00000000 0x80000000 0 0x80000000>; 427 }; 428 429 ddr1: memory-controller@1080000 { 430 compatible = "fsl,qoriq-memory-controller"; 431 reg = <0x0 0x1080000 0x0 0x1000>; 432 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 433 little-endian; 434 }; 435 436 ddr2: memory-controller@1090000 { 437 compatible = "fsl,qoriq-memory-controller"; 438 reg = <0x0 0x1090000 0x0 0x1000>; 439 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 440 little-endian; 441 }; 442 443 // One clock unit-sysclk node which bootloader require during DT fix-up 444 sysclk: sysclk { 445 compatible = "fixed-clock"; 446 #clock-cells = <0>; 447 clock-frequency = <100000000>; // fixed up by bootloader 448 clock-output-names = "sysclk"; 449 }; 450 451 thermal-zones { 452 cluster6-7 { 453 polling-delay-passive = <1000>; 454 polling-delay = <5000>; 455 thermal-sensors = <&tmu 0>; 456 457 trips { 458 cluster6_7_alert: cluster6-7-alert { 459 temperature = <85000>; 460 hysteresis = <2000>; 461 type = "passive"; 462 }; 463 464 cluster6_7_crit: cluster6-7-crit { 465 temperature = <95000>; 466 hysteresis = <2000>; 467 type = "critical"; 468 }; 469 }; 470 471 cooling-maps { 472 map0 { 473 trip = <&cluster6_7_alert>; 474 cooling-device = 475 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 476 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 477 <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 478 <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 479 <&cpu200 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 480 <&cpu201 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 481 <&cpu300 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 482 <&cpu301 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 483 <&cpu400 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 484 <&cpu401 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 485 <&cpu500 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 486 <&cpu501 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 487 <&cpu600 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 488 <&cpu601 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 489 <&cpu700 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 490 <&cpu701 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 491 }; 492 }; 493 }; 494 495 ddr-cluster5 { 496 polling-delay-passive = <1000>; 497 polling-delay = <5000>; 498 thermal-sensors = <&tmu 1>; 499 500 trips { 501 ddr-cluster5-alert { 502 temperature = <85000>; 503 hysteresis = <2000>; 504 type = "passive"; 505 }; 506 507 ddr-cluster5-crit { 508 temperature = <95000>; 509 hysteresis = <2000>; 510 type = "critical"; 511 }; 512 }; 513 }; 514 515 wriop { 516 polling-delay-passive = <1000>; 517 polling-delay = <5000>; 518 thermal-sensors = <&tmu 2>; 519 520 trips { 521 wriop-alert { 522 temperature = <85000>; 523 hysteresis = <2000>; 524 type = "passive"; 525 }; 526 527 wriop-crit { 528 temperature = <95000>; 529 hysteresis = <2000>; 530 type = "critical"; 531 }; 532 }; 533 }; 534 535 dce-qbman-hsio2 { 536 polling-delay-passive = <1000>; 537 polling-delay = <5000>; 538 thermal-sensors = <&tmu 3>; 539 540 trips { 541 dce-qbman-alert { 542 temperature = <85000>; 543 hysteresis = <2000>; 544 type = "passive"; 545 }; 546 547 dce-qbman-crit { 548 temperature = <95000>; 549 hysteresis = <2000>; 550 type = "critical"; 551 }; 552 }; 553 }; 554 555 ccn-dpaa-tbu { 556 polling-delay-passive = <1000>; 557 polling-delay = <5000>; 558 thermal-sensors = <&tmu 4>; 559 560 trips { 561 ccn-dpaa-alert { 562 temperature = <85000>; 563 hysteresis = <2000>; 564 type = "passive"; 565 }; 566 567 ccn-dpaa-crit { 568 temperature = <95000>; 569 hysteresis = <2000>; 570 type = "critical"; 571 }; 572 }; 573 }; 574 575 cluster4-hsio3 { 576 polling-delay-passive = <1000>; 577 polling-delay = <5000>; 578 thermal-sensors = <&tmu 5>; 579 580 trips { 581 clust4-hsio3-alert { 582 temperature = <85000>; 583 hysteresis = <2000>; 584 type = "passive"; 585 }; 586 587 clust4-hsio3-crit { 588 temperature = <95000>; 589 hysteresis = <2000>; 590 type = "critical"; 591 }; 592 }; 593 }; 594 595 cluster2-3 { 596 polling-delay-passive = <1000>; 597 polling-delay = <5000>; 598 thermal-sensors = <&tmu 6>; 599 600 trips { 601 cluster2-3-alert { 602 temperature = <85000>; 603 hysteresis = <2000>; 604 type = "passive"; 605 }; 606 607 cluster2-3-crit { 608 temperature = <95000>; 609 hysteresis = <2000>; 610 type = "critical"; 611 }; 612 }; 613 }; 614 }; 615 616 soc { 617 compatible = "simple-bus"; 618 #address-cells = <2>; 619 #size-cells = <2>; 620 ranges; 621 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; 622 623 serdes_1: phy@1ea0000 { 624 compatible = "fsl,lynx-28g"; 625 reg = <0x0 0x1ea0000 0x0 0x1e30>; 626 #phy-cells = <1>; 627 }; 628 629 serdes_2: phy@1eb0000 { 630 compatible = "fsl,lynx-28g"; 631 reg = <0x0 0x1eb0000 0x0 0x1e30>; 632 #phy-cells = <1>; 633 status = "disabled"; 634 }; 635 636 crypto: crypto@8000000 { 637 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 638 fsl,sec-era = <10>; 639 #address-cells = <1>; 640 #size-cells = <1>; 641 ranges = <0x0 0x00 0x8000000 0x100000>; 642 reg = <0x00 0x8000000 0x0 0x100000>; 643 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 644 dma-coherent; 645 status = "disabled"; 646 647 sec_jr0: jr@10000 { 648 compatible = "fsl,sec-v5.0-job-ring", 649 "fsl,sec-v4.0-job-ring"; 650 reg = <0x10000 0x10000>; 651 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 652 }; 653 654 sec_jr1: jr@20000 { 655 compatible = "fsl,sec-v5.0-job-ring", 656 "fsl,sec-v4.0-job-ring"; 657 reg = <0x20000 0x10000>; 658 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 659 }; 660 661 sec_jr2: jr@30000 { 662 compatible = "fsl,sec-v5.0-job-ring", 663 "fsl,sec-v4.0-job-ring"; 664 reg = <0x30000 0x10000>; 665 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 666 }; 667 668 sec_jr3: jr@40000 { 669 compatible = "fsl,sec-v5.0-job-ring", 670 "fsl,sec-v4.0-job-ring"; 671 reg = <0x40000 0x10000>; 672 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 673 }; 674 }; 675 676 clockgen: clock-controller@1300000 { 677 compatible = "fsl,lx2160a-clockgen"; 678 reg = <0 0x1300000 0 0xa0000>; 679 #clock-cells = <2>; 680 clocks = <&sysclk>; 681 }; 682 683 dcfg: syscon@1e00000 { 684 compatible = "fsl,lx2160a-dcfg", "syscon"; 685 reg = <0x0 0x1e00000 0x0 0x10000>; 686 little-endian; 687 }; 688 689 sfp: efuse@1e80000 { 690 compatible = "fsl,ls1028a-sfp"; 691 reg = <0x0 0x1e80000 0x0 0x10000>; 692 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 693 QORIQ_CLK_PLL_DIV(4)>; 694 clock-names = "sfp"; 695 }; 696 697 isc: syscon@1f70000 { 698 compatible = "fsl,lx2160a-isc", "syscon"; 699 reg = <0x0 0x1f70000 0x0 0x10000>; 700 little-endian; 701 #address-cells = <1>; 702 #size-cells = <1>; 703 ranges = <0x0 0x0 0x1f70000 0x10000>; 704 705 extirq: interrupt-controller@14 { 706 compatible = "fsl,lx2160a-extirq", "fsl,ls1088a-extirq"; 707 #interrupt-cells = <2>; 708 #address-cells = <0>; 709 interrupt-controller; 710 reg = <0x14 4>; 711 interrupt-map = 712 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 713 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 714 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 715 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 716 <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 717 <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 718 <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 719 <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 720 <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 721 <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 722 <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 723 <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 724 interrupt-map-mask = <0xf 0x0>; 725 }; 726 }; 727 728 tmu: tmu@1f80000 { 729 compatible = "fsl,qoriq-tmu"; 730 reg = <0x0 0x1f80000 0x0 0x10000>; 731 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 732 fsl,tmu-range = <0x800000e6 0x8001017d>; 733 fsl,tmu-calibration = 734 /* Calibration data group 1 */ 735 <0x00000000 0x00000035>, 736 /* Calibration data group 2 */ 737 <0x00000001 0x00000154>; 738 little-endian; 739 #thermal-sensor-cells = <1>; 740 }; 741 742 i2c0: i2c@2000000 { 743 compatible = "fsl,vf610-i2c"; 744 #address-cells = <1>; 745 #size-cells = <0>; 746 reg = <0x0 0x2000000 0x0 0x10000>; 747 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 748 clock-names = "i2c"; 749 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 750 QORIQ_CLK_PLL_DIV(16)>; 751 scl-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; 752 status = "disabled"; 753 }; 754 755 i2c1: i2c@2010000 { 756 compatible = "fsl,vf610-i2c"; 757 #address-cells = <1>; 758 #size-cells = <0>; 759 reg = <0x0 0x2010000 0x0 0x10000>; 760 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 761 clock-names = "i2c"; 762 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 763 QORIQ_CLK_PLL_DIV(16)>; 764 status = "disabled"; 765 }; 766 767 i2c2: i2c@2020000 { 768 compatible = "fsl,vf610-i2c"; 769 #address-cells = <1>; 770 #size-cells = <0>; 771 reg = <0x0 0x2020000 0x0 0x10000>; 772 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 773 clock-names = "i2c"; 774 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 775 QORIQ_CLK_PLL_DIV(16)>; 776 status = "disabled"; 777 }; 778 779 i2c3: i2c@2030000 { 780 compatible = "fsl,vf610-i2c"; 781 #address-cells = <1>; 782 #size-cells = <0>; 783 reg = <0x0 0x2030000 0x0 0x10000>; 784 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 785 clock-names = "i2c"; 786 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 787 QORIQ_CLK_PLL_DIV(16)>; 788 status = "disabled"; 789 }; 790 791 i2c4: i2c@2040000 { 792 compatible = "fsl,vf610-i2c"; 793 #address-cells = <1>; 794 #size-cells = <0>; 795 reg = <0x0 0x2040000 0x0 0x10000>; 796 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 797 clock-names = "i2c"; 798 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 799 QORIQ_CLK_PLL_DIV(16)>; 800 scl-gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>; 801 status = "disabled"; 802 }; 803 804 i2c5: i2c@2050000 { 805 compatible = "fsl,vf610-i2c"; 806 #address-cells = <1>; 807 #size-cells = <0>; 808 reg = <0x0 0x2050000 0x0 0x10000>; 809 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 810 clock-names = "i2c"; 811 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 812 QORIQ_CLK_PLL_DIV(16)>; 813 status = "disabled"; 814 }; 815 816 i2c6: i2c@2060000 { 817 compatible = "fsl,vf610-i2c"; 818 #address-cells = <1>; 819 #size-cells = <0>; 820 reg = <0x0 0x2060000 0x0 0x10000>; 821 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 822 clock-names = "i2c"; 823 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 824 QORIQ_CLK_PLL_DIV(16)>; 825 status = "disabled"; 826 }; 827 828 i2c7: i2c@2070000 { 829 compatible = "fsl,vf610-i2c"; 830 #address-cells = <1>; 831 #size-cells = <0>; 832 reg = <0x0 0x2070000 0x0 0x10000>; 833 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 834 clock-names = "i2c"; 835 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 836 QORIQ_CLK_PLL_DIV(16)>; 837 status = "disabled"; 838 }; 839 840 fspi: spi@20c0000 { 841 compatible = "nxp,lx2160a-fspi"; 842 #address-cells = <1>; 843 #size-cells = <0>; 844 reg = <0x0 0x20c0000 0x0 0x10000>, 845 <0x0 0x20000000 0x0 0x10000000>; 846 reg-names = "fspi_base", "fspi_mmap"; 847 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 848 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 849 QORIQ_CLK_PLL_DIV(4)>, 850 <&clockgen QORIQ_CLK_PLATFORM_PLL 851 QORIQ_CLK_PLL_DIV(4)>; 852 clock-names = "fspi_en", "fspi"; 853 status = "disabled"; 854 }; 855 856 dspi0: spi@2100000 { 857 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi"; 858 #address-cells = <1>; 859 #size-cells = <0>; 860 reg = <0x0 0x2100000 0x0 0x10000>; 861 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 862 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 863 QORIQ_CLK_PLL_DIV(8)>; 864 clock-names = "dspi"; 865 spi-num-chipselects = <5>; 866 bus-num = <0>; 867 status = "disabled"; 868 }; 869 870 dspi1: spi@2110000 { 871 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi"; 872 #address-cells = <1>; 873 #size-cells = <0>; 874 reg = <0x0 0x2110000 0x0 0x10000>; 875 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 876 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 877 QORIQ_CLK_PLL_DIV(8)>; 878 clock-names = "dspi"; 879 spi-num-chipselects = <5>; 880 bus-num = <1>; 881 status = "disabled"; 882 }; 883 884 dspi2: spi@2120000 { 885 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi"; 886 #address-cells = <1>; 887 #size-cells = <0>; 888 reg = <0x0 0x2120000 0x0 0x10000>; 889 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 890 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 891 QORIQ_CLK_PLL_DIV(8)>; 892 clock-names = "dspi"; 893 spi-num-chipselects = <5>; 894 bus-num = <2>; 895 status = "disabled"; 896 }; 897 898 esdhc0: esdhc@2140000 { 899 compatible = "fsl,esdhc"; 900 reg = <0x0 0x2140000 0x0 0x10000>; 901 interrupts = <0 28 0x4>; /* Level high type */ 902 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 903 QORIQ_CLK_PLL_DIV(2)>; 904 dma-coherent; 905 voltage-ranges = <1800 1800 3300 3300>; 906 sdhci,auto-cmd12; 907 little-endian; 908 bus-width = <4>; 909 status = "disabled"; 910 }; 911 912 esdhc1: esdhc@2150000 { 913 compatible = "fsl,esdhc"; 914 reg = <0x0 0x2150000 0x0 0x10000>; 915 interrupts = <0 63 0x4>; /* Level high type */ 916 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 917 QORIQ_CLK_PLL_DIV(2)>; 918 dma-coherent; 919 voltage-ranges = <1800 1800 3300 3300>; 920 sdhci,auto-cmd12; 921 broken-cd; 922 little-endian; 923 bus-width = <4>; 924 status = "disabled"; 925 }; 926 927 can0: can@2180000 { 928 compatible = "fsl,lx2160ar1-flexcan"; 929 reg = <0x0 0x2180000 0x0 0x10000>; 930 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 931 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 932 QORIQ_CLK_PLL_DIV(8)>, 933 <&clockgen QORIQ_CLK_SYSCLK 0>; 934 clock-names = "ipg", "per"; 935 fsl,clk-source = /bits/ 8 <0>; 936 status = "disabled"; 937 }; 938 939 can1: can@2190000 { 940 compatible = "fsl,lx2160ar1-flexcan"; 941 reg = <0x0 0x2190000 0x0 0x10000>; 942 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 943 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 944 QORIQ_CLK_PLL_DIV(8)>, 945 <&clockgen QORIQ_CLK_SYSCLK 0>; 946 clock-names = "ipg", "per"; 947 fsl,clk-source = /bits/ 8 <0>; 948 status = "disabled"; 949 }; 950 951 uart0: serial@21c0000 { 952 compatible = "arm,pl011", "arm,primecell"; 953 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 954 QORIQ_CLK_PLL_DIV(8)>, 955 <&clockgen QORIQ_CLK_PLATFORM_PLL 956 QORIQ_CLK_PLL_DIV(8)>; 957 clock-names = "uartclk", "apb_pclk"; 958 reg = <0x0 0x21c0000 0x0 0x1000>; 959 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 960 status = "disabled"; 961 }; 962 963 uart1: serial@21d0000 { 964 compatible = "arm,pl011", "arm,primecell"; 965 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 966 QORIQ_CLK_PLL_DIV(8)>, 967 <&clockgen QORIQ_CLK_PLATFORM_PLL 968 QORIQ_CLK_PLL_DIV(8)>; 969 clock-names = "uartclk", "apb_pclk"; 970 reg = <0x0 0x21d0000 0x0 0x1000>; 971 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 972 status = "disabled"; 973 }; 974 975 uart2: serial@21e0000 { 976 compatible = "arm,pl011", "arm,primecell"; 977 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 978 QORIQ_CLK_PLL_DIV(8)>, 979 <&clockgen QORIQ_CLK_PLATFORM_PLL 980 QORIQ_CLK_PLL_DIV(8)>; 981 clock-names = "uartclk", "apb_pclk"; 982 reg = <0x0 0x21e0000 0x0 0x1000>; 983 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 984 status = "disabled"; 985 }; 986 987 uart3: serial@21f0000 { 988 compatible = "arm,pl011", "arm,primecell"; 989 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 990 QORIQ_CLK_PLL_DIV(8)>, 991 <&clockgen QORIQ_CLK_PLATFORM_PLL 992 QORIQ_CLK_PLL_DIV(8)>; 993 clock-names = "uartclk", "apb_pclk"; 994 reg = <0x0 0x21f0000 0x0 0x1000>; 995 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 996 status = "disabled"; 997 }; 998 999 gpio0: gpio@2300000 { 1000 compatible = "fsl,qoriq-gpio"; 1001 reg = <0x0 0x2300000 0x0 0x10000>; 1002 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1003 gpio-controller; 1004 little-endian; 1005 #gpio-cells = <2>; 1006 interrupt-controller; 1007 #interrupt-cells = <2>; 1008 }; 1009 1010 gpio1: gpio@2310000 { 1011 compatible = "fsl,qoriq-gpio"; 1012 reg = <0x0 0x2310000 0x0 0x10000>; 1013 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1014 gpio-controller; 1015 little-endian; 1016 #gpio-cells = <2>; 1017 interrupt-controller; 1018 #interrupt-cells = <2>; 1019 }; 1020 1021 gpio2: gpio@2320000 { 1022 compatible = "fsl,qoriq-gpio"; 1023 reg = <0x0 0x2320000 0x0 0x10000>; 1024 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1025 gpio-controller; 1026 little-endian; 1027 #gpio-cells = <2>; 1028 interrupt-controller; 1029 #interrupt-cells = <2>; 1030 }; 1031 1032 gpio3: gpio@2330000 { 1033 compatible = "fsl,qoriq-gpio"; 1034 reg = <0x0 0x2330000 0x0 0x10000>; 1035 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1036 gpio-controller; 1037 little-endian; 1038 #gpio-cells = <2>; 1039 interrupt-controller; 1040 #interrupt-cells = <2>; 1041 }; 1042 1043 watchdog@23a0000 { 1044 compatible = "arm,sbsa-gwdt"; 1045 reg = <0x0 0x23a0000 0 0x1000>, 1046 <0x0 0x2390000 0 0x1000>; 1047 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1048 timeout-sec = <30>; 1049 }; 1050 1051 rcpm: power-controller@1e34040 { 1052 compatible = "fsl,lx2160a-rcpm", "fsl,qoriq-rcpm-2.1+"; 1053 reg = <0x0 0x1e34040 0x0 0x1c>; 1054 #fsl,rcpm-wakeup-cells = <7>; 1055 little-endian; 1056 }; 1057 1058 ftm_alarm0: timer@2800000 { 1059 compatible = "fsl,lx2160a-ftm-alarm"; 1060 reg = <0x0 0x2800000 0x0 0x10000>; 1061 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; 1062 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1063 }; 1064 1065 usb0: usb@3100000 { 1066 compatible = "snps,dwc3"; 1067 reg = <0x0 0x3100000 0x0 0x10000>; 1068 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1069 dr_mode = "host"; 1070 snps,quirk-frame-length-adjustment = <0x20>; 1071 usb3-lpm-capable; 1072 snps,dis_rxdet_inp3_quirk; 1073 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 1074 status = "disabled"; 1075 }; 1076 1077 usb1: usb@3110000 { 1078 compatible = "snps,dwc3"; 1079 reg = <0x0 0x3110000 0x0 0x10000>; 1080 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1081 dr_mode = "host"; 1082 snps,quirk-frame-length-adjustment = <0x20>; 1083 usb3-lpm-capable; 1084 snps,dis_rxdet_inp3_quirk; 1085 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 1086 status = "disabled"; 1087 }; 1088 1089 sata0: sata@3200000 { 1090 compatible = "fsl,lx2160a-ahci"; 1091 reg = <0x0 0x3200000 0x0 0x10000>, 1092 <0x7 0x100520 0x0 0x4>; 1093 reg-names = "ahci", "sata-ecc"; 1094 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1095 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1096 QORIQ_CLK_PLL_DIV(4)>; 1097 dma-coherent; 1098 status = "disabled"; 1099 }; 1100 1101 sata1: sata@3210000 { 1102 compatible = "fsl,lx2160a-ahci"; 1103 reg = <0x0 0x3210000 0x0 0x10000>, 1104 <0x7 0x100520 0x0 0x4>; 1105 reg-names = "ahci", "sata-ecc"; 1106 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1107 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1108 QORIQ_CLK_PLL_DIV(4)>; 1109 dma-coherent; 1110 status = "disabled"; 1111 }; 1112 1113 sata2: sata@3220000 { 1114 compatible = "fsl,lx2160a-ahci"; 1115 reg = <0x0 0x3220000 0x0 0x10000>, 1116 <0x7 0x100520 0x0 0x4>; 1117 reg-names = "ahci", "sata-ecc"; 1118 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1119 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1120 QORIQ_CLK_PLL_DIV(4)>; 1121 dma-coherent; 1122 status = "disabled"; 1123 }; 1124 1125 sata3: sata@3230000 { 1126 compatible = "fsl,lx2160a-ahci"; 1127 reg = <0x0 0x3230000 0x0 0x10000>, 1128 <0x7 0x100520 0x0 0x4>; 1129 reg-names = "ahci", "sata-ecc"; 1130 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1131 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1132 QORIQ_CLK_PLL_DIV(4)>; 1133 dma-coherent; 1134 status = "disabled"; 1135 }; 1136 1137 pcie1: pcie@3400000 { 1138 compatible = "fsl,lx2160a-pcie"; 1139 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ 1140 <0x80 0x00000000 0x0 0x00002000>; /* configuration space */ 1141 reg-names = "csr_axi_slave", "config_axi_slave"; 1142 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1143 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1144 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1145 interrupt-names = "aer", "pme", "intr"; 1146 #address-cells = <3>; 1147 #size-cells = <2>; 1148 device_type = "pci"; 1149 dma-coherent; 1150 apio-wins = <8>; 1151 ppio-wins = <8>; 1152 bus-range = <0x0 0xff>; 1153 ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1154 msi-parent = <&its>; 1155 #interrupt-cells = <1>; 1156 interrupt-map-mask = <0 0 0 7>; 1157 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1158 <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1159 <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1160 <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1161 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1162 status = "disabled"; 1163 }; 1164 1165 pcie2: pcie@3500000 { 1166 compatible = "fsl,lx2160a-pcie"; 1167 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ 1168 <0x88 0x00000000 0x0 0x00002000>; /* configuration space */ 1169 reg-names = "csr_axi_slave", "config_axi_slave"; 1170 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1171 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1172 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1173 interrupt-names = "aer", "pme", "intr"; 1174 #address-cells = <3>; 1175 #size-cells = <2>; 1176 device_type = "pci"; 1177 dma-coherent; 1178 apio-wins = <8>; 1179 ppio-wins = <8>; 1180 bus-range = <0x0 0xff>; 1181 ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1182 msi-parent = <&its>; 1183 #interrupt-cells = <1>; 1184 interrupt-map-mask = <0 0 0 7>; 1185 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1186 <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1187 <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1188 <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 1189 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1190 status = "disabled"; 1191 }; 1192 1193 pcie3: pcie@3600000 { 1194 compatible = "fsl,lx2160a-pcie"; 1195 reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ 1196 <0x90 0x00000000 0x0 0x00002000>; /* configuration space */ 1197 reg-names = "csr_axi_slave", "config_axi_slave"; 1198 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1199 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1200 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1201 interrupt-names = "aer", "pme", "intr"; 1202 #address-cells = <3>; 1203 #size-cells = <2>; 1204 device_type = "pci"; 1205 dma-coherent; 1206 apio-wins = <256>; 1207 ppio-wins = <24>; 1208 bus-range = <0x0 0xff>; 1209 ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1210 msi-parent = <&its>; 1211 #interrupt-cells = <1>; 1212 interrupt-map-mask = <0 0 0 7>; 1213 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1214 <0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1215 <0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1216 <0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1217 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1218 status = "disabled"; 1219 }; 1220 1221 pcie4: pcie@3700000 { 1222 compatible = "fsl,lx2160a-pcie"; 1223 reg = <0x00 0x03700000 0x0 0x00100000>, /* controller registers */ 1224 <0x98 0x00000000 0x0 0x00002000>; /* configuration space */ 1225 reg-names = "csr_axi_slave", "config_axi_slave"; 1226 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1227 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1228 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1229 interrupt-names = "aer", "pme", "intr"; 1230 #address-cells = <3>; 1231 #size-cells = <2>; 1232 device_type = "pci"; 1233 dma-coherent; 1234 apio-wins = <8>; 1235 ppio-wins = <8>; 1236 bus-range = <0x0 0xff>; 1237 ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1238 msi-parent = <&its>; 1239 #interrupt-cells = <1>; 1240 interrupt-map-mask = <0 0 0 7>; 1241 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1242 <0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1243 <0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1244 <0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1245 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1246 status = "disabled"; 1247 }; 1248 1249 pcie5: pcie@3800000 { 1250 compatible = "fsl,lx2160a-pcie"; 1251 reg = <0x00 0x03800000 0x0 0x00100000>, /* controller registers */ 1252 <0xa0 0x00000000 0x0 0x00002000>; /* configuration space */ 1253 reg-names = "csr_axi_slave", "config_axi_slave"; 1254 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1255 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1256 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1257 interrupt-names = "aer", "pme", "intr"; 1258 #address-cells = <3>; 1259 #size-cells = <2>; 1260 device_type = "pci"; 1261 dma-coherent; 1262 apio-wins = <256>; 1263 ppio-wins = <24>; 1264 bus-range = <0x0 0xff>; 1265 ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1266 msi-parent = <&its>; 1267 #interrupt-cells = <1>; 1268 interrupt-map-mask = <0 0 0 7>; 1269 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 1270 <0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1271 <0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1272 <0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 1273 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1274 status = "disabled"; 1275 }; 1276 1277 pcie6: pcie@3900000 { 1278 compatible = "fsl,lx2160a-pcie"; 1279 reg = <0x00 0x03900000 0x0 0x00100000>, /* controller registers */ 1280 <0xa8 0x00000000 0x0 0x00002000>; /* configuration space */ 1281 reg-names = "csr_axi_slave", "config_axi_slave"; 1282 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1283 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1284 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1285 interrupt-names = "aer", "pme", "intr"; 1286 #address-cells = <3>; 1287 #size-cells = <2>; 1288 device_type = "pci"; 1289 dma-coherent; 1290 apio-wins = <8>; 1291 ppio-wins = <8>; 1292 bus-range = <0x0 0xff>; 1293 ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1294 msi-parent = <&its>; 1295 #interrupt-cells = <1>; 1296 interrupt-map-mask = <0 0 0 7>; 1297 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1298 <0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1299 <0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1300 <0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1301 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1302 status = "disabled"; 1303 }; 1304 1305 smmu: iommu@5000000 { 1306 compatible = "arm,mmu-500"; 1307 reg = <0 0x5000000 0 0x800000>; 1308 #iommu-cells = <1>; 1309 #global-interrupts = <14>; 1310 // global secure fault 1311 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1312 // combined secure 1313 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1314 // global non-secure fault 1315 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1316 // combined non-secure 1317 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1318 // performance counter interrupts 0-9 1319 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 1320 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 1321 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 1322 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 1323 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 1324 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 1325 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 1326 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 1327 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 1328 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 1329 // per context interrupt, 64 interrupts 1330 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1331 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1332 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1333 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1334 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 1335 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 1336 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 1337 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 1338 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 1339 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1340 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 1341 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 1342 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 1343 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 1344 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 1345 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 1346 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 1347 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1348 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 1349 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 1350 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 1351 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 1352 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 1353 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 1354 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1355 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 1356 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 1357 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 1358 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 1359 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 1360 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1361 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 1362 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 1363 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 1364 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 1365 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1366 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1367 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1368 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1369 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 1370 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1371 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1372 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1373 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1374 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1375 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1376 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1377 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 1378 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 1379 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 1380 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 1381 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 1382 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 1383 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 1384 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 1385 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 1386 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 1387 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 1388 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 1389 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 1390 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 1391 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 1392 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 1393 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 1394 dma-coherent; 1395 }; 1396 1397 console@8340020 { 1398 compatible = "fsl,dpaa2-console"; 1399 reg = <0x00000000 0x08340020 0 0x2>; 1400 }; 1401 1402 ptp-timer@8b95000 { 1403 compatible = "fsl,dpaa2-ptp"; 1404 reg = <0x0 0x8b95000 0x0 0x100>; 1405 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1406 QORIQ_CLK_PLL_DIV(2)>; 1407 little-endian; 1408 fsl,extts-fifo; 1409 }; 1410 1411 /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */ 1412 emdio1: mdio@8b96000 { 1413 compatible = "fsl,fman-memac-mdio"; 1414 reg = <0x0 0x8b96000 0x0 0x1000>; 1415 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1416 #address-cells = <1>; 1417 #size-cells = <0>; 1418 little-endian; 1419 clock-frequency = <2500000>; 1420 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1421 QORIQ_CLK_PLL_DIV(2)>; 1422 status = "disabled"; 1423 }; 1424 1425 emdio2: mdio@8b97000 { 1426 compatible = "fsl,fman-memac-mdio"; 1427 reg = <0x0 0x8b97000 0x0 0x1000>; 1428 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1429 little-endian; 1430 #address-cells = <1>; 1431 #size-cells = <0>; 1432 clock-frequency = <2500000>; 1433 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1434 QORIQ_CLK_PLL_DIV(2)>; 1435 status = "disabled"; 1436 }; 1437 1438 pcs_mdio1: mdio@8c07000 { 1439 compatible = "fsl,fman-memac-mdio"; 1440 reg = <0x0 0x8c07000 0x0 0x1000>; 1441 little-endian; 1442 #address-cells = <1>; 1443 #size-cells = <0>; 1444 status = "disabled"; 1445 1446 pcs1: ethernet-phy@0 { 1447 reg = <0>; 1448 }; 1449 }; 1450 1451 pcs_mdio2: mdio@8c0b000 { 1452 compatible = "fsl,fman-memac-mdio"; 1453 reg = <0x0 0x8c0b000 0x0 0x1000>; 1454 little-endian; 1455 #address-cells = <1>; 1456 #size-cells = <0>; 1457 status = "disabled"; 1458 1459 pcs2: ethernet-phy@0 { 1460 reg = <0>; 1461 }; 1462 }; 1463 1464 pcs_mdio3: mdio@8c0f000 { 1465 compatible = "fsl,fman-memac-mdio"; 1466 reg = <0x0 0x8c0f000 0x0 0x1000>; 1467 little-endian; 1468 #address-cells = <1>; 1469 #size-cells = <0>; 1470 status = "disabled"; 1471 1472 pcs3: ethernet-phy@0 { 1473 reg = <0>; 1474 }; 1475 }; 1476 1477 pcs_mdio4: mdio@8c13000 { 1478 compatible = "fsl,fman-memac-mdio"; 1479 reg = <0x0 0x8c13000 0x0 0x1000>; 1480 little-endian; 1481 #address-cells = <1>; 1482 #size-cells = <0>; 1483 status = "disabled"; 1484 1485 pcs4: ethernet-phy@0 { 1486 reg = <0>; 1487 }; 1488 }; 1489 1490 pcs_mdio5: mdio@8c17000 { 1491 compatible = "fsl,fman-memac-mdio"; 1492 reg = <0x0 0x8c17000 0x0 0x1000>; 1493 little-endian; 1494 #address-cells = <1>; 1495 #size-cells = <0>; 1496 status = "disabled"; 1497 1498 pcs5: ethernet-phy@0 { 1499 reg = <0>; 1500 }; 1501 }; 1502 1503 pcs_mdio6: mdio@8c1b000 { 1504 compatible = "fsl,fman-memac-mdio"; 1505 reg = <0x0 0x8c1b000 0x0 0x1000>; 1506 little-endian; 1507 #address-cells = <1>; 1508 #size-cells = <0>; 1509 status = "disabled"; 1510 1511 pcs6: ethernet-phy@0 { 1512 reg = <0>; 1513 }; 1514 }; 1515 1516 pcs_mdio7: mdio@8c1f000 { 1517 compatible = "fsl,fman-memac-mdio"; 1518 reg = <0x0 0x8c1f000 0x0 0x1000>; 1519 little-endian; 1520 #address-cells = <1>; 1521 #size-cells = <0>; 1522 status = "disabled"; 1523 1524 pcs7: ethernet-phy@0 { 1525 reg = <0>; 1526 }; 1527 }; 1528 1529 pcs_mdio8: mdio@8c23000 { 1530 compatible = "fsl,fman-memac-mdio"; 1531 reg = <0x0 0x8c23000 0x0 0x1000>; 1532 little-endian; 1533 #address-cells = <1>; 1534 #size-cells = <0>; 1535 status = "disabled"; 1536 1537 pcs8: ethernet-phy@0 { 1538 reg = <0>; 1539 }; 1540 }; 1541 1542 pcs_mdio9: mdio@8c27000 { 1543 compatible = "fsl,fman-memac-mdio"; 1544 reg = <0x0 0x8c27000 0x0 0x1000>; 1545 little-endian; 1546 #address-cells = <1>; 1547 #size-cells = <0>; 1548 status = "disabled"; 1549 1550 pcs9: ethernet-phy@0 { 1551 reg = <0>; 1552 }; 1553 }; 1554 1555 pcs_mdio10: mdio@8c2b000 { 1556 compatible = "fsl,fman-memac-mdio"; 1557 reg = <0x0 0x8c2b000 0x0 0x1000>; 1558 little-endian; 1559 #address-cells = <1>; 1560 #size-cells = <0>; 1561 status = "disabled"; 1562 1563 pcs10: ethernet-phy@0 { 1564 reg = <0>; 1565 }; 1566 }; 1567 1568 pcs_mdio11: mdio@8c2f000 { 1569 compatible = "fsl,fman-memac-mdio"; 1570 reg = <0x0 0x8c2f000 0x0 0x1000>; 1571 little-endian; 1572 #address-cells = <1>; 1573 #size-cells = <0>; 1574 status = "disabled"; 1575 1576 pcs11: ethernet-phy@0 { 1577 reg = <0>; 1578 }; 1579 }; 1580 1581 pcs_mdio12: mdio@8c33000 { 1582 compatible = "fsl,fman-memac-mdio"; 1583 reg = <0x0 0x8c33000 0x0 0x1000>; 1584 little-endian; 1585 #address-cells = <1>; 1586 #size-cells = <0>; 1587 status = "disabled"; 1588 1589 pcs12: ethernet-phy@0 { 1590 reg = <0>; 1591 }; 1592 }; 1593 1594 pcs_mdio13: mdio@8c37000 { 1595 compatible = "fsl,fman-memac-mdio"; 1596 reg = <0x0 0x8c37000 0x0 0x1000>; 1597 little-endian; 1598 #address-cells = <1>; 1599 #size-cells = <0>; 1600 status = "disabled"; 1601 1602 pcs13: ethernet-phy@0 { 1603 reg = <0>; 1604 }; 1605 }; 1606 1607 pcs_mdio14: mdio@8c3b000 { 1608 compatible = "fsl,fman-memac-mdio"; 1609 reg = <0x0 0x8c3b000 0x0 0x1000>; 1610 little-endian; 1611 #address-cells = <1>; 1612 #size-cells = <0>; 1613 status = "disabled"; 1614 1615 pcs14: ethernet-phy@0 { 1616 reg = <0>; 1617 }; 1618 }; 1619 1620 pcs_mdio15: mdio@8c3f000 { 1621 compatible = "fsl,fman-memac-mdio"; 1622 reg = <0x0 0x8c3f000 0x0 0x1000>; 1623 little-endian; 1624 #address-cells = <1>; 1625 #size-cells = <0>; 1626 status = "disabled"; 1627 1628 pcs15: ethernet-phy@0 { 1629 reg = <0>; 1630 }; 1631 }; 1632 1633 pcs_mdio16: mdio@8c43000 { 1634 compatible = "fsl,fman-memac-mdio"; 1635 reg = <0x0 0x8c43000 0x0 0x1000>; 1636 little-endian; 1637 #address-cells = <1>; 1638 #size-cells = <0>; 1639 status = "disabled"; 1640 1641 pcs16: ethernet-phy@0 { 1642 reg = <0>; 1643 }; 1644 }; 1645 1646 pcs_mdio17: mdio@8c47000 { 1647 compatible = "fsl,fman-memac-mdio"; 1648 reg = <0x0 0x8c47000 0x0 0x1000>; 1649 little-endian; 1650 #address-cells = <1>; 1651 #size-cells = <0>; 1652 status = "disabled"; 1653 1654 pcs17: ethernet-phy@0 { 1655 reg = <0>; 1656 }; 1657 }; 1658 1659 pcs_mdio18: mdio@8c4b000 { 1660 compatible = "fsl,fman-memac-mdio"; 1661 reg = <0x0 0x8c4b000 0x0 0x1000>; 1662 little-endian; 1663 #address-cells = <1>; 1664 #size-cells = <0>; 1665 status = "disabled"; 1666 1667 pcs18: ethernet-phy@0 { 1668 reg = <0>; 1669 }; 1670 }; 1671 1672 fsl_mc: fsl-mc@80c000000 { 1673 compatible = "fsl,qoriq-mc"; 1674 reg = <0x00000008 0x0c000000 0 0x40>, 1675 <0x00000000 0x08340000 0 0x40000>; 1676 msi-parent = <&its>; 1677 /* iommu-map property is fixed up by u-boot */ 1678 iommu-map = <0 &smmu 0 0>; 1679 dma-coherent; 1680 #address-cells = <3>; 1681 #size-cells = <1>; 1682 1683 /* 1684 * Region type 0x0 - MC portals 1685 * Region type 0x1 - QBMAN portals 1686 */ 1687 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 1688 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; 1689 1690 /* 1691 * Define the maximum number of MACs present on the SoC. 1692 */ 1693 dpmacs { 1694 #address-cells = <1>; 1695 #size-cells = <0>; 1696 1697 dpmac1: ethernet@1 { 1698 compatible = "fsl,qoriq-mc-dpmac"; 1699 reg = <0x1>; 1700 pcs-handle = <&pcs1>; 1701 }; 1702 1703 dpmac2: ethernet@2 { 1704 compatible = "fsl,qoriq-mc-dpmac"; 1705 reg = <0x2>; 1706 pcs-handle = <&pcs2>; 1707 }; 1708 1709 dpmac3: ethernet@3 { 1710 compatible = "fsl,qoriq-mc-dpmac"; 1711 reg = <0x3>; 1712 pcs-handle = <&pcs3>; 1713 }; 1714 1715 dpmac4: ethernet@4 { 1716 compatible = "fsl,qoriq-mc-dpmac"; 1717 reg = <0x4>; 1718 pcs-handle = <&pcs4>; 1719 }; 1720 1721 dpmac5: ethernet@5 { 1722 compatible = "fsl,qoriq-mc-dpmac"; 1723 reg = <0x5>; 1724 pcs-handle = <&pcs5>; 1725 }; 1726 1727 dpmac6: ethernet@6 { 1728 compatible = "fsl,qoriq-mc-dpmac"; 1729 reg = <0x6>; 1730 pcs-handle = <&pcs6>; 1731 }; 1732 1733 dpmac7: ethernet@7 { 1734 compatible = "fsl,qoriq-mc-dpmac"; 1735 reg = <0x7>; 1736 pcs-handle = <&pcs7>; 1737 }; 1738 1739 dpmac8: ethernet@8 { 1740 compatible = "fsl,qoriq-mc-dpmac"; 1741 reg = <0x8>; 1742 pcs-handle = <&pcs8>; 1743 }; 1744 1745 dpmac9: ethernet@9 { 1746 compatible = "fsl,qoriq-mc-dpmac"; 1747 reg = <0x9>; 1748 pcs-handle = <&pcs9>; 1749 }; 1750 1751 dpmac10: ethernet@a { 1752 compatible = "fsl,qoriq-mc-dpmac"; 1753 reg = <0xa>; 1754 pcs-handle = <&pcs10>; 1755 }; 1756 1757 dpmac11: ethernet@b { 1758 compatible = "fsl,qoriq-mc-dpmac"; 1759 reg = <0xb>; 1760 pcs-handle = <&pcs11>; 1761 }; 1762 1763 dpmac12: ethernet@c { 1764 compatible = "fsl,qoriq-mc-dpmac"; 1765 reg = <0xc>; 1766 pcs-handle = <&pcs12>; 1767 }; 1768 1769 dpmac13: ethernet@d { 1770 compatible = "fsl,qoriq-mc-dpmac"; 1771 reg = <0xd>; 1772 pcs-handle = <&pcs13>; 1773 }; 1774 1775 dpmac14: ethernet@e { 1776 compatible = "fsl,qoriq-mc-dpmac"; 1777 reg = <0xe>; 1778 pcs-handle = <&pcs14>; 1779 }; 1780 1781 dpmac15: ethernet@f { 1782 compatible = "fsl,qoriq-mc-dpmac"; 1783 reg = <0xf>; 1784 pcs-handle = <&pcs15>; 1785 }; 1786 1787 dpmac16: ethernet@10 { 1788 compatible = "fsl,qoriq-mc-dpmac"; 1789 reg = <0x10>; 1790 pcs-handle = <&pcs16>; 1791 }; 1792 1793 dpmac17: ethernet@11 { 1794 compatible = "fsl,qoriq-mc-dpmac"; 1795 reg = <0x11>; 1796 pcs-handle = <&pcs17>; 1797 }; 1798 1799 dpmac18: ethernet@12 { 1800 compatible = "fsl,qoriq-mc-dpmac"; 1801 reg = <0x12>; 1802 pcs-handle = <&pcs18>; 1803 }; 1804 }; 1805 }; 1806 }; 1807 1808 firmware { 1809 optee: optee { 1810 compatible = "linaro,optee-tz"; 1811 method = "smc"; 1812 status = "disabled"; 1813 }; 1814 }; 1815}; 1816