1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2019 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/irq.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/gpio/meson-a1-gpio.h> 9 10/ { 11 compatible = "amlogic,a1"; 12 13 interrupt-parent = <&gic>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 cpus { 18 #address-cells = <2>; 19 #size-cells = <0>; 20 21 cpu0: cpu@0 { 22 device_type = "cpu"; 23 compatible = "arm,cortex-a35"; 24 reg = <0x0 0x0>; 25 enable-method = "psci"; 26 next-level-cache = <&l2>; 27 }; 28 29 cpu1: cpu@1 { 30 device_type = "cpu"; 31 compatible = "arm,cortex-a35"; 32 reg = <0x0 0x1>; 33 enable-method = "psci"; 34 next-level-cache = <&l2>; 35 }; 36 37 l2: l2-cache0 { 38 compatible = "cache"; 39 cache-level = <2>; 40 cache-unified; 41 }; 42 }; 43 44 psci { 45 compatible = "arm,psci-1.0"; 46 method = "smc"; 47 }; 48 49 reserved-memory { 50 #address-cells = <2>; 51 #size-cells = <2>; 52 ranges; 53 54 linux,cma { 55 compatible = "shared-dma-pool"; 56 reusable; 57 size = <0x0 0x800000>; 58 alignment = <0x0 0x400000>; 59 linux,cma-default; 60 }; 61 }; 62 63 sm: secure-monitor { 64 compatible = "amlogic,meson-gxbb-sm"; 65 66 pwrc: power-controller { 67 compatible = "amlogic,meson-a1-pwrc"; 68 #power-domain-cells = <1>; 69 status = "okay"; 70 }; 71 }; 72 73 soc { 74 compatible = "simple-bus"; 75 #address-cells = <2>; 76 #size-cells = <2>; 77 ranges; 78 79 apb: bus@fe000000 { 80 compatible = "simple-bus"; 81 reg = <0x0 0xfe000000 0x0 0x1000000>; 82 #address-cells = <2>; 83 #size-cells = <2>; 84 ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x1000000>; 85 86 87 reset: reset-controller@0 { 88 compatible = "amlogic,meson-a1-reset"; 89 reg = <0x0 0x0 0x0 0x8c>; 90 #reset-cells = <1>; 91 }; 92 93 periphs_pinctrl: pinctrl@400 { 94 compatible = "amlogic,meson-a1-periphs-pinctrl"; 95 #address-cells = <2>; 96 #size-cells = <2>; 97 ranges; 98 99 gpio: bank@400 { 100 reg = <0x0 0x0400 0x0 0x003c>, 101 <0x0 0x0480 0x0 0x0118>; 102 reg-names = "mux", "gpio"; 103 gpio-controller; 104 #gpio-cells = <2>; 105 gpio-ranges = <&periphs_pinctrl 0 0 62>; 106 }; 107 108 }; 109 110 uart_AO: serial@1c00 { 111 compatible = "amlogic,meson-a1-uart", 112 "amlogic,meson-ao-uart"; 113 reg = <0x0 0x1c00 0x0 0x18>; 114 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; 115 clocks = <&xtal>, <&xtal>, <&xtal>; 116 clock-names = "xtal", "pclk", "baud"; 117 status = "disabled"; 118 }; 119 120 uart_AO_B: serial@2000 { 121 compatible = "amlogic,meson-a1-uart", 122 "amlogic,meson-ao-uart"; 123 reg = <0x0 0x2000 0x0 0x18>; 124 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 125 clocks = <&xtal>, <&xtal>, <&xtal>; 126 clock-names = "xtal", "pclk", "baud"; 127 status = "disabled"; 128 }; 129 130 gpio_intc: interrupt-controller@0440 { 131 compatible = "amlogic,meson-a1-gpio-intc", 132 "amlogic,meson-gpio-intc"; 133 reg = <0x0 0x0440 0x0 0x14>; 134 interrupt-controller; 135 #interrupt-cells = <2>; 136 amlogic,channel-interrupts = 137 <49 50 51 52 53 54 55 56>; 138 }; 139 }; 140 141 gic: interrupt-controller@ff901000 { 142 compatible = "arm,gic-400"; 143 reg = <0x0 0xff901000 0x0 0x1000>, 144 <0x0 0xff902000 0x0 0x2000>, 145 <0x0 0xff904000 0x0 0x2000>, 146 <0x0 0xff906000 0x0 0x2000>; 147 interrupt-controller; 148 interrupts = <GIC_PPI 9 149 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 150 #interrupt-cells = <3>; 151 #address-cells = <0>; 152 }; 153 }; 154 155 timer { 156 compatible = "arm,armv8-timer"; 157 interrupts = <GIC_PPI 13 158 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 159 <GIC_PPI 14 160 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 161 <GIC_PPI 11 162 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 163 <GIC_PPI 10 164 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 165 }; 166 167 xtal: xtal-clk { 168 compatible = "fixed-clock"; 169 clock-frequency = <24000000>; 170 clock-output-names = "xtal"; 171 #clock-cells = <0>; 172 }; 173}; 174