1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * r8a7779 processor support 4 * 5 * Copyright (C) 2011, 2013 Renesas Solutions Corp. 6 * Copyright (C) 2011 Magnus Damm 7 * Copyright (C) 2013 Cogent Embedded, Inc. 8 */ 9 #include <linux/init.h> 10 #include <linux/irqchip.h> 11 12 #include <asm/mach/arch.h> 13 #include <asm/mach/map.h> 14 15 #include "common.h" 16 #include "r8a7779.h" 17 18 #define HPBREG_BASE 0xfe700000 19 20 /* IRQ */ 21 #define INT2SMSKCR0 0x822a0 /* Interrupt Submask Clear Register 0 */ 22 #define INT2SMSKCR1 0x822a4 /* Interrupt Submask Clear Register 1 */ 23 #define INT2SMSKCR2 0x822a8 /* Interrupt Submask Clear Register 2 */ 24 #define INT2SMSKCR3 0x822ac /* Interrupt Submask Clear Register 3 */ 25 #define INT2SMSKCR4 0x822b0 /* Interrupt Submask Clear Register 4 */ 26 27 #define INT2NTSR0 0x00060 /* Interrupt Notification Select Register 0 */ 28 #define INT2NTSR1 0x00064 /* Interrupt Notification Select Register 1 */ 29 30 static void __init r8a7779_init_irq_dt(void) 31 { 32 void __iomem *base = ioremap(HPBREG_BASE, 0x00100000); 33 34 irqchip_init(); 35 36 /* route all interrupts to ARM */ 37 writel(0xffffffff, base + INT2NTSR0); 38 writel(0x3fffffff, base + INT2NTSR1); 39 40 /* unmask all known interrupts in INTCS2 */ 41 writel(0xfffffff0, base + INT2SMSKCR0); 42 writel(0xfff7ffff, base + INT2SMSKCR1); 43 writel(0xfffbffdf, base + INT2SMSKCR2); 44 writel(0xbffffffc, base + INT2SMSKCR3); 45 writel(0x003fee3f, base + INT2SMSKCR4); 46 47 iounmap(base); 48 } 49 50 static const char *const r8a7779_compat_dt[] __initconst = { 51 "renesas,r8a7779", 52 NULL, 53 }; 54 55 DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)") 56 .smp = smp_ops(r8a7779_smp_ops), 57 .init_irq = r8a7779_init_irq_dt, 58 .init_late = shmobile_init_late, 59 .dt_compat = r8a7779_compat_dt, 60 MACHINE_END 61