1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm SuperSpeed DWC3 USB SoC controller 8 9maintainers: 10 - Manu Gautam <mgautam@codeaurora.org> 11 12properties: 13 compatible: 14 items: 15 - enum: 16 - qcom,ipq4019-dwc3 17 - qcom,ipq6018-dwc3 18 - qcom,ipq8064-dwc3 19 - qcom,msm8996-dwc3 20 - qcom,msm8998-dwc3 21 - qcom,sc7180-dwc3 22 - qcom,sc7280-dwc3 23 - qcom,sdm660-dwc3 24 - qcom,sdm845-dwc3 25 - qcom,sdx55-dwc3 26 - qcom,sm4250-dwc3 27 - qcom,sm6115-dwc3 28 - qcom,sm6350-dwc3 29 - qcom,sm8150-dwc3 30 - qcom,sm8250-dwc3 31 - qcom,sm8350-dwc3 32 - qcom,sm8450-dwc3 33 - const: qcom,dwc3 34 35 reg: 36 description: Offset and length of register set for QSCRATCH wrapper 37 maxItems: 1 38 39 "#address-cells": 40 enum: [ 1, 2 ] 41 42 "#size-cells": 43 enum: [ 1, 2 ] 44 45 ranges: true 46 47 power-domains: 48 description: specifies a phandle to PM domain provider node 49 maxItems: 1 50 51 clocks: 52 description: 53 A list of phandle and clock-specifier pairs for the clocks 54 listed in clock-names. 55 items: 56 - description: System Config NOC clock. 57 - description: Master/Core clock, has to be >= 125 MHz 58 for SS operation and >= 60MHz for HS operation. 59 - description: System bus AXI clock. 60 - description: Mock utmi clock needed for ITP/SOF generation 61 in host mode. Its frequency should be 19.2MHz. 62 - description: Sleep clock, used for wakeup when 63 USB3 core goes into low power mode (U3). 64 65 clock-names: 66 items: 67 - const: cfg_noc 68 - const: core 69 - const: iface 70 - const: mock_utmi 71 - const: sleep 72 73 assigned-clocks: 74 items: 75 - description: Phandle and clock specifier of MOCK_UTMI_CLK. 76 - description: Phandle and clock specifoer of MASTER_CLK. 77 78 assigned-clock-rates: 79 items: 80 - description: Must be 19.2MHz (19200000). 81 - description: Must be >= 60 MHz in HS mode, >= 125 MHz in SS mode. 82 resets: 83 maxItems: 1 84 85 interconnects: 86 maxItems: 2 87 88 interconnect-names: 89 items: 90 - const: usb-ddr 91 - const: apps-usb 92 93 interrupts: 94 items: 95 - description: The interrupt that is asserted 96 when a wakeup event is received on USB2 bus. 97 - description: The interrupt that is asserted 98 when a wakeup event is received on USB3 bus. 99 - description: Wakeup event on DM line. 100 - description: Wakeup event on DP line. 101 102 interrupt-names: 103 items: 104 - const: hs_phy_irq 105 - const: ss_phy_irq 106 - const: dm_hs_phy_irq 107 - const: dp_hs_phy_irq 108 109 qcom,select-utmi-as-pipe-clk: 110 description: 111 If present, disable USB3 pipe_clk requirement. 112 Used when dwc3 operates without SSPHY and only 113 HS/FS/LS modes are supported. 114 type: boolean 115 116# Required child node: 117 118patternProperties: 119 "^usb@[0-9a-f]+$": 120 $ref: snps,dwc3.yaml# 121 122required: 123 - compatible 124 - reg 125 - "#address-cells" 126 - "#size-cells" 127 - ranges 128 - power-domains 129 - clocks 130 - clock-names 131 - interrupts 132 - interrupt-names 133 134additionalProperties: false 135 136examples: 137 - | 138 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 139 #include <dt-bindings/interrupt-controller/arm-gic.h> 140 #include <dt-bindings/interrupt-controller/irq.h> 141 soc { 142 #address-cells = <2>; 143 #size-cells = <2>; 144 145 usb@a6f8800 { 146 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 147 reg = <0 0x0a6f8800 0 0x400>; 148 149 #address-cells = <2>; 150 #size-cells = <2>; 151 ranges; 152 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 153 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 154 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 155 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 156 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 157 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 158 "sleep"; 159 160 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 161 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 162 assigned-clock-rates = <19200000>, <150000000>; 163 164 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 165 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 167 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 168 interrupt-names = "hs_phy_irq", "ss_phy_irq", 169 "dm_hs_phy_irq", "dp_hs_phy_irq"; 170 171 power-domains = <&gcc USB30_PRIM_GDSC>; 172 173 resets = <&gcc GCC_USB30_PRIM_BCR>; 174 175 usb@a600000 { 176 compatible = "snps,dwc3"; 177 reg = <0 0x0a600000 0 0xcd00>; 178 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 179 iommus = <&apps_smmu 0x740 0>; 180 snps,dis_u2_susphy_quirk; 181 snps,dis_enblslpm_quirk; 182 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 183 phy-names = "usb2-phy", "usb3-phy"; 184 }; 185 }; 186 }; 187