xref: /linux/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.yaml (revision 58f6259b7a08f8d47d4629609703d358b042f0fd) 
1# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/serial/qcom,msm-uartdm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm MSM Serial UARTDM
8
9maintainers:
10  - Andy Gross <agross@kernel.org>
11  - Bjorn Andersson <bjorn.andersson@linaro.org>
12  - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
13
14description: |
15  The MSM serial UARTDM hardware is designed for high-speed use cases where the
16  transmit and/or receive channels can be offloaded to a dma-engine. From a
17  software perspective it's mostly compatible with the MSM serial UART except
18  that it supports reading and writing multiple characters at a time.
19
20  Note:: Aliases may be defined to ensure the correct ordering of the UARTs.
21  The alias serialN will result in the UART being assigned port N.  If any
22  serialN alias exists, then an alias must exist for each enabled UART.  The
23  serialN aliases should be in a .dts file instead of in a .dtsi file.
24
25properties:
26  compatible:
27    items:
28      - enum:
29          - qcom,msm-uartdm-v1.1
30          - qcom,msm-uartdm-v1.2
31          - qcom,msm-uartdm-v1.3
32          - qcom,msm-uartdm-v1.4
33      - const: qcom,msm-uartdm
34
35  clocks:
36    maxItems: 2
37
38  clock-names:
39    items:
40      - const: core
41      - const: iface
42
43  dmas:
44    maxItems: 2
45
46  dma-names:
47    items:
48      - const: tx
49      - const: rx
50
51  interrupts:
52    maxItems: 1
53
54  qcom,rx-crci:
55    $ref: /schemas/types.yaml#/definitions/uint32
56    description:
57      Identificator for Client Rate Control Interface to be used with RX DMA
58      channel. Required when using DMA for reception with UARTDM v1.3 and
59      below.
60
61  qcom,tx-crci:
62    $ref: /schemas/types.yaml#/definitions/uint32
63    description:
64      Identificator for Client Rate Control Interface to be used with TX DMA
65      channel. Required when using DMA for transmission with UARTDM v1.3 and
66      below.
67
68  reg:
69    minItems: 1
70    items:
71      - description: Main control registers
72      - description: An optional second register location shall specify the GSBI control region.
73
74required:
75  - compatible
76  - clock-names
77  - clocks
78  - interrupts
79  - reg
80
81unevaluatedProperties: false
82
83allOf:
84  - $ref: /schemas/serial/serial.yaml#
85
86  - if:
87      properties:
88        compatible:
89          contains:
90            const: qcom,msm-uartdm-v1.3
91    then:
92      properties:
93        reg:
94          minItems: 2
95    else:
96      properties:
97        reg:
98          maxItems: 1
99
100examples:
101  - |
102    #include <dt-bindings/interrupt-controller/arm-gic.h>
103
104    serial@f991e000 {
105        compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
106        reg = <0xf991e000 0x1000>;
107        interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
108        clocks = <&blsp1_uart2_apps_cxc>, <&blsp1_ahb_cxc>;
109        clock-names = "core", "iface";
110        dmas = <&dma0 0>, <&dma0 1>;
111        dma-names = "tx", "rx";
112    };
113