1# SPDX-License-Identifier: (GPL-2.0 OR MIT) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/riscv/cpus.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: RISC-V CPUs 8 9maintainers: 10 - Paul Walmsley <paul.walmsley@sifive.com> 11 - Palmer Dabbelt <palmer@sifive.com> 12 - Conor Dooley <conor@kernel.org> 13 14description: | 15 This document uses some terminology common to the RISC-V community 16 that is not widely used, the definitions of which are listed here: 17 18 hart: A hardware execution context, which contains all the state 19 mandated by the RISC-V ISA: a PC and some registers. This 20 terminology is designed to disambiguate software's view of execution 21 contexts from any particular microarchitectural implementation 22 strategy. For example, an Intel laptop containing one socket with 23 two cores, each of which has two hyperthreads, could be described as 24 having four harts. 25 26properties: 27 compatible: 28 oneOf: 29 - items: 30 - enum: 31 - andestech,ax45mp 32 - canaan,k210 33 - sifive,bullet0 34 - sifive,e5 35 - sifive,e7 36 - sifive,e71 37 - sifive,rocket0 38 - sifive,u5 39 - sifive,u54 40 - sifive,u7 41 - sifive,u74 42 - sifive,u74-mc 43 - thead,c906 44 - thead,c910 45 - const: riscv 46 - items: 47 - enum: 48 - sifive,e51 49 - sifive,u54-mc 50 - const: sifive,rocket0 51 - const: riscv 52 - const: riscv # Simulator only 53 description: 54 Identifies that the hart uses the RISC-V instruction set 55 and identifies the type of the hart. 56 57 mmu-type: 58 description: 59 Identifies the MMU address translation mode used on this 60 hart. These values originate from the RISC-V Privileged 61 Specification document, available from 62 https://riscv.org/specifications/ 63 $ref: "/schemas/types.yaml#/definitions/string" 64 enum: 65 - riscv,sv32 66 - riscv,sv39 67 - riscv,sv48 68 - riscv,none 69 70 riscv,cbom-block-size: 71 $ref: /schemas/types.yaml#/definitions/uint32 72 description: 73 The blocksize in bytes for the Zicbom cache operations. 74 75 riscv,isa: 76 description: 77 Identifies the specific RISC-V instruction set architecture 78 supported by the hart. These are documented in the RISC-V 79 User-Level ISA document, available from 80 https://riscv.org/specifications/ 81 82 While the isa strings in ISA specification are case 83 insensitive, letters in the riscv,isa string must be all 84 lowercase to simplify parsing. 85 $ref: "/schemas/types.yaml#/definitions/string" 86 pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:_[hsxz](?:[a-z])+)*$ 87 88 # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here 89 timebase-frequency: false 90 91 interrupt-controller: 92 type: object 93 description: Describes the CPU's local interrupt controller 94 95 properties: 96 '#interrupt-cells': 97 const: 1 98 99 compatible: 100 const: riscv,cpu-intc 101 102 interrupt-controller: true 103 104 required: 105 - '#interrupt-cells' 106 - compatible 107 - interrupt-controller 108 109 cpu-idle-states: 110 $ref: '/schemas/types.yaml#/definitions/phandle-array' 111 items: 112 maxItems: 1 113 description: | 114 List of phandles to idle state nodes supported 115 by this hart (see ./idle-states.yaml). 116 117required: 118 - riscv,isa 119 - interrupt-controller 120 121additionalProperties: true 122 123examples: 124 - | 125 // Example 1: SiFive Freedom U540G Development Kit 126 cpus { 127 #address-cells = <1>; 128 #size-cells = <0>; 129 timebase-frequency = <1000000>; 130 cpu@0 { 131 clock-frequency = <0>; 132 compatible = "sifive,rocket0", "riscv"; 133 device_type = "cpu"; 134 i-cache-block-size = <64>; 135 i-cache-sets = <128>; 136 i-cache-size = <16384>; 137 reg = <0>; 138 riscv,isa = "rv64imac"; 139 cpu_intc0: interrupt-controller { 140 #interrupt-cells = <1>; 141 compatible = "riscv,cpu-intc"; 142 interrupt-controller; 143 }; 144 }; 145 cpu@1 { 146 clock-frequency = <0>; 147 compatible = "sifive,rocket0", "riscv"; 148 d-cache-block-size = <64>; 149 d-cache-sets = <64>; 150 d-cache-size = <32768>; 151 d-tlb-sets = <1>; 152 d-tlb-size = <32>; 153 device_type = "cpu"; 154 i-cache-block-size = <64>; 155 i-cache-sets = <64>; 156 i-cache-size = <32768>; 157 i-tlb-sets = <1>; 158 i-tlb-size = <32>; 159 mmu-type = "riscv,sv39"; 160 reg = <1>; 161 riscv,isa = "rv64imafdc"; 162 tlb-split; 163 cpu_intc1: interrupt-controller { 164 #interrupt-cells = <1>; 165 compatible = "riscv,cpu-intc"; 166 interrupt-controller; 167 }; 168 }; 169 }; 170 171 - | 172 // Example 2: Spike ISA Simulator with 1 Hart 173 cpus { 174 #address-cells = <1>; 175 #size-cells = <0>; 176 cpu@0 { 177 device_type = "cpu"; 178 reg = <0>; 179 compatible = "riscv"; 180 riscv,isa = "rv64imafdc"; 181 mmu-type = "riscv,sv48"; 182 interrupt-controller { 183 #interrupt-cells = <1>; 184 interrupt-controller; 185 compatible = "riscv,cpu-intc"; 186 }; 187 }; 188 }; 189... 190