xref: /linux/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.yaml (revision ac84bac4062e7fc24f5e2c61c6a414b2a00a29ad) 
1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pwm/renesas,tpu-pwm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas R-Car Timer Pulse Unit PWM Controller
8
9maintainers:
10  - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
11
12properties:
13  compatible:
14    items:
15      - enum:
16          - renesas,tpu-r8a73a4   # R-Mobile APE6
17          - renesas,tpu-r8a7740   # R-Mobile A1
18          - renesas,tpu-r8a7743   # RZ/G1M
19          - renesas,tpu-r8a7744   # RZ/G1N
20          - renesas,tpu-r8a7745   # RZ/G1E
21          - renesas,tpu-r8a7790   # R-Car H2
22          - renesas,tpu-r8a7791   # R-Car M2-W
23          - renesas,tpu-r8a7792   # R-Car V2H
24          - renesas,tpu-r8a7793   # R-Car M2-N
25          - renesas,tpu-r8a7794   # R-Car E2
26          - renesas,tpu-r8a7795   # R-Car H3
27          - renesas,tpu-r8a7796   # R-Car M3-W
28          - renesas,tpu-r8a77965  # R-Car M3-N
29          - renesas,tpu-r8a77970  # R-Car V3M
30          - renesas,tpu-r8a77980  # R-Car V3H
31      - const: renesas,tpu
32
33  reg:
34    # Base address and length of each memory resource used by the PWM
35    # controller hardware module.
36    maxItems: 1
37
38  interrupts:
39    maxItems: 1
40
41  '#pwm-cells':
42    # should be 3. See pwm.yaml in this directory for a description of
43    # the cells format. The only third cell flag supported by this binding is
44    # PWM_POLARITY_INVERTED.
45    const: 3
46
47  clocks:
48    maxItems: 1
49
50  power-domains:
51    maxItems: 1
52
53  resets:
54    maxItems: 1
55
56required:
57  - compatible
58  - reg
59  - '#pwm-cells'
60
61additionalProperties: false
62
63examples:
64  - |
65    #include <dt-bindings/clock/r8a7740-clock.h>
66
67    tpu: pwm@e6600000 {
68        compatible = "renesas,tpu-r8a7740", "renesas,tpu";
69        reg = <0xe6600000 0x148>;
70        clocks = <&mstp3_clks R8A7740_CLK_TPU0>;
71        power-domains = <&pd_a3sp>;
72        #pwm-cells = <3>;
73    };
74