xref: /linux/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml (revision 42874e4eb35bdfc54f8514685e50434098ba4f6c) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm QMP USB4-USB3-DP PHY controller (SC8280XP)
8
9maintainers:
10  - Vinod Koul <vkoul@kernel.org>
11
12description:
13  The QMP PHY controller supports physical layer functionality for a number of
14  controllers on Qualcomm chipsets, such as, PCIe, UFS and USB.
15
16properties:
17  compatible:
18    enum:
19      - qcom,sc7180-qmp-usb3-dp-phy
20      - qcom,sc7280-qmp-usb3-dp-phy
21      - qcom,sc8180x-qmp-usb3-dp-phy
22      - qcom,sc8280xp-qmp-usb43dp-phy
23      - qcom,sdm845-qmp-usb3-dp-phy
24      - qcom,sm6350-qmp-usb3-dp-phy
25      - qcom,sm8150-qmp-usb3-dp-phy
26      - qcom,sm8250-qmp-usb3-dp-phy
27      - qcom,sm8350-qmp-usb3-dp-phy
28      - qcom,sm8450-qmp-usb3-dp-phy
29      - qcom,sm8550-qmp-usb3-dp-phy
30
31  reg:
32    maxItems: 1
33
34  clocks:
35    minItems: 4
36    maxItems: 5
37
38  clock-names:
39    minItems: 4
40    items:
41      - const: aux
42      - const: ref
43      - const: com_aux
44      - const: usb3_pipe
45      - const: cfg_ahb
46
47  power-domains:
48    maxItems: 1
49
50  resets:
51    maxItems: 2
52
53  reset-names:
54    items:
55      - const: phy
56      - const: common
57
58  vdda-phy-supply: true
59
60  vdda-pll-supply: true
61
62  "#clock-cells":
63    const: 1
64    description:
65      See include/dt-bindings/dt-bindings/phy/phy-qcom-qmp.h
66
67  "#phy-cells":
68    const: 1
69    description:
70      See include/dt-bindings/dt-bindings/phy/phy-qcom-qmp.h
71
72  orientation-switch:
73    description:
74      Flag the PHY as possible handler of USB Type-C orientation switching
75    type: boolean
76
77  ports:
78    $ref: /schemas/graph.yaml#/properties/ports
79    properties:
80      port@0:
81        $ref: /schemas/graph.yaml#/properties/port
82        description: Output endpoint of the PHY
83
84      port@1:
85        $ref: /schemas/graph.yaml#/properties/port
86        description: Incoming endpoint from the USB controller
87
88      port@2:
89        $ref: /schemas/graph.yaml#/properties/port
90        description: Incoming endpoint from the DisplayPort controller
91
92required:
93  - compatible
94  - reg
95  - clocks
96  - clock-names
97  - resets
98  - reset-names
99  - vdda-phy-supply
100  - vdda-pll-supply
101  - "#clock-cells"
102  - "#phy-cells"
103
104allOf:
105  - if:
106      properties:
107        compatible:
108          enum:
109            - qcom,sc7180-qmp-usb3-dp-phy
110            - qcom,sdm845-qmp-usb3-dp-phy
111    then:
112      properties:
113        clocks:
114          maxItems: 5
115        clock-names:
116          maxItems: 5
117    else:
118      properties:
119        clocks:
120          maxItems: 4
121        clock-names:
122          maxItems: 4
123
124  - if:
125      properties:
126        compatible:
127          enum:
128            - qcom,sc8280xp-qmp-usb43dp-phy
129            - qcom,sm6350-qmp-usb3-dp-phy
130            - qcom,sm8550-qmp-usb3-dp-phy
131    then:
132      required:
133        - power-domains
134    else:
135      properties:
136        power-domains: false
137
138additionalProperties: false
139
140examples:
141  - |
142    #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
143
144    phy@88eb000 {
145      compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
146      reg = <0x088eb000 0x4000>;
147
148      clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
149               <&gcc GCC_USB4_EUD_CLKREF_CLK>,
150               <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
151               <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
152      clock-names = "aux", "ref", "com_aux", "usb3_pipe";
153
154      power-domains = <&gcc USB30_PRIM_GDSC>;
155
156      resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
157               <&gcc GCC_USB4_DP_PHY_PRIM_BCR>;
158      reset-names = "phy", "common";
159
160      vdda-phy-supply = <&vreg_l9d>;
161      vdda-pll-supply = <&vreg_l4d>;
162
163      orientation-switch;
164
165      #clock-cells = <1>;
166      #phy-cells = <1>;
167
168      ports {
169          #address-cells = <1>;
170          #size-cells = <0>;
171
172          port@0 {
173              reg = <0>;
174
175              endpoint {
176                  remote-endpoint = <&typec_connector_ss>;
177              };
178          };
179
180          port@1 {
181              reg = <1>;
182
183              endpoint {
184                  remote-endpoint = <&dwc3_ss_out>;
185              };
186          };
187
188          port@2 {
189              reg = <2>;
190
191              endpoint {
192                  remote-endpoint = <&mdss_dp_out>;
193              };
194          };
195      };
196    };
197