xref: /linux/Documentation/devicetree/bindings/pci/ti,am65-pci-ep.yaml (revision cbdb1f163af2bb90d01be1f0263df1d8d5c9d9d3) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/pci/ti,am65-pci-ep.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: TI AM65 PCI Endpoint
9
10maintainers:
11  - Kishon Vijay Abraham I <kishon@ti.com>
12
13allOf:
14  - $ref: pci-ep.yaml#
15
16properties:
17  compatible:
18    enum:
19      - ti,am654-pcie-ep
20
21  reg:
22    maxItems: 4
23
24  reg-names:
25    items:
26      - const: app
27      - const: dbics
28      - const: addr_space
29      - const: atu
30
31  power-domains:
32    maxItems: 1
33
34  ti,syscon-pcie-mode:
35    $ref: /schemas/types.yaml#/definitions/phandle-array
36    items:
37      - items:
38          - description: Phandle to the SYSCON entry
39          - description: pcie_ctrl register offset within SYSCON
40    description: Phandle to the SYSCON entry required for configuring PCIe in RC or EP mode.
41
42  interrupts:
43    minItems: 1
44
45  dma-coherent: true
46
47required:
48  - compatible
49  - reg
50  - reg-names
51  - max-link-speed
52  - power-domains
53  - ti,syscon-pcie-mode
54  - dma-coherent
55
56unevaluatedProperties: false
57
58examples:
59  - |
60    #include <dt-bindings/interrupt-controller/arm-gic.h>
61    #include <dt-bindings/interrupt-controller/irq.h>
62    #include <dt-bindings/soc/ti,sci_pm_domain.h>
63
64    pcie0_ep: pcie-ep@5500000 {
65        compatible = "ti,am654-pcie-ep";
66        reg =  <0x5500000 0x1000>,
67               <0x5501000 0x1000>,
68               <0x10000000 0x8000000>,
69               <0x5506000 0x1000>;
70        reg-names = "app", "dbics", "addr_space", "atu";
71        power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
72        ti,syscon-pcie-mode = <&scm_conf 0x4060>;
73        max-link-speed = <2>;
74        dma-coherent;
75        interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
76    };
77