xref: /linux/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml (revision cbdb1f163af2bb90d01be1f0263df1d8d5c9d9d3) 
1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/hisilicon,kirin-pcie.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: HiSilicon Kirin SoCs PCIe host DT description
8
9maintainers:
10  - Xiaowei Song <songxiaowei@hisilicon.com>
11  - Binghui Wang <wangbinghui@hisilicon.com>
12
13description: |
14  Kirin PCIe host controller is based on the Synopsys DesignWare PCI core.
15  It shares common functions with the PCIe DesignWare core driver and
16  inherits common properties defined in
17  Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
18
19allOf:
20  - $ref: /schemas/pci/snps,dw-pcie.yaml#
21
22properties:
23  compatible:
24    contains:
25      enum:
26        - hisilicon,kirin960-pcie
27        - hisilicon,kirin970-pcie
28
29  reg:
30    description: |
31      Should contain dbi, apb, config registers location and length.
32      For hisilicon,kirin960-pcie, it should also contain phy.
33    minItems: 3
34    maxItems: 4
35
36  reg-names:
37    minItems: 3
38    maxItems: 4
39
40  clocks: true
41
42  clock-names:
43    items:
44      - const: pcie_phy_ref
45      - const: pcie_aux
46      - const: pcie_apb_phy
47      - const: pcie_apb_sys
48      - const: pcie_aclk
49
50  phys:
51    maxItems: 1
52
53  hisilicon,clken-gpios:
54    description: |
55      Clock input enablement GPIOs from PCI devices like Ethernet, M.2 and
56      mini-PCIe slots.
57
58required:
59  - compatible
60  - reg
61  - reg-names
62
63unevaluatedProperties: false
64
65examples:
66  - |
67    #include <dt-bindings/interrupt-controller/arm-gic.h>
68    #include <dt-bindings/clock/hi3660-clock.h>
69    #include <dt-bindings/clock/hi3670-clock.h>
70
71    soc {
72      #address-cells = <2>;
73      #size-cells = <2>;
74
75      pcie@f4000000 {
76        compatible = "hisilicon,kirin960-pcie";
77        reg = <0x0 0xf4000000 0x0 0x1000>,
78              <0x0 0xff3fe000 0x0 0x1000>,
79              <0x0 0xf3f20000 0x0 0x40000>,
80              <0x0 0xf5000000 0x0 0x2000>;
81        reg-names = "dbi", "apb", "phy", "config";
82        bus-range = <0x0  0xff>;
83        #address-cells = <3>;
84        #size-cells = <2>;
85        device_type = "pci";
86        ranges = <0x02000000 0x0 0x00000000
87                  0x0 0xf6000000
88                  0x0 0x02000000>;
89        num-lanes = <1>;
90        #interrupt-cells = <1>;
91        interrupts = <0 283 4>;
92        interrupt-names = "msi";
93        interrupt-map-mask = <0xf800 0 0 7>;
94        interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
95                        <0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
96                        <0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
97                        <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
98        clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
99                 <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
100                 <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
101                 <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
102                 <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
103        clock-names = "pcie_phy_ref", "pcie_aux", "pcie_apb_phy",
104                      "pcie_apb_sys", "pcie_aclk";
105      };
106
107      pcie@f5000000 {
108        compatible = "hisilicon,kirin970-pcie";
109        reg = <0x0 0xf4000000 0x0 0x1000000>,
110              <0x0 0xfc180000 0x0 0x1000>,
111              <0x0 0xf5000000 0x0 0x2000>;
112        reg-names = "dbi", "apb", "config";
113        bus-range = <0x0  0xff>;
114        #address-cells = <3>;
115        #size-cells = <2>;
116        device_type = "pci";
117        phys = <&pcie_phy>;
118        ranges = <0x02000000 0x0 0x00000000
119                  0x0 0xf6000000
120                  0x0 0x02000000>;
121        num-lanes = <1>;
122        #interrupt-cells = <1>;
123        interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>;
124        interrupt-names = "msi";
125        interrupt-map-mask = <0 0 0 7>;
126        interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
127                        <0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
128                        <0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
129                        <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
130        reset-gpios = <&gpio7 0 0>;
131        hisilicon,clken-gpios = <&gpio27 3 0>, <&gpio17 0 0>, <&gpio20 6 0>;
132        pcie@0,0 { // Lane 0: PCIe switch: Bus 1, Device 0
133          reg = <0 0 0 0 0>;
134          compatible = "pciclass,0604";
135          device_type = "pci";
136          #address-cells = <3>;
137          #size-cells = <2>;
138          ranges;
139
140          pcie@0,0 { // Lane 0: upstream
141            reg = <0 0 0 0 0>;
142            compatible = "pciclass,0604";
143            device_type = "pci";
144            #address-cells = <3>;
145            #size-cells = <2>;
146            ranges;
147
148            pcie@1,0 { // Lane 4: M.2
149              reg = <0x0800 0 0 0 0>;
150              compatible = "pciclass,0604";
151              device_type = "pci";
152              reset-gpios = <&gpio3 1 0>;
153              #address-cells = <3>;
154              #size-cells = <2>;
155              ranges;
156            };
157
158            pcie@5,0 { // Lane 5: Mini PCIe
159              reg = <0x2800 0 0 0 0>;
160              compatible = "pciclass,0604";
161              device_type = "pci";
162              reset-gpios = <&gpio27 4 0 >;
163              #address-cells = <3>;
164              #size-cells = <2>;
165              ranges;
166            };
167
168            pcie@7,0 { // Lane 6: Ethernet
169              reg = <0x03800 0 0 0 0>;
170              compatible = "pciclass,0604";
171              device_type = "pci";
172              reset-gpios = <&gpio25 2 0 >;
173              #address-cells = <3>;
174              #size-cells = <2>;
175              ranges;
176            };
177          };
178        };
179      };
180    };
181