1* STMicroelectronics 10/100/1000 Ethernet driver (GMAC) 2 3Required properties: 4- compatible: Should be "snps,dwmac-<ip_version>" "snps,dwmac" 5 For backwards compatibility: "st,spear600-gmac" is also supported. 6- reg: Address and length of the register set for the device 7- interrupt-parent: Should be the phandle for the interrupt controller 8 that services interrupts for this device 9- interrupts: Should contain the STMMAC interrupts 10- interrupt-names: Should contain the interrupt names "macirq" 11 "eth_wake_irq" if this interrupt is supported in the "interrupts" 12 property 13- phy-mode: See ethernet.txt file in the same directory. 14- snps,reset-gpio gpio number for phy reset. 15- snps,reset-active-low boolean flag to indicate if phy reset is active low. 16- snps,reset-delays-us is triplet of delays 17 The 1st cell is reset pre-delay in micro seconds. 18 The 2nd cell is reset pulse in micro seconds. 19 The 3rd cell is reset post-delay in micro seconds. 20 21Optional properties: 22- resets: Should contain a phandle to the STMMAC reset signal, if any 23- reset-names: Should contain the reset signal name "stmmaceth", if a 24 reset phandle is given 25- max-frame-size: See ethernet.txt file in the same directory 26- clocks: If present, the first clock should be the GMAC main clock and 27 the second clock should be peripheral's register interface clock. Further 28 clocks may be specified in derived bindings. 29- clock-names: One name for each entry in the clocks property, the 30 first one should be "stmmaceth" and the second one should be "pclk". 31- clk_ptp_ref: this is the PTP reference clock; in case of the PTP is 32 available this clock is used for programming the Timestamp Addend Register. 33 If not passed then the system clock will be used and this is fine on some 34 platforms. 35- tx-fifo-depth: See ethernet.txt file in the same directory 36- rx-fifo-depth: See ethernet.txt file in the same directory 37- snps,pbl Programmable Burst Length 38- snps,aal Address-Aligned Beats 39- snps,fixed-burst Program the DMA to use the fixed burst mode 40- snps,mixed-burst Program the DMA to use the mixed burst mode 41- snps,force_thresh_dma_mode Force DMA to use the threshold mode for 42 both tx and rx 43- snps,force_sf_dma_mode Force DMA to use the Store and Forward 44 mode for both tx and rx. This flag is 45 ignored if force_thresh_dma_mode is set. 46- snps,multicast-filter-bins: Number of multicast filter hash bins 47 supported by this device instance 48- snps,perfect-filter-entries: Number of perfect filter entries supported 49 by this device instance 50- AXI BUS Mode parameters: below the list of all the parameters to program the 51 AXI register inside the DMA module: 52 - snps,lpi_en: enable Low Power Interface 53 - snps,xit_frm: unlock on WoL 54 - snps,wr_osr_lmt: max write outstanding req. limit 55 - snps,rd_osr_lmt: max read outstanding req. limit 56 - snps,kbbe: do not cross 1KiB boundary. 57 - snps,axi_all: align address 58 - snps,blen: this is a vector of supported burst length. 59 - snps,fb: fixed-burst 60 - snps,mb: mixed-burst 61 - snps,rb: rebuild INCRx Burst 62 - snps,tso: this enables the TSO feature otherwise it will be managed by 63 MAC HW capability register. 64- mdio: with compatible = "snps,dwmac-mdio", create and register mdio bus. 65 66Examples: 67 68 stmmac_axi_setup: stmmac-axi-config { 69 snps,wr_osr_lmt = <0xf>; 70 snps,rd_osr_lmt = <0xf>; 71 snps,blen = <256 128 64 32 0 0 0>; 72 }; 73 74 gmac0: ethernet@e0800000 { 75 compatible = "st,spear600-gmac"; 76 reg = <0xe0800000 0x8000>; 77 interrupt-parent = <&vic1>; 78 interrupts = <24 23>; 79 interrupt-names = "macirq", "eth_wake_irq"; 80 mac-address = [000000000000]; /* Filled in by U-Boot */ 81 max-frame-size = <3800>; 82 phy-mode = "gmii"; 83 snps,multicast-filter-bins = <256>; 84 snps,perfect-filter-entries = <128>; 85 rx-fifo-depth = <16384>; 86 tx-fifo-depth = <16384>; 87 clocks = <&clock>; 88 clock-names = "stmmaceth"; 89 snps,axi-config = <&stmmac_axi_setup>; 90 mdio0 { 91 #address-cells = <1>; 92 #size-cells = <0>; 93 compatible = "snps,dwmac-mdio"; 94 phy1: ethernet-phy@0 { 95 }; 96 }; 97 }; 98