xref: /linux/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml (revision 164666fa66669d437bdcc8d5f1744a2aee73be41) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NVIDIA Tegra186 (and later) SoC Memory Controller
8
9maintainers:
10  - Jon Hunter <jonathanh@nvidia.com>
11  - Thierry Reding <thierry.reding@gmail.com>
12
13description: |
14  The NVIDIA Tegra186 SoC features a 128 bit memory controller that is split
15  into four 32 bit channels to support LPDDR4 with x16 subpartitions. The MC
16  handles memory requests for 40-bit virtual addresses from internal clients
17  and arbitrates among them to allocate memory bandwidth.
18
19  Up to 15 GiB of physical memory can be supported. Security features such as
20  encryption of traffic to and from DRAM via general security apertures are
21  available for video and other secure applications, as well as DRAM ECC for
22  automotive safety applications (single bit error correction and double bit
23  error detection).
24
25properties:
26  $nodename:
27    pattern: "^memory-controller@[0-9a-f]+$"
28
29  compatible:
30    items:
31      - enum:
32          - nvidia,tegra186-mc
33          - nvidia,tegra194-mc
34          - nvidia,tegra234-mc
35
36  reg:
37    minItems: 1
38    maxItems: 3
39
40  interrupts:
41    items:
42      - description: MC general interrupt
43
44  "#address-cells":
45    const: 2
46
47  "#size-cells":
48    const: 2
49
50  ranges: true
51
52  dma-ranges: true
53
54  "#interconnect-cells":
55    const: 1
56
57patternProperties:
58  "^external-memory-controller@[0-9a-f]+$":
59    description:
60      The bulk of the work involved in controlling the external memory
61      controller on NVIDIA Tegra186 and later is performed on the BPMP. This
62      coprocessor exposes the EMC clock that is used to set the frequency at
63      which the external memory is clocked and a remote procedure call that
64      can be used to obtain the set of available frequencies.
65    type: object
66    properties:
67      compatible:
68        items:
69          - enum:
70              - nvidia,tegra186-emc
71              - nvidia,tegra194-emc
72              - nvidia,tegra234-emc
73
74      reg:
75        minItems: 1
76        maxItems: 2
77
78      interrupts:
79        items:
80          - description: EMC general interrupt
81
82      clocks:
83        items:
84          - description: external memory clock
85
86      clock-names:
87        items:
88          - const: emc
89
90      "#interconnect-cells":
91        const: 0
92
93      nvidia,bpmp:
94        $ref: /schemas/types.yaml#/definitions/phandle
95        description:
96          phandle of the node representing the BPMP
97
98    allOf:
99      - if:
100          properties:
101            compatible:
102              const: nvidia,tegra186-emc
103        then:
104          properties:
105            reg:
106              maxItems: 1
107
108      - if:
109          properties:
110            compatible:
111              const: nvidia,tegra194-emc
112        then:
113          properties:
114            reg:
115              minItems: 2
116
117      - if:
118          properties:
119            compatible:
120              const: nvidia,tegra234-emc
121        then:
122          properties:
123            reg:
124              minItems: 2
125
126    additionalProperties: false
127
128    required:
129      - compatible
130      - reg
131      - interrupts
132      - clocks
133      - clock-names
134      - "#interconnect-cells"
135      - nvidia,bpmp
136
137allOf:
138  - if:
139      properties:
140        compatible:
141          const: nvidia,tegra186-mc
142    then:
143      properties:
144        reg:
145          maxItems: 1
146
147  - if:
148      properties:
149        compatible:
150          const: nvidia,tegra194-mc
151    then:
152      properties:
153        reg:
154          minItems: 3
155
156  - if:
157      properties:
158        compatible:
159          const: nvidia,tegra234-mc
160    then:
161      properties:
162        reg:
163          minItems: 3
164
165additionalProperties: false
166
167required:
168  - compatible
169  - reg
170  - interrupts
171  - "#address-cells"
172  - "#size-cells"
173
174examples:
175  - |
176    #include <dt-bindings/clock/tegra186-clock.h>
177    #include <dt-bindings/interrupt-controller/arm-gic.h>
178
179    bus {
180        #address-cells = <2>;
181        #size-cells = <2>;
182
183        memory-controller@2c00000 {
184            compatible = "nvidia,tegra186-mc";
185            reg = <0x0 0x02c00000 0x0 0xb0000>;
186            interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
187
188            #address-cells = <2>;
189            #size-cells = <2>;
190
191            ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>;
192
193            /*
194             * Memory clients have access to all 40 bits that the memory
195             * controller can address.
196             */
197            dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
198
199            external-memory-controller@2c60000 {
200                compatible = "nvidia,tegra186-emc";
201                reg = <0x0 0x02c60000 0x0 0x50000>;
202                interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
203                clocks = <&bpmp TEGRA186_CLK_EMC>;
204                clock-names = "emc";
205
206                #interconnect-cells = <0>;
207
208                nvidia,bpmp = <&bpmp>;
209            };
210        };
211    };
212