1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: "http://devicetree.org/schemas/mailbox/st,stm32-ipcc.yaml#" 5$schema: "http://devicetree.org/meta-schemas/core.yaml#" 6 7title: STMicroelectronics STM32 IPC controller bindings 8 9description: 10 The IPCC block provides a non blocking signaling mechanism to post and 11 retrieve messages in an atomic way between two processors. 12 It provides the signaling for N bidirectionnal channels. The number of 13 channels (N) can be read from a dedicated register. 14 15maintainers: 16 - Fabien Dessenne <fabien.dessenne@st.com> 17 - Arnaud Pouliquen <arnaud.pouliquen@st.com> 18 19properties: 20 compatible: 21 const: st,stm32mp1-ipcc 22 23 reg: 24 maxItems: 1 25 26 clocks: 27 maxItems: 1 28 29 interrupts: 30 items: 31 - description: rx channel occupied 32 - description: tx channel free 33 - description: wakeup source 34 minItems: 2 35 maxItems: 3 36 37 interrupt-names: 38 items: 39 - const: rx 40 - const: tx 41 - const: wakeup 42 minItems: 2 43 maxItems: 3 44 45 wakeup-source: true 46 47 "#mbox-cells": 48 const: 1 49 50 st,proc-id: 51 description: Processor id using the mailbox (0 or 1) 52 allOf: 53 - $ref: /schemas/types.yaml#/definitions/uint32 54 - enum: [ 0, 1 ] 55 56required: 57 - compatible 58 - reg 59 - st,proc-id 60 - clocks 61 - interrupt-names 62 - "#mbox-cells" 63 - interrupts 64 65additionalProperties: false 66 67examples: 68 - | 69 #include <dt-bindings/interrupt-controller/arm-gic.h> 70 #include <dt-bindings/clock/stm32mp1-clks.h> 71 ipcc: mailbox@4c001000 { 72 compatible = "st,stm32mp1-ipcc"; 73 #mbox-cells = <1>; 74 reg = <0x4c001000 0x400>; 75 st,proc-id = <0>; 76 interrupts-extended = <&intc GIC_SPI 100 IRQ_TYPE_NONE>, 77 <&intc GIC_SPI 101 IRQ_TYPE_NONE>, 78 <&aiec 62 1>; 79 interrupt-names = "rx", "tx", "wakeup"; 80 clocks = <&rcc_clk IPCC>; 81 wakeup-source; 82 }; 83 84... 85