xref: /linux/Documentation/devicetree/bindings/interconnect/fsl,imx8m-noc.yaml (revision 3503d56cc7233ced602e38a4c13caa64f00ab2aa) 
1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/interconnect/fsl,imx8m-noc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Generic i.MX bus frequency device
8
9maintainers:
10  - Leonard Crestez <leonard.crestez@nxp.com>
11
12description: |
13  The i.MX SoC family has multiple buses for which clock frequency (and
14  sometimes voltage) can be adjusted.
15
16  Some of those buses expose register areas mentioned in the memory maps as GPV
17  ("Global Programmers View") but not all. Access to this area might be denied
18  for normal (non-secure) world.
19
20  The buses are based on externally licensed IPs such as ARM NIC-301 and
21  Arteris FlexNOC but DT bindings are specific to the integration of these bus
22  interconnect IPs into imx SOCs.
23
24properties:
25  compatible:
26    oneOf:
27      - items:
28        - enum:
29          - fsl,imx8mn-nic
30          - fsl,imx8mm-nic
31          - fsl,imx8mq-nic
32        - const: fsl,imx8m-nic
33      - items:
34        - enum:
35          - fsl,imx8mn-noc
36          - fsl,imx8mm-noc
37          - fsl,imx8mq-noc
38        - const: fsl,imx8m-noc
39      - const: fsl,imx8m-nic
40
41  reg:
42    maxItems: 1
43
44  clocks:
45    maxItems: 1
46
47  operating-points-v2: true
48  opp-table: true
49
50  fsl,ddrc:
51    $ref: "/schemas/types.yaml#/definitions/phandle"
52    description:
53      Phandle to DDR Controller.
54
55  '#interconnect-cells':
56    description:
57      If specified then also act as an interconnect provider. Should only be
58      set once per soc on the main noc.
59    const: 1
60
61required:
62  - compatible
63  - clocks
64
65additionalProperties: false
66
67examples:
68  - |
69    #include <dt-bindings/clock/imx8mm-clock.h>
70    #include <dt-bindings/interconnect/imx8mm.h>
71    #include <dt-bindings/interrupt-controller/arm-gic.h>
72
73    noc: interconnect@32700000 {
74        compatible = "fsl,imx8mm-noc", "fsl,imx8m-noc";
75        reg = <0x32700000 0x100000>;
76        clocks = <&clk IMX8MM_CLK_NOC>;
77        #interconnect-cells = <1>;
78        fsl,ddrc = <&ddrc>;
79
80        operating-points-v2 = <&noc_opp_table>;
81        noc_opp_table: opp-table {
82            compatible = "operating-points-v2";
83
84            opp-133M {
85                opp-hz = /bits/ 64 <133333333>;
86            };
87            opp-800M {
88                opp-hz = /bits/ 64 <800000000>;
89            };
90        };
91    };
92
93    ddrc: memory-controller@3d400000 {
94        compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
95        reg = <0x3d400000 0x400000>;
96        clock-names = "core", "pll", "alt", "apb";
97        clocks = <&clk IMX8MM_CLK_DRAM_CORE>,
98                 <&clk IMX8MM_DRAM_PLL>,
99                 <&clk IMX8MM_CLK_DRAM_ALT>,
100                 <&clk IMX8MM_CLK_DRAM_APB>;
101    };
102