xref: /linux/Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml (revision 42874e4eb35bdfc54f8514685e50434098ba4f6c) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,gcc-sdx65.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Global Clock & Reset Controller on SDX65
8
9maintainers:
10  - Vamsi krishna Lanka <quic_vamslank@quicinc.com>
11
12description: |
13  Qualcomm global clock control module provides the clocks, resets and power
14  domains on SDX65
15
16  See also:: include/dt-bindings/clock/qcom,gcc-sdx65.h
17
18properties:
19  compatible:
20    const: qcom,gcc-sdx65
21
22  clocks:
23    items:
24      - description: Board XO source
25      - description: Board active XO source
26      - description: Sleep clock source
27      - description: PCIE Pipe clock source
28      - description: USB3 phy wrapper pipe clock source
29
30  clock-names:
31    items:
32      - const: bi_tcxo
33      - const: bi_tcxo_ao
34      - const: sleep_clk
35      - const: pcie_pipe_clk
36      - const: usb3_phy_wrapper_gcc_usb30_pipe_clk
37
38required:
39  - compatible
40  - clocks
41  - clock-names
42
43allOf:
44  - $ref: qcom,gcc.yaml#
45
46unevaluatedProperties: false
47
48examples:
49  - |
50    #include <dt-bindings/clock/qcom,rpmh.h>
51    clock-controller@100000 {
52      compatible = "qcom,gcc-sdx65";
53      reg = <0x100000 0x1f7400>;
54      clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
55               <&pcie_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
56      clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
57                    "pcie_pipe_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk";
58      #clock-cells = <1>;
59      #reset-cells = <1>;
60      #power-domain-cells = <1>;
61    };
62...
63