1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 /* 27 * The file has been code generated. Do NOT modify this file directly. Please 28 * use the sun4v PCIe FMA code generation tool. 29 * 30 * This file was generated for the following platforms: 31 * - Fire 32 * - N2PIU 33 * - Rainbow Falls 34 * - Victoria Falls 35 */ 36 37 /* ARGSUSED */ 38 static int 39 px_cb_epkt_severity(dev_info_t *dip, ddi_fm_error_t *derr, px_rc_err_t *epkt) 40 { 41 int err = 0; 42 43 /* STOP bit indicates a secondary error. Panic if it is set */ 44 if (epkt->rc_descr.STOP == 1) 45 return (PX_PANIC); 46 47 switch (epkt->rc_descr.op) { 48 case OP_DMA: 49 switch (epkt->rc_descr.phase) { 50 case PH_ADDR: 51 switch (epkt->rc_descr.cond) { 52 case CND_ILL: 53 switch (epkt->rc_descr.dir) { 54 case DIR_WRITE: 55 err = PX_PANIC; 56 break; 57 } /* DIR */ 58 break; 59 } /* CND */ 60 break; 61 case PH_DATA: 62 switch (epkt->rc_descr.cond) { 63 case CND_INT: 64 switch (epkt->rc_descr.dir) { 65 case DIR_READ: 66 err = PX_PANIC; 67 break; 68 case DIR_RDWR: 69 err = PX_PANIC; 70 break; 71 case DIR_UNKNOWN: 72 err = PX_PANIC; 73 break; 74 case DIR_WRITE: 75 err = PX_PANIC; 76 break; 77 } /* DIR */ 78 break; 79 case CND_TO: 80 switch (epkt->rc_descr.dir) { 81 case DIR_READ: 82 err = PX_PANIC; 83 break; 84 case DIR_WRITE: 85 err = PX_PANIC; 86 break; 87 } /* DIR */ 88 break; 89 case CND_UE: 90 switch (epkt->rc_descr.dir) { 91 case DIR_READ: 92 err = PX_PANIC; 93 break; 94 } /* DIR */ 95 break; 96 } /* CND */ 97 break; 98 case PH_UNKNOWN: 99 switch (epkt->rc_descr.cond) { 100 case CND_ILL: 101 switch (epkt->rc_descr.dir) { 102 case DIR_READ: 103 err = PX_PANIC; 104 break; 105 } /* DIR */ 106 break; 107 case CND_UNKNOWN: 108 switch (epkt->rc_descr.dir) { 109 case DIR_READ: 110 err = PX_PANIC; 111 break; 112 } /* DIR */ 113 break; 114 } /* CND */ 115 break; 116 } /* PH */ 117 break; 118 case OP_PIO: 119 switch (epkt->rc_descr.phase) { 120 case PH_ADDR: 121 switch (epkt->rc_descr.cond) { 122 case CND_UNMAP: 123 switch (epkt->rc_descr.dir) { 124 case DIR_READ: 125 err = PX_PANIC; 126 break; 127 case DIR_WRITE: 128 err = PX_PANIC; 129 break; 130 } /* DIR */ 131 break; 132 } /* CND */ 133 break; 134 case PH_DATA: 135 switch (epkt->rc_descr.cond) { 136 case CND_INT: 137 switch (epkt->rc_descr.dir) { 138 case DIR_RDWR: 139 err = PX_PANIC; 140 break; 141 case DIR_UNKNOWN: 142 err = PX_PANIC; 143 break; 144 case DIR_WRITE: 145 err = PX_PANIC; 146 break; 147 } /* DIR */ 148 break; 149 case CND_ILL: 150 switch (epkt->rc_descr.dir) { 151 case DIR_WRITE: 152 err = PX_PANIC; 153 break; 154 } /* DIR */ 155 break; 156 } /* CND */ 157 break; 158 case PH_UNKNOWN: 159 switch (epkt->rc_descr.cond) { 160 case CND_ILL: 161 switch (epkt->rc_descr.dir) { 162 case DIR_READ: 163 err = PX_PANIC; 164 break; 165 case DIR_WRITE: 166 err = PX_PANIC; 167 break; 168 } /* DIR */ 169 break; 170 case CND_TO: 171 switch (epkt->rc_descr.dir) { 172 case DIR_RDWR: 173 err = PX_PANIC; 174 break; 175 } /* DIR */ 176 break; 177 } /* CND */ 178 break; 179 } /* PH */ 180 break; 181 case OP_UNKNOWN: 182 switch (epkt->rc_descr.phase) { 183 case PH_ADDR: 184 switch (epkt->rc_descr.cond) { 185 case CND_UNMAP: 186 switch (epkt->rc_descr.dir) { 187 case DIR_RDWR: 188 err = PX_PANIC; 189 break; 190 } /* DIR */ 191 break; 192 } /* CND */ 193 break; 194 case PH_DATA: 195 switch (epkt->rc_descr.cond) { 196 case CND_INT: 197 switch (epkt->rc_descr.dir) { 198 case DIR_UNKNOWN: 199 err = PX_PANIC; 200 break; 201 } /* DIR */ 202 break; 203 case CND_UE: 204 switch (epkt->rc_descr.dir) { 205 case DIR_IRR: 206 err = PX_PANIC; 207 break; 208 } /* DIR */ 209 break; 210 } /* CND */ 211 break; 212 case PH_UNKNOWN: 213 switch (epkt->rc_descr.cond) { 214 case CND_ILL: 215 switch (epkt->rc_descr.dir) { 216 case DIR_IRR: 217 err = PX_PANIC; 218 break; 219 } /* DIR */ 220 } /* CND */ 221 } /* PH */ 222 } /* OP */ 223 224 return (err); 225 } 226 227 228 /* ARGSUSED */ 229 static int 230 px_mmu_epkt_severity(dev_info_t *dip, ddi_fm_error_t *derr, px_rc_err_t *epkt) 231 { 232 int err = 0; 233 234 /* STOP bit indicates a secondary error. Panic if it is set */ 235 if (epkt->rc_descr.STOP == 1) 236 return (PX_PANIC); 237 238 switch (epkt->rc_descr.op) { 239 case OP_BYPASS: 240 switch (epkt->rc_descr.phase) { 241 case PH_ADDR: 242 switch (epkt->rc_descr.cond) { 243 case CND_ILL: 244 switch (epkt->rc_descr.dir) { 245 case DIR_RDWR: 246 err = PX_NO_PANIC; 247 break; 248 } /* DIR */ 249 break; 250 } /* CND */ 251 break; 252 case PH_UNKNOWN: 253 switch (epkt->rc_descr.cond) { 254 case CND_ILL: 255 switch (epkt->rc_descr.dir) { 256 case DIR_UNKNOWN: 257 err = PX_NO_PANIC; 258 break; 259 } /* DIR */ 260 break; 261 } /* CND */ 262 break; 263 } /* PH */ 264 break; 265 case OP_TBW: 266 switch (epkt->rc_descr.phase) { 267 case PH_ADDR: 268 switch (epkt->rc_descr.cond) { 269 case CND_UNKNOWN: 270 switch (epkt->rc_descr.dir) { 271 case DIR_UNKNOWN: 272 err = PX_PANIC; 273 break; 274 } /* DIR */ 275 break; 276 case CND_UNMAP: 277 switch (epkt->rc_descr.dir) { 278 case DIR_UNKNOWN: 279 err = PX_PANIC; 280 break; 281 } /* DIR */ 282 break; 283 } /* CND */ 284 break; 285 case PH_DATA: 286 switch (epkt->rc_descr.cond) { 287 case CND_INT: 288 switch (epkt->rc_descr.dir) { 289 case DIR_IRR: 290 err = PX_PANIC; 291 break; 292 } /* DIR */ 293 break; 294 } /* CND */ 295 break; 296 case PH_UNKNOWN: 297 switch (epkt->rc_descr.cond) { 298 case CND_ILL: 299 switch (epkt->rc_descr.dir) { 300 case DIR_IRR: 301 err = PX_PANIC; 302 break; 303 } /* DIR */ 304 break; 305 case CND_UNKNOWN: 306 switch (epkt->rc_descr.dir) { 307 case DIR_IRR: 308 err = PX_PANIC; 309 break; 310 case DIR_UNKNOWN: 311 err = PX_PANIC; 312 break; 313 } /* DIR */ 314 break; 315 } /* CND */ 316 break; 317 } /* PH */ 318 break; 319 case OP_XLAT: 320 switch (epkt->rc_descr.phase) { 321 case PH_ADDR: 322 switch (epkt->rc_descr.cond) { 323 case CND_ILL: 324 switch (epkt->rc_descr.dir) { 325 case DIR_RDWR: 326 err = PX_NO_PANIC; 327 break; 328 } /* DIR */ 329 break; 330 case CND_IRR: 331 switch (epkt->rc_descr.dir) { 332 case DIR_IRR: 333 err = PX_PANIC; 334 break; 335 } /* DIR */ 336 break; 337 case CND_PROT: 338 switch (epkt->rc_descr.dir) { 339 case DIR_RDWR: 340 err = PX_NO_PANIC; 341 break; 342 } /* DIR */ 343 break; 344 case CND_UNMAP: 345 switch (epkt->rc_descr.dir) { 346 case DIR_RDWR: 347 err = PX_NO_PANIC; 348 break; 349 } /* DIR */ 350 break; 351 } /* CND */ 352 break; 353 case PH_DATA: 354 switch (epkt->rc_descr.cond) { 355 case CND_INT: 356 switch (epkt->rc_descr.dir) { 357 case DIR_UNKNOWN: 358 err = PX_PANIC; 359 break; 360 } /* DIR */ 361 break; 362 case CND_INV: 363 switch (epkt->rc_descr.dir) { 364 case DIR_RDWR: 365 err = PX_NO_PANIC; 366 break; 367 case DIR_UNKNOWN: 368 err = PX_NO_PANIC; 369 break; 370 } /* DIR */ 371 break; 372 case CND_IRR: 373 switch (epkt->rc_descr.dir) { 374 case DIR_IRR: 375 err = PX_PANIC; 376 break; 377 } /* DIR */ 378 break; 379 case CND_PROT: 380 switch (epkt->rc_descr.dir) { 381 case DIR_RDWR: 382 err = PX_NO_PANIC; 383 break; 384 case DIR_WRITE: 385 err = PX_NO_PANIC; 386 break; 387 } /* DIR */ 388 break; 389 } /* CND */ 390 break; 391 case PH_UNKNOWN: 392 switch (epkt->rc_descr.cond) { 393 case CND_ILL: 394 switch (epkt->rc_descr.dir) { 395 case DIR_IRR: 396 err = PX_PANIC; 397 break; 398 } /* DIR */ 399 } /* CND */ 400 } /* PH */ 401 } /* OP */ 402 403 if (epkt->rc_descr.D && (err & (PX_PANIC | PX_PROTECTED)) && 404 px_mmu_handle_lookup(dip, derr, epkt) == PF_HDL_FOUND) 405 err = PX_NO_PANIC; 406 407 return (err); 408 } 409 410 411 /* ARGSUSED */ 412 static int 413 px_intr_epkt_severity(dev_info_t *dip, ddi_fm_error_t *derr, px_rc_err_t *epkt) 414 { 415 int err = 0; 416 417 /* STOP bit indicates a secondary error. Panic if it is set */ 418 if (epkt->rc_descr.STOP == 1) 419 return (PX_PANIC); 420 421 switch (epkt->rc_descr.op) { 422 case OP_FIXED: 423 switch (epkt->rc_descr.phase) { 424 case PH_UNKNOWN: 425 switch (epkt->rc_descr.cond) { 426 case CND_ILL: 427 switch (epkt->rc_descr.dir) { 428 case DIR_INGRESS: 429 err = PX_PANIC; 430 break; 431 } /* DIR */ 432 break; 433 } /* CND */ 434 break; 435 } /* PH */ 436 break; 437 case OP_MSI32: 438 switch (epkt->rc_descr.phase) { 439 case PH_DATA: 440 switch (epkt->rc_descr.cond) { 441 case CND_INT: 442 switch (epkt->rc_descr.dir) { 443 case DIR_UNKNOWN: 444 err = PX_PANIC; 445 break; 446 } /* DIR */ 447 break; 448 case CND_ILL: 449 switch (epkt->rc_descr.dir) { 450 case DIR_IRR: 451 err = PX_PANIC; 452 break; 453 } /* DIR */ 454 break; 455 } /* CND */ 456 break; 457 case PH_UNKNOWN: 458 switch (epkt->rc_descr.cond) { 459 case CND_ILL: 460 switch (epkt->rc_descr.dir) { 461 case DIR_IRR: 462 err = PX_PANIC; 463 break; 464 } /* DIR */ 465 break; 466 } /* CND */ 467 break; 468 } /* PH */ 469 break; 470 case OP_MSI64: 471 switch (epkt->rc_descr.phase) { 472 case PH_DATA: 473 switch (epkt->rc_descr.cond) { 474 case CND_INT: 475 switch (epkt->rc_descr.dir) { 476 case DIR_UNKNOWN: 477 err = PX_PANIC; 478 break; 479 } /* DIR */ 480 break; 481 case CND_ILL: 482 switch (epkt->rc_descr.dir) { 483 case DIR_IRR: 484 err = PX_PANIC; 485 break; 486 } /* DIR */ 487 break; 488 } /* CND */ 489 break; 490 case PH_UNKNOWN: 491 switch (epkt->rc_descr.cond) { 492 case CND_ILL: 493 switch (epkt->rc_descr.dir) { 494 case DIR_IRR: 495 err = PX_PANIC; 496 break; 497 } /* DIR */ 498 break; 499 } /* CND */ 500 break; 501 } /* PH */ 502 break; 503 case OP_MSIQ: 504 switch (epkt->rc_descr.phase) { 505 case PH_DATA: 506 switch (epkt->rc_descr.cond) { 507 case CND_INT: 508 switch (epkt->rc_descr.dir) { 509 case DIR_UNKNOWN: 510 err = PX_PANIC; 511 break; 512 } /* DIR */ 513 break; 514 } /* CND */ 515 break; 516 case PH_UNKNOWN: 517 switch (epkt->rc_descr.cond) { 518 case CND_ILL: 519 switch (epkt->rc_descr.dir) { 520 case DIR_IRR: 521 err = PX_PANIC; 522 break; 523 } /* DIR */ 524 break; 525 case CND_OV: 526 switch (epkt->rc_descr.dir) { 527 case DIR_IRR: 528 err = px_intr_handle_errors(dip, derr, 529 epkt); 530 break; 531 } /* DIR */ 532 break; 533 } /* CND */ 534 break; 535 } /* PH */ 536 break; 537 case OP_PCIEMSG: 538 switch (epkt->rc_descr.phase) { 539 case PH_UNKNOWN: 540 switch (epkt->rc_descr.cond) { 541 case CND_ILL: 542 switch (epkt->rc_descr.dir) { 543 case DIR_INGRESS: 544 err = PX_PANIC; 545 break; 546 } /* DIR */ 547 break; 548 } /* CND */ 549 break; 550 } /* PH */ 551 break; 552 case OP_UNKNOWN: 553 switch (epkt->rc_descr.phase) { 554 case PH_DATA: 555 switch (epkt->rc_descr.cond) { 556 case CND_INT: 557 switch (epkt->rc_descr.dir) { 558 case DIR_UNKNOWN: 559 err = PX_PANIC; 560 break; 561 } /* DIR */ 562 break; 563 case CND_ILL: 564 switch (epkt->rc_descr.dir) { 565 case DIR_IRR: 566 err = PX_PANIC; 567 break; 568 } /* DIR */ 569 break; 570 } /* CND */ 571 break; 572 case PH_UNKNOWN: 573 switch (epkt->rc_descr.cond) { 574 case CND_ILL: 575 switch (epkt->rc_descr.dir) { 576 case DIR_IRR: 577 err = PX_PANIC; 578 break; 579 } /* DIR */ 580 } /* CND */ 581 } /* PH */ 582 } /* OP */ 583 584 return (err); 585 } 586 587 588 /* ARGSUSED */ 589 static int 590 px_port_epkt_severity(dev_info_t *dip, ddi_fm_error_t *derr, px_rc_err_t *epkt) 591 { 592 int err = 0; 593 594 /* STOP bit indicates a secondary error. Panic if it is set */ 595 if (epkt->rc_descr.STOP == 1) 596 return (PX_PANIC); 597 598 switch (epkt->rc_descr.op) { 599 case OP_DMA: 600 switch (epkt->rc_descr.phase) { 601 case PH_DATA: 602 switch (epkt->rc_descr.cond) { 603 case CND_INT: 604 switch (epkt->rc_descr.dir) { 605 case DIR_READ: 606 err = PX_PANIC; 607 break; 608 } /* DIR */ 609 break; 610 } /* CND */ 611 break; 612 } /* PH */ 613 break; 614 case OP_LINK: 615 switch (epkt->rc_descr.phase) { 616 case PH_FC: 617 switch (epkt->rc_descr.cond) { 618 case CND_TO: 619 switch (epkt->rc_descr.dir) { 620 case DIR_IRR: 621 err = PX_PANIC; 622 break; 623 } /* DIR */ 624 break; 625 } /* CND */ 626 break; 627 } /* PH */ 628 break; 629 case OP_PIO: 630 switch (epkt->rc_descr.phase) { 631 case PH_DATA: 632 switch (epkt->rc_descr.cond) { 633 case CND_INT: 634 switch (epkt->rc_descr.dir) { 635 case DIR_READ: 636 err = PX_PANIC; 637 break; 638 case DIR_UNKNOWN: 639 err = PX_PANIC; 640 break; 641 } /* DIR */ 642 break; 643 } /* CND */ 644 break; 645 case PH_IRR: 646 switch (epkt->rc_descr.cond) { 647 case CND_INV: 648 switch (epkt->rc_descr.dir) { 649 case DIR_RDWR: 650 err = PX_PANIC; 651 break; 652 } /* DIR */ 653 break; 654 case CND_RCA: 655 switch (epkt->rc_descr.dir) { 656 case DIR_WRITE: 657 err = px_port_handle_errors(dip, derr, 658 epkt); 659 break; 660 } /* DIR */ 661 break; 662 case CND_RUR: 663 switch (epkt->rc_descr.dir) { 664 case DIR_WRITE: 665 err = px_port_handle_errors(dip, derr, 666 epkt); 667 break; 668 } /* DIR */ 669 break; 670 case CND_TO: 671 switch (epkt->rc_descr.dir) { 672 case DIR_WRITE: 673 err = PX_PANIC; 674 break; 675 } /* DIR */ 676 break; 677 case CND_UC: 678 switch (epkt->rc_descr.dir) { 679 case DIR_IRR: 680 err = PX_NO_PANIC; 681 break; 682 } /* DIR */ 683 break; 684 } /* CND */ 685 break; 686 } /* PH */ 687 break; 688 case OP_UNKNOWN: 689 switch (epkt->rc_descr.phase) { 690 case PH_DATA: 691 switch (epkt->rc_descr.cond) { 692 case CND_INT: 693 switch (epkt->rc_descr.dir) { 694 case DIR_UNKNOWN: 695 err = PX_PANIC; 696 break; 697 } /* DIR */ 698 } /* CND */ 699 } /* PH */ 700 } /* OP */ 701 702 return (err); 703 } 704