xref: /illumos-gate/usr/src/uts/sun4u/sys/spitregs.h (revision 2a1fd0ffe121888d44fdec321c25b53dcfaa9118)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License, Version 1.0 only
6  * (the "License").  You may not use this file except in compliance
7  * with the License.
8  *
9  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10  * or http://www.opensolaris.org/os/licensing.
11  * See the License for the specific language governing permissions
12  * and limitations under the License.
13  *
14  * When distributing Covered Code, include this CDDL HEADER in each
15  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16  * If applicable, add the following below this CDDL HEADER, with the
17  * fields enclosed by brackets "[]" replaced with your own identifying
18  * information: Portions Copyright [yyyy] [name of copyright owner]
19  *
20  * CDDL HEADER END
21  */
22 /*
23  * Copyright 2004 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 /*
27  * Copyright 2019 Peter Tribble.
28  */
29 
30 #ifndef _SYS_SPITREGS_H
31 #define	_SYS_SPITREGS_H
32 
33 #ifdef	__cplusplus
34 extern "C" {
35 #endif
36 
37 /*
38  * This file is cpu dependent.
39  */
40 
41 /*
42  * The mid is the same as the cpu id.
43  * We might want to change this later
44  */
45 #define	CPUID_TO_UPAID(cpuid)	(cpuid)
46 
47 /*
48  * LSU Control Register
49  *
50  * +------+----+----+----+----+----+----+-----+------+----+----+----+---+
51  * | Resv | PM | VM | PR | PW | VR | VW | Rsv |  FM  | DM | IM | DC | IC|
52  * +------+----+----+----+----+----+----+-----+------+----+----+----+---+
53  *  63  41   33   25   24   23	 22   21   20  19   4	3    2	  1   0
54  *
55  */
56 
57 #define	LSU_IC		0x00000000001	/* icache enable */
58 #define	LSU_DC		0x00000000002	/* dcache enable */
59 #define	LSU_IM		0x00000000004	/* immu enable */
60 #define	LSU_DM		0x00000000008	/* dmmu enable */
61 #define	LSU_FM		0x000000FFFF0	/* parity mask */
62 #define	LSU_VW		0x00000200000	/* virtual watchpoint write enable */
63 #define	LSU_VR		0x00000400000	/* virtual watchpoint read enable */
64 #define	LSU_PW		0x00000800000	/* physical watchpoint write enable */
65 #define	LSU_PR		0x00001000000	/* physical watchpoint read enable */
66 #define	LSU_VM		0x001fe000000	/* virtual watchpoint byte mask */
67 #define	LSU_PM		0x1fe00000000	/* physical watch point byte mask */
68 
69 #define	LSU_VM_SHIFT	25
70 #define	LSU_PM_SHIFT	33
71 
72 /*
73  * Defines for the different types of dcache_flush
74  * it is stored in dflush_type
75  */
76 #define	FLUSHALL_TYPE	0x0		/* blasts all cache lines */
77 #define	FLUSHMATCH_TYPE	0x1		/* flush entire cache but check each */
78 					/* each line for a match */
79 #define	FLUSHPAGE_TYPE	0x2		/* flush only one page and check */
80 					/* each line for a match */
81 
82 /*
83  * D-Cache Tag Data Register
84  *
85  * +----------+--------+----------+
86  * | Reserved | DC_Tag | DC_Valid |
87  * +----------+--------+----------+
88  *  63	    30 29    2	1	 0
89  *
90  */
91 #define	ICACHE_FLUSHSZ	0x20	/* one line in i$ */
92 #define	DC_PTAG_SHIFT	34
93 #define	DC_LINE_SHIFT	30
94 #define	SF_DC_VBIT_SHIFT 2
95 #define	SF_DC_VBIT_MASK	0x3
96 #define	IC_LINE_SHIFT	3
97 #define	IC_LINE		512
98 #define	INDEX_BIT_SHIFT	13
99 
100 /*
101  * Definitions of sun4u cpu implementations as specified in version register
102  */
103 #define	SPITFIRE_IMPL	0x10
104 #define	IS_SPITFIRE(impl)	((impl) == SPITFIRE_IMPL)
105 #define	SPITFIRE_MAJOR_VERSION(rev)	(((rev) >> 4) & 0xf)
106 #define	SPITFIRE_MINOR_VERSION(rev)	((rev) & 0xf)
107 
108 #define	BLACKBIRD_IMPL	0x11
109 #define	IS_BLACKBIRD(impl)	((impl) == BLACKBIRD_IMPL)
110 #define	BLACKBIRD_MAJOR_VERSION(rev)	(((rev) >> 4) & 0xf)
111 #define	BLACKBIRD_MINOR_VERSION(rev)	((rev) & 0xf)
112 
113 #define	SABRE_IMPL	0x12
114 #define	HUMMBRD_IMPL	0x13
115 
116 /*
117  * Bits of Spitfire Asynchronous Fault Status Register
118  */
119 #define	P_AFSR_STICKY	0x00000001FFF00000ULL /* mask for all sticky bits */
120 #define	P_AFSR_ERRS	0x000000001EE00000ULL /* mask for remaining errors */
121 #define	P_AFSR_ME	0x0000000100000000ULL /* errors > 1, same type!=CE */
122 #define	P_AFSR_PRIV	0x0000000080000000ULL /* priv/supervisor access */
123 #define	P_AFSR_ISAP	0x0000000040000000ULL /* incoming system addr. parity */
124 #define	P_AFSR_ETP	0x0000000020000000ULL /* ecache tag parity */
125 #define	P_AFSR_IVUE	0x0000000010000000ULL /* interrupt vector with UE */
126 #define	P_AFSR_TO	0x0000000008000000ULL /* bus timeout */
127 #define	P_AFSR_BERR	0x0000000004000000ULL /* bus error */
128 #define	P_AFSR_LDP	0x0000000002000000ULL /* data parity error from SDB */
129 #define	P_AFSR_CP	0x0000000001000000ULL /* copyout parity error */
130 #define	P_AFSR_WP	0x0000000000800000ULL /* writeback ecache data parity */
131 #define	P_AFSR_EDP	0x0000000000400000ULL /* ecache data parity */
132 #define	P_AFSR_UE	0x0000000000200000ULL /* uncorrectable ECC error */
133 #define	P_AFSR_CE	0x0000000000100000ULL /* correctable ECC error */
134 #define	P_AFSR_ETS	0x00000000000F0000ULL /* cache tag parity syndrome */
135 #define	P_AFSR_P_SYND	0x000000000000FFFFULL /* data parity syndrome */
136 
137 /*
138  * All error types
139  */
140 #define	S_AFSR_ALL_ERRS	(P_AFSR_STICKY & ~P_AFSR_PRIV)
141 
142 /*
143  * Shifts for Spitfire Asynchronous Fault Status Register
144  */
145 #define	P_AFSR_D_SIZE_SHIFT	(57)
146 #define	P_AFSR_CP_SHIFT		(24)
147 #define	P_AFSR_ETS_SHIFT	(16)
148 
149 /*
150  * AFSR error bits for AFT Level 1 messages (uncorrected + parity + BERR + TO)
151  */
152 #define	P_AFSR_LEVEL1   (P_AFSR_UE | P_AFSR_EDP | P_AFSR_WP | P_AFSR_CP |\
153 			P_AFSR_LDP | P_AFSR_BERR | P_AFSR_TO)
154 
155 /*
156  * Bits of Spitfire Asynchronous Fault Status Register
157  */
158 #define	S_AFSR_MASK	0x00000001FFFFFFFFULL /* <33:0>: valid AFSR bits */
159 
160 /*
161  * Bits of Spitfire Asynchronous Fault Address Register
162  * The Sabre AFAR includes more bits since it only has a UDBH, no UDBL
163  */
164 #define	S_AFAR_PA	0x000001FFFFFFFFF0ULL /* PA<40:4>: physical address */
165 #define	SABRE_AFAR_PA	0x000001FFFFFFFFF8ULL /* PA<40:3>: physical address */
166 
167 /*
168  * Bits of Spitfire/Sabre/Hummingbird Error Enable Registers
169  */
170 #define	EER_EPEN	0x00000000000000010ULL /* enable ETP, EDP, WP, CP */
171 #define	EER_UEEN	0x00000000000000008ULL /* enable UE */
172 #define	EER_ISAPEN	0x00000000000000004ULL /* enable ISAP */
173 #define	EER_NCEEN	0x00000000000000002ULL /* enable the other errors */
174 #define	EER_CEEN	0x00000000000000001ULL /* enable CE */
175 #define	EER_DISABLE	0x00000000000000000ULL /* no errors enabled */
176 #define	EER_ECC_DISABLE	(EER_EPEN|EER_UEEN|EER_ISAPEN)
177 #define	EER_CE_DISABLE	(EER_EPEN|EER_UEEN|EER_ISAPEN|EER_NCEEN)
178 #define	EER_ENABLE	(EER_EPEN|EER_UEEN|EER_ISAPEN|EER_NCEEN|EER_CEEN)
179 
180 /*
181  * Bits and vaddrs of Spitfire Datapath Error Registers
182  */
183 #define	P_DER_UE	0x00000000000000200ULL	/* UE has occurred */
184 #define	P_DER_CE	0x00000000000000100ULL	/* CE has occurred */
185 #define	P_DER_E_SYND	0x000000000000000FFULL	/* SYND<7:0>: ECC syndrome */
186 #define	P_DER_H		0x0			/* datapath error reg upper */
187 #define	P_DER_L		0x18			/* datapath error reg upper */
188 
189 /*
190  * Bits of Spitfire Datapath Control Register
191  */
192 #define	P_DCR_VER	0x000001E00		/* datapath version */
193 #define	P_DCR_F_MODE	0x000000100		/* send FCB<7:0> */
194 #define	P_DCR_FCB	0x0000000FF		/* ECC check bits to force */
195 #define	P_DCR_H		0x20			/* datapath control reg upper */
196 #define	P_DCR_L		0x38			/* datapath control reg lower */
197 
198 /*
199  * Bits and shifts for the Spitfire (S), Sabre (SB) and Hummingbird (HB)
200  * Ecache tag data
201  */
202 #define	S_ECTAG_MASK	0x000000000003FFFFFULL	/* spitfire ecache tag mask */
203 #define	SB_ECTAG_MASK	0x00000000000000FFFULL	/* sabre ecache tag mask */
204 #define	HB_ECTAG_MASK	0x0000000000000FFFFULL	/* hbird ecache tag mask */
205 #define	S_ECSTATE_MASK	0x00000000001C00000ULL	/* spitfire tag state mask */
206 #define	SB_ECSTATE_MASK 0x0000000000000C000ULL	/* sabre tag state mask */
207 #define	HB_ECSTATE_MASK 0x00000000000030000ULL	/* hbird tag state mask */
208 #define	S_ECPAR_MASK	0x0000000001E000000ULL	/* spitfire tag parity mask */
209 #define	SB_ECPAR_MASK	0x00000000000030000ULL	/* sabre tag parity mask */
210 #define	HB_ECPAR_MASK	0x00000000000300000ULL	/* hbird tag parity mask */
211 #define	S_ECTAG_SHIFT		19		/* spitfire ecache tag shift */
212 #define	SB_ECTAG_SHIFT		18		/* sabre ecache tag shift */
213 #define	HB_ECTAG_SHIFT		16		/* hbird ecache tag shift */
214 #define	S_ECSTATE_SHIFT		22		/* spitfire tag state shift */
215 #define	SB_ECSTATE_SHIFT	14		/* sabre tag state shift */
216 #define	HB_ECSTATE_SHIFT	16		/* hbird tag state shift */
217 #define	S_ECPAR_SHIFT		25		/* spitfire tag parity shift */
218 #define	SB_ECPAR_SHIFT		16		/* sabre tag parity shift */
219 #define	HB_ECPAR_SHIFT		20		/* hbird tag parity shift */
220 #define	S_ECACHE_MAX_LSIZE	64		/* E$ line size */
221 
222 /*
223  * Constants representing the complete Spitfire (S), Sabre (SB) and Hummingbird
224  * (HB) tag state:
225  */
226 #define	S_ECSTATE_SHR		0x1		/* shared */
227 #define	S_ECSTATE_EXL		0x3		/* exclusive */
228 #define	S_ECSTATE_OWN		0x5		/* owner */
229 #define	S_ECSTATE_MOD		0x7		/* modified */
230 #define	SB_ECSTATE_EXL		0x2		/* exclusive */
231 #define	SB_ECSTATE_MOD		0x3		/* modified */
232 #define	HB_ECSTATE_EXL		0x2		/* exclusive */
233 #define	HB_ECSTATE_MOD		0x3		/* modified */
234 
235 /*
236  * Constants representing the individual Spitfire (S), Sabre (SB) and
237  * Hummingbird (HB) state bits:
238  */
239 #define	S_ECSTATE_VALID		0x1		/* line is valid */
240 #define	S_ECSTATE_DIRTY		0x4		/* line is dirty */
241 #define	SB_ECSTATE_VALID	0x2		/* line is valid */
242 #define	SB_ECSTATE_DIRTY	0x1		/* line is dirty */
243 #define	HB_ECSTATE_VALID	0x2		/* line is valid */
244 #define	HB_ECSTATE_DIRTY	0x1		/* line is dirty */
245 
246 /*
247  * Constants representing the individual Spitfire (S), Sabre (SB) and
248  * Hummingbird (HB) state parity and address parity bits:
249  */
250 #define	S_ECSTATE_PARITY	0x8		/* tag state parity bit */
251 #define	S_EC_PARITY		0xF		/* all parity bits */
252 #define	SB_ECSTATE_PARITY	0x2		/* tag state parity bit */
253 #define	SB_EC_PARITY		0x3		/* all parity bits */
254 #define	HB_ECSTATE_PARITY	0x2		/* tag state parity bit */
255 #define	HB_EC_PARITY		0x3		/* all parity bits */
256 
257 #ifdef HUMMINGBIRD
258 
259 #define	HB_ESTAR_MODE		INT64_C(0x1FE0000F080)	/* estar mode reg */
260 #define	HB_MEM_CNTRL0		INT64_C(0x1FE0000F010)	/* mem control0 reg */
261 #define	HB_REFRESH_COUNT_MASK	0x7F00			/* mc0<14:8>: ref cnt */
262 #define	HB_REFRESH_COUNT_SHIFT	8			/* bits to shift */
263 #define	HB_REFRESH_INTERVAL	INT64_C(7800)		/* 7800 nsecs memory */
264 							/* refresh interval */
265 							/* works for all DIMM */
266 							/* same value as OBP */
267 #define	HB_REFRESH_CLOCKS_PER_COUNT	INT64_C(64)	/* cpu clks per count */
268 #define	HB_SELF_REFRESH_MASK	0x10000			/* mc0<16>: self ref */
269 #define	HB_SELF_REFRESH_SHIFT	16			/* bits to shift */
270 #define	HB_SELF_REFRESH_DISABLE	0			/* disable self ref */
271 #define	HB_SELF_REFRESH_ENABLE	1			/* enable self ref */
272 
273 #define	HB_ECLK_1	INT64_C(0x0000000000000000) 	/* 1/1 clock */
274 #define	HB_ECLK_2	INT64_C(0x0000000000000001) 	/* 1/2 clock */
275 #define	HB_ECLK_4	INT64_C(0x0000000000000003) 	/* 1/4 clock */
276 #define	HB_ECLK_6	INT64_C(0x0000000000000002) 	/* 1/6 clock */
277 #define	HB_ECLK_8	INT64_C(0x0000000000000004) 	/* 1/8 clock */
278 #define	HB_ECLK_MASK	(HB_ECLK_1|HB_ECLK_2|HB_ECLK_4|HB_ECLK_6|HB_ECLK_8)
279 
280 
281 /*
282  * UPA Configuration Register
283  *
284  * +--------------+----+------+------+----------+------+-------------+
285  * |     Resv     | RR |  DM  | ELIM |   PCON   | MID  |     PCAP    |
286  * +--------------+----+------+------+----------+------+-------------+
287  *  63          39  38  37..36 35..33 32......22 21..17 16..........0
288  *
289  */
290 
291 #define	HB_UPA_DMAP_DATA_BIT	36	/* loads and stores direct mapped */
292 #define	HB_UPA_DMAP_INSTR_BIT	37	/* instruction misses direct mapped */
293 #define	HB_UPA_RR_BIT		38	/* reset rand generator */
294 
295 #endif /* HUMMINGBIRD */
296 
297 /*
298  * The minimum size needed to ensure consistency on a virtually address
299  * cache.  Computed by taking the largest virtually indexed cache and dividing
300  * by its associativity.
301  */
302 #define	S_VAC_SIZE	0x4000
303 
304 #ifdef _KERNEL
305 
306 #ifndef _ASM
307 #include <sys/kstat.h>
308 
309 void	get_udb_errors(uint64_t *udbh, uint64_t *udbl);
310 
311 /*
312  * The scrub_misc structure contains miscellaneous bookeepping items for
313  * scrubbing the E$.
314  *
315  * Counter of outstanding E$ scrub requests. The counter for a given CPU id
316  * is atomically incremented and decremented _only_  on that CPU,
317  * to avoid cacheline ownership bouncing.
318  */
319 
320 typedef struct spitfire_scrub_misc {
321 	uint32_t	ec_scrub_outstanding;	/* outstanding reqs */
322 	int		ecache_flush_index;	/* offset into E$ for flush */
323 	int		ecache_busy;		/* keeps track if cpu busy */
324 	int		ecache_nlines;		/* no. of E$ lines */
325 	int		ecache_mirror;		/* E$ is mirrored */
326 	kstat_t		*ecache_ksp;		/* ptr to the kstat */
327 } spitfire_scrub_misc_t;
328 
329 /*
330  * Spitfire module private data structure. One of these is allocated for each
331  * valid cpu at setup time and is pointed to by the machcpu "cpu_private"
332  * pointer.
333  */
334 typedef struct spitfire_private {
335 	spitfire_scrub_misc_t	sfpr_scrub_misc;
336 	uint64_t		sfpr_scrub_afsr;
337 } spitfire_private_t;
338 
339 #endif /* !_ASM */
340 
341 #endif /* _KERNEL */
342 
343 #ifdef	__cplusplus
344 }
345 #endif
346 
347 #endif	/* _SYS_SPITREGS_H */
348