1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 1999 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include <sys/types.h> 30 #include <sys/param.h> 31 #include <sys/ddi.h> 32 #include <sys/sunddi.h> 33 #include <sys/ddi_impldefs.h> 34 #include <sys/obpdefs.h> 35 #include <sys/cmn_err.h> 36 #include <sys/errno.h> 37 #include <sys/debug.h> 38 #include <sys/fhc.h> 39 #include <sys/jtag.h> 40 #include <sys/ac.h> 41 #include <sys/machsystm.h> 42 #include <sys/cpu.h> 43 #include <sys/cpuvar.h> 44 45 /* 46 * Defines for data structures used only in this module. They will 47 * not be exported to external modules. 48 */ 49 50 /* 51 * Define the hardware structure of JTAG 52 */ 53 54 #define JTAG_CSR_BASE ((jtag_csr *)0xF0300000) 55 56 57 #define JTAG_CR 0x08000f0 58 #define JTAG_CMD 0x0800100 59 60 /* JTAG status flags */ 61 #define JTAG_BUSY_BIT 0x100 62 63 /* JTAG commands */ 64 #define JTAG_SEL_RING 0x6000 65 #define JTAG_SEL_DR 0x5050 66 #define JTAG_SEL_IR 0x5068 67 #define JTAG_SHIFT 0x00A0 68 #define JTAG_RUNIDLE 0x50C0 69 #define JTAG_IR_TO_DR 0x50E8 70 #define JTAG_DR_TO_IR 0x50F4 71 #define JTAG_TAP_RESET 0x50FF 72 73 74 /* 75 * Definitions of data types. 76 * 77 */ 78 79 /* 80 * Most routines in this interface return a negative value when 81 * an error occurs. In the normal case, the routines return a non-negative 82 * value, which may be of interest to the caller. The following enumeration 83 * provides the meaning of each error return code. 84 */ 85 86 /* 87 * When calling verify_jtag_chip, you must pass PRINT_ERR if you 88 * want the cmn_err call to occur. This is because sometimes 89 * when we verify rings, (checking for NPB's) we do not want to 90 * print error messages. 91 */ 92 #define PRINT_JTAG_ERR 5 93 94 /* 95 * You must pass in the proper chip masks when calling 96 * config board() 97 */ 98 #define AC_INIT 1 99 #define DCU1500_INIT 2 100 #define DCU1600_INIT 2 101 #define DCU1700_INIT 2 102 #define DCU1800_INIT 2 103 #define DCU1900_INIT 2 104 #define DCU2000_INIT 2 105 #define DCU2100_INIT 2 106 #define DCU2200_INIT 2 107 #define FHC_INIT 4 108 109 #define SYSIO_INIT 8 110 111 /* scan ring numbers */ 112 #define RING0 0 113 #define RING1 1 114 #define RING2 2 115 116 /* 117 * Scan ring 0 lengths. Boards are typed by their scan ring length. This 118 * is inherently flawed if a new board type has the same number of 119 * components as one of the original boards. 120 * 121 * The inherently flawed scenario now exists with the introduction 122 * of the soc+ versions of the 2-SBus and UPA/SBus boards. Argh... 123 */ 124 #define CPU_TYPE_LEN 12 /* CPU board ring length */ 125 #define IO_TYPE1_LEN 15 /* 2 sysio 1 HM */ 126 #define IO_TYPE2_LEN 14 /* 1 sysio 1 ffb */ 127 #define PCI_TYPE_LEN 16 /* PCI board ring length */ 128 #define PCI_TYPEA_LEN 110 /* PCI ISP off ring */ 129 #define PCI_TYPEB_LEN 104 /* PCI ISP in ring */ 130 #define DSK_TYPE_LEN 2 /* Disk board ring length */ 131 #define IO_TYPE4_LEN 126 /* 2 sysio soc+ */ 132 #define IO_TYPE5_LEN 110 /* 1 sysio 1 ffb soc+ */ 133 134 #define CPU_0_5_LEN 8 /* 0.5 Meg Module ring length */ 135 #define CPU_1_0_LEN 12 /* 1 Meg and 2 Meg ring length */ 136 #define FFB_SNG_LEN 6 /* Single bufferef FFB */ 137 #define FFB_DBL_LEN 18 /* Double buffered FFB */ 138 139 /* 140 * Component IDs of various SRAM chips. The only way to distinguish between 141 * 1M, 2M, and 4M Ecache is via the component IDs of the SRAMs. 142 */ 143 #define SRAM_256K 0x00000000 144 #define SRAM_128K 0x000090E3 145 #define SRAM_64K_1 0x000000E3 146 #define SRAM_64K_2 0x01901149 147 148 typedef enum { 149 JTAG_OK = 0, /* no error */ 150 JTAG_FAIL = -1, /* generic JTAG failure */ 151 TAP_TIMEOUT = -1, /* JTAG TAP state machine not responding */ 152 BAD_ARGS = -2, /* incorrect arguments passed by caller */ 153 BAD_CID = -3, /* JTAG component ID does not match */ 154 RING_BROKEN = -4, /* JTAG ring continuity test failed */ 155 INIT_MISMATCH = -5, /* State after initialization not expected */ 156 LENGTH_MISMATCH = -6 /* Ring length does not match expected */ 157 } jtag_error; 158 159 typedef u_short jtag_instruction; 160 typedef u_char jtag_ring; /* format is bbbb rrrr in binary */ 161 162 /* Internal macros */ 163 static int tap_issue_cmd(volatile u_int *, u_int); 164 165 /* TAP register access macros */ 166 167 /* NOTE the only status is the busy bit (8) */ 168 169 /* read the jtag data bits */ 170 #define jtag_data(reg, nbits) (*(reg) >> (32 - (nbits))) 171 172 #define JTAG_TIMEOUT 0x10000 173 174 #define TAP_DECLARE int timeout; 175 176 #define TAP_WAIT(reg) timeout = JTAG_TIMEOUT; \ 177 while ((*(reg) & JTAG_BUSY_BIT) != 0) \ 178 if ((--timeout) < 0) \ 179 return (TAP_TIMEOUT) 180 181 #define TAP_SHIFT(reg, data, nbits) \ 182 *(reg) = ((data<<16) | ((nbits-1)<<12) | JTAG_SHIFT); \ 183 TAP_WAIT(reg) 184 185 /* Error-checking macros to simplify the coding */ 186 187 #define TAP_ISSUE_CMD(reg, cmd, status) \ 188 status = tap_issue_cmd(reg, cmd); \ 189 if (status < 0) \ 190 return (status) 191 192 #define TAP_SHIFT_CONSTANT(reg, val, nbits, status) \ 193 status = tap_shift_constant(reg, val, nbits); \ 194 if (status < 0) \ 195 return (status) 196 197 #define TAP_SHIFT_SINGLE(reg, val, nbits, status) \ 198 status = tap_shift_single(reg, val, nbits); \ 199 if (status < 0) \ 200 return (status) 201 202 #define TAP_SHIFT_MULTIPLE(reg, in, nbits, out, status) \ 203 status = tap_shift_multiple(reg, in, nbits, out); \ 204 if (status < 0) \ 205 return (status) 206 207 /* 208 * A jtag_log_comp describes a component as seen by JTAG. 209 * 210 * Since there are multiple versions & revision for a single 211 * component, this can be a bit complicated... 212 * 213 * The implementation assumes that all components which can be used 214 * interchangeably have the exact same programming model regarding 215 * JTAG programming. Then, interchangeable components differ only by 216 * their component IDs. The field id points to a NULL-terminated list 217 * of component IDs. Allowable component IDs may differ only in the rev 218 * number, which must be higher than or equal to the one in the list. 219 * 220 * The init_pdesc field points to a byte string which describes how to 221 * initialize the component. The structure of this byte string is not 222 * exported (see the implementation of jtag_init_chip). 223 * 224 * The fmt_desc field points to a byte string which describes how to 225 * convert the scan-out format to the more usual DCSR format. The 226 * structure of this string is not exported (see the implementation 227 * of jtag_scanout_chip). 228 */ 229 230 typedef struct { 231 u_int *id; /* Pointer to component IDs, 0 if no CID */ 232 u_char ir_len; /* number of bits in instruction register */ 233 u_char dr_len; /* number of bits in DR for init/dump */ 234 jtag_instruction id_code; /* instruction to read component ID */ 235 jtag_instruction init_code; /* instruction to write parameters */ 236 jtag_instruction dump_code; /* instruction to read parameters */ 237 u_char *init_pdesc; /* initialization patch descriptors */ 238 u_char *fmt_desc; /* reformat descriptor */ 239 } jtag_log_comp; 240 241 242 /* A jtag_phys_comp describes a component position inside a ring */ 243 244 typedef struct { 245 jtag_log_comp *chip; /* pointer to chip descriptor */ 246 short ir_after; /* number of IR bits after chip in ring */ 247 short ir_before; /* number of IR bits before chip in ring */ 248 short by_after; /* number of bypass bits after chip in ring */ 249 short by_before; /* number of bypass bits before chip in ring */ 250 } jtag_phys_comp; 251 252 253 /* Board ring description */ 254 255 typedef struct { 256 int size; 257 jtag_phys_comp *components; 258 } jtag_ring_desc; 259 260 /* 261 * Initialization options 262 * 263 * These data types describe the options for each type of component 264 * internally to the jtag_init_*_ring routines. They can all be 265 * recast into arrays of unsigned integers. 266 * 267 * Note that these types DEPEND on the *_init_pdesc structures, which 268 * use indices to the components of the *_options types. As a result, 269 * the data structure & the type must be modified simultaneously, 270 * although this dependency is not immediately visible. This is ugly, 271 * but it makes the initialization routines much more readable. 272 */ 273 274 typedef struct { 275 u_int frozen; 276 u_int reset_a; 277 u_int reset_b; 278 u_int board_id; 279 u_int mask_hwerr; 280 u_int arb_fast; 281 u_int node_id; 282 u_int pcr_hi; 283 u_int pcr_lo; 284 u_int pcc_ctl1; 285 u_int pcc_ctl0; 286 u_int pcc_tctrl; 287 } ac_options; 288 289 struct ac_regs { 290 unsigned int bcsr; 291 unsigned int brscr; 292 unsigned int esr_hi; 293 unsigned int esr_lo; 294 unsigned int emr_hi; 295 unsigned int emr_lo; 296 unsigned int ccr; 297 unsigned int cntr_hi; 298 unsigned int cntr_lo; 299 }; 300 301 typedef struct { 302 u_int frozen; 303 u_int mask_pe; 304 u_int mask_oe; 305 } dc_options; 306 307 typedef struct { 308 u_int csr_hi; /* CSR 20:18 */ 309 u_int csr_mid; /* CSR 16:8 */ 310 u_int csr_midlo; /* CSR 6:4 */ 311 } fhc_options; 312 313 314 struct fhc_regs { 315 u_int por; 316 u_int csr; 317 u_int rcsr; 318 u_int bsr; 319 }; 320 321 /* Structure to capture the scan data from the bct8244's. */ 322 struct bct_fields { 323 u_int disk1_pres; 324 u_int disk0_pres; 325 u_int disk1_id; 326 u_int disk0_id; 327 }; 328 329 /* Collective type for *_options * */ 330 typedef u_int *jtag_opt; 331 332 /* 333 * The following definitions are the action flags used in the byte 334 * string which is used to describe component initialization. The 335 * only piece of code which understands those flags is jtag_init_chip. 336 * 337 * Initializing a component consists of scanning successive values 338 * into the component. The data for each pass is obtained by applying 339 * successive patches to a reference pattern. The patch descriptors 340 * are a byte string which form a succession of operations. The first 341 * byte of an operation is a set of flags defining the action: 342 */ 343 #define JTIN_INDEX 0x0F 344 #define JTIN_INSERT 0x10 345 #define JTIN_UPDATE 0x20 346 #define JTIN_COMPARE 0x40 347 #define JTIN_END 0x80 348 349 /* 350 * When JTIN_INSERT is specified, the flag byte is followed by 351 * two bytes indicating the lsb and msb of the field to be updated, and 352 * the JTIN_INDEX part of the flags indicate which value should be 353 * inserted: if JTIN_INDEX is zero, the value to insert is the next 354 * byte in the aray, extended to a 32-bit word; if JTIN_INDEX is 355 * non-zero, the value to insert is at word offset index in the patch 356 * array passed to jtag_init_chip. 357 */ 358 359 /* 360 * The fmt_desc field points to a reformat table which converts the 361 * scan-out format to the standard DSCR-style format. The format descriptor 362 * is a byte string, with special bytes indicating functional operations 363 * as indicated by bit fields in the following table: 364 */ 365 #define JTSO_END 0x80 /* end of table */ 366 #define JTSO_XTRACT 0x40 /* extract & merge [lsb, msb] */ 367 #define JTSO_ST 0x20 /* store & increment */ 368 #define JTSO_SHIFT 0x1F /* shift count for extract & merge */ 369 370 /* 371 * Function Declarations 372 */ 373 static void jtag_error_print(int, jtag_error); 374 static int jtag_get_comp_id(volatile u_int *, jtag_phys_comp *); 375 376 /* 377 * Bit-field manipulations 378 */ 379 static u_int jtag_bf_extract(u_char *s, int lsb, int msb); 380 static void jtag_bf_insert(u_char *s, int lsb, int msb, int value); 381 static void jtag_bf_zero(u_char *s, int nbits); 382 static int jtag_bf_cmp(u_char *s1, u_char *s2, int nbits); 383 384 /* 385 * Test-access port interface 386 */ 387 static int tap_wait(volatile u_int *); 388 static int tap_shift_single(volatile u_int *, int, int); 389 static int tap_shift_multiple(volatile u_int *, u_char *, int, u_char *); 390 391 /* 392 * Ring-level interface 393 */ 394 395 static int select_ring(volatile u_int *, jtag_ring, int); 396 static int jtag_rescan_IR_DR(volatile u_int *, jtag_phys_comp *, 397 jtag_instruction, u_char *, int, u_char *); 398 static int jtag_single_IR_DR(volatile u_int *, jtag_phys_comp *, 399 jtag_instruction, u_char *, int, u_char *); 400 static int jtag_ring_length(volatile u_int *, jtag_ring); 401 static int jtag_ring_ir_length(volatile u_int *, jtag_ring); 402 403 /* 404 * Component-level interface 405 */ 406 407 static int jtag_scanout_chip(volatile u_int *, jtag_ring, jtag_phys_comp *, 408 u_int *); 409 static int jtag_init_chip(volatile u_int *, jtag_ring, jtag_phys_comp *, 410 const u_int *, u_char *); 411 static jtag_phys_comp *find_chip(jtag_ring_desc *, jtag_log_comp *, int); 412 static void format_chip_data(u_char *, u_int *, u_char *); 413 static int jtag_init_ac(volatile u_int *, int, enum board_type); 414 415 /* 416 * Data tables. 417 * 418 * The JTAG implementation is data table driven. These tables describe 419 * the chip, ring, and board components. 420 */ 421 422 /* 423 * Data structures describing the scannable components 424 */ 425 426 static char jtag_err[] = "JTAG ERROR"; 427 428 /* Constants defining the IR lengths for each of the chips */ 429 430 #define IR_LEN 8 /* all sunfire asics, spitfire, and sdb are 8 bits */ 431 #define HM_LEN 4 /* happy meal is 4 bits */ 432 #define NDP_LEN 2 /* ndp83840 is 2 bits */ 433 #define SOC_LEN 4 /* SOC is 4 bits */ 434 #define SOCPLUS_LEN 8 /* SOC+ is 8 bits */ 435 #define SIO_LEN 16 /* sysio asic is 16 bits */ 436 #define PSYO_LEN 4 /* psycho asic is 4 bits */ 437 #define CHEO_LEN 4 /* cheerio asic is 4 bits */ 438 #define EC_LEN 3 /* ecache tag rams is 3 bits each */ 439 440 #define FFB_LEN 16 /* ffb module is 16 bits */ 441 #define THREED_LEN 4 /* IR length for three D rams */ 442 #define BT498_LEN 4 /* IR length for bt 498 chip (ramdac) */ 443 444 445 446 /* Standard instructions */ 447 #define IDCODE 0xFFFE 448 #define INITCODE 0xbe 449 #define DUMPCODE 0xbe 450 451 #define CID_TO_REV(cid) ((cid) >> 28) 452 453 /* ASIC Jag IDs */ 454 static u_int cid_sf[] = { 455 0x0002502f, 456 0 457 }; 458 459 static u_int cid_sdb[] = { 460 0x0002602f, 461 0 462 }; 463 464 static u_int cid_fbc[] = { 465 0x1241906d, 466 0 467 }; 468 469 static u_int cid_lvt[] = { 470 0x0001d02f, 471 0 472 }; 473 474 static u_int cid_3dram[] = { 475 0X0E9A103B, 476 0 477 }; 478 479 static u_int cid_bt498[] = { 480 0x0001d02f, 481 0 482 }; 483 484 static u_int cid_sio[] = { 485 0x0ef0703b, 486 0 487 }; 488 489 static u_int cid_hm[] = { 490 0x01792045, 491 0 492 }; 493 494 static u_int cid_ac[] = { 495 0x10f9e07d, 496 0 497 }; 498 499 static u_int cid_dc[] = { 500 0x10f9f07d, 501 0 502 }; 503 504 static u_int cid_fhc[] = { 505 0x10fa007d, 506 0 507 }; 508 509 static u_int cid_psyo[] = { 510 0x3195401d, 511 0 512 }; 513 514 static u_int cid_cheo[] = { 515 0x11791022, 516 0 517 }; 518 519 520 /* 521 * NOTE the following chips are ignored for the most part by the POST JTAG 522 * If if is later determined that scan data may be of interest then we need 523 * to fill in the blanks below. 524 */ 525 526 static u_char ec_init_pdesc[] = { 527 JTIN_END|JTIN_INSERT|0, 0, 0, 0x0 528 }; 529 530 static u_char ec_fmt[] = { 531 JTSO_ST|JTSO_XTRACT|JTSO_END| 0, 0, 4 532 }; 533 534 static u_char sio_init_pdesc[] = { 535 JTIN_END|JTIN_INSERT|0, 0, 0, 0x0 536 }; 537 538 static u_char sio_fmt[] = { 539 JTSO_ST|JTSO_XTRACT|JTSO_END| 0, 0, 4 540 }; 541 542 static u_char psyo_init_pdesc[] = { 543 JTIN_END|JTIN_INSERT|0, 0, 0, 0x0 544 }; 545 546 static u_char psyo_fmt[] = { 547 JTSO_ST|JTSO_XTRACT|JTSO_END| 0, 0, 4 548 }; 549 550 static u_char hm_init_pdesc[] = { 551 JTIN_END|JTIN_INSERT|0, 0, 0, 0x0 552 }; 553 554 static u_char hm_fmt[] = { 555 JTSO_ST|JTSO_XTRACT|JTSO_END| 0, 0, 4 556 }; 557 558 static u_char ndp_init_pdesc[] = { 559 JTIN_END|JTIN_INSERT|0, 0, 0, 0x0 560 }; 561 562 static u_char ndp_fmt[] = { 563 JTSO_ST|JTSO_XTRACT|JTSO_END| 0, 0, 4 564 }; 565 566 static u_char cheo_init_pdesc[] = { 567 JTIN_END|JTIN_INSERT|0, 0, 0, 0x0 568 }; 569 570 static u_char cheo_fmt[] = { 571 JTSO_ST|JTSO_XTRACT|JTSO_END| 0, 0, 4 572 }; 573 574 575 /* The main ASCIS of interest are the AC, DC and FHC */ 576 577 /* 578 * The initialization of DC is as follows: 579 * 580 * Do NOT change the following data structure without checking 581 * _options in jtag_private.h, which depends on it. 582 */ 583 static u_char dc_init_pdesc[] = { 584 JTIN_INSERT|1, 0, 0, /* NFZN */ 585 JTIN_INSERT|2, 4, 4, /* Mask PE */ 586 JTIN_INSERT|3, 3, 3, /* Mask OE */ 587 JTIN_INSERT|0, 1, 2, 3, /* W1C Errors */ 588 JTIN_END|JTIN_UPDATE, 589 }; 590 591 static u_char dc_fmt[] = { 592 JTSO_ST|JTSO_XTRACT|JTSO_END| 0, 0, 4 /* DC[4:0] */ 593 }; 594 595 /* 596 * The initialization of AC is as follows: 597 * 598 * Do NOT change the following data structure without checking 599 * _options in jtag_private.h, which depends on it. 600 */ 601 static u_char ac_init_pdesc[] = { 602 JTIN_INSERT|0, 161, 161, 1, /* BOARD ADDR 40 */ 603 JTIN_INSERT|7, 159, 160, /* BOARD ADDR 39:38, wfi node */ 604 JTIN_INSERT|4, 155, 158, /* BOARD ADDR 37:34 */ 605 JTIN_INSERT|4, 151, 154, /* BOARD ID */ 606 JTIN_INSERT|6, 146, 146, /* ARB_FAST */ 607 JTIN_INSERT|1, 134, 134, /* NFZN */ 608 JTIN_INSERT|0, 133, 133, 0, /* ENWAKPOR */ 609 JTIN_INSERT|2, 135, 135, /* Reset B */ 610 JTIN_INSERT|3, 136, 136, /* Reset A */ 611 JTIN_INSERT|0, 99, 106, 0xff, /* W1C Errors */ 612 JTIN_INSERT|0, 107, 114, 0xff, /* W1C Errors */ 613 JTIN_INSERT|0, 115, 122, 0xff, /* W1C Errors */ 614 JTIN_INSERT|0, 123, 130, 0xff, /* W1C Errors */ 615 JTIN_INSERT|0, 131, 132, 0xff, /* W1C Errors */ 616 JTIN_INSERT|5, 88, 98, /* Error Masks */ 617 JTIN_INSERT|12, 76, 87, /* CNT1_CTL_<27:16> */ 618 JTIN_INSERT|10, 70, 75, /* CNT1_CTL <13:8> */ 619 JTIN_INSERT|11, 64, 69, /* CNT0_CTL <5:0> */ 620 JTIN_INSERT|8, 32, 63, /* CNT1 */ 621 JTIN_INSERT|9, 0, 31, /* CNT0 */ 622 JTIN_END|JTIN_UPDATE, /* Clears counters */ 623 }; 624 625 static u_char ac_fmt[] = { 626 JTSO_XTRACT|17, 148, 162, /* BCSR[31:17] */ 627 JTSO_XTRACT|15, 147, 147, /* BSCR[15] */ 628 JTSO_XTRACT|5, 138, 146, /* BSCR[13:5] */ 629 JTSO_ST|JTSO_XTRACT|0, 134, 137, /* BSCR[3:0] */ 630 JTSO_ST|JTSO_XTRACT|22, 133, 133, /* BRSCR[22] */ 631 JTSO_XTRACT|16, 131, 132, /* ESR[49:48] */ 632 JTSO_XTRACT|8, 124, 130, /* ESR[46:40] */ 633 JTSO_XTRACT|4, 122, 123, /* ESR[37:36] */ 634 JTSO_ST|JTSO_XTRACT|0, 120, 121, /* ESR[33:32] */ 635 JTSO_XTRACT|28, 116, 119, /* ESR[31:28] */ 636 JTSO_XTRACT|24, 115, 115, /* ESR[24] */ 637 JTSO_XTRACT|20, 112, 114, /* ESR[22:20] */ 638 JTSO_XTRACT|12, 107, 111, /* ESR[16:12] */ 639 JTSO_XTRACT|4, 101, 106, /* ESR[9:4] */ 640 JTSO_ST|JTSO_XTRACT|0, 99, 100, /* ESR[1:0] */ 641 JTSO_XTRACT|16, 97, 98, /* EMR[49:48] */ 642 JTSO_XTRACT|8, 96, 96, /* EMR[40] */ 643 JTSO_ST|JTSO_XTRACT|4, 94, 95, /* EMR[37:36] */ 644 JTSO_XTRACT|28, 93, 93, /* EMR[28] */ 645 JTSO_XTRACT|24, 92, 92, /* EMR[24] */ 646 JTSO_XTRACT|20, 91, 91, /* EMR[20] */ 647 JTSO_XTRACT|12, 90, 90, /* EMR[12] */ 648 JTSO_XTRACT|8, 89, 89, /* EMR[8] */ 649 JTSO_ST|JTSO_XTRACT|4, 88, 88, /* EMR[4] */ 650 JTSO_XTRACT|16, 76, 87, /* CCR[27:16] */ 651 JTSO_XTRACT|8, 70, 75, /* CCR[13:8] */ 652 JTSO_ST|JTSO_XTRACT|0, 64, 69, /* CCR[5:0] */ 653 JTSO_ST|JTSO_XTRACT|0, 32, 63, /* CNT[63:32] */ 654 JTSO_ST|JTSO_XTRACT|JTSO_END|0, 0, 31 /* CNT[31:0] */ 655 }; 656 657 /* 658 */ 659 660 /* 661 * The following structure has three variable elements, as noted 662 * by the 1,2 and 3 digits or'ed in with the JTIN_INSERT flags. 663 * The number nad position of these elements must correspond with 664 * the fhc_ structure apssed into fhc_chip_init. 665 */ 666 static u_char fhc_init_pdesc[] = { 667 JTIN_INSERT|0, 41, 41, 0, /* POR */ 668 JTIN_INSERT|1, 38, 40, /* CSR[20:18] */ 669 JTIN_INSERT|2, 29, 37, /* CSR[16:8] */ 670 JTIN_INSERT|3, 26, 28, /* CSR[6:4] */ 671 JTIN_INSERT|0, 24, 25, 0x0, /* CSR[1:0] */ 672 JTIN_INSERT|0, 16, 23, 0x0, /* RCSR[31:24] */ 673 JTIN_INSERT|0, 2, 15, 0x0, /* BSR[18:5] */ 674 JTIN_INSERT|0, 0, 1, 0x0, /* BSR[1:0] */ 675 JTIN_END|JTIN_UPDATE, 676 }; 677 678 static u_char fhc_fmt[] = { 679 JTSO_ST|JTSO_XTRACT|0, 41, 41, /* POR State */ 680 JTSO_XTRACT|18, 38, 40, /* CSR[20:18] */ 681 JTSO_XTRACT|8, 29, 37, /* CSR[16:8] */ 682 JTSO_XTRACT|4, 26, 28, /* CSR[6:4] */ 683 JTSO_ST|JTSO_XTRACT|0, 24, 25, /* CSR[1:0] */ 684 JTSO_ST|JTSO_XTRACT|24, 16, 23, /* RCSR[31:24] */ 685 JTSO_XTRACT|5, 2, 15, /* BSR[18:5] */ 686 JTSO_ST|JTSO_XTRACT|JTSO_END|0, 0, 1, /* BSR[1:0] */ 687 }; 688 689 690 static u_char bct8244_fmt[] = { 691 JTSO_ST|JTSO_XTRACT|0, 17, 17, /* Disk 1 present */ 692 JTSO_ST|JTSO_XTRACT|0, 16, 16, /* Disk 0 present */ 693 JTSO_ST|JTSO_XTRACT|0, 12, 15, /* Disk 1 Target */ 694 JTSO_ST|JTSO_XTRACT|JTSO_END|0, 8, 11, /* Disk 0 Target */ 695 }; 696 697 /* A jtag_log_comp describes a component as seen by JTAG. */ 698 699 static jtag_log_comp chip_ac = { 700 cid_ac, 701 IR_LEN, 163, 702 IDCODE, INITCODE, DUMPCODE, 703 ac_init_pdesc, ac_fmt 704 }; 705 706 static jtag_log_comp chip_bct8244 = { 707 0, 708 IR_LEN, 18, 709 0x2, 0x2, 0x2, 710 NULL, bct8244_fmt 711 }; 712 713 static jtag_log_comp chip_dc = { 714 cid_dc, 715 IR_LEN, 5, 716 IDCODE, INITCODE, DUMPCODE, 717 dc_init_pdesc, dc_fmt 718 }; 719 720 static jtag_log_comp chip_fhc = { 721 cid_fhc, 722 IR_LEN, 42, 723 IDCODE, INITCODE, DUMPCODE, 724 fhc_init_pdesc, fhc_fmt 725 }; 726 727 static jtag_log_comp chip_ec = { 728 0, 729 EC_LEN, 42, 730 1, INITCODE, IDCODE, 731 ec_init_pdesc, ec_fmt 732 }; 733 734 static jtag_log_comp chip_fbc = { 735 cid_fbc, 736 FFB_LEN, 42, 737 0xb000, 0xb000, 0xb000, 738 NULL, NULL 739 }; 740 741 static jtag_log_comp chip_lvt = { 742 cid_lvt, 743 IR_LEN, 42, 744 IDCODE, INITCODE, DUMPCODE, 745 NULL, NULL 746 }; 747 748 static jtag_log_comp chip_3dram = { 749 cid_3dram, 750 THREED_LEN, 42, 751 IDCODE, INITCODE, DUMPCODE, 752 NULL, NULL 753 }; 754 755 static jtag_log_comp chip_bt498 = { 756 cid_bt498, 757 BT498_LEN, 42, 758 IDCODE, INITCODE, DUMPCODE, 759 NULL, NULL 760 }; 761 762 static jtag_log_comp chip_sio = { 763 cid_sio, 764 SIO_LEN, 42, 765 0xb000, 0xb000, 0xb000, 766 sio_init_pdesc, sio_fmt 767 }; 768 769 static jtag_log_comp chip_hm = { 770 cid_hm, 771 HM_LEN, 42, 772 0xe, 0xe, 0xe, 773 hm_init_pdesc, hm_fmt 774 }; 775 776 static jtag_log_comp chip_ndp = { 777 0, 778 NDP_LEN, 42, 779 2, 2, 2, 780 ndp_init_pdesc, ndp_fmt 781 }; 782 783 static jtag_log_comp chip_soc = { 784 0, 785 SOC_LEN, 42, 786 4, 4, 4, 787 NULL, NULL 788 }; 789 790 static jtag_log_comp chip_socplus = { 791 0, 792 SOCPLUS_LEN, 42, 793 0xfe, 4, 4, 794 NULL, NULL 795 }; 796 797 static jtag_log_comp chip_spitfire = { 798 cid_sf, 799 IR_LEN, 42, 800 0xfe, 0xfe, 0xfe, 801 NULL, NULL 802 }; 803 804 805 static jtag_log_comp chip_sdb = { 806 cid_sdb, 807 IR_LEN, 42, 808 0xfe, 0xfe, 0xfe, 809 NULL, NULL 810 }; 811 812 static jtag_log_comp chip_psyo = { 813 cid_psyo, 814 PSYO_LEN, 42, 815 0xb000, 0xb000, 0xb000, 816 psyo_init_pdesc, psyo_fmt 817 }; 818 819 static jtag_log_comp chip_cheo = { 820 cid_cheo, 821 CHEO_LEN, 42, 822 0xb000, 0xb000, 0xb000, 823 cheo_init_pdesc, cheo_fmt 824 }; 825 826 /* 827 * Ring descriptions for sunfire boards 828 * 829 * For each ring, there is a generic type descriptor which describes 830 * the order of chips in the static data structure describing the 831 * ring. 832 * 833 * Rings are described by an array of physical components, and are 834 * recast into the specific ring type by routines which use them, see 835 * for example the jtag_init_*_ring routines. 836 * 837 * Although the ring data structures are declared as jtag_phys_comp[], 838 * the components must be ordered as required by the corresponding 839 * *_*_ring type (in jtag_private.h). 840 */ 841 842 /* 843 * Data structures describing the system board rings 844 */ 845 846 static jtag_phys_comp cpu_sysbd_ring_components[] = { 847 { &chip_ac, 11*IR_LEN, 0, 11, 0 }, /* AC */ 848 { &chip_dc, 10*IR_LEN, 1*IR_LEN, 10, 1 }, /* DC 1 */ 849 { &chip_dc, 9*IR_LEN, 2*IR_LEN, 9, 2 }, /* DC 2 */ 850 { &chip_dc, 8*IR_LEN, 3*IR_LEN, 8, 3 }, /* DC 3 */ 851 { &chip_dc, 7*IR_LEN, 4*IR_LEN, 7, 4 }, /* DC 4 */ 852 { &chip_dc, 6*IR_LEN, 5*IR_LEN, 6, 5 }, /* DC 5 */ 853 { &chip_dc, 5*IR_LEN, 6*IR_LEN, 5, 6 }, /* DC 6 */ 854 { &chip_dc, 4*IR_LEN, 7*IR_LEN, 4, 7 }, /* DC 7 */ 855 { &chip_dc, 3*IR_LEN, 8*IR_LEN, 3, 8 }, /* DC 8 */ 856 { &chip_fhc, 2*IR_LEN, 9*IR_LEN, 2, 9 }, /* FHC */ 857 { &chip_ec, 1*IR_LEN, 10*IR_LEN, 1, 10 }, /* RAM 0 */ 858 { &chip_ec, 0*IR_LEN, 11*IR_LEN, 0, 11 }, /* RAM 1 */ 859 }; 860 861 static jtag_ring_desc cpu_sysbd_ring = { 862 12, cpu_sysbd_ring_components 863 }; 864 865 866 static jtag_phys_comp cpu_mod_1m_ring_components[] = { 867 { &chip_spitfire, 43, 0, 11, 0 }, /* Spitfire */ 868 { &chip_ec, 40, 8, 10, 1 }, /* Parity chip */ 869 { &chip_ec, 37, 11, 9, 2 }, /* Byte 0 */ 870 { &chip_ec, 34, 14, 8, 3 }, /* Byte 1 */ 871 { &chip_ec, 31, 17, 7, 4 }, /* Byte 2 */ 872 { &chip_ec, 28, 20, 6, 5 }, /* Byte 3 */ 873 { &chip_ec, 25, 23, 5, 6 }, /* Byte 4 */ 874 { &chip_ec, 22, 26, 4, 7 }, /* Byte 5 */ 875 { &chip_ec, 19, 29, 3, 8 }, /* Byte 6 */ 876 { &chip_ec, 16, 32, 2, 9 }, /* Byte 7 */ 877 { &chip_sdb, 8, 35, 1, 10 }, /* SDB */ 878 { &chip_sdb, 0, 43, 0, 11 }, /* SDB */ 879 }; 880 881 static jtag_ring_desc cpu_mod_1m_ring = { 882 12, cpu_mod_1m_ring_components 883 }; 884 885 static jtag_phys_comp cpu_mod_ring_components[] = { 886 { &chip_spitfire, 31, 0, 7, 0 }, /* Spitfire */ 887 { &chip_ec, 28, 8, 6, 1 }, /* Parity chip */ 888 { &chip_ec, 25, 11, 5, 2 }, /* Byte 0 */ 889 { &chip_ec, 22, 14, 4, 3 }, /* Byte 1 */ 890 { &chip_ec, 19, 17, 3, 4 }, /* Byte 2 */ 891 { &chip_ec, 16, 20, 2, 5 }, /* Byte 3 */ 892 { &chip_sdb, 8, 23, 1, 6 }, /* SDB */ 893 { &chip_sdb, 0, 31, 0, 7 }, /* SDB */ 894 }; 895 896 static jtag_ring_desc cpu_mod_ring = { 897 8, cpu_mod_ring_components 898 }; 899 900 static jtag_phys_comp io1_sysbd_ring_components[] = { 901 { &chip_ac, 114, 0, 14, 0 }, /* AC */ 902 { &chip_dc, 106, 8, 13, 1 }, /* DC 1 */ 903 { &chip_dc, 98, 16, 12, 2 }, /* DC 2 */ 904 { &chip_dc, 90, 24, 11, 3 }, /* DC 3 */ 905 { &chip_dc, 82, 32, 10, 4 }, /* DC 4 */ 906 { &chip_dc, 74, 40, 9, 5 }, /* DC 5 */ 907 { &chip_dc, 66, 48, 8, 6 }, /* DC 6 */ 908 { &chip_dc, 58, 56, 7, 7 }, /* DC 7 */ 909 { &chip_dc, 50, 64, 6, 8 }, /* DC 8 */ 910 { &chip_fhc, 42, 72, 5, 9 }, /* FHC */ 911 { &chip_sio, 26, 80, 4, 10 }, /* SIO 0 */ 912 { &chip_sio, 10, 96, 3, 11 }, /* SIO 1 */ 913 { &chip_hm, 6, 112, 2, 12 }, /* HM */ 914 { &chip_ndp, 4, 116, 1, 13 }, /* NDP */ 915 { &chip_soc, 0, 118, 0, 14 }, /* SOC */ 916 }; 917 918 static jtag_phys_comp io2_sysbd_ring_components[] = { 919 { &chip_ac, 98, 0, 13, 0 }, /* AC */ 920 { &chip_dc, 90, 8, 12, 1 }, /* DC 1 */ 921 { &chip_dc, 82, 16, 11, 2 }, /* DC 2 */ 922 { &chip_dc, 74, 24, 10, 3 }, /* DC 3 */ 923 { &chip_dc, 66, 32, 9, 4 }, /* DC 4 */ 924 { &chip_dc, 58, 40, 8, 5 }, /* DC 5 */ 925 { &chip_dc, 50, 48, 7, 6 }, /* DC 6 */ 926 { &chip_dc, 42, 56, 6, 7 }, /* DC 7 */ 927 { &chip_dc, 34, 64, 5, 8 }, /* DC 8 */ 928 { &chip_fhc, 26, 72, 4, 9 }, /* FHC */ 929 { &chip_sio, 10, 80, 3, 10 }, /* SIO */ 930 { &chip_hm, 6, 96, 2, 11 }, /* HM */ 931 { &chip_ndp, 4, 100, 1, 12 }, /* NDP */ 932 { &chip_soc, 0, 102, 0, 13 }, /* SOC */ 933 }; 934 935 static jtag_phys_comp io1plus_sysbd_ring_components[] = { 936 { &chip_ac, 118, 0, 14, 0 }, /* AC */ 937 { &chip_dc, 110, 8, 13, 1 }, /* DC 1 */ 938 { &chip_dc, 102, 16, 12, 2 }, /* DC 2 */ 939 { &chip_dc, 94, 24, 11, 3 }, /* DC 3 */ 940 { &chip_dc, 86, 32, 10, 4 }, /* DC 4 */ 941 { &chip_dc, 78, 40, 9, 5 }, /* DC 5 */ 942 { &chip_dc, 70, 48, 8, 6 }, /* DC 6 */ 943 { &chip_dc, 62, 56, 7, 7 }, /* DC 7 */ 944 { &chip_dc, 54, 64, 6, 8 }, /* DC 8 */ 945 { &chip_fhc, 46, 72, 5, 9 }, /* FHC */ 946 { &chip_sio, 30, 80, 4, 10 }, /* SIO 0 */ 947 { &chip_sio, 14, 96, 3, 11 }, /* SIO 1 */ 948 { &chip_hm, 10, 112, 2, 12 }, /* HM */ 949 { &chip_ndp, 8, 116, 1, 13 }, /* NDP */ 950 { &chip_socplus, 0, 118, 0, 14 }, /* SOC+ */ 951 }; 952 953 static jtag_phys_comp io2plus_sysbd_ring_components[] = { 954 { &chip_ac, 102, 0, 13, 0 }, /* AC */ 955 { &chip_dc, 94, 8, 12, 1 }, /* DC 1 */ 956 { &chip_dc, 86, 16, 11, 2 }, /* DC 2 */ 957 { &chip_dc, 78, 24, 10, 3 }, /* DC 3 */ 958 { &chip_dc, 70, 32, 9, 4 }, /* DC 4 */ 959 { &chip_dc, 62, 40, 8, 5 }, /* DC 5 */ 960 { &chip_dc, 54, 48, 7, 6 }, /* DC 6 */ 961 { &chip_dc, 46, 56, 6, 7 }, /* DC 7 */ 962 { &chip_dc, 38, 64, 5, 8 }, /* DC 8 */ 963 { &chip_fhc, 30, 72, 4, 9 }, /* FHC */ 964 { &chip_sio, 14, 80, 3, 10 }, /* SIO */ 965 { &chip_hm, 10, 96, 2, 11 }, /* HM */ 966 { &chip_ndp, 8, 100, 1, 12 }, /* NDP */ 967 { &chip_socplus, 0, 102, 0, 13 }, /* SOC+ */ 968 }; 969 970 static jtag_phys_comp io3_sysbd_ring_components[] = { 971 { &chip_ac, 102, 0, 15, 0 }, /* AC */ 972 { &chip_dc, 94, 8, 14, 1 }, /* DC 1 */ 973 { &chip_dc, 86, 16, 13, 2 }, /* DC 2 */ 974 { &chip_dc, 78, 24, 12, 3 }, /* DC 3 */ 975 { &chip_dc, 70, 32, 11, 4 }, /* DC 4 */ 976 { &chip_dc, 62, 40, 10, 5 }, /* DC 5 */ 977 { &chip_dc, 54, 48, 9, 6 }, /* DC 6 */ 978 { &chip_dc, 46, 56, 8, 7 }, /* DC 7 */ 979 { &chip_dc, 38, 64, 7, 8 }, /* DC 8 */ 980 { &chip_fhc, 30, 72, 6, 9 }, /* FHC */ 981 { &chip_psyo, 26, 80, 5, 10 }, /* PSYO 0 */ 982 { &chip_cheo, 22, 84, 4, 11 }, /* CHEO */ 983 { &chip_ndp, 20, 88, 3, 12 }, /* NDP */ 984 { &chip_psyo, 16, 90, 2, 13 }, /* PSYO 1 */ 985 { &chip_bct8244, 8, 94, 1, 14 }, /* BCT 8244 */ 986 { &chip_bct8244, 0, 102, 0, 15 }, /* BCT 8244 */ 987 }; 988 989 static jtag_phys_comp dsk_sysbd_ring_components[] = { 990 { &chip_bct8244, 8, 0, 1, 0 }, /* BCT 8244 */ 991 { &chip_fhc, 0, 8, 0, 1 }, /* FHC */ 992 }; 993 994 static jtag_ring_desc io1_sysbd_ring = { 995 15, io1_sysbd_ring_components 996 }; 997 998 static jtag_ring_desc io1plus_sysbd_ring = { 999 15, io1plus_sysbd_ring_components 1000 }; 1001 1002 static jtag_ring_desc io2_sysbd_ring = { 1003 14, io2_sysbd_ring_components 1004 }; 1005 1006 static jtag_ring_desc io2plus_sysbd_ring = { 1007 14, io2plus_sysbd_ring_components 1008 }; 1009 1010 static jtag_ring_desc io3_sysbd_ring = { 1011 16, io3_sysbd_ring_components 1012 }; 1013 1014 static jtag_ring_desc dsk_sysbd_ring = { 1015 2, dsk_sysbd_ring_components 1016 }; 1017 1018 /* 1019 * Ring descriptors for single and double buffered FFB boards. 1020 * Note - Only the FBC has a component ID register. None of the 1021 * other chips on the FFB board has one, so do not check them. 1022 */ 1023 static jtag_phys_comp ffb_sngl_ring_components[] = { 1024 { &chip_fbc, 20, 0, 5, 0 }, /* FBC */ 1025 { &chip_3dram, 16, 16, 4, 1 }, /* 3DRAM */ 1026 { &chip_3dram, 12, 20, 3, 2 }, /* 3DRAM */ 1027 { &chip_3dram, 8, 24, 2, 3 }, /* 3DRAM */ 1028 { &chip_3dram, 4, 28, 1, 4 }, /* 3DRAM */ 1029 { &chip_bt498, 0, 32, 0, 5 }, /* RAMDAC */ 1030 }; 1031 1032 static jtag_phys_comp ffb_dbl_ring_components[] = { 1033 { &chip_fbc, 84, 0, 17, 0 }, /* FBC */ 1034 { &chip_lvt, 76, 16, 16, 1 }, /* LVT */ 1035 { &chip_lvt, 68, 24, 15, 2 }, /* LVT */ 1036 { &chip_lvt, 60, 32, 14, 3 }, /* LVT */ 1037 { &chip_lvt, 52, 40, 13, 4 }, /* LVT */ 1038 { &chip_3dram, 48, 48, 12, 5 }, /* 3DRAM */ 1039 { &chip_3dram, 44, 52, 11, 6 }, /* 3DRAM */ 1040 { &chip_3dram, 40, 56, 10, 7 }, /* 3DRAM */ 1041 { &chip_3dram, 36, 60, 9, 8 }, /* 3DRAM */ 1042 { &chip_3dram, 32, 64, 8, 9 }, /* 3DRAM */ 1043 { &chip_3dram, 28, 68, 7, 10 }, /* 3DRAM */ 1044 { &chip_3dram, 24, 72, 6, 11 }, /* 3DRAM */ 1045 { &chip_3dram, 20, 76, 5, 12 }, /* 3DRAM */ 1046 { &chip_3dram, 16, 80, 4, 13 }, /* 3DRAM */ 1047 { &chip_3dram, 12, 84, 3, 14 }, /* 3DRAM */ 1048 { &chip_3dram, 8, 88, 2, 15 }, /* 3DRAM */ 1049 { &chip_3dram, 4, 92, 1, 16 }, /* 3DRAM */ 1050 { &chip_bt498, 0, 96, 0, 17 }, /* RAMDAC */ 1051 }; 1052 1053 static jtag_ring_desc ffb_sngl_ring = { 1054 6, ffb_sngl_ring_components 1055 }; 1056 1057 static jtag_ring_desc ffb_dbl_ring = { 1058 18, ffb_dbl_ring_components 1059 }; 1060 1061 /* 1062 * Board descriptions 1063 */ 1064 1065 static jtag_ring_desc *cpu_system_board[] = { 1066 &cpu_sysbd_ring, /* Ring 0 */ 1067 &cpu_mod_ring, /* Ring 1 */ 1068 &cpu_mod_ring, /* Ring 2 */ 1069 }; 1070 1071 static jtag_ring_desc *io1_system_board[] = { 1072 &io1_sysbd_ring, /* Ring 0 */ 1073 (jtag_ring_desc *) NULL, /* Ring 1 */ 1074 (jtag_ring_desc *) NULL, /* Ring 2 */ 1075 }; 1076 1077 static jtag_ring_desc *io1plus_system_board[] = { 1078 &io1plus_sysbd_ring, /* Ring 0 */ 1079 (jtag_ring_desc *) NULL, /* Ring 1 */ 1080 (jtag_ring_desc *) NULL, /* Ring 2 */ 1081 }; 1082 1083 static jtag_ring_desc *io2_system_board[] = { 1084 &io2_sysbd_ring, /* Ring 0 */ 1085 (jtag_ring_desc *) NULL, /* Ring 1 (ffb) */ 1086 (jtag_ring_desc *) NULL, /* Ring 2 */ 1087 }; 1088 1089 static jtag_ring_desc *io2plus_system_board[] = { 1090 &io2plus_sysbd_ring, /* Ring 0 */ 1091 (jtag_ring_desc *) NULL, /* Ring 1 (ffb) */ 1092 (jtag_ring_desc *) NULL, /* Ring 2 */ 1093 }; 1094 1095 static jtag_ring_desc *io3_system_board[] = { 1096 &io3_sysbd_ring, /* Ring 0 */ 1097 (jtag_ring_desc *) NULL, /* Ring 1 */ 1098 (jtag_ring_desc *) NULL, /* Ring 2 */ 1099 }; 1100 1101 static jtag_ring_desc *disk_system_board[] = { 1102 &dsk_sysbd_ring, /* Ring 0 */ 1103 (jtag_ring_desc *) NULL, /* Ring 1 */ 1104 (jtag_ring_desc *) NULL, /* Ring 2 */ 1105 }; 1106 1107 /* 1108 * Function Definitions: 1109 * --------------------- 1110 */ 1111 1112 /* For sunfire there will be a ring descriptor for each type of board */ 1113 static jtag_ring_desc * 1114 get_ring_descriptor_bytype(int ring, enum board_type type) 1115 { 1116 1117 switch (type) { 1118 case CPU_BOARD: 1119 return (cpu_system_board[ring & 0xf]); 1120 1121 case IO_2SBUS_BOARD: 1122 return (io1_system_board[ring & 0xf]); 1123 1124 case IO_2SBUS_SOCPLUS_BOARD: 1125 return (io1plus_system_board[ring & 0xf]); 1126 1127 case IO_SBUS_FFB_BOARD: 1128 return (io2_system_board[ring & 0xf]); 1129 1130 case IO_SBUS_FFB_SOCPLUS_BOARD: 1131 return (io2plus_system_board[ring & 0xf]); 1132 1133 case IO_PCI_BOARD: 1134 return (io3_system_board[ring & 0xf]); 1135 1136 case DISK_BOARD: 1137 return (disk_system_board[ring & 0xf]); 1138 1139 default: 1140 return (NULL); 1141 } 1142 } 1143 1144 static void 1145 jtag_check_plus_board( 1146 volatile u_int *jreg, 1147 jtag_ring ring, 1148 jtag_phys_comp *comp, 1149 sysc_cfga_stat_t *sc) 1150 { 1151 struct fhc_regs fhc_data; 1152 1153 /* 1154 * the FHC Board Status Register indicates whether 1155 * the board 100 Mhz capable or not. 1156 */ 1157 fhc_data.bsr = (u_int)0xffffffff; 1158 1159 if ((jtag_scanout_chip(jreg, ring, comp, (u_int *)&fhc_data) >= 0) && 1160 (FHC_BSR_TO_BD(fhc_data.bsr) == sc->board) && 1161 ISPLUSBRD(fhc_data.bsr)) 1162 sc->plus_board = 1; 1163 } 1164 1165 /* 1166 * Returns (positive) board type if something detected, including 1167 * UNKNOWN_BOARD. 1168 * Returns -1 if nothing there. 1169 */ 1170 enum board_type 1171 jtag_get_board_type(volatile u_int *jreg, sysc_cfga_stat_t *sc) 1172 { 1173 int len; 1174 int ring; 1175 int result; 1176 int board; 1177 int status; 1178 1179 /* 1180 * Select Board Ring 0 to scan. This contains the AC, FHC, 1181 * and DC ASICs 1182 */ 1183 1184 /* 1185 * Ring number is JTAG Board (7:4) and ring number (3:0) 1186 */ 1187 board = sc->board; 1188 ring = (board << 4) | 0; 1189 1190 if ((status = select_ring(jreg, ring, 1)) < 0) { 1191 cmn_err(CE_WARN, "Select ring error %d\n", status); 1192 } 1193 1194 len = jtag_ring_length(jreg, ring); 1195 switch (len) { 1196 case CPU_TYPE_LEN: 1197 result = CPU_BOARD; 1198 1199 jtag_check_plus_board(jreg, ring, 1200 &cpu_sysbd_ring_components[9], sc); 1201 1202 break; 1203 1204 case IO_TYPE1_LEN: 1205 switch (jtag_ring_ir_length(jreg, ring)) { 1206 case RING_BROKEN: 1207 result = UNKNOWN_BOARD; 1208 break; 1209 case IO_TYPE4_LEN: 1210 result = IO_2SBUS_SOCPLUS_BOARD; 1211 jtag_check_plus_board(jreg, ring, 1212 &io1plus_sysbd_ring_components[9], sc); 1213 break; 1214 default: 1215 result = IO_2SBUS_BOARD; 1216 jtag_check_plus_board(jreg, ring, 1217 &io1_sysbd_ring_components[9], sc); 1218 break; 1219 } 1220 1221 break; 1222 1223 case IO_TYPE2_LEN: 1224 switch (jtag_ring_ir_length(jreg, ring)) { 1225 case RING_BROKEN: 1226 result = UNKNOWN_BOARD; 1227 break; 1228 case IO_TYPE5_LEN: 1229 result = IO_SBUS_FFB_SOCPLUS_BOARD; 1230 jtag_check_plus_board(jreg, ring, 1231 &io2plus_sysbd_ring_components[9], sc); 1232 break; 1233 default: 1234 result = IO_SBUS_FFB_BOARD; 1235 jtag_check_plus_board(jreg, ring, 1236 &io2_sysbd_ring_components[9], sc); 1237 break; 1238 } 1239 1240 break; 1241 1242 case PCI_TYPE_LEN: 1243 switch (jtag_ring_ir_length(jreg, ring)) { 1244 case RING_BROKEN: 1245 result = UNKNOWN_BOARD; 1246 break; 1247 case PCI_TYPEA_LEN: 1248 result = IO_PCI_BOARD; 1249 jtag_check_plus_board(jreg, ring, 1250 &io3_sysbd_ring_components[9], sc); 1251 break; 1252 case PCI_TYPEB_LEN: 1253 default: 1254 result = UNKNOWN_BOARD; 1255 break; 1256 } 1257 break; 1258 1259 case DSK_TYPE_LEN: 1260 result = DISK_BOARD; 1261 break; 1262 1263 case RING_BROKEN: 1264 result = -1; 1265 break; 1266 1267 default: 1268 result = UNKNOWN_BOARD; 1269 break; 1270 } 1271 1272 TAP_ISSUE_CMD(jreg, JTAG_TAP_RESET, status); 1273 1274 return (result); 1275 } 1276 1277 #ifndef RFE_4174486 1278 /* 1279 * Until the RFE is fully investigated the likelyhood is that the 1280 * CPU frequency may be incorrectly displayed. Coupled with the lack of 1281 * Ecache size information and no information at all unless the 1282 * CPU board is physically plugged in, the default is not to get any 1283 * CPU information. 1284 * This patchable flag is provided so that more testing can be done 1285 * without re-compilation. 1286 */ 1287 static int jtag_cpu_scan_enable = 0; 1288 #endif /* RFE_4174486 */ 1289 1290 int 1291 jtag_get_board_info(volatile u_int *jreg, sysc_cfga_stat_t *sc) 1292 { 1293 jtag_ring_desc *rd; 1294 jtag_phys_comp *rc; 1295 int status; 1296 int ring; 1297 int len; 1298 int i; 1299 struct cpu_info *cpu; 1300 struct bct_fields bct_data; 1301 1302 /* fill in the board info structure */ 1303 1304 ring = sc->board << 4; 1305 1306 if ((status = select_ring(jreg, ring, 1)) < 0) { 1307 return (status); 1308 } 1309 1310 rd = get_ring_descriptor_bytype(ring, sc->type); 1311 1312 if (rd == NULL) { 1313 return (JTAG_FAIL); 1314 } 1315 1316 /* scan in the generic data common to all board types. */ 1317 1318 /* get the AC component ID */ 1319 rc = find_chip(rd, &chip_ac, 0); 1320 if (rc != NULL) { 1321 sc->ac_compid = jtag_get_comp_id(jreg, rc); 1322 } 1323 1324 /* get the FHC component ID */ 1325 rc = find_chip(rd, &chip_fhc, 0); 1326 if (rc != NULL) { 1327 sc->fhc_compid = jtag_get_comp_id(jreg, rc); 1328 } 1329 1330 /* Now scan the board type dependent components */ 1331 switch (sc->type) { 1332 case CPU_BOARD: 1333 /* 1334 * first determine the cache size of each module, then 1335 * use that ring descriptor. 1336 */ 1337 1338 for (i = 0, cpu = &sc->bd.cpu[i]; i < 2; i++, cpu++) { 1339 bzero(cpu, sizeof (*cpu)); 1340 #ifndef RFE_4174486 1341 if (!jtag_cpu_scan_enable) 1342 continue; 1343 #endif /* RFE_4174486 */ 1344 if (select_ring(jreg, ring | (i + 1), 1) < 0) { 1345 continue; 1346 } 1347 1348 len = jtag_ring_length(jreg, ring | (i + 1)); 1349 1350 switch (len) { 1351 case CPU_0_5_LEN: 1352 rd = &cpu_mod_ring; 1353 cpu->cpu_detected = 1; 1354 break; 1355 1356 case CPU_1_0_LEN: 1357 rd = &cpu_mod_1m_ring; 1358 cpu->cpu_detected = 1; 1359 break; 1360 1361 case RING_BROKEN: 1362 default: 1363 rd = NULL; 1364 break; 1365 } 1366 1367 if (!cpu->cpu_detected) 1368 continue; 1369 1370 if (rd != NULL) { 1371 rc = find_chip(rd, &chip_spitfire, 0); 1372 if (rc != NULL) { 1373 cpu->cpu_compid = 1374 jtag_get_comp_id(jreg, rc); 1375 } 1376 1377 /* 1378 * Do not get the component ID from the 1379 * first E$ chip. This is the tag chip 1380 * and does not help determine cache size. 1381 */ 1382 rc = find_chip(rd, &chip_ec, 1); 1383 if (rc != NULL) { 1384 cpu->ec_compid = 1385 jtag_get_comp_id(jreg, rc); 1386 } 1387 1388 rc = find_chip(rd, &chip_sdb, 0); 1389 if (rc != NULL) { 1390 cpu->sdb0_compid = 1391 jtag_get_comp_id(jreg, rc); 1392 } 1393 1394 rc = find_chip(rd, &chip_sdb, 1); 1395 if (rc != NULL) { 1396 cpu->sdb1_compid = 1397 jtag_get_comp_id(jreg, rc); 1398 } 1399 } 1400 1401 #ifdef RFE_4174486 1402 /* Work out Ecache size. */ 1403 switch (len) { 1404 case CPU_0_5_LEN: 1405 cpu->cache_size = 0x80000; 1406 break; 1407 1408 case CPU_1_0_LEN: 1409 /* default cache size for 9 SRAM chips */ 1410 cpu->cache_size = 0x100000; 1411 break; 1412 1413 default: 1414 break; 1415 } 1416 #endif /* RFE_4174486 */ 1417 } 1418 1419 break; 1420 1421 case IO_2SBUS_BOARD: 1422 rc = find_chip(rd, &chip_sio, 0); 1423 if (rc != NULL) { 1424 sc->bd.io1.sio0_compid = 1425 jtag_get_comp_id(jreg, rc); 1426 } 1427 1428 rc = find_chip(rd, &chip_sio, 1); 1429 if (rc != NULL) { 1430 sc->bd.io1.sio1_compid = 1431 jtag_get_comp_id(jreg, rc); 1432 } 1433 1434 rc = find_chip(rd, &chip_hm, 0); 1435 if (rc != NULL) { 1436 sc->bd.io1.hme_compid = jtag_get_comp_id(jreg, rc); 1437 } 1438 1439 rc = find_chip(rd, &chip_soc, 0); 1440 if (rc != NULL) { 1441 sc->bd.io1.soc_compid = jtag_get_comp_id(jreg, rc); 1442 } 1443 1444 break; 1445 1446 case IO_2SBUS_SOCPLUS_BOARD: 1447 rc = find_chip(rd, &chip_sio, 0); 1448 if (rc != NULL) { 1449 sc->bd.io1.sio0_compid = 1450 jtag_get_comp_id(jreg, rc); 1451 } 1452 1453 rc = find_chip(rd, &chip_sio, 1); 1454 if (rc != NULL) { 1455 sc->bd.io1.sio1_compid = 1456 jtag_get_comp_id(jreg, rc); 1457 } 1458 1459 rc = find_chip(rd, &chip_hm, 0); 1460 if (rc != NULL) { 1461 sc->bd.io1.hme_compid = jtag_get_comp_id(jreg, rc); 1462 } 1463 1464 rc = find_chip(rd, &chip_socplus, 0); 1465 if (rc != NULL) { 1466 sc->bd.io1plus.socplus_compid = 1467 jtag_get_comp_id(jreg, rc); 1468 } 1469 1470 break; 1471 1472 case IO_SBUS_FFB_BOARD: 1473 rc = find_chip(rd, &chip_sio, 0); 1474 if (rc != NULL) { 1475 sc->bd.io2.sio1_compid = jtag_get_comp_id(jreg, rc); 1476 } 1477 1478 rc = find_chip(rd, &chip_hm, 0); 1479 if (rc != NULL) { 1480 sc->bd.io2.hme_compid = jtag_get_comp_id(jreg, rc); 1481 } 1482 1483 rc = find_chip(rd, &chip_soc, 0); 1484 if (rc != NULL) { 1485 sc->bd.io2.soc_compid = jtag_get_comp_id(jreg, rc); 1486 } 1487 1488 /* Now scan for an FFB board */ 1489 if (select_ring(jreg, ring | 1, 1) < 0) { 1490 len = RING_BROKEN; 1491 } else { 1492 len = jtag_ring_length(jreg, ring | 1); 1493 } 1494 1495 switch (len) { 1496 case FFB_SNG_LEN: 1497 rd = &ffb_sngl_ring; 1498 sc->bd.io2.ffb_size = FFB_SINGLE; 1499 break; 1500 1501 case FFB_DBL_LEN: 1502 rd = &ffb_dbl_ring; 1503 sc->bd.io2.ffb_size = FFB_DOUBLE; 1504 break; 1505 1506 case RING_BROKEN: 1507 rd = NULL; 1508 sc->bd.io2.ffb_size = FFB_NOT_FOUND; 1509 break; 1510 1511 default: 1512 rd = NULL; 1513 sc->bd.io2.ffb_size = FFB_FAILED; 1514 break; 1515 } 1516 1517 /* Now scan out the FBC component ID */ 1518 if (rd != NULL) { 1519 rc = find_chip(rd, &chip_fbc, 0); 1520 } 1521 1522 if (rc != NULL) { 1523 sc->bd.io2.fbc_compid = jtag_get_comp_id(jreg, rc); 1524 } 1525 break; 1526 1527 case IO_SBUS_FFB_SOCPLUS_BOARD: 1528 rc = find_chip(rd, &chip_sio, 0); 1529 if (rc != NULL) { 1530 sc->bd.io2.sio1_compid = jtag_get_comp_id(jreg, rc); 1531 } 1532 1533 rc = find_chip(rd, &chip_hm, 0); 1534 if (rc != NULL) { 1535 sc->bd.io2.hme_compid = jtag_get_comp_id(jreg, rc); 1536 } 1537 1538 rc = find_chip(rd, &chip_socplus, 0); 1539 if (rc != NULL) { 1540 sc->bd.io2plus.socplus_compid = 1541 jtag_get_comp_id(jreg, rc); 1542 } 1543 1544 /* Now scan for an FFB board */ 1545 if (select_ring(jreg, ring | 1, 1) < 0) { 1546 len = RING_BROKEN; 1547 } else { 1548 len = jtag_ring_length(jreg, ring | 1); 1549 } 1550 1551 switch (len) { 1552 case FFB_SNG_LEN: 1553 rd = &ffb_sngl_ring; 1554 sc->bd.io2.ffb_size = FFB_SINGLE; 1555 break; 1556 1557 case FFB_DBL_LEN: 1558 rd = &ffb_dbl_ring; 1559 sc->bd.io2.ffb_size = FFB_DOUBLE; 1560 break; 1561 1562 case RING_BROKEN: 1563 rd = NULL; 1564 sc->bd.io2.ffb_size = FFB_NOT_FOUND; 1565 break; 1566 1567 default: 1568 rd = NULL; 1569 sc->bd.io2.ffb_size = FFB_FAILED; 1570 break; 1571 } 1572 1573 /* Now scan out the FBC component ID */ 1574 if (rd != NULL) { 1575 rc = find_chip(rd, &chip_fbc, 0); 1576 } 1577 1578 if (rc != NULL) { 1579 sc->bd.io2.fbc_compid = jtag_get_comp_id(jreg, rc); 1580 } 1581 break; 1582 1583 case IO_PCI_BOARD: 1584 rc = find_chip(rd, &chip_psyo, 0); 1585 if (rc != NULL) { 1586 sc->bd.io3.psyo0_compid = 1587 jtag_get_comp_id(jreg, rc); 1588 } 1589 1590 rc = find_chip(rd, &chip_psyo, 1); 1591 if (rc != NULL) { 1592 sc->bd.io3.psyo1_compid = 1593 jtag_get_comp_id(jreg, rc); 1594 } 1595 1596 rc = find_chip(rd, &chip_cheo, 0); 1597 if (rc != NULL) { 1598 sc->bd.io3.cheo_compid = jtag_get_comp_id(jreg, rc); 1599 } 1600 1601 break; 1602 1603 case DISK_BOARD: 1604 /* 1605 * Scan the BCT8244 to get the disk drive info out of 1606 * the chip. 1607 */ 1608 if (jtag_scanout_chip(jreg, ring, 1609 &dsk_sysbd_ring_components[0], (u_int *)&bct_data) < 0) { 1610 TAP_ISSUE_CMD(jreg, JTAG_TAP_RESET, status); 1611 return (-1); 1612 } 1613 1614 if ((bct_data.disk0_pres && 0x1) == 0) { 1615 sc->bd.dsk.disk_pres[0] = 1; 1616 sc->bd.dsk.disk_id[0] = 0xf & ~bct_data.disk0_id; 1617 } else { 1618 sc->bd.dsk.disk_pres[0] = 0; 1619 } 1620 1621 if ((bct_data.disk1_pres && 0x1) == 0) { 1622 sc->bd.dsk.disk_pres[1] = 1; 1623 sc->bd.dsk.disk_id[1] = 0xf & ~bct_data.disk1_id; 1624 } else { 1625 sc->bd.dsk.disk_pres[1] = 0; 1626 } 1627 1628 break; 1629 1630 default: 1631 break; 1632 } 1633 1634 return (JTAG_OK); 1635 } 1636 1637 static jtag_phys_comp * 1638 find_chip(jtag_ring_desc *rd, jtag_log_comp *chip, int instance) 1639 { 1640 int i; 1641 int found = 0; 1642 jtag_phys_comp *rc; 1643 1644 for (i = rd->size, rc = rd->components; i != 0; rc++, i--) { 1645 if (rc->chip == chip) { 1646 if (found == instance) { 1647 return (rc); 1648 } else { 1649 found++; 1650 } 1651 } 1652 } 1653 return (NULL); 1654 } 1655 1656 /* 1657 * Function jtag_error() : 1658 * 1659 * This function centrailizes the use of the JTAG error strings. 1660 * It should be called with the JTAG error code anytime the programmer 1661 * wants to print the type of JTAG error encountered. Just call with the 1662 * error code returned by the JTAG function. If no error occurred, nothing 1663 * is printed. 1664 */ 1665 static void 1666 jtag_error_print(int ring, jtag_error code) 1667 { 1668 char *ring_str = "System Board"; 1669 1670 switch (code) { 1671 case JTAG_OK : 1672 break; 1673 1674 case TAP_TIMEOUT : 1675 cmn_err(CE_WARN, "%s : TAP controller timeout\n", jtag_err); 1676 break; 1677 1678 case BAD_ARGS : 1679 cmn_err(CE_WARN, 1680 "%s : routine reports bad args: Board %d, %s Ring\n", 1681 jtag_err, ring >> 4, ring_str); 1682 break; 1683 1684 case BAD_CID : 1685 cmn_err(CE_WARN, 1686 "%s : Bad component ID detected: Board %d, %s Ring\n", 1687 jtag_err, ring >> 4, ring_str); 1688 break; 1689 1690 case RING_BROKEN : 1691 cmn_err(CE_WARN, "%s : ring broken: Board %d, %s Ring\n", 1692 jtag_err, ring >> 4, ring_str); 1693 break; 1694 1695 case INIT_MISMATCH: 1696 cmn_err(CE_WARN, 1697 "%s : State after init not expected: Board %d, " 1698 "%s Ring\n", jtag_err, ring >> 4, ring_str); 1699 break; 1700 1701 case LENGTH_MISMATCH : 1702 cmn_err(CE_WARN, 1703 "%s : Scan Chain Length mismatch: Board %d," 1704 " %s Ring\n", 1705 jtag_err, ring >> 4, ring_str); 1706 break; 1707 1708 } /* end of switch on code */ 1709 } /* end of jtag_error_print() */ 1710 1711 1712 static int 1713 jtag_get_comp_id(volatile u_int *jreg, jtag_phys_comp *comp) 1714 { 1715 u_char b[4]; 1716 u_int id; 1717 int status; 1718 1719 status = jtag_single_IR_DR(jreg, comp, comp->chip->id_code, 1720 b, 32, b); 1721 1722 /* Reorder the bytes of the ID read out */ 1723 id = b[0] | (b[1] << 8) | (b[2] << 16) | (b[3] << 24); 1724 1725 if (status < 0) { 1726 return (0); 1727 } else { 1728 return (id); 1729 } 1730 } 1731 1732 /* 1733 * Bit-manipulation routines 1734 */ 1735 1736 /* 1737 * jtag_bf_extract() 1738 * 1739 * This routine extracts bit strings from JTAG data scanout strings. This 1740 * routine is used to decode data scanned out of chips via JTAG. 1741 */ 1742 static u_int 1743 jtag_bf_extract(u_char *s, int lsb, int msb) 1744 { 1745 u_int result = 0; 1746 1747 ASSERT(s); 1748 1749 /* 1750 * lsb and msb are assumed to be within string, 1751 * and to span 32 bits at most 1752 */ 1753 for (; msb >= lsb; msb--) { 1754 result = (result << 1) | ((s[msb>>3] >> (msb & 7)) & 1); 1755 } 1756 return (result); 1757 } 1758 1759 /* 1760 * jtag_bf_insert() 1761 * 1762 * This routine is used to build bit strings for scanning into the 1763 * shadow chains of ASICs. 1764 */ 1765 static void 1766 jtag_bf_insert(u_char *s, int lsb, int msb, int value) 1767 { 1768 ASSERT(s); 1769 1770 /* 1771 * lsb and msb are assumed to be within string, 1772 * and to span 32 bits at most 1773 */ 1774 1775 for (; msb >= lsb; lsb++) { 1776 s[lsb>>3] = (s[lsb>>3] & ~ (1 << (lsb & 7))) | 1777 ((value & 1) << (lsb & 7)); 1778 value = value >> 1; 1779 } 1780 } 1781 1782 /* 1783 * 1784 */ 1785 static void 1786 jtag_bf_zero(u_char *s, int nbits) 1787 { 1788 int nbytes = (nbits+7)>>3; 1789 1790 while (nbytes-- != 0) { 1791 *s++ = 0; 1792 } 1793 } 1794 1795 /* 1796 * Return 0 if equal, != 0 else 1797 */ 1798 static int 1799 jtag_bf_cmp(u_char *s1, u_char *s2, int nbits) 1800 { 1801 int mask; 1802 for (nbits -= 8; nbits > 0; nbits -= 8) { 1803 if (*s1++ != *s2++) { 1804 return (-1); 1805 } 1806 mask = 0xFF >> (-nbits); 1807 if ((*s1++ & mask) != (*s2++ & mask)) { 1808 return (-1); 1809 } 1810 } 1811 1812 return (0); 1813 } 1814 1815 1816 /* 1817 * Generic chip-level top routines 1818 */ 1819 static int 1820 jtag_init_chip( 1821 volatile u_int *jreg, 1822 jtag_ring ring, 1823 jtag_phys_comp *component, 1824 const u_int *pval, 1825 u_char scan_out[32]) 1826 { 1827 int status; 1828 jtag_log_comp *chip; 1829 u_char scan_in[32]; 1830 u_char *pdesc; 1831 1832 status = select_ring(jreg, ring, 1); 1833 if (status < 0) { 1834 return (status); 1835 } 1836 1837 pval = pval - 1; /* adjust pval since indices start at 1 */ 1838 chip = component->chip; 1839 pdesc = chip->init_pdesc; 1840 1841 /* Zero out the scan-in area */ 1842 jtag_bf_zero(scan_in, 8*32); 1843 jtag_bf_zero(scan_out, 8*32); 1844 1845 for (;;) { 1846 u_int flags, lsb, msb, patch; 1847 flags = *pdesc++; 1848 if ((flags & JTIN_INSERT) != 0) { 1849 lsb = *pdesc++; 1850 msb = *pdesc++; 1851 if ((flags & JTIN_INDEX) != 0) { 1852 patch = pval[flags & JTIN_INDEX]; 1853 } else { 1854 patch = *pdesc++; 1855 } 1856 jtag_bf_insert(scan_in, lsb, msb, patch); 1857 } 1858 1859 if ((flags & JTIN_UPDATE) != 0) { 1860 status = jtag_single_IR_DR(jreg, component, 1861 chip->init_code, scan_in, chip->dr_len, 1862 scan_out); 1863 1864 if (status < 0) { 1865 return (status); 1866 } 1867 1868 if ((status = select_ring(jreg, ring, 1)) < 0) { 1869 return (status); 1870 } 1871 } 1872 1873 if ((flags & JTIN_COMPARE) != 0) { 1874 if (jtag_bf_cmp(scan_in, scan_out, chip->dr_len) != 0) 1875 return (INIT_MISMATCH); 1876 } 1877 1878 if ((flags & JTIN_END) != 0) { 1879 break; 1880 } 1881 } 1882 1883 return (JTAG_OK); /* all is OK... */ 1884 } 1885 1886 /* 1887 * Dump the info from a chip. 1888 * Return the number of bytes used, or <0 if failed 1889 */ 1890 static int 1891 jtag_scanout_chip( 1892 volatile u_int *jreg, 1893 jtag_ring ring, 1894 jtag_phys_comp *component, 1895 u_int *result) 1896 { 1897 int status; 1898 jtag_log_comp *chip; 1899 u_char scan_in[32]; 1900 u_char scan_out[32]; 1901 u_char *p; 1902 u_int value; 1903 int bytes_used = 0; 1904 1905 if ((status = select_ring(jreg, ring, 1)) < 0) { 1906 return (status); 1907 } 1908 1909 chip = component->chip; 1910 1911 p = chip->fmt_desc; 1912 if (p == NULL) { 1913 return (bytes_used); 1914 } 1915 1916 status = jtag_rescan_IR_DR(jreg, component, chip->dump_code, scan_in, 1917 chip->dr_len, scan_out); 1918 1919 if (status < 0) { 1920 return (status); 1921 } 1922 1923 if ((status = select_ring(jreg, ring, 1)) < 0) { 1924 return (status); 1925 } 1926 1927 for (value = 0; ; ) { 1928 u_char cmd = *p++; 1929 1930 if ((cmd & JTSO_XTRACT) != 0) { 1931 u_int lsb, msb; 1932 lsb = *p++; 1933 msb = *p++; 1934 value |= jtag_bf_extract(scan_out, lsb, msb) << 1935 (cmd & JTSO_SHIFT); 1936 } 1937 1938 if ((cmd & JTSO_ST) != 0) { 1939 *result++ = value; 1940 bytes_used += 4; 1941 value = 0; 1942 } 1943 1944 if ((cmd & JTSO_END) != 0) { 1945 break; 1946 } 1947 } 1948 return (bytes_used); 1949 } 1950 1951 /* 1952 * Set the AC into hotplug mode upon insertion 1953 */ 1954 static int 1955 jtag_init_ac(volatile u_int *jreg, int bid, enum board_type brdtype) 1956 { 1957 int rc = JTAG_OK; 1958 int status; 1959 int ring = (bid << 4); 1960 ac_options ac_opt; 1961 u_char scan_out[64]; 1962 uint_t cs_value; 1963 1964 if (brdtype == UNKNOWN_BOARD) 1965 return (rc); 1966 1967 ac_opt.frozen = 0; /* 0 = frozen */ 1968 ac_opt.reset_a = 1; 1969 ac_opt.reset_b = 1; 1970 ac_opt.board_id = bid; 1971 ac_opt.mask_hwerr = (uint_t)-1; 1972 ac_opt.node_id = 3; 1973 1974 /* Get a good AC BCSR value from the board we are running on. */ 1975 cs_value = ldphysio(AC_BCSR(FHC_CPU2BOARD(CPU->cpu_id))); 1976 1977 ac_opt.arb_fast = (cs_value & AC_ARB_FAST) ? 1 : 0; 1978 ac_opt.pcr_hi = 0; 1979 ac_opt.pcr_lo = 0x80000000LL - 0x9ac4 - (bid << 3); 1980 ac_opt.pcc_ctl0 = 0x3f; 1981 ac_opt.pcc_ctl1 = 0x3f; 1982 ac_opt.pcc_tctrl = (1 << 11); /* TREN */ 1983 1984 if ((brdtype == CPU_BOARD) || (brdtype == MEM_BOARD)) { 1985 rc = jtag_init_chip(jreg, ring, &cpu_sysbd_ring_components[0], 1986 (jtag_opt)&ac_opt, scan_out); 1987 } else if (brdtype == IO_2SBUS_BOARD) { 1988 rc = jtag_init_chip(jreg, ring, &io1_sysbd_ring_components[0], 1989 (jtag_opt)&ac_opt, scan_out); 1990 } else if (brdtype == IO_2SBUS_SOCPLUS_BOARD) { 1991 rc = jtag_init_chip(jreg, ring, 1992 &io1plus_sysbd_ring_components[0], 1993 (jtag_opt)&ac_opt, scan_out); 1994 } else if (brdtype == IO_SBUS_FFB_BOARD) { 1995 rc = jtag_init_chip(jreg, ring, &io2_sysbd_ring_components[0], 1996 (jtag_opt)&ac_opt, scan_out); 1997 } else if (brdtype == IO_SBUS_FFB_SOCPLUS_BOARD) { 1998 rc = jtag_init_chip(jreg, ring, 1999 &io2plus_sysbd_ring_components[0], 2000 (jtag_opt)&ac_opt, scan_out); 2001 } else if (brdtype == IO_PCI_BOARD) { 2002 rc = jtag_init_chip(jreg, ring, &io3_sysbd_ring_components[0], 2003 (jtag_opt)&ac_opt, scan_out); 2004 } else { 2005 cmn_err(CE_NOTE, " jtag_init_ac() Board %d" 2006 " unsupported type %2X", bid, brdtype); 2007 } 2008 2009 TAP_ISSUE_CMD(jreg, JTAG_TAP_RESET, status); 2010 2011 if (rc != JTAG_OK) { 2012 jtag_error_print(ring, rc); 2013 } 2014 2015 return (rc); 2016 } 2017 2018 #define EN_LOC_FATAL 0x02 2019 #define MOD_OFF 0x80 2020 #define ACDC_OFF 0x40 2021 #define EPDA_OFF 0x10 2022 #define EPDB_OFF 0x08 2023 #define NOT_BRD_PRESENT 0x02 2024 #define NOT_BRD_LED_LEFT 0x04 2025 #define BRD_LED_MID 0x02 2026 #define BRD_LED_RIGHT 0x01 2027 2028 /* 2029 * Each board has an FHC asic. 2030 */ 2031 int 2032 jtag_powerdown_board(volatile u_int *jreg, int board, enum board_type type, 2033 u_int *fhc_csr, u_int *fhc_bsr, int intr) 2034 { 2035 int rc = JTAG_OK; 2036 fhc_options fhc_opt; 2037 struct fhc_regs fhc_data; 2038 u_char scan_out[32]; 2039 int status; 2040 int ring; 2041 2042 if (type == UNKNOWN_BOARD) { 2043 sysc_cfga_stat_t asc; 2044 2045 bzero(&asc, sizeof (asc)); 2046 asc.board = board; 2047 type = jtag_get_board_type(jreg, &asc); 2048 } 2049 2050 if (!intr) 2051 (void) jtag_init_ac(jreg, board, type); 2052 2053 ring = board << 4; 2054 2055 fhc_opt.csr_hi = 0; 2056 fhc_opt.csr_mid = MOD_OFF | EPDA_OFF | EPDB_OFF | NOT_BRD_PRESENT; 2057 if (intr) { 2058 /* 2059 * by not setting NOT_BRD_PRESENT we can simulate a board 2060 * insertion 2061 */ 2062 fhc_opt.csr_mid &= ~NOT_BRD_PRESENT; 2063 } 2064 2065 fhc_opt.csr_midlo = NOT_BRD_LED_LEFT | BRD_LED_MID; 2066 2067 if ((type == CPU_BOARD) || (type == MEM_BOARD)) { 2068 rc = jtag_init_chip(jreg, ring, &cpu_sysbd_ring_components[9], 2069 (jtag_opt)&fhc_opt, scan_out); 2070 } else if (type == IO_2SBUS_BOARD) { 2071 rc = jtag_init_chip(jreg, ring, &io1_sysbd_ring_components[9], 2072 (jtag_opt)&fhc_opt, scan_out); 2073 } else if (type == IO_2SBUS_SOCPLUS_BOARD) { 2074 rc = jtag_init_chip(jreg, ring, 2075 &io1plus_sysbd_ring_components[9], 2076 (jtag_opt)&fhc_opt, scan_out); 2077 } else if (type == IO_SBUS_FFB_BOARD) { 2078 rc = jtag_init_chip(jreg, ring, &io2_sysbd_ring_components[9], 2079 (jtag_opt)&fhc_opt, scan_out); 2080 } else if (type == IO_SBUS_FFB_SOCPLUS_BOARD) { 2081 rc = jtag_init_chip(jreg, ring, 2082 &io2plus_sysbd_ring_components[9], 2083 (jtag_opt)&fhc_opt, scan_out); 2084 } else if (type == IO_PCI_BOARD) { 2085 rc = jtag_init_chip(jreg, ring, &io3_sysbd_ring_components[9], 2086 (jtag_opt)&fhc_opt, scan_out); 2087 } else if (type == UNKNOWN_BOARD) { 2088 rc = jtag_init_chip(jreg, ring, &cpu_sysbd_ring_components[9], 2089 (jtag_opt)&fhc_opt, scan_out); 2090 } else { 2091 cmn_err(CE_WARN, "Unsupported Board type %2X\n", 2092 fhc_bd_type(board)); 2093 } 2094 2095 TAP_ISSUE_CMD(jreg, JTAG_TAP_RESET, status); 2096 2097 if (rc != JTAG_OK) { 2098 jtag_error_print(ring, rc); 2099 } 2100 2101 /* Reformat the FHC shadow chain scan data */ 2102 format_chip_data(chip_fhc.fmt_desc, (u_int *)&fhc_data, 2103 scan_out); 2104 2105 *fhc_csr = fhc_data.csr; 2106 *fhc_bsr = fhc_data.bsr; 2107 2108 2109 return (rc); 2110 } 2111 2112 /* 2113 * This function performs the fhc initialization for a disk board. The 2114 * hotplug variable tells the function whether to put the LED into low 2115 * power mode or not. 2116 */ 2117 int 2118 jtag_init_disk_board(volatile u_int *jreg, int board, 2119 u_int *fhc_csr, u_int *fhc_bsr) 2120 { 2121 int rc = JTAG_OK; 2122 fhc_options fhc_opt; 2123 struct fhc_regs fhc_data; 2124 u_char scan_out[32]; 2125 int status; 2126 int ring; 2127 2128 ring = board << 4; 2129 2130 fhc_opt.csr_hi = 0; 2131 fhc_opt.csr_mid = NOT_BRD_PRESENT; 2132 fhc_opt.csr_midlo = NOT_BRD_LED_LEFT | BRD_LED_MID; 2133 2134 rc = jtag_init_chip(jreg, ring, &dsk_sysbd_ring_components[1], 2135 (jtag_opt)&fhc_opt, scan_out); 2136 2137 TAP_ISSUE_CMD(jreg, JTAG_TAP_RESET, status); 2138 2139 if (rc != JTAG_OK) { 2140 jtag_error_print(ring, rc); 2141 return (-1); 2142 } 2143 2144 /* Reformat the FHC shadow chain scan data */ 2145 format_chip_data(chip_fhc.fmt_desc, (u_int *)&fhc_data, 2146 scan_out); 2147 2148 *fhc_csr = fhc_data.csr; 2149 *fhc_bsr = fhc_data.bsr; 2150 2151 return (0); 2152 } 2153 2154 /* 2155 * NOTES: 2156 * 1. Scan data streams are little-endian sequences of bytes: byte 0 2157 * will provide the 8 lsb of the scan chain, and so on. If the last 2158 * byte is not full (count not a multiple of 8), the least significant 2159 * bits are used. 2160 * 2. All procedures assume that the JTAG control register 2161 * is non-busy on entry, and return with the control register 2162 * non-busy. It is a good idea to call tap_wait as part of the JTAG 2163 * sanity check sequence to verify there is no obvious malfunction. 2164 */ 2165 2166 2167 /* 2168 * Non-data TAP commands 2169 */ 2170 2171 /* 2172 * Wait for the TAP to be idle. 2173 * Return <0 if error, >=0 if OK. 2174 */ 2175 2176 int 2177 tap_wait(volatile u_int *jreg) 2178 { 2179 TAP_DECLARE; 2180 TAP_WAIT(jreg); 2181 return (JTAG_OK); 2182 } 2183 2184 /* 2185 * Send a TAP command, wait for completion. 2186 * Return <0 if error, >=0 if OK. 2187 */ 2188 2189 static int 2190 tap_issue_cmd(volatile u_int *jreg, u_int command) 2191 { 2192 TAP_DECLARE; 2193 2194 *jreg = command; 2195 TAP_WAIT(jreg); 2196 return (JTAG_OK); 2197 } 2198 2199 /* 2200 * Data TAP commands 2201 */ 2202 2203 /* 2204 * Shift 1 to 16 bits into the component. 2205 * Return <0 if error, the shifted out bits (always >=0) if OK. 2206 */ 2207 2208 int 2209 tap_shift_single(volatile u_int *jreg, int data, int nbits) 2210 { 2211 /* Return <0 if error, >0 (16-bit data) if OK */ 2212 TAP_DECLARE; 2213 TAP_SHIFT(jreg, data, nbits); 2214 return (jtag_data(jreg, nbits)); 2215 } 2216 2217 /* 2218 * Shift the required number of bits from in into the component, 2219 * retrieve the bits shifted out. 2220 * Return <0 if error, >=0 if OK. 2221 */ 2222 2223 int 2224 tap_shift_multiple( 2225 volatile u_int *jreg, 2226 u_char *data_in, 2227 int nbits, 2228 u_char *data_out) /* data_out may be NULL if not needed */ 2229 { 2230 TAP_DECLARE; 2231 2232 /* 2233 * The loop is done a byte at a time to avoid stepping out 2234 * of the caller's buffer 2235 */ 2236 for (; nbits > 0; nbits = nbits - 8) { 2237 int bits_this_pass = nbits > 8 ? 8 : nbits; 2238 TAP_SHIFT(jreg, *data_in++, bits_this_pass); 2239 if (data_out != NULL) { 2240 *data_out = jtag_data(jreg, bits_this_pass); 2241 data_out++; 2242 } 2243 } 2244 2245 return (JTAG_OK); 2246 } 2247 2248 /* 2249 * Shift the required number of bits of the specified 2250 * value into the selected register. Note that this routine makes 2251 * sense only for value = 0 and value = -1. 2252 * Return <0 if error, >=0 if OK. 2253 */ 2254 2255 static int 2256 tap_shift_constant(volatile u_int *jreg, int value, int nbits) 2257 { 2258 TAP_DECLARE; 2259 2260 TAP_WAIT(jreg); 2261 2262 /* 2263 * The loop is done a half-word at a time 2264 */ 2265 for (; nbits > 0; nbits = nbits - 16) { 2266 int bits_this_pass = nbits > 16 ? 16 : nbits; 2267 TAP_SHIFT(jreg, value, bits_this_pass); 2268 } 2269 2270 return (JTAG_OK); 2271 } 2272 2273 2274 /* 2275 * Ring-level commands 2276 */ 2277 2278 /* 2279 * Select the required ring. Reset it if required (reset != 0). 2280 * Return <0 if error, >=0 if OK. 2281 */ 2282 2283 static int 2284 select_ring(volatile u_int *jreg, jtag_ring ring, int reset) 2285 { 2286 int status; 2287 jtag_ring jring; 2288 2289 status = tap_wait(jreg); 2290 if (status < 0) { 2291 return (status); 2292 } 2293 2294 /* Translate a Physical Board number to a JTAG board number */ 2295 jring = ((u_int)(ring & 0x10) << 3) | ((u_int)(ring & 0xE0) >> 1) | 2296 (ring & 0xF); 2297 status = tap_issue_cmd(jreg, (jring << 16) | JTAG_SEL_RING); 2298 if (status < 0) { 2299 return (status); 2300 } 2301 2302 if (reset != 0) { 2303 status = tap_issue_cmd(jreg, JTAG_TAP_RESET); 2304 } 2305 2306 return (status); 2307 } 2308 2309 /* 2310 * Shift the specified instruction into the component, then 2311 * shift the required data in & retrieve the data out. 2312 * Return <0 if error, >=0 if OK. 2313 */ 2314 2315 static int 2316 jtag_single_IR_DR( 2317 volatile u_int *jreg, 2318 jtag_phys_comp *component, 2319 jtag_instruction instr, 2320 u_char *in, 2321 int nbits, 2322 u_char *out) 2323 { 2324 int status; 2325 2326 TAP_ISSUE_CMD(jreg, JTAG_SEL_IR, status); 2327 TAP_SHIFT_CONSTANT(jreg, -1, component->ir_after, status); 2328 TAP_SHIFT_SINGLE(jreg, instr, component->chip->ir_len, status); 2329 TAP_SHIFT_CONSTANT(jreg, -1, component->ir_before, status); 2330 TAP_ISSUE_CMD(jreg, JTAG_IR_TO_DR, status); 2331 TAP_SHIFT_CONSTANT(jreg, 0, component->by_after, status); 2332 TAP_SHIFT_MULTIPLE(jreg, in, nbits, out, status); 2333 TAP_SHIFT_CONSTANT(jreg, 0, component->by_before, status); 2334 TAP_ISSUE_CMD(jreg, JTAG_RUNIDLE, status); 2335 2336 return (status); 2337 } 2338 2339 /* 2340 * jtag_rescan_IR_DR() 2341 * 2342 * This function is used in order to rescan the DC ASICs when taking 2343 * them out of the frozen state. This is necessary because of a problem 2344 * when taking DCs out of the frozen state. Sometimes the operation must 2345 * be retryed. 2346 * 2347 * TODO - Eliminate the *in input parameter if able to. 2348 */ 2349 2350 /* ARGSUSED */ 2351 static int 2352 jtag_rescan_IR_DR( 2353 volatile u_int *jreg, 2354 jtag_phys_comp *component, 2355 jtag_instruction instr, 2356 u_char *in, 2357 int nbits, 2358 u_char *out) 2359 { 2360 int status, i; 2361 u_char tmp[32]; 2362 2363 for (i = 0; i < 32; i++) 2364 tmp[i] = 0; 2365 2366 TAP_ISSUE_CMD(jreg, JTAG_SEL_IR, status); 2367 TAP_SHIFT_CONSTANT(jreg, -1, component->ir_after, status); 2368 TAP_SHIFT_SINGLE(jreg, instr, component->chip->ir_len, status); 2369 TAP_SHIFT_CONSTANT(jreg, -1, component->ir_before, status); 2370 TAP_ISSUE_CMD(jreg, JTAG_IR_TO_DR, status); 2371 2372 /* scan the chip out */ 2373 TAP_SHIFT_CONSTANT(jreg, 0, component->by_after, status); 2374 TAP_SHIFT_MULTIPLE(jreg, tmp, nbits, out, status); 2375 TAP_SHIFT_CONSTANT(jreg, 0, component->by_before, status); 2376 2377 /* re scan the chip */ 2378 TAP_SHIFT_CONSTANT(jreg, 0, component->by_after, status); 2379 TAP_SHIFT_MULTIPLE(jreg, out, nbits, tmp, status); 2380 TAP_SHIFT_CONSTANT(jreg, 0, component->by_before, status); 2381 2382 TAP_ISSUE_CMD(jreg, JTAG_RUNIDLE, status); 2383 2384 return (status); 2385 } 2386 2387 /* 2388 * Return the number of components of the current ring, or <0 if failed 2389 */ 2390 static int 2391 jtag_ring_length(volatile u_int *jreg, jtag_ring ring) 2392 { 2393 int status, length; 2394 2395 /* 2396 * Reset the ring & check that there is a component 2397 * This is based on the fact that TAP reset forces the IDCODE, 2398 * or BYPASS (with 0 preloaded) if there is no ID 2399 */ 2400 2401 status = select_ring(jreg, ring, 1); 2402 if (status < 0) { 2403 cmn_err(CE_WARN, "select ring error jtag status %x\n", 2404 status); 2405 return (status); 2406 } 2407 2408 TAP_ISSUE_CMD(jreg, JTAG_SEL_DR, status); 2409 TAP_SHIFT_SINGLE(jreg, -1, 8, status); 2410 if (status == 0xFF) { 2411 return (RING_BROKEN); /* no CID detected */ 2412 } 2413 2414 /* 2415 * Put all components in BYPASS. This assumes the chain has 2416 * at most 32 components, and that each IR is at most 16-bits. 2417 * Note that the algorithm depends on the bypass FF to be cleared 2418 * on a tap reset! 2419 */ 2420 TAP_ISSUE_CMD(jreg, JTAG_TAP_RESET, status); 2421 TAP_ISSUE_CMD(jreg, JTAG_SEL_IR, status); 2422 TAP_SHIFT_CONSTANT(jreg, -1, 32*16, status); 2423 TAP_ISSUE_CMD(jreg, JTAG_IR_TO_DR, status); 2424 TAP_SHIFT_CONSTANT(jreg, 0, 32, status); 2425 2426 for (length = 0; length <= 33; length++) { /* bit by bit */ 2427 TAP_SHIFT_SINGLE(jreg, -1, 1, status); 2428 2429 if (status != 0) { 2430 break; 2431 } 2432 } 2433 TAP_ISSUE_CMD(jreg, JTAG_RUNIDLE, status); 2434 /* more than 32 components ??? */ 2435 return ((length <= 32) ? length : RING_BROKEN); 2436 } 2437 2438 /* 2439 * Return the total number of instruction register bits in the 2440 * current ring, or < 0 if failed. 2441 */ 2442 int 2443 jtag_ring_ir_length(volatile u_int *jreg, jtag_ring ring) 2444 { 2445 int status, length; 2446 2447 /* 2448 * Reset the ring & check that there is a component 2449 * This is based on the fact that TAP reset forces the IDCODE, 2450 * or BYPASS (with 0 preloaded) if there is no ID 2451 */ 2452 status = select_ring(jreg, ring, 1); 2453 if (status < 0) { 2454 cmn_err(CE_WARN, "select error status %x", status); 2455 return (status); 2456 } 2457 2458 /* 2459 * Reset, Select IR, Shift in all 1's assuming the chain has 2460 * at most 32 components, and that each IR is at most 16-bits. 2461 * Then shift in 0's and count until a 0 comes out. 2462 * And cleanup by flushing with all 1's before reset or idle 2463 * --- FATAL's if you don't as you go through update-ir state 2464 */ 2465 TAP_ISSUE_CMD(jreg, JTAG_TAP_RESET, status); 2466 TAP_ISSUE_CMD(jreg, JTAG_SEL_IR, status); 2467 2468 /* 1 fill, look for 0 */ 2469 TAP_SHIFT_CONSTANT(jreg, -1, 32 * 16, status); 2470 for (length = 0; length <= 32 * 16; length++) { /* bit by bit */ 2471 TAP_SHIFT_SINGLE(jreg, 0, 1, status); 2472 if (status == 0) 2473 break; 2474 } 2475 2476 /* bypass should be safe */ 2477 TAP_SHIFT_CONSTANT(jreg, -1, 32 * 16, status); 2478 TAP_ISSUE_CMD(jreg, JTAG_RUNIDLE, status); 2479 /* more than 32*16 ir bits ??? */ 2480 return ((length <= 32 * 16) ? length : RING_BROKEN); 2481 } 2482 2483 /* 2484 * Format the jtag shadow scan data from scan_out bit string and store 2485 * in the array on u_ints. The datap represents the registers from 2486 * the chip under scan. 2487 * XXX - How to represent 64 bit registers here? 2488 */ 2489 static void 2490 format_chip_data(u_char *fmt, u_int *datap, u_char *scan_out) 2491 { 2492 u_int value; 2493 2494 for (value = 0; ; ) { 2495 u_char cmd = *fmt++; 2496 2497 if ((cmd & JTSO_XTRACT) != 0) { 2498 u_int lsb, msb; 2499 lsb = *fmt++; 2500 msb = *fmt++; 2501 value |= jtag_bf_extract(scan_out, lsb, msb) << 2502 (cmd & JTSO_SHIFT); 2503 } 2504 2505 if ((cmd & JTSO_ST) != 0) { 2506 *datap++ = value; 2507 value = 0; 2508 } 2509 2510 if ((cmd & JTSO_END) != 0) { 2511 break; 2512 } 2513 } 2514 } 2515