1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _AUDIO_4231_H 27 #define _AUDIO_4231_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 /* 34 * Header file for the audiocs device driver. 35 */ 36 37 /* 38 * Values returned by the AUDIO_GETDEV ioctl() 39 */ 40 #define CS_DEV_NAME "SUNW,CS4231" 41 #define CS_DEV_CONFIG_ONBRD1 "onboard1" 42 #define CS_DEV_VERSION "a" /* SS5 */ 43 #define CS_DEV_VERSION_A CS_DEV_VERSION 44 #define CS_DEV_VERSION_B "b" /* Electron - internal loopback */ 45 #define CS_DEV_VERSION_C "c" /* Positron */ 46 #define CS_DEV_VERSION_D "d" /* PowerPC - Retired */ 47 #define CS_DEV_VERSION_E "e" /* x86 - Retired */ 48 #define CS_DEV_VERSION_F "f" /* Tazmo */ 49 #define CS_DEV_VERSION_G "g" /* Quark Audio Module */ 50 #define CS_DEV_VERSION_H "h" /* Darwin */ 51 52 /* 53 * Driver supported configuration information 54 */ 55 #define CS4231_NAME "audiocs" 56 #define CS4231_MOD_NAME "CS4231 audio driver" 57 58 #define CS4231_INTS (175) /* default interrupt rate */ 59 #define CS4231_MIN_INTS (10) /* minimum interrupt rate */ 60 #define CS4231_MAX_INTS (2000) /* maximum interrupt rate */ 61 62 /* 63 * Implementation specific header file for the audiocs device driver. 64 */ 65 66 #ifdef _KERNEL 67 68 enum { 69 CTL_VOLUME = 0, 70 CTL_IGAIN, 71 CTL_MGAIN, 72 CTL_INPUTS, 73 CTL_OUTPUTS, 74 CTL_MICBOOST, 75 CTL_NUM 76 }; 77 78 typedef struct CS_engine CS_engine_t; 79 typedef struct CS_ctrl CS_ctrl_t; 80 typedef struct CS_state CS_state_t; 81 82 /* 83 * These are the registers for the APC DMA channel interface to the 84 * 4231. One handle provides access the CODEC and the DMA engine's 85 * registers. 86 */ 87 88 struct cs4231_apc { 89 uint32_t dmacsr; /* APC CSR */ 90 uint32_t lpad[3]; /* PAD */ 91 uint32_t dmacva; /* Capture Virtual Address */ 92 uint32_t dmacc; /* Capture Count */ 93 uint32_t dmacnva; /* Capture Next VAddress */ 94 uint32_t dmacnc; /* Capture next count */ 95 uint32_t dmapva; /* Playback Virtual Address */ 96 uint32_t dmapc; /* Playback Count */ 97 uint32_t dmapnva; /* Playback Next VAddress */ 98 uint32_t dmapnc; /* Playback Next Count */ 99 }; 100 typedef struct cs4231_apc cs4231_apc_t; 101 102 #define APC_DMACSR state->cs_regs->apc.dmacsr 103 #define APC_DMACVA state->cs_regs->apc.dmacva 104 #define APC_DMACC state->cs_regs->apc.dmacc 105 #define APC_DMACNVA state->cs_regs->apc.dmacnva 106 #define APC_DMACNC state->cs_regs->apc.dmacnc 107 #define APC_DMAPVA state->cs_regs->apc.dmapva 108 #define APC_DMAPC state->cs_regs->apc.dmapc 109 #define APC_DMAPNVA state->cs_regs->apc.dmapnva 110 #define APC_DMAPNC state->cs_regs->apc.dmapnc 111 112 /* 113 * APC CSR Register bit definitions 114 */ 115 116 #define APC_RESET 0x00000001u /* Reset the DMA engine, R/W */ 117 #define APC_CDMA_GO 0x00000004u /* Capture DMA go, R/W */ 118 #define APC_PDMA_GO 0x00000008u /* Playback DMA go, R/W */ 119 #define APC_LOOP_BACK 0x00000010u /* Loopback, Capture to Play */ 120 #define APC_COD_PDWN 0x00000020u /* CODEC power down, R/W */ 121 #define APC_C_ABORT 0x00000040u /* Capture abort, R/W */ 122 #define APC_P_ABORT 0x00000080u /* Play abort, R/W */ 123 #define APC_CXI_EN 0x00000100u /* Capture expired int. enable, R/W */ 124 #define APC_CXI 0x00000200u /* Capture expired interrupt, R/W */ 125 #define APC_CD 0x00000400u /* Capture next VA dirty, R/O */ 126 #define APC_CX 0x00000800u /* Capture expired (pipe empty), R/O */ 127 #define APC_PMI_EN 0x00001000u /* Play pipe empty int. enable, R/W */ 128 #define APC_PD 0x00002000u /* Playback next VA dirty, R/O */ 129 #define APC_PM 0x00004000u /* Play pipe empty, R/O */ 130 #define APC_PMI 0x00008000u /* Play pipe empty interrupt, R/W */ 131 #define APC_EIE 0x00010000u /* Error interrupt enable, R/W */ 132 #define APC_CIE 0x00020000u /* Capture interrupt enable, R/W */ 133 #define APC_PIE 0x00040000u /* Playback interrupt enable, R/W */ 134 #define APC_IE 0x00080000u /* Interrupt enable, R/W */ 135 #define APC_EI 0x00100000u /* Error interrupt, R/W */ 136 #define APC_CI 0x00200000u /* Capture interrupt, R/W */ 137 #define APC_PI 0x00400000u /* Playback interrupt, R/W */ 138 #define APC_IP 0x00800000u /* Interrupt Pending, R/O */ 139 #define APC_ID 0xff000000u /* ID bits, set to 7E, R/O */ 140 141 #define APC_ID_VALUE 0x7E000000u /* ID read from CSR */ 142 #define APC_CLEAR_RESET_VALUE 0x00 143 144 #define APC_PINTR_MASK (APC_PI|APC_PMI) 145 #define APC_CINTR_MASK (APC_CI|APC_CXI) 146 #define APC_COMMON_MASK (APC_IP|APC_EI) 147 #define APC_PINTR_ENABLE (APC_PIE|APC_PMI_EN) 148 #define APC_CINTR_ENABLE (APC_CIE|APC_CXI_EN) 149 #define APC_COMMON_ENABLE (APC_IE|APC_EIE) 150 151 #define APC_PLAY_ENABLE (APC_PINTR_MASK|APC_COMMON_MASK|\ 152 APC_PINTR_ENABLE|APC_COMMON_ENABLE|APC_PDMA_GO) 153 154 #define APC_PLAY_DISABLE (APC_PINTR_MASK|APC_PINTR_ENABLE|APC_PDMA_GO) 155 156 #define APC_CAP_ENABLE (APC_CINTR_MASK|APC_COMMON_MASK|\ 157 APC_CINTR_ENABLE|APC_COMMON_ENABLE|APC_CDMA_GO) 158 159 #define APC_CAP_DISABLE (APC_CINTR_MASK|APC_CINTR_ENABLE|APC_CDMA_GO) 160 161 /* 162 * These are the registers for the EBUS2 DMA channel interface to the 163 * 4231. One struct per channel for playback and record, therefore there 164 * individual handles for the CODEC and the two DMA engines. 165 */ 166 167 struct cs4231_eb2regs { 168 uint32_t eb2csr; /* Ebus 2 csr */ 169 uint32_t eb2acr; /* ebus 2 Addrs */ 170 uint32_t eb2bcr; /* ebus 2 counts */ 171 }; 172 typedef struct cs4231_eb2regs cs4231_eb2regs_t; 173 174 #define EB2_PLAY_CSR state->cs_eb2_regs.play->eb2csr 175 #define EB2_PLAY_ACR state->cs_eb2_regs.play->eb2acr 176 #define EB2_PLAY_BCR state->cs_eb2_regs.play->eb2bcr 177 #define EB2_REC_CSR state->cs_eb2_regs.record->eb2csr 178 #define EB2_REC_ACR state->cs_eb2_regs.record->eb2acr 179 #define EB2_REC_BCR state->cs_eb2_regs.record->eb2bcr 180 #define EB2_AUXIO_REG state->cs_eb2_regs.auxio 181 182 /* 183 * Audio auxio register definitions 184 */ 185 #define EB2_AUXIO_COD_PDWN 0x00000001u /* power down Codec */ 186 187 /* 188 * EBUS 2 CSR definitions 189 */ 190 191 #define EB2_INT_PEND 0x00000001u /* Interrupt pending, R/O */ 192 #define EB2_ERR_PEND 0x00000002u /* Error interrupt, R/O */ 193 #define EB2_DRAIN 0x00000004u /* FIFO being drained, R/O */ 194 #define EB2_INT_EN 0x00000010u /* Enable interrupts, R/W */ 195 #define EB2_RESET 0x00000080u /* Reset DMA engine, R/W */ 196 #define EB2_WRITE 0x00000100u /* DMA direction (to mem) R/W */ 197 #define EB2_READ 0x00000000u /* DMA direction (to dev) R/W */ 198 #define EB2_EN_DMA 0x00000200u /* Enable DMA, R/W */ 199 #define EB2_CYC_PENDING 0x00000400u /* DMA cycle pending, R/O */ 200 #define EB2_DIAG_RD_DONE 0x00000800u /* Diag RD done, R/O */ 201 #define EB2_DIAG_WR_DONE 0x00001000u /* Diag WR done, R/O */ 202 #define EB2_EN_CNT 0x00002000u /* Enable byte count, R/W */ 203 #define EB2_TC 0x00004000u /* Terminal count, R/W */ 204 #define EB2_DIS_CSR_DRN 0x00010000u /* Dis. drain with W-CSR, R/W */ 205 #define EB2_16 0x00000000u /* 19,18 == 0,0, R/W */ 206 #define EB2_32 0x00040000u /* 19,18 == 0,1, R/W */ 207 #define EB2_4 0x00080000u /* 19,18 == 1,0, R/W */ 208 #define EB2_64 0x000C0000u /* 19,18 == 1,1, R/W */ 209 #define EB2_DIAG_EN 0x00100000u /* DMA diag. enable, R/W */ 210 #define EB2_DIS_ERR_PEND 0x00400000u /* Disable Error int., R/W */ 211 #define EB2_TCI_DIS 0x00800000u /* Disable TC int., R/W */ 212 #define EB2_EN_NEXT 0x01000000u /* Next addr. enabled, R/W */ 213 #define EB2_DMA_ON 0x02000000u /* DMA engine enabled, R/O */ 214 #define EB2_A_LOADED 0x04000000u /* Address loaded, R/O */ 215 #define EB2_NA_LOADED 0x08000000u /* Next add. loaded, R/O */ 216 #define EB2_DEV_ID 0xf0000000u /* Device ID -0x0C, R/O */ 217 218 #define EB2_ID_VALUE 0xC0000000u /* ID read from CSR */ 219 #define EB2_PCLEAR_RESET_VALUE (EB2_READ|EB2_EN_NEXT|EB2_EN_CNT) 220 #define EB2_RCLEAR_RESET_VALUE (EB2_WRITE|EB2_EN_NEXT|EB2_EN_CNT) 221 222 #define EB2_PLAY_ENABLE (EB2_INT_EN|EB2_EN_DMA|EB2_EN_CNT|EB2_64|\ 223 EB2_PCLEAR_RESET_VALUE) 224 225 #define EB2_REC_ENABLE (EB2_INT_EN|EB2_EN_DMA|EB2_EN_CNT|EB2_64|\ 226 EB2_RCLEAR_RESET_VALUE) 227 228 #define EB2_FIFO_DRAIN (EB2_DRAIN|EB2_CYC_PENDING) 229 230 /* 231 * Misc. defines 232 */ 233 #define CS4231_REGS (32) 234 #define CS4231_NCOMPONENTS (1) 235 #define CS4231_COMPONENT (0) 236 #define CS4231_PWR_OFF (0) 237 #define CS4231_PWR_ON (1) 238 #define CS4231_TIMEOUT (100000) 239 #define CS4231_300MS (300*1000) 240 #define CS4231_PLAY 0 241 #define CS4231_REC 1 242 #define CS4231_NFRAGS 8 243 244 /* 245 * Supported dma engines and the ops vector 246 */ 247 enum cs_dmae_types {APC_DMA, EB2_DMA}; 248 typedef enum cs_dmae_types cs_dmae_types_e; 249 250 /* 251 * Hardware registers 252 */ 253 struct cs4231_pioregs { 254 uint8_t iar; /* index address register */ 255 uint8_t pad1[3]; /* pad */ 256 uint8_t idr; /* indexed data register */ 257 uint8_t pad2[3]; /* pad */ 258 uint8_t statr; /* status register */ 259 uint8_t pad3[3]; /* pad */ 260 uint8_t piodr; /* PIO data regsiter */ 261 uint8_t pad4[3]; 262 }; 263 typedef struct cs4231_pioregs cs4231_pioregs_t; 264 265 266 struct cs4231_eb2 { 267 cs4231_eb2regs_t *play; /* play EB2 registers */ 268 cs4231_eb2regs_t *record; /* record EB2 registers */ 269 uint_t *auxio; /* aux io - power down */ 270 }; 271 typedef struct cs4231_eb2 cs4231_eb2_t; 272 273 struct cs4231_regs { 274 cs4231_pioregs_t codec; /* CS4231 CODEC registers */ 275 cs4231_apc_t apc; /* gets mapped with CODEC */ 276 }; 277 typedef struct cs4231_regs cs4231_regs_t; 278 279 #define CS4231_IAR state->cs_regs->codec.iar /* Index Add. Reg. */ 280 #define CS4231_IDR state->cs_regs->codec.idr /* Index Data Reg. */ 281 #define CS4231_STATUS state->cs_regs->codec.statr /* Status Reg. */ 282 #define CS4231_PIODR state->cs_regs->codec.piodr /* PIO Data Reg. */ 283 284 /* 285 * Misc. state enumerations and structures 286 */ 287 struct cs4231_handle { 288 ddi_acc_handle_t cs_codec_hndl; /* CODEC handle, APC & EB2 */ 289 ddi_acc_handle_t cs_eb2_play_hndl; /* EB2 only, play handle */ 290 ddi_acc_handle_t cs_eb2_rec_hndl; /* EB2 only, record handle */ 291 ddi_acc_handle_t cs_eb2_auxio_hndl; /* EB2 only, auxio handle */ 292 }; 293 typedef struct cs4231_handle cs4231_handle_t; 294 #define CODEC_HANDLE state->cs_handles.cs_codec_hndl 295 #define APC_HANDLE state->cs_handles.cs_codec_hndl 296 #define EB2_PLAY_HNDL state->cs_handles.cs_eb2_play_hndl 297 #define EB2_REC_HNDL state->cs_handles.cs_eb2_rec_hndl 298 #define EB2_AUXIO_HNDL state->cs_handles.cs_eb2_auxio_hndl 299 300 /* 301 * CS_port_t - per port (playback or record) state 302 */ 303 struct CS_engine { 304 CS_state_t *ce_state; 305 audio_engine_t *ce_engine; 306 int ce_num; 307 unsigned ce_syncdir; 308 unsigned ce_intrs; 309 unsigned ce_fragfr; 310 unsigned ce_fragsz; 311 unsigned ce_nframes; 312 unsigned ce_cfrag; 313 boolean_t ce_started; 314 uint64_t ce_count; 315 316 size_t ce_size; 317 caddr_t ce_kaddr; 318 ddi_dma_handle_t ce_dmah; 319 ddi_acc_handle_t ce_acch; 320 uint32_t ce_paddr[CS4231_NFRAGS]; 321 322 /* registers (EB2 only) */ 323 ddi_acc_handle_t ce_regsh; 324 cs4231_eb2regs_t *ce_eb2regs; /* EB2 registers */ 325 326 /* codec enable */ 327 uint8_t ce_codec_en; 328 }; 329 330 struct CS_ctrl { 331 CS_state_t *cc_state; 332 audio_ctrl_t *cc_ctrl; 333 uint32_t cc_num; 334 uint64_t cc_val; 335 }; 336 337 /* 338 * CS_state_t - per instance state and operation data 339 */ 340 struct CS_state { 341 kmutex_t cs_lock; /* state protection lock */ 342 kcondvar_t cs_cv; /* suspend/resume cond. var. */ 343 ddi_iblock_cookie_t cs_iblock; /* iblock cookie */ 344 kstat_t *cs_ksp; /* kernel statistics */ 345 dev_info_t *cs_dip; /* used by cs4231_getinfo() */ 346 audio_dev_t *cs_adev; /* audio device state */ 347 348 cs_dmae_types_e cs_dma_engine; /* dma engine for this h/w */ 349 struct cs4231_dma_ops *cs_dma_ops; /* dma engine ops vector */ 350 cs4231_regs_t *cs_regs; /* hardware registers */ 351 cs4231_eb2_t cs_eb2_regs; /* eb2 DMA registers */ 352 cs4231_handle_t cs_handles; /* hardware handles */ 353 354 boolean_t cs_suspended; /* power management state */ 355 boolean_t cs_powered; /* device powered up? */ 356 357 CS_engine_t *cs_engines[2]; 358 359 boolean_t cs_revA; /* B_TRUE if Rev A CODEC */ 360 uint8_t cs_save[CS4231_REGS]; /* PM reg. storage */ 361 362 /* 363 * Control related fields. 364 */ 365 uint64_t cs_imask; 366 uint64_t cs_omask; 367 uint64_t cs_omod; /* modifiable ports */ 368 369 CS_ctrl_t *cs_ogain; 370 CS_ctrl_t *cs_igain; 371 CS_ctrl_t *cs_micboost; 372 CS_ctrl_t *cs_mgain; 373 CS_ctrl_t *cs_outputs; 374 CS_ctrl_t *cs_inputs; 375 }; 376 377 #define KIOP(X) ((kstat_intr_t *)(X->cs_ksp->ks_data)) 378 379 /* 380 * DMA ops vector definition 381 */ 382 struct cs4231_dma_ops { 383 char *dma_device; 384 ddi_dma_attr_t *cs_dma_attr; 385 int (*cs_dma_map_regs)(CS_state_t *); 386 void (*cs_dma_unmap_regs)(CS_state_t *); 387 void (*cs_dma_reset)(CS_state_t *); 388 int (*cs_dma_add_intr)(CS_state_t *); 389 void (*cs_dma_rem_intr)(CS_state_t *); 390 int (*cs_dma_start)(CS_engine_t *); 391 void (*cs_dma_stop)(CS_engine_t *); 392 void (*cs_dma_power)(CS_state_t *, int); 393 }; 394 typedef struct cs4231_dma_ops cs4231_dma_ops_t; 395 396 extern cs4231_dma_ops_t cs4231_apcdma_ops; 397 extern cs4231_dma_ops_t cs4231_eb2dma_ops; 398 399 #define CS4231_DMA_MAP_REGS(S) ((S)->cs_dma_ops->cs_dma_map_regs)(S) 400 #define CS4231_DMA_UNMAP_REGS(S) ((S)->cs_dma_ops->cs_dma_unmap_regs)(S) 401 #define CS4231_DMA_RESET(S) ((S)->cs_dma_ops->cs_dma_reset)(S) 402 #define CS4231_DMA_ADD_INTR(S) ((S)->cs_dma_ops->cs_dma_add_intr)(S) 403 #define CS4231_DMA_REM_INTR(S) ((S)->cs_dma_ops->cs_dma_rem_intr)(S) 404 #define CS4231_DMA_START(S, E) ((S)->cs_dma_ops->cs_dma_start)(E) 405 #define CS4231_DMA_STOP(S, E) ((S)->cs_dma_ops->cs_dma_stop)(E) 406 #define CS4231_DMA_POWER(S, L) ((S)->cs_dma_ops->cs_dma_power)(S, L) 407 #define CS4231_DMA_ATTR(S) ((S)->cs_dma_ops->cs_dma_attr) 408 409 /* 410 * Useful bit twiddlers 411 */ 412 #define CS4231_RETRIES 10 413 414 #define OR_SET_WORD(handle, addr, val) \ 415 ddi_put32((handle), (uint_t *)(addr), \ 416 (ddi_get32((handle), (uint_t *)(addr)) | (uint_t)(val))) 417 418 #define AND_SET_WORD(handle, addr, val) \ 419 ddi_put32((handle), (uint_t *)(addr), \ 420 (ddi_get32((handle), (uint_t *)(addr)) & (uint_t)(val))) 421 422 /* 423 * CS4231 Register Set Definitions 424 */ 425 /* Index Address Register */ 426 #define IAR_ADDRESS_MASK 0x1f /* mask for index addresses, R/W */ 427 #define IAR_TRD 0x20 /* Transfer Request Disable, R/W */ 428 #define IAR_MCE 0x40 /* Mode Change Enable, R/W */ 429 #define IAR_INIT 0x80 /* 4231 init cycle, R/O */ 430 431 /* Status Register */ 432 #define STATUS_INT 0x01 /* Interrupt status, R/O */ 433 #define STATUS_PRDY 0x02 /* Playback Data Ready */ 434 #define STATUS_PLR 0x04 /* Playback Left/Right sample */ 435 #define STATUS_PUL 0x08 /* Playback Upper/Lower byte */ 436 #define STATUS_SER 0x10 /* Sample Error, see Index 24 */ 437 #define STATUS_CRDY 0x20 /* Capture Data Ready */ 438 #define STATUS_CLR 0x40 /* Capture Left/Right sample */ 439 #define STATUS_CUL 0x80 /* Capture Upper/Lower byte */ 440 #define STATUS_RESET 0x00 /* Reset the status register */ 441 442 /* Index 00 - Left ADC Input Control, Modes 1&2 */ 443 #define LADCI_REG 0x00 /* Left ADC Register */ 444 #define LADCI_GAIN_MASK 0x0f /* Left gain mask, 1.5 dB/step */ 445 #define LADCI_LMGE 0x20 /* Left Mic Gain Enable, 20 dB stage */ 446 #define LADCI_LLINE 0x00 /* Left Line in enable */ 447 #define LADCI_LAUX1 0x40 /* Left AUX1 in enable */ 448 #define LADCI_LMIC 0x80 /* Left MIC in enable */ 449 #define LADCI_LLOOP 0xc0 /* Left Loopback enable */ 450 #define LADCI_IN_MASK 0xc0 /* Left input mask */ 451 #define LADCI_VALID_MASK 0xef /* Left valid bits mask */ 452 453 /* Index 01 - Right ADC Input Control, Modes 1&2 */ 454 #define RADCI_REG 0x01 /* Right ADC Register */ 455 #define RADCI_GAIN_MASK 0x0f /* Right gain mask, 1.5 dB/step */ 456 #define RADCI_RMGE 0x20 /* Right Mic Gain Enable, 20 dB stage */ 457 #define RADCI_RLINE 0x00 /* Right Line in enable */ 458 #define RADCI_RAUX1 0x40 /* Right AUX1 in enable */ 459 #define RADCI_RMIC 0x80 /* Right MIC in enable */ 460 #define RADCI_RLOOP 0xc0 /* Right Loopback enable */ 461 #define RADCI_IN_MASK 0xc0 /* Right input mask */ 462 #define RADCI_VALID_MASK 0xef /* Right valid bits mask */ 463 464 /* Index 02 - Left Aux #1 Input Control, Modes 1&2 */ 465 #define LAUX1_REG 0x02 /* Left Aux#1 Register */ 466 #define LAUX1_GAIN_MASK 0x1f /* Left Aux#1 gain mask, 1.5 dB/step */ 467 #define LAUX1_LX1M 0x80 /* Left Aux#1 mute */ 468 #define LAUX1_UNITY_GAIN 0x08 /* Left Aux#1 unity gain */ 469 #define LAUX1_VALID_MASK 0x9f /* Left valid bits mask */ 470 471 /* Index 03 - Right Aux #1 Input Control, Modes 1&2 */ 472 #define RAUX1_REG 0x03 /* Right Aux#1 Register */ 473 #define RAUX1_GAIN_MASK 0x1f /* Right Aux#1 gain mask, 1.5 dB/step */ 474 #define RAUX1_RX1M 0x80 /* Right Aux#1 mute */ 475 #define RAUX1_UNITY_GAIN 0x08 /* Right Aux#1 unity gain */ 476 #define RAUX1_VALID_MASK 0x9f /* Right valid bits mask */ 477 478 /* Index 04 - Left Aux #2 Input Control, Modes 1&2 */ 479 #define LAUX2_REG 0x04 /* Left Aux#2 Register */ 480 #define LAUX2_GAIN_MASK 0x1f /* Left Aux#2 gain mask, 1.5 dB/step */ 481 #define LAUX2_LX2M 0x80 /* Left Aux#2 mute */ 482 #define LAUX2_UNITY_GAIN 0x08 /* Left Aux#2 unity gain */ 483 #define LAUX2_VALID_MASK 0x9f /* Left valid bits mask */ 484 485 /* Index 05 - Right Aux #2 Input Control, Modes 1&2 */ 486 #define RAUX2_REG 0x05 /* Right Aux#2 Register */ 487 #define RAUX2_GAIN_MASK 0x1f /* Right Aux#2 gain mask, 1.5 dB/step */ 488 #define RAUX2_RX2M 0x80 /* Right Aux#2 mute */ 489 #define RAUX2_UNITY_GAIN 0x08 /* Right Aux#2 unity gain */ 490 #define RAUX2_VALID_MASK 0x9f /* Right valid bits mask */ 491 492 /* Index 06 - Left DAC Output Control, Modes 1&2 */ 493 #define LDACO_REG 0x06 /* Left DAC Register */ 494 #define LDACO_ATTEN_MASK 0x3f /* Left attenuation mask, 1.5 dB/setp */ 495 #define LDACO_LDM 0x80 /* Left mute */ 496 #define LDACO_MID_GAIN 0x11 /* Left DAC mid gain */ 497 #define LDAC0_VALID_MASK 0xbf /* Left valid bits mask */ 498 499 /* Index 07 - Right DAC Output Control, Modes 1&2 */ 500 #define RDACO_REG 0x07 /* Right DAC Register */ 501 #define RDACO_ATTEN_MASK 0x3f /* Right atten. mask, 1.5 dB/setp */ 502 #define RDACO_RDM 0x80 /* Right mute */ 503 #define RDACO_MID_GAIN 0x11 /* Right DAC mid gain */ 504 #define RDAC0_VALID_MASK 0xbf /* Right valid bits mask */ 505 506 /* Index 08 - Sample Rate and Data Format, Mode 2 only */ 507 #define FSDF_REG 0x08 /* Sample Rate & Data Format Register */ 508 #define FS_5510 0x01 /* XTAL2, Freq. Divide #0 */ 509 #define FS_6620 0x0f /* XTAL2, Freq. Divide #7 */ 510 #define FS_8000 0x00 /* XTAL1, Freq. Divide #0 */ 511 #define FS_9600 0x0e /* XTAL2, Freq. Divide #7 */ 512 #define FS_11025 0x03 /* XTAL2, Freq. Divide #1 */ 513 #define FS_16000 0x02 /* XTAL1, Freq. Divide #1 */ 514 #define FS_18900 0x05 /* XTAL2, Freq. Divide #2 */ 515 #define FS_22050 0x07 /* XTAL2, Freq. Divide #3 */ 516 #define FS_27420 0x04 /* XTAL1, Freq. Divide #2 */ 517 #define FS_32000 0x06 /* XTAL1, Freq. Divide #3 */ 518 #define FS_33075 0x0d /* XTAL2, Freq. Divide #6 */ 519 #define FS_37800 0x09 /* XTAL2, Freq. Divide #4 */ 520 #define FS_44100 0x0b /* XTAL2, Freq. Divide #5 */ 521 #define FS_48000 0x0c /* XTAL1, Freq. Divide #6 */ 522 #define PDF_STEREO 0x10 /* Stereo Playback */ 523 #define PDF_MONO 0x00 /* Mono Playback */ 524 #define PDF_LINEAR8 0x00 /* Linear, 8-bit unsigned */ 525 #define PDF_ULAW8 0x20 /* u-Law, 8-bit companded */ 526 #define PDF_LINEAR16LE 0x40 /* Linear, 16-bit signed, little end. */ 527 #define PDF_ALAW8 0x60 /* A-Law, 8-bit companded */ 528 #define PDF_ADPCM4 0xa0 /* ADPCM, 4-bit, IMA compatible */ 529 #define PDF_LINEAR16BE 0xc0 /* Linear, 16-bit signed, big endian */ 530 #define FSDF_VALID_MASK 0xff /* Valid bits mask */ 531 #ifdef _BIG_ENDIAN 532 #define PDF_LINEAR16NE PDF_LINEAR16BE 533 #else 534 #define PDF_LINEAR16NE PDF_LINEAR16LE 535 #endif 536 537 /* Index 09 - Interface Configuration, Mode 1&2 */ 538 #define INTC_REG 0x09 /* Interrupt Configuration Register */ 539 #define INTC_PEN 0x01 /* Playback enable */ 540 #define INTC_CEN 0x02 /* Capture enable */ 541 #define INTC_SDC 0x04 /* Single DMA channel */ 542 #define INTC_DDC 0x00 /* Dual DMA channels */ 543 #define INTC_ACAL 0x08 /* Auto-Calibrate Enable */ 544 #define INTC_PPIO 0x40 /* Playback vi PIO */ 545 #define INTC_PDMA 0x00 /* Playback vi DMA */ 546 #define INTC_CPIO 0x80 /* Capture vi PIO */ 547 #define INTC_CDMA 0x00 /* Capture vi DMA */ 548 #define INTC_VALID_MASK 0xcf /* Valid bits mask */ 549 550 /* Index 10 - Pin Control, Mode 1&2 */ 551 #define PC_REG 0x0a /* Pin Control Register */ 552 #define PC_IEN 0x02 /* Interrupt Enable */ 553 #define PC_DEN 0x04 /* Dither Enable */ 554 #define PC_XCTL0 0x40 /* External control 0 */ 555 #define PC_LINE_OUT_MUTE 0x40 /* Line Out Mute */ 556 #define PC_XCTL1 0x80 /* External control 1 */ 557 #define PC_HEADPHONE_MUTE 0x80 /* Headphone Mute */ 558 #define PC_VALID_MASK 0xca /* Valid bits mask */ 559 560 /* Index 11 - Error Status and Initialization, Mode 1&2 */ 561 #define ESI_REG 0x0b /* Error Status & Init. Register */ 562 #define ESI_ORL_MASK 0x03 /* Left ADC Overrange */ 563 #define ESI_ORR_MASK 0x0c /* Right ADC Overrange */ 564 #define ESI_DRS 0x10 /* DRQ status */ 565 #define ESI_ACI 0x20 /* Auto-Calibrate In Progress */ 566 #define ESI_PUR 0x40 /* Playback Underrun */ 567 #define ESI_COR 0x80 /* Capture Overrun */ 568 #define ESI_VALID_MASK 0xff /* Valid bits mask */ 569 570 /* Index 12 - Mode and ID, Modes 1&2 */ 571 #define MID_REG 0x0c /* Mode and ID Register */ 572 #define MID_ID_MASK 0x0f /* CODEC ID */ 573 #define MID_MODE2 0x40 /* Mode 2 enable */ 574 #define MID_VALID_MASK 0xcf /* Valid bits mask */ 575 576 /* Index 13 - Loopback Control, Modes 1&2 */ 577 #define LC_REG 0x0d /* Loopback Control Register */ 578 #define LC_LBE 0x01 /* Loopback Enable */ 579 #define LC_ATTEN_MASK 0xfc /* Loopback attenuation mask */ 580 #define LC_OFF 0x00 /* Loopback off */ 581 #define LC_VALID_MASK 0xfd /* Valid bits mask */ 582 583 /* Index 14 - Playback Upper Base, Mode 2 only */ 584 #define PUB_REG 0x0e /* Playback Upper Base Register */ 585 #define PUB_VALID_MASK 0xff /* Valid bits mask */ 586 587 /* Index 15 - Playback Lower Base, Mode 2 only */ 588 #define PLB_REG 0x0f /* Playback Lower Base Register */ 589 #define PLB_VALID_MASK 0xff /* Valid bits mask */ 590 591 /* Index 16 - Alternate Feature Enable 1, Mode 2 only */ 592 #define AFE1_REG 0x10 /* Alternate Feature Enable 1 Reg */ 593 #define AFE1_DACZ 0x01 /* DAC Zero */ 594 #define AFE1_TE 0x40 /* Timer Enable */ 595 #define AFE1_OLB 0x80 /* Output Level Bit, 1=2.8Vpp, 0=2Vpp */ 596 #define AFE1_VALID_MASK 0xc1 /* Valid bits mask */ 597 598 /* Index 17 - Alternate Feature Enable 2, Mode 2 only */ 599 #define AFE2_REG 0x11 /* Alternate Feature Enable 2 Reg */ 600 #define AFE2_HPF 0x01 /* High Pass Filter - DC blocking */ 601 #define AFE2_VALID_MASK 0x01 /* Valid bits mask */ 602 603 /* Index 18 - Left Line Input Control, Mode 2 only */ 604 #define LLIC_REG 0x12 /* Left Line Input Control Register */ 605 #define LLIC_MIX_GAIN_MASK 0x1f /* Left Mix Gain Mask, 1.5 dB/step */ 606 #define LLIC_LLM 0x80 /* Left Line Mute */ 607 #define LLIC_UNITY_GAIN 0x08 /* Left unit gain */ 608 #define LLIC_VALID_MASK 0x9f /* Left valid bits mask */ 609 610 /* Index 19 - Right Line Input Control, Mode 2 only */ 611 #define RLIC_REG 0x13 /* Right Line Input Control Register */ 612 #define RLIC_MIX_GAIN_MASK 0x1f /* Right Mix Gain Mask, 1.5 dB/step */ 613 #define RLIC_RLM 0x80 /* Right Line Mute */ 614 #define RLIC_UNITY_GAIN 0x08 /* Right unit gain */ 615 #define RLIC_VALID_MASK 0x9f /* Right valid bits mask */ 616 617 /* Index 20 - Timer Lower Byte, Mode 2 only */ 618 #define TLB_REG 0x14 /* Timer Lower Byte Register */ 619 #define TLB_VALID_MASK 0xff /* Valid bits mask */ 620 621 /* Index 21 - Timer Upper Byte, Mode 2 only */ 622 #define TUB_REG 0x15 /* Timer Upper Byte Register */ 623 #define TUB_VALID_MASK 0xff /* Valid bits mask */ 624 625 /* Index 22 and 23 are reserved */ 626 627 /* Index 24 - Alternate Feature Status, Mode 2 only */ 628 #define AFS_REG 0x18 /* Alternate Feature Status Register */ 629 #define AFS_PU 0x01 /* Playback Underrun */ 630 #define AFS_PO 0x02 /* Playback Overrun */ 631 #define AFS_CO 0x04 /* Capture Overrun */ 632 #define AFS_CU 0x08 /* Capture Underrun */ 633 #define AFS_PI 0x10 /* Playback Interrupt */ 634 #define AFS_CI 0x20 /* Capture Interrupt */ 635 #define AFS_TI 0x40 /* Timer Interrupt */ 636 #define AFS_RESET_STATUS 0x00 /* Reset the status register */ 637 #define AFS_VALID_MASK 0x7f /* Valid bits mask */ 638 639 /* Index 25 - Version and ID, Mode 2 only */ 640 #define VID_REG 0x19 /* Version and ID Register */ 641 #define VID_CID_MASK 0x07 /* Chip ID Mask */ 642 #define VID_VERSION_MASK 0xe0 /* Version number Mask */ 643 #define VID_A 0x20 /* Version A */ 644 #define VID_CDE 0x80 /* Versions C, D or E */ 645 #define VID_VALID_MASK 0xe7 /* Valid bits mask */ 646 647 /* Index 26 - Mono I/O Control, Mode 2 only */ 648 #define MIOC_REG 0x1a /* Mono I/O Control Register */ 649 #define MIOC_MI_ATTEN_MASK 0x0f /* Mono In Attenuation Mask */ 650 #define MIOC_MOM 0x40 /* Mono Out Mute */ 651 #define MIOC_MONO_SPKR_MUTE 0x40 /* Mono (internal) speaker mute */ 652 #define MIOC_MIM 0x80 /* Mono In Mute */ 653 #define MIOC_VALID_MASK 0xcf /* Valid bits mask */ 654 655 /* Index 27 is reserved */ 656 657 /* Index 28 - Capture Data Format, Mode 2 only */ 658 #define CDF_REG 0x1c /* Capture Date Foramt Register */ 659 #define CDF_STEREO 0x10 /* Stereo Capture */ 660 #define CDF_MONO 0x00 /* Mono Capture */ 661 #define CDF_LINEAR8 0x00 /* Linear, 8-bit unsigned */ 662 #define CDF_ULAW8 0x20 /* u-Law, 8-bit companded */ 663 #define CDF_LINEAR16LE 0x40 /* Linear, 16-bit signed, little end. */ 664 #define CDF_ALAW8 0x60 /* A-Law, 8-bit companded */ 665 #define CDF_ADPCM4 0xa0 /* ADPCM, 4-bit, IMA compatible */ 666 #define CDF_LINEAR16BE 0xc0 /* Linear, 16-bit signed, big endian */ 667 #define CDF_VALID_MASK 0xf0 /* Valid bits mask */ 668 #ifdef _BIG_ENDIAN 669 #define CDF_LINEAR16NE CDF_LINEAR16BE 670 #else 671 #define CDF_LINEAR16NE CDF_LINEAR16LE 672 #endif 673 674 /* Index 29 is reserved */ 675 676 /* Index 30 - Capture Upper Base, Mode 2 only */ 677 #define CUB_REG 0x1e /* Capture Upper Base Register */ 678 #define CUB_VALID_MASK 0xff /* Valid bits mask */ 679 680 /* Index 31 - Capture Lower Base, Mode 2 only */ 681 #define CLB_REG 0x1f /* Capture Lower Base Register */ 682 #define CLB_VALID_MASK 0xff /* Valid bits mask */ 683 684 #endif /* _KERNEL */ 685 686 #ifdef __cplusplus 687 } 688 #endif 689 690 #endif /* _AUDIO_4231_H */ 691