1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_VIS_SIMULATOR_H 28 #define _SYS_VIS_SIMULATOR_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 /* 33 * VIS opf codes, instruction type 34 */ 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 40 /* kstat structure for reporting kstats */ 41 extern struct visinfo_kstat visinfo; 42 43 typedef /* typical VIS instruction. */ 44 struct { 45 unsigned int op : 2; /* Top two bits. */ 46 unsigned int rd : 5; /* Destination. */ 47 unsigned int op3 : 6; /* Main op code. */ 48 unsigned int rs1 : 5; /* First operand. */ 49 unsigned int opf : 9; /* Floating-point op code. */ 50 unsigned int rs2 : 5; /* Second operand. */ 51 } vis_inst_type; 52 53 enum vis_opf { /* VIS opf codes. */ 54 edge8 = 0x0, 55 edge8n = 0x1, 56 edge8l = 0x2, 57 edge8ln = 0x3, 58 edge16 = 0x4, 59 edge16n = 0x5, 60 edge16l = 0x6, 61 edge16ln = 0x7, 62 edge32 = 0x8, 63 edge32n = 0x9, 64 edge32l = 0xa, 65 edge32ln = 0xb, 66 array8 = 0x10, 67 array16 = 0x12, 68 array32 = 0x14, 69 alignaddr = 0x18, 70 bmask = 0x19, 71 alignaddrl = 0x1a, 72 fcmple16 = 0x20, 73 fcmpne16 = 0x22, 74 fcmple32 = 0x24, 75 fcmpne32 = 0x26, 76 fcmpgt16 = 0x28, 77 fcmpeq16 = 0x2a, 78 fcmpgt32 = 0x2c, 79 fcmpeq32 = 0x2e, 80 fmul8x16 = 0x31, 81 fmul8x16au = 0x33, 82 fmul8x16al = 0x35, 83 fmul8sux16 = 0x36, 84 fmul8ulx16 = 0x37, 85 fmuld8sux16 = 0x38, 86 fmuld8ulx16 = 0x39, 87 fpack32 = 0x3a, 88 fpack16 = 0x3b, 89 fpackfix = 0x3d, 90 pdist = 0x3e, 91 faligndata = 0x48, 92 fpmerge = 0x4b, 93 bshuffle = 0x4c, 94 fexpand = 0x4d, 95 fpadd16 = 0x50, 96 fpadd16s = 0x51, 97 fpadd32 = 0x52, 98 fpadd32s = 0x53, 99 fpsub16 = 0x54, 100 fpsub16s = 0x55, 101 fpsub32 = 0x56, 102 fpsub32s = 0x57, 103 fzero = 0x60, 104 fzeros = 0x61, 105 fnor = 0x62, 106 fnors = 0x63, 107 fandnot2 = 0x64, 108 fandnot2s = 0x65, 109 fnot2 = 0x66, 110 fnot2s = 0x67, 111 fandnot1 = 0x68, 112 fandnot1s = 0x69, 113 fnot1 = 0x6a, 114 fnot1s = 0x6b, 115 fxor = 0x6c, 116 fxors = 0x6d, 117 fnand = 0x6e, 118 fnands = 0x6f, 119 fand = 0x70, 120 fands = 0x71, 121 fxnor = 0x72, 122 fxnors = 0x73, 123 fsrc1 = 0x74, 124 fsrc1s = 0x75, 125 fornot2 = 0x76, 126 fornot2s = 0x77, 127 fsrc2 = 0x78, 128 fsrc2s = 0x79, 129 fornot1 = 0x7a, 130 fornot1s = 0x7b, 131 for_op = 0x7c, /* compiler does not like the use */ 132 fors_op = 0x7d, /* of the key word "for" ! */ 133 fone = 0x7e, 134 fones = 0x7f, 135 siam = 0x81 136 }; 137 138 #define GSR_ALIGN_MASK UINT64_C(0x0000000000000007) 139 #define GSR_ALIGN_SHIFT 0 140 #define GSR_SCALE_MASK UINT64_C(0x00000000000000f8) 141 #define GSR_SCALE_SHIFT 3 142 #define GSR_IRND_MASK UINT64_C(0x0000000006000000) 143 #define GSR_IRND_SHIFT 25 144 #define GSR_IM_MASK UINT64_C(0x0000000008000000) 145 #define GSR_IM_SHIFT 27 146 #define GSR_MASK_MASK UINT64_C(0xffffffff00000000) 147 #define GSR_MASK_SHIFT 32 148 149 #define GSR_IM_IRND_MASK (GSR_IM_MASK | GSR_IRND_MASK) 150 #define GSR_ALIGN(gsr) ((gsr & GSR_ALIGN_MASK) >> GSR_ALIGN_SHIFT) 151 #define GSR_SCALE(gsr) ((gsr & GSR_SCALE_MASK) >> GSR_SCALE_SHIFT) 152 #define GSR_IRND(gsr) ((gsr & GSR_IRND_MASK) >> GSR_IRND_SHIFT) 153 #define GSR_IM(gsr) ((gsr & GSR_IM_MASK) >> GSR_IM_SHIFT) 154 #define GSR_MASK(gsr) ((gsr & GSR_MASK_MASK) >> GSR_MASK_SHIFT) 155 156 /* PUBLIC FUNCTIONS */ 157 158 /* 159 * vis_fpu_simulator simulates VIS FPU instructions only; reads and writes 160 * FPU data registers directly. 161 */ 162 163 extern enum ftt_type vis_fpu_simulator(fp_simd_type *, fp_inst_type, 164 struct regs *, void *, kfpu_t *); 165 166 /* 167 * Simulator for VIS loads and stores between floating-point unit and memory. 168 */ 169 enum ftt_type vis_fldst(fp_simd_type *, fp_inst_type, struct regs *, 170 void *, unsigned); 171 172 /* 173 * Simulator for rd %gsr instruction. 174 */ 175 enum ftt_type vis_rdgsr(fp_simd_type *, fp_inst_type, struct regs *, 176 void *, kfpu_t *); 177 178 /* 179 * Simulator for wr %gsr instruction. 180 */ 181 enum ftt_type vis_wrgsr(fp_simd_type *, fp_inst_type, struct regs *, 182 void *, kfpu_t *); 183 184 #ifdef __cplusplus 185 } 186 #endif 187 188 #endif /* _SYS_VIS_SIMULATOR_H */ 189