xref: /illumos-gate/usr/src/uts/intel/sys/cpu_module.h (revision dd23d762c65e503874085a3893fbd3df9688da30)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 2010 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  * Copyright 2019 Joyent, Inc.
26  * Copyright 2023 Oxide Computer Co.
27  */
28 
29 #ifndef _SYS_CPU_MODULE_H
30 #define	_SYS_CPU_MODULE_H
31 
32 #include <sys/types.h>
33 #include <sys/cpuvar.h>
34 #include <sys/nvpair.h>
35 #include <sys/mc.h>
36 #include <sys/sunddi.h>
37 #include <sys/x86_archext.h>
38 
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42 
43 #ifdef _KERNEL
44 
45 #define	CMIERR_BASE	0xc000
46 
47 typedef enum cmi_errno {
48 	CMI_SUCCESS = 0,
49 	/*
50 	 * CPU Module Interface API error return values/
51 	 */
52 	CMIERR_UNKNOWN = CMIERR_BASE,	/* no specific error reason reported */
53 	CMIERR_API,			/* API usage error caught */
54 	CMIERR_NOTSUP,			/* Unsupported operation */
55 	CMIERR_HDL_CLASS,		/* Inappropriate handle class */
56 	CMIERR_HDL_NOTFOUND,		/* Can't find handle for resource */
57 	CMIERR_MSRGPF,			/* #GP during cmi_hdl_{wr,rd}msr */
58 	CMIERR_INTERPOSE,		/* MSR/PCICFG interposition error */
59 	CMIERR_DEADLOCK,		/* Deadlock avoidance */
60 	/*
61 	 * Memory-controller related errors
62 	 */
63 	CMIERR_MC_ABSENT,		/* No, or not yet registered, MC ops */
64 	CMIERR_MC_NOTSUP,		/* Requested functionality unimpld */
65 	CMIERR_MC_NOMEMSCRUB,		/* No dram scrubber, or disabled */
66 	CMIERR_MC_SYNDROME,		/* Invalid syndrome or syndrome type */
67 	CMIERR_MC_BADSTATE,		/* MC driver state is invalid */
68 	CMIERR_MC_NOADDR,		/* Address not found */
69 	CMIERR_MC_RSRCNOTPRESENT,	/* Resource not present in system */
70 	CMIERR_MC_ADDRBITS,		/* Too few valid addr bits */
71 	CMIERR_MC_INVALUNUM,		/* Invalid input unum */
72 	CMIERR_MC_PARTIALUNUMTOPA,	/* unum to pa reflected physaddr */
73 	CMIERR_MC_NOTDIMMADDR,		/* Address not backed by DRAM */
74 	/*
75 	 * Cache related errors
76 	 */
77 	CMIERR_C_NODATA,		/* CPU didn't provide required data */
78 	CMIERR_C_BADCACHENO		/* Invalid cache number */
79 } cmi_errno_t;
80 
81 /*
82  * All access to cpu information is made via a handle, in order to get
83  * the desired info even when running non-natively.
84  *
85  * A CMI_HDL_NATIVE handle is used when we believe we are running on
86  * bare-metal.  If we *are* on bare metal then this handle type will
87  * get us through to the real hardware, and there will be a 1:1 correspondence
88  * between handles and cpu_t structures; if not, say we are a domU to
89  * some unknown/undetected/unannounced hypervisor then chances are the
90  * hypervisor is not exposing much hardware detail to us so we should
91  * be prepared for some operations that "cannot fail" to fail or return
92  * odd data.
93  *
94  * A CMI_HDL_SOLARIS_xVM_MCA handle is used when we are running
95  * in i86xpv architecture - dom0 to a Solaris xVM hypervisor - and want to
96  * use a handle on each real execution core (as opposed to vcpu)
97  * to perform MCA related activities.  The model for this handle type
98  * is that the hypervisor continues to own the real hardware and
99  * includes a polling service and #MC handler which forward error
100  * telemetry to dom0 for logging and diagnosis.  As such, the operations
101  * such as RDMSR and WRMSR for this handle type do *not* read and write
102  * real MSRs via hypercalls- instead they should provide the values from
103  * already-read MCA bank telemetry, and writes are discarded.
104  *
105  * If some application requires real MSR read and write access another
106  * handle class should be introduced.
107  */
108 
109 typedef struct cmi_hdl *cmi_hdl_t;	/* opaque chip/core/strand handle */
110 
111 enum cmi_hdl_class {
112 	CMI_HDL_NATIVE,
113 	CMI_HDL_SOLARIS_xVM_MCA,
114 	CMI_HDL_NEUTRAL
115 };
116 
117 struct regs;
118 
119 typedef struct cmi_mc_ops {
120 	cmi_errno_t (*cmi_mc_patounum)(void *, uint64_t, uint8_t, uint8_t,
121 	    uint32_t, int, mc_unum_t *);
122 	cmi_errno_t (*cmi_mc_unumtopa)(void *, mc_unum_t *, nvlist_t *,
123 	    uint64_t *);
124 	void (*cmi_mc_logout)(cmi_hdl_t, boolean_t, boolean_t);
125 } cmi_mc_ops_t;
126 
127 extern cmi_hdl_t cmi_init(enum cmi_hdl_class, uint_t, uint_t, uint_t);
128 extern void cmi_post_startup(void);
129 extern void cmi_post_mpstartup(void);
130 extern void cmi_fini(cmi_hdl_t);
131 
132 extern void cmi_hdl_hold(cmi_hdl_t);
133 extern void cmi_hdl_rele(cmi_hdl_t);
134 extern void *cmi_hdl_getcmidata(cmi_hdl_t);
135 extern void cmi_hdl_setspecific(cmi_hdl_t, void *);
136 extern void *cmi_hdl_getspecific(cmi_hdl_t);
137 extern const struct cmi_mc_ops *cmi_hdl_getmcops(cmi_hdl_t);
138 extern void *cmi_hdl_getmcdata(cmi_hdl_t);
139 extern enum cmi_hdl_class cmi_hdl_class(cmi_hdl_t);
140 
141 extern cmi_hdl_t cmi_hdl_lookup(enum cmi_hdl_class, uint_t, uint_t, uint_t);
142 extern cmi_hdl_t cmi_hdl_any(void);
143 
144 #define	CMI_HDL_WALK_NEXT	0
145 #define	CMI_HDL_WALK_DONE	1
146 extern void cmi_hdl_walk(int (*)(cmi_hdl_t, void *, void *, void *),
147     void *, void *, void *);
148 
149 extern void cmi_hdlconf_rdmsr_nohw(cmi_hdl_t);
150 extern void cmi_hdlconf_wrmsr_nohw(cmi_hdl_t);
151 extern cmi_errno_t cmi_hdl_rdmsr(cmi_hdl_t, uint_t, uint64_t *);
152 extern cmi_errno_t cmi_hdl_wrmsr(cmi_hdl_t, uint_t, uint64_t);
153 
154 extern void cmi_hdl_enable_mce(cmi_hdl_t);
155 extern uint_t cmi_hdl_vendor(cmi_hdl_t);
156 extern const char *cmi_hdl_vendorstr(cmi_hdl_t);
157 extern uint_t cmi_hdl_family(cmi_hdl_t);
158 extern uint_t cmi_hdl_model(cmi_hdl_t);
159 extern uint_t cmi_hdl_stepping(cmi_hdl_t);
160 extern uint_t cmi_hdl_chipid(cmi_hdl_t);
161 extern uint_t cmi_hdl_procnodeid(cmi_hdl_t);
162 extern uint_t cmi_hdl_coreid(cmi_hdl_t);
163 extern uint_t cmi_hdl_strandid(cmi_hdl_t);
164 extern uint_t cmi_hdl_strand_apicid(cmi_hdl_t);
165 extern uint_t cmi_hdl_procnodes_per_pkg(cmi_hdl_t);
166 extern boolean_t cmi_hdl_is_cmt(cmi_hdl_t);
167 extern x86_chiprev_t cmi_hdl_chiprev(cmi_hdl_t);
168 extern const char *cmi_hdl_chiprevstr(cmi_hdl_t);
169 extern uint32_t cmi_hdl_getsockettype(cmi_hdl_t);
170 extern const char *cmi_hdl_getsocketstr(cmi_hdl_t);
171 extern id_t cmi_hdl_logical_id(cmi_hdl_t);
172 extern uint16_t cmi_hdl_smbiosid(cmi_hdl_t);
173 extern uint_t cmi_hdl_smb_chipid(cmi_hdl_t);
174 extern nvlist_t *cmi_hdl_smb_bboard(cmi_hdl_t);
175 extern uint_t cmi_hdl_chipsig(cmi_hdl_t);
176 extern const char *cmi_hdl_chipident(cmi_hdl_t);
177 
178 extern int cmi_hdl_online(cmi_hdl_t, int, int *);
179 
180 #ifndef	__xpv
181 extern uint_t cmi_ntv_hwchipid(cpu_t *);
182 extern uint_t cmi_ntv_hwprocnodeid(cpu_t *);
183 extern uint_t cmi_ntv_hwcoreid(cpu_t *);
184 extern uint_t cmi_ntv_hwstrandid(cpu_t *);
185 extern void cmi_ntv_hwdisable_mce(cmi_hdl_t);
186 #endif	/* __xpv */
187 
188 typedef struct cmi_mca_regs {
189 	uint_t cmr_msrnum;
190 	uint64_t cmr_msrval;
191 } cmi_mca_regs_t;
192 
193 extern cmi_errno_t cmi_hdl_msrinject(cmi_hdl_t, cmi_mca_regs_t *, uint_t,
194     int);
195 extern void cmi_hdl_msrinterpose(cmi_hdl_t, cmi_mca_regs_t *, uint_t);
196 extern void cmi_hdl_msrforward(cmi_hdl_t, cmi_mca_regs_t *, uint_t);
197 extern boolean_t cmi_inj_tainted(void);
198 
199 extern void cmi_faulted_enter(cmi_hdl_t);
200 extern void cmi_faulted_exit(cmi_hdl_t);
201 
202 extern void cmi_pcird_nohw(void);
203 extern void cmi_pciwr_nohw(void);
204 extern uint8_t cmi_pci_getb(int, int, int, int, int *, ddi_acc_handle_t);
205 extern uint16_t cmi_pci_getw(int, int, int, int, int *, ddi_acc_handle_t);
206 extern uint32_t cmi_pci_getl(int, int, int, int, int *, ddi_acc_handle_t);
207 extern void cmi_pci_interposeb(int, int, int, int, uint8_t);
208 extern void cmi_pci_interposew(int, int, int, int, uint16_t);
209 extern void cmi_pci_interposel(int, int, int, int, uint32_t);
210 extern void cmi_pci_putb(int, int, int, int, ddi_acc_handle_t, uint8_t);
211 extern void cmi_pci_putw(int, int, int, int, ddi_acc_handle_t, uint16_t);
212 extern void cmi_pci_putl(int, int, int, int, ddi_acc_handle_t, uint32_t);
213 
214 extern void cmi_mca_init(cmi_hdl_t);
215 
216 extern void cmi_hdl_poke(cmi_hdl_t);
217 extern void cmi_hdl_int(cmi_hdl_t, int);
218 
219 extern void cmi_mca_trap(struct regs *);
220 
221 extern boolean_t cmi_panic_on_ue(void);
222 
223 extern void cmi_mc_register(cmi_hdl_t, const struct cmi_mc_ops *, void *);
224 extern cmi_errno_t cmi_mc_register_global(const struct cmi_mc_ops *, void *);
225 extern void cmi_mc_sw_memscrub_disable(void);
226 extern cmi_errno_t cmi_mc_patounum(uint64_t, uint8_t, uint8_t, uint32_t, int,
227     mc_unum_t *);
228 extern cmi_errno_t cmi_mc_unumtopa(mc_unum_t *, nvlist_t *, uint64_t *);
229 extern void cmi_mc_logout(cmi_hdl_t, boolean_t, boolean_t);
230 
231 extern void cmi_panic_callback(void);
232 
233 extern cmi_errno_t cmi_cache_ncaches(cmi_hdl_t, uint32_t *);
234 extern cmi_errno_t cmi_cache_info(cmi_hdl_t, uint32_t, x86_cache_t *);
235 
236 #endif /* _KERNEL */
237 
238 #ifdef __cplusplus
239 }
240 #endif
241 
242 #endif /* _SYS_CPU_MODULE_H */
243