xref: /illumos-gate/usr/src/uts/intel/io/pciex/pcie_nvidia.c (revision bd97c7ce2344fa3252d8785c35895490916bc79b)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
24  * Copyright 2023 Oxide Computer Company
25  */
26 
27 /*
28  *	Library file that has code for PCIe booting
29  */
30 
31 #include <sys/conf.h>
32 #include <sys/pci.h>
33 #include <sys/sunndi.h>
34 #include <sys/pcie.h>
35 #include <sys/pcie_impl.h>
36 #include <sys/pci_cfgspace.h>
37 #include <io/pciex/pcie_nvidia.h>
38 
39 /*
40  * PCI Configuration (Nvidia chipsets, PCIe) related library functions
41  */
42 
43 /* Globals */
44 extern int pci_boot_debug;
45 
46 extern uint64_t mcfg_mem_base;
47 
48 boolean_t
check_if_device_is_pciex(dev_info_t * cdip,uchar_t bus,uchar_t dev,uchar_t func,boolean_t * slot_valid,ushort_t * slot_number,ushort_t * is_pci_bridge)49 check_if_device_is_pciex(dev_info_t *cdip, uchar_t bus, uchar_t dev,
50     uchar_t func, boolean_t *slot_valid, ushort_t *slot_number,
51     ushort_t *is_pci_bridge)
52 {
53 	boolean_t found_pciex = B_FALSE;
54 	ushort_t cap;
55 	ushort_t capsp;
56 	ushort_t cap_count = PCI_CAP_MAX_PTR;
57 	ushort_t status;
58 	uint32_t slot_cap;
59 
60 	*slot_valid = B_FALSE;
61 
62 	status = (*pci_getw_func)(bus, dev, func, PCI_CONF_STAT);
63 	if (!(status & PCI_STAT_CAP))
64 		return (B_FALSE);
65 
66 	capsp = (*pci_getb_func)(bus, dev, func, PCI_CONF_CAP_PTR);
67 	while (cap_count-- && capsp >= PCI_CAP_PTR_OFF) {
68 		capsp &= PCI_CAP_PTR_MASK;
69 		cap = (*pci_getb_func)(bus, dev, func, capsp);
70 
71 		if (cap == PCI_CAP_ID_PCI_E) {
72 #ifdef	DEBUG
73 			if (pci_boot_debug)
74 				cmn_err(CE_CONT, "PCI-Express (%x,%x,%x) "
75 				    "capability found\n", bus, dev, func);
76 #endif	/* DEBUG */
77 
78 			status = (*pci_getw_func)(bus, dev, func, capsp + 2);
79 			/*
80 			 * See section 7.8.2 of PCI-Express Base Spec v1.0a
81 			 * for Device/Port Type.
82 			 * PCIE_PCIECAP_DEV_TYPE_PCIE2PCI implies that the
83 			 * device is a PCIe2PCI bridge
84 			 */
85 			*is_pci_bridge =
86 			    ((status & PCIE_PCIECAP_DEV_TYPE_MASK) ==
87 			    PCIE_PCIECAP_DEV_TYPE_PCIE2PCI) ? 1 : 0;
88 
89 			/*
90 			 * Check for "Slot  Implemented" bit
91 			 * PCIE_PCIECAP_SLOT_IMPL implies that.
92 			 */
93 			if (status & PCIE_PCIECAP_SLOT_IMPL) {
94 				/* offset 14h is Slot Cap Register */
95 				slot_cap = (*pci_getl_func)(bus, dev, func,
96 				    capsp + PCIE_SLOTCAP);
97 				*slot_valid = B_TRUE;
98 				*slot_number =
99 				    PCIE_SLOTCAP_PHY_SLOT_NUM(slot_cap);
100 			}
101 
102 			found_pciex = B_TRUE;
103 		}
104 
105 		capsp = (*pci_getb_func)(bus, dev, func,
106 		    capsp + PCI_CAP_NEXT_PTR);
107 	}
108 
109 	return (found_pciex);
110 }
111 
112 
113 /*
114  * scan all buses, devices, functions to look for any
115  * PCI-Express device in the system.
116  * If found, return B_TRUE else B_FALSE
117  */
118 boolean_t
look_for_any_pciex_device(uchar_t bus)119 look_for_any_pciex_device(uchar_t bus)
120 {
121 	uchar_t dev, func;
122 	uchar_t nfunc, header;
123 	ushort_t venid, slot_num, is_pci_bridge = 0;
124 	boolean_t slot_valid;
125 
126 	for (dev = 0; dev < 32; dev++) {
127 		nfunc = 1;
128 		for (func = 0; func < nfunc; func++) {
129 #ifdef	DEBUG
130 			if (pci_boot_debug)
131 				cmn_err(CE_NOTE, "pciex dev 0x%x, func 0x%x",
132 				    dev, func);
133 #endif	/* DEBUG */
134 
135 			venid = (*pci_getw_func)(bus, dev, func,
136 			    PCI_CONF_VENID);
137 			/* no function at this address */
138 			if ((venid == 0xffff) || (venid == 0))
139 				continue;
140 
141 			header = (*pci_getb_func)(bus, dev, func,
142 			    PCI_CONF_HEADER);
143 			if (header == 0xff)
144 				continue; /* illegal value */
145 
146 			/*
147 			 * according to some mail from Microsoft posted to
148 			 * the pci-drivers alias, their only requirement for
149 			 * a multifunction device is for the 1st function to
150 			 * have to PCI_HEADER_MULTI bit set.
151 			 */
152 			if ((func == 0) && (header & PCI_HEADER_MULTI))
153 				nfunc = 8;
154 
155 			if (check_if_device_is_pciex(NULL, bus, dev, func,
156 			    &slot_valid, &slot_num, &is_pci_bridge) == B_TRUE)
157 				return (B_TRUE);
158 		} /* end of func */
159 	} /* end of dev */
160 
161 	return (B_FALSE);
162 }
163 
164 boolean_t
create_pcie_root_bus(uchar_t bus,dev_info_t * dip)165 create_pcie_root_bus(uchar_t bus, dev_info_t *dip)
166 {
167 	/*
168 	 * Currently this is being hard-coded.
169 	 * We need to figure out if the root bus does indeed
170 	 * have PCI-Ex in the path by looking for MCFG in
171 	 * the ACPI tables
172 	 */
173 	if (look_for_any_pciex_device(bus) == B_FALSE)
174 		return (B_FALSE);
175 
176 #ifdef	DEBUG
177 	if (pci_boot_debug)
178 		cmn_err(CE_CONT, "Found PCI-Ex in the system\n");
179 #endif	/* DEBUG */
180 	(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip,
181 	    "device_type", "pciex");
182 	(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip,
183 	    "compatible", "pciex_root_complex");
184 
185 	pcie_rc_init_bus(dip);
186 
187 	return (B_TRUE);
188 }
189 
190 
191 /*
192  * add_nvidia_isa_bridge_props():
193  *	To enable native hotplug; we need to map in two I/O BARs
194  *	from ISA bridge's config space
195  *
196  * NOTE: For now, this function is only used for Nvidia's CrushK 8-04 chipsets.
197  */
198 void
add_nvidia_isa_bridge_props(dev_info_t * dip,uchar_t bus,uchar_t dev,uchar_t func)199 add_nvidia_isa_bridge_props(dev_info_t *dip, uchar_t bus, uchar_t dev,
200     uchar_t func)
201 {
202 	uint_t devloc, base;
203 	pci_regspec_t regs[2] = {{0}};
204 	pci_regspec_t assigned[2] = {{0}};
205 
206 	devloc = PCI_REG_MAKE_BDFR(bus, dev, func, 0);
207 	regs[0].pci_phys_hi = devloc;
208 
209 	/* System Control BAR i/o space */
210 	base = (*pci_getl_func)(bus, dev, func,
211 	    NVIDIA_CK804_ISA_SYSCTRL_BAR_OFF);
212 	regs[0].pci_size_low = assigned[0].pci_size_low = PCI_CONF_HDR_SIZE;
213 	assigned[0].pci_phys_hi = regs[0].pci_phys_hi = (PCI_RELOCAT_B |
214 	    PCI_ADDR_IO | devloc | NVIDIA_CK804_ISA_SYSCTRL_BAR_OFF);
215 	assigned[0].pci_phys_low = regs[0].pci_phys_low =
216 	    base & PCI_BASE_IO_ADDR_M;
217 
218 	/* Analog BAR i/o space */
219 	base = (*pci_getl_func)(bus, dev, func,
220 	    NVIDIA_CK804_ISA_ANALOG_BAR_OFF);
221 	regs[1].pci_size_low = assigned[1].pci_size_low = PCI_CONF_HDR_SIZE;
222 	assigned[1].pci_phys_hi = regs[1].pci_phys_hi = (PCI_RELOCAT_B |
223 	    PCI_ADDR_IO | devloc | NVIDIA_CK804_ISA_ANALOG_BAR_OFF);
224 	assigned[1].pci_phys_low = regs[1].pci_phys_low =
225 	    base & PCI_BASE_IO_ADDR_M;
226 
227 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "reg",
228 	    (int *)regs, 2 * sizeof (pci_regspec_t) / sizeof (int));
229 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip,
230 	    "assigned-addresses",
231 	    (int *)assigned, 2 * sizeof (pci_regspec_t) / sizeof (int));
232 }
233