1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved. 23 * Copyright 2019 Joyent, Inc. 24 * Copyright 2019 Western Digital Corporation 25 * Copyright 2020 OmniOS Community Edition (OmniOSce) Association. 26 * Copyright 2023 Oxide Computer Company 27 */ 28 29 /* 30 * PCI bus enumeration and device programming are done in several passes. The 31 * following is a high level overview of this process. 32 * 33 * pci_enumerate(reprogram=0) 34 * The main entry point to PCI bus enumeration is 35 * pci_enumerate(). This function is invoked 36 * twice, once to set up the PCI portion of the 37 * device tree, and then a second time to 38 * reprogram any devices which were not set up by 39 * the system firmware. On this first call, the 40 * reprogram parameter is set to 0. 41 * add_pci_fixes() 42 * enumerate_bus_devs(CONFIG_FIX) 43 * <foreach bus> 44 * process_devfunc(CONFIG_FIX) 45 * Some devices need a specific action taking in 46 * order for subsequent enumeration to be 47 * successful. add_pci_fixes() retrieves the 48 * vendor and device IDs for each item on the bus 49 * and applies fixes as required. It also creates 50 * a list which is used by undo_pci_fixes() to 51 * reverse the process later. 52 * pci_setup_tree() 53 * enumerate_bus_devs(CONFIG_INFO) 54 * <foreach bus> 55 * process_devfunc(CONFIG_INFO) 56 * <set up most device properties> 57 * The next stage is to enumerate the bus and set 58 * up the bulk of the properties for each device. 59 * This is where the generic properties such as 60 * 'device-id' are created. 61 * <if PPB device> 62 * add_ppb_props() 63 * For a PCI-to-PCI bridge (ppb) device, any 64 * memory ranges for IO, memory or pre-fetchable 65 * memory that have been programmed by the system 66 * firmware (BIOS/EFI) are retrieved and stored in 67 * bus-specific lists (pci_bus_res[bus].io_avail, 68 * mem_avail and pmem_avail). The contents of 69 * these lists are used to set the initial 'ranges' 70 * property on the ppb device. Later, as children 71 * are found for this bridge, resources will be 72 * removed from these avail lists as necessary. 73 * 74 * If the IO or memory ranges have not been 75 * programmed by this point, indicated by the 76 * appropriate bit in the control register being 77 * unset or, in the memory case only, by the base 78 * address being 0, then the range is explicitly 79 * disabled here by setting base > limit for 80 * the resource. Since a zero address is 81 * technically valid for the IO case, the base 82 * address is not checked for IO. 83 * 84 * This is an initial pass so the ppb devices can 85 * still be reprogrammed later in fix_ppb_res(). 86 * <else> 87 * <add to list of non-PPB devices for the bus> 88 * Any non-PPB device on the bus is recorded in a 89 * bus-specific list, to be set up (and possibly 90 * reprogrammed) later. 91 * add_reg_props(CONFIG_INFO) 92 * The final step in this phase is to add the 93 * initial 'reg' and 'assigned-addresses' 94 * properties to all devices. At the same time, 95 * any IO or memory ranges which have been 96 * assigned to the bus are moved from the avail 97 * list to the corresponding used one. If no 98 * resources have been assigned to a device at 99 * this stage, then it is flagged for subsequent 100 * reprogramming. 101 * undo_pci_fixes() 102 * Any fixes which were applied in add_pci_fixes() 103 * are now undone before returning, using the 104 * undo list which was created earier. 105 * 106 * pci_enumerate(reprogram=1) 107 * The second bus enumeration pass is to take care 108 * of any devices that were not set up by the 109 * system firmware. These devices were flagged 110 * during the first pass. This pass is bracketed 111 * by the same pci fix application and removal as 112 * the first. 113 * add_pci_fixes() 114 * As for first pass. 115 * pci_reprogram() 116 * pci_prd_root_complex_iter() 117 * The platform is asked to tell us of all root 118 * complexes that it knows about (e.g. using the 119 * _BBN method via ACPI). This will include buses 120 * that we've already discovered and those that we 121 * potentially haven't. Anything that has not been 122 * previously discovered (or inferred to exist) is 123 * then added to the system. 124 * <foreach ROOT bus> 125 * populate_bus_res() 126 * Find resources associated with this root bus 127 * based on what the platform provides through the 128 * pci platform interfaces defined in 129 * sys/plat/pci_prd.h. On i86pc this is driven by 130 * ACPI and BIOS tables. 131 * <foreach bus> 132 * fix_ppb_res() 133 * Reprogram pci(e) bridges which have not already 134 * had resources assigned, or which are under a 135 * bus that has been flagged for reprogramming. 136 * If the parent bus has not been flagged, then IO 137 * space is reprogrammed only if there are no 138 * assigned IO resources. Memory space is 139 * reprogrammed only if there is both no assigned 140 * ordinary memory AND no assigned pre-fetchable 141 * memory. However, if memory reprogramming is 142 * necessary then both ordinary and prefetch are 143 * done together so that both memory ranges end up 144 * in the avail lists for add_reg_props() to find 145 * later. 146 * enumerate_bus_devs(CONFIG_NEW) 147 * <foreach non-PPB device on the bus> 148 * add_reg_props(CONFIG_NEW) 149 * Using the list of non-PPB devices on the bus 150 * which was assembled during the first pass, add 151 * or update the 'reg' and 'assigned-address' 152 * properties for these devices. For devices which 153 * have been flagged for reprogramming or have no 154 * assigned resources, this is where resources are 155 * finally assigned and programmed into the 156 * device. This can result in these properties 157 * changing from their previous values. 158 * <foreach bus> 159 * add_bus_available_prop() 160 * Finally, the 'available' properties is set on 161 * each device, representing that device's final 162 * unallocated (available) IO and memory ranges. 163 * undo_pci_fixes() 164 * As for first pass. 165 */ 166 167 #include <sys/types.h> 168 #include <sys/stat.h> 169 #include <sys/sysmacros.h> 170 #include <sys/sunndi.h> 171 #include <sys/pci.h> 172 #include <sys/pci_impl.h> 173 #include <sys/pcie_impl.h> 174 #include <sys/memlist.h> 175 #include <sys/bootconf.h> 176 #include <sys/pci_cfgacc.h> 177 #include <sys/pci_cfgspace.h> 178 #include <sys/pci_cfgspace_impl.h> 179 #include <sys/psw.h> 180 #include "../../../../common/pci/pci_strings.h" 181 #include <sys/apic.h> 182 #include <io/pciex/pcie_nvidia.h> 183 #include <sys/hotplug/pci/pciehpc_acpi.h> 184 #include <sys/acpi/acpi.h> 185 #include <sys/acpica.h> 186 #include <sys/iommulib.h> 187 #include <sys/devcache.h> 188 #include <sys/pci_cfgacc_x86.h> 189 #include <sys/plat/pci_prd.h> 190 191 #define pci_getb (*pci_getb_func) 192 #define pci_getw (*pci_getw_func) 193 #define pci_getl (*pci_getl_func) 194 #define pci_putb (*pci_putb_func) 195 #define pci_putw (*pci_putw_func) 196 #define pci_putl (*pci_putl_func) 197 #define dcmn_err if (pci_boot_debug != 0) cmn_err 198 #define bus_debug(bus) (pci_boot_debug != 0 && pci_debug_bus_start != -1 && \ 199 pci_debug_bus_end != -1 && (bus) >= pci_debug_bus_start && \ 200 (bus) <= pci_debug_bus_end) 201 #define dump_memlists(tag, bus) \ 202 if (bus_debug((bus))) dump_memlists_impl((tag), (bus)) 203 #define MSGHDR "!%s[%02x/%02x/%x]: " 204 205 #define CONFIG_INFO 0 206 #define CONFIG_UPDATE 1 207 #define CONFIG_NEW 2 208 #define CONFIG_FIX 3 209 #define COMPAT_BUFSIZE 512 210 211 #define PPB_IO_ALIGNMENT 0x1000 /* 4K aligned */ 212 #define PPB_MEM_ALIGNMENT 0x100000 /* 1M aligned */ 213 /* round down to nearest power of two */ 214 #define P2LE(align) \ 215 { \ 216 uint_t i = 0; \ 217 while (align >>= 1) \ 218 i++; \ 219 align = 1 << i; \ 220 } \ 221 222 /* 223 * Determining the size of a PCI BAR is done by writing all 1s to the base 224 * register and then reading the value back. The retrieved value will either 225 * be zero, indicating that the BAR is unimplemented, or a mask in which 226 * the significant bits for the required memory space are 0. 227 * For example, a 32-bit BAR could return 0xfff00000 which equates to a 228 * length of 0x100000 (1MiB). The following macro does that conversion. 229 * The input value must have already had the lower encoding bits cleared. 230 */ 231 #define BARMASKTOLEN(value) ((((value) ^ ((value) - 1)) + 1) >> 1) 232 233 typedef enum { 234 RES_IO, 235 RES_MEM, 236 RES_PMEM 237 } mem_res_t; 238 239 /* 240 * In order to disable an IO or memory range on a bridge, the range's base must 241 * be set to a value greater than its limit. The following values are used for 242 * this purpose. 243 */ 244 #define PPB_DISABLE_IORANGE_BASE 0x9fff 245 #define PPB_DISABLE_IORANGE_LIMIT 0x1000 246 #define PPB_DISABLE_MEMRANGE_BASE 0x9ff00000 247 #define PPB_DISABLE_MEMRANGE_LIMIT 0x100fffff 248 249 /* See AMD-8111 Datasheet Rev 3.03, Page 149: */ 250 #define LPC_IO_CONTROL_REG_1 0x40 251 #define AMD8111_ENABLENMI (uint8_t)0x80 252 #define DEVID_AMD8111_LPC 0x7468 253 254 struct pci_fixundo { 255 uint8_t bus; 256 uint8_t dev; 257 uint8_t fn; 258 void (*undofn)(uint8_t, uint8_t, uint8_t); 259 struct pci_fixundo *next; 260 }; 261 262 struct pci_devfunc { 263 struct pci_devfunc *next; 264 dev_info_t *dip; 265 uchar_t dev; 266 uchar_t func; 267 boolean_t reprogram; /* this device needs to be reprogrammed */ 268 }; 269 270 extern int apic_nvidia_io_max; 271 extern int pseudo_isa; 272 static uchar_t max_dev_pci = 32; /* PCI standard */ 273 int pci_boot_maxbus; 274 275 int pci_boot_debug = 0; 276 int pci_debug_bus_start = -1; 277 int pci_debug_bus_end = -1; 278 279 static struct pci_fixundo *undolist = NULL; 280 static int num_root_bus = 0; /* count of root buses */ 281 extern void pci_cfgacc_add_workaround(uint16_t, uchar_t, uchar_t); 282 extern dev_info_t *pcie_get_rc_dip(dev_info_t *); 283 284 /* 285 * Module prototypes 286 */ 287 static void enumerate_bus_devs(uchar_t bus, int config_op); 288 static void create_root_bus_dip(uchar_t bus); 289 static void process_devfunc(uchar_t, uchar_t, uchar_t, uchar_t, 290 ushort_t, int); 291 static void add_compatible(dev_info_t *, ushort_t, ushort_t, 292 ushort_t, ushort_t, uchar_t, uint_t, int); 293 static boolean_t add_reg_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int, 294 boolean_t); 295 static void add_ppb_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int, 296 ushort_t); 297 static void add_model_prop(dev_info_t *, uint_t); 298 static void add_bus_range_prop(int); 299 static void add_ranges_prop(int, boolean_t); 300 static void add_bus_available_prop(int); 301 static int get_pci_cap(uchar_t bus, uchar_t dev, uchar_t func, uint8_t cap_id); 302 static void fix_ppb_res(uchar_t, boolean_t); 303 static void alloc_res_array(void); 304 static void create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid, 305 ushort_t deviceid); 306 static void pciex_slot_names_prop(dev_info_t *, ushort_t); 307 static void populate_bus_res(uchar_t bus); 308 static void memlist_remove_list(struct memlist **list, 309 struct memlist *remove_list); 310 static void ck804_fix_aer_ptr(dev_info_t *, pcie_req_id_t); 311 312 static int pci_unitaddr_cache_valid(void); 313 static int pci_bus_unitaddr(int); 314 static void pci_unitaddr_cache_create(void); 315 316 static int pci_cache_unpack_nvlist(nvf_handle_t, nvlist_t *, char *); 317 static int pci_cache_pack_nvlist(nvf_handle_t, nvlist_t **); 318 static void pci_cache_free_list(nvf_handle_t); 319 320 /* set non-zero to force PCI peer-bus renumbering */ 321 int pci_bus_always_renumber = 0; 322 323 /* 324 * used to register ISA resource usage which must not be made 325 * "available" from other PCI node' resource maps 326 */ 327 static struct { 328 struct memlist *io_used; 329 struct memlist *mem_used; 330 } isa_res; 331 332 /* 333 * PCI unit-address cache management 334 */ 335 static nvf_ops_t pci_unitaddr_cache_ops = { 336 "/etc/devices/pci_unitaddr_persistent", /* path to cache */ 337 pci_cache_unpack_nvlist, /* read in nvlist form */ 338 pci_cache_pack_nvlist, /* convert to nvlist form */ 339 pci_cache_free_list, /* free data list */ 340 NULL /* write complete callback */ 341 }; 342 343 typedef struct { 344 list_node_t pua_nodes; 345 int pua_index; 346 int pua_addr; 347 } pua_node_t; 348 349 nvf_handle_t puafd_handle; 350 int pua_cache_valid = 0; 351 352 dev_info_t * 353 pci_boot_bus_to_dip(uint32_t busno) 354 { 355 ASSERT3U(busno, <=, pci_boot_maxbus); 356 return (pci_bus_res[busno].dip); 357 } 358 359 static void 360 dump_memlists_impl(const char *tag, int bus) 361 { 362 printf("Memlist dump at %s - bus %x\n", tag, bus); 363 if (pci_bus_res[bus].io_used != NULL) { 364 printf(" io_used "); 365 memlist_dump(pci_bus_res[bus].io_used); 366 } 367 if (pci_bus_res[bus].io_avail != NULL) { 368 printf(" io_avail "); 369 memlist_dump(pci_bus_res[bus].io_avail); 370 } 371 if (pci_bus_res[bus].mem_used != NULL) { 372 printf(" mem_used "); 373 memlist_dump(pci_bus_res[bus].mem_used); 374 } 375 if (pci_bus_res[bus].mem_avail != NULL) { 376 printf(" mem_avail "); 377 memlist_dump(pci_bus_res[bus].mem_avail); 378 } 379 if (pci_bus_res[bus].pmem_used != NULL) { 380 printf(" pmem_used "); 381 memlist_dump(pci_bus_res[bus].pmem_used); 382 } 383 if (pci_bus_res[bus].pmem_avail != NULL) { 384 printf(" pmem_avail "); 385 memlist_dump(pci_bus_res[bus].pmem_avail); 386 } 387 } 388 389 static boolean_t 390 pci_rc_scan_cb(uint32_t busno, void *arg) 391 { 392 if (busno > pci_boot_maxbus) { 393 dcmn_err(CE_NOTE, "platform root complex scan returned bus " 394 "with invalid bus id: 0x%x", busno); 395 return (B_TRUE); 396 } 397 398 if (pci_bus_res[busno].par_bus == (uchar_t)-1 && 399 pci_bus_res[busno].dip == NULL) { 400 create_root_bus_dip((uchar_t)busno); 401 } 402 403 return (B_TRUE); 404 } 405 406 static void 407 pci_unitaddr_cache_init(void) 408 { 409 410 puafd_handle = nvf_register_file(&pci_unitaddr_cache_ops); 411 ASSERT(puafd_handle); 412 413 list_create(nvf_list(puafd_handle), sizeof (pua_node_t), 414 offsetof(pua_node_t, pua_nodes)); 415 416 rw_enter(nvf_lock(puafd_handle), RW_WRITER); 417 (void) nvf_read_file(puafd_handle); 418 rw_exit(nvf_lock(puafd_handle)); 419 } 420 421 /* 422 * Format of /etc/devices/pci_unitaddr_persistent: 423 * 424 * The persistent record of unit-address assignments contains 425 * a list of name/value pairs, where name is a string representation 426 * of the "index value" of the PCI root-bus and the value is 427 * the assigned unit-address. 428 * 429 * The "index value" is simply the zero-based index of the PCI 430 * root-buses ordered by physical bus number; first PCI bus is 0, 431 * second is 1, and so on. 432 */ 433 434 static int 435 pci_cache_unpack_nvlist(nvf_handle_t hdl, nvlist_t *nvl, char *name) 436 { 437 long index; 438 int32_t value; 439 nvpair_t *np; 440 pua_node_t *node; 441 442 np = NULL; 443 while ((np = nvlist_next_nvpair(nvl, np)) != NULL) { 444 /* name of nvpair is index value */ 445 if (ddi_strtol(nvpair_name(np), NULL, 10, &index) != 0) 446 continue; 447 448 if (nvpair_value_int32(np, &value) != 0) 449 continue; 450 451 node = kmem_zalloc(sizeof (pua_node_t), KM_SLEEP); 452 node->pua_index = index; 453 node->pua_addr = value; 454 list_insert_tail(nvf_list(hdl), node); 455 } 456 457 pua_cache_valid = 1; 458 return (DDI_SUCCESS); 459 } 460 461 static int 462 pci_cache_pack_nvlist(nvf_handle_t hdl, nvlist_t **ret_nvl) 463 { 464 int rval; 465 nvlist_t *nvl, *sub_nvl; 466 list_t *listp; 467 pua_node_t *pua; 468 char buf[13]; 469 470 ASSERT(RW_WRITE_HELD(nvf_lock(hdl))); 471 472 rval = nvlist_alloc(&nvl, NV_UNIQUE_NAME, KM_SLEEP); 473 if (rval != DDI_SUCCESS) { 474 nvf_error("%s: nvlist alloc error %d\n", 475 nvf_cache_name(hdl), rval); 476 return (DDI_FAILURE); 477 } 478 479 sub_nvl = NULL; 480 rval = nvlist_alloc(&sub_nvl, NV_UNIQUE_NAME, KM_SLEEP); 481 if (rval != DDI_SUCCESS) 482 goto error; 483 484 listp = nvf_list(hdl); 485 for (pua = list_head(listp); pua != NULL; 486 pua = list_next(listp, pua)) { 487 (void) snprintf(buf, sizeof (buf), "%d", pua->pua_index); 488 rval = nvlist_add_int32(sub_nvl, buf, pua->pua_addr); 489 if (rval != DDI_SUCCESS) 490 goto error; 491 } 492 493 rval = nvlist_add_nvlist(nvl, "table", sub_nvl); 494 if (rval != DDI_SUCCESS) 495 goto error; 496 nvlist_free(sub_nvl); 497 498 *ret_nvl = nvl; 499 return (DDI_SUCCESS); 500 501 error: 502 nvlist_free(sub_nvl); 503 ASSERT(nvl); 504 nvlist_free(nvl); 505 *ret_nvl = NULL; 506 return (DDI_FAILURE); 507 } 508 509 static void 510 pci_cache_free_list(nvf_handle_t hdl) 511 { 512 list_t *listp; 513 pua_node_t *pua; 514 515 ASSERT(RW_WRITE_HELD(nvf_lock(hdl))); 516 517 listp = nvf_list(hdl); 518 for (pua = list_head(listp); pua != NULL; 519 pua = list_next(listp, pua)) { 520 list_remove(listp, pua); 521 kmem_free(pua, sizeof (pua_node_t)); 522 } 523 } 524 525 526 static int 527 pci_unitaddr_cache_valid(void) 528 { 529 530 /* read only, no need for rw lock */ 531 return (pua_cache_valid); 532 } 533 534 535 static int 536 pci_bus_unitaddr(int index) 537 { 538 pua_node_t *pua; 539 list_t *listp; 540 int addr; 541 542 rw_enter(nvf_lock(puafd_handle), RW_READER); 543 544 addr = -1; /* default return if no match */ 545 listp = nvf_list(puafd_handle); 546 for (pua = list_head(listp); pua != NULL; 547 pua = list_next(listp, pua)) { 548 if (pua->pua_index == index) { 549 addr = pua->pua_addr; 550 break; 551 } 552 } 553 554 rw_exit(nvf_lock(puafd_handle)); 555 return (addr); 556 } 557 558 static void 559 pci_unitaddr_cache_create(void) 560 { 561 int i, index; 562 pua_node_t *node; 563 list_t *listp; 564 565 rw_enter(nvf_lock(puafd_handle), RW_WRITER); 566 567 index = 0; 568 listp = nvf_list(puafd_handle); 569 for (i = 0; i <= pci_boot_maxbus; i++) { 570 /* skip non-root (peer) PCI busses */ 571 if ((pci_bus_res[i].par_bus != (uchar_t)-1) || 572 pci_bus_res[i].dip == NULL) 573 continue; 574 node = kmem_zalloc(sizeof (pua_node_t), KM_SLEEP); 575 node->pua_index = index++; 576 node->pua_addr = pci_bus_res[i].root_addr; 577 list_insert_tail(listp, node); 578 } 579 580 (void) nvf_mark_dirty(puafd_handle); 581 rw_exit(nvf_lock(puafd_handle)); 582 nvf_wake_daemon(); 583 } 584 585 586 /* 587 * Enumerate all PCI devices 588 */ 589 void 590 pci_setup_tree(void) 591 { 592 uint_t i, root_bus_addr = 0; 593 594 alloc_res_array(); 595 for (i = 0; i <= pci_boot_maxbus; i++) { 596 pci_bus_res[i].par_bus = (uchar_t)-1; 597 pci_bus_res[i].root_addr = (uchar_t)-1; 598 pci_bus_res[i].sub_bus = i; 599 } 600 601 pci_bus_res[0].root_addr = root_bus_addr++; 602 create_root_bus_dip(0); 603 enumerate_bus_devs(0, CONFIG_INFO); 604 605 /* 606 * Now enumerate peer busses 607 * 608 * We loop till pci_boot_maxbus. On most systems, there is 609 * one more bus at the high end, which implements the ISA 610 * compatibility bus. We don't care about that. 611 * 612 * Note: In the old (bootconf) enumeration, the peer bus 613 * address did not use the bus number, and there were 614 * too many peer busses created. The root_bus_addr is 615 * used to maintain the old peer bus address assignment. 616 * However, we stop enumerating phantom peers with no 617 * device below. 618 */ 619 for (i = 1; i <= pci_boot_maxbus; i++) { 620 if (pci_bus_res[i].dip == NULL) { 621 pci_bus_res[i].root_addr = root_bus_addr++; 622 } 623 enumerate_bus_devs(i, CONFIG_INFO); 624 } 625 } 626 627 void 628 pci_register_isa_resources(int type, uint32_t base, uint32_t size) 629 { 630 (void) memlist_insert( 631 (type == 1) ? &isa_res.io_used : &isa_res.mem_used, 632 base, size); 633 } 634 635 /* 636 * Remove the resources which are already used by devices under a subtractive 637 * bridge from the bus's resources lists, because they're not available, and 638 * shouldn't be allocated to other buses. This is necessary because tracking 639 * resources for subtractive bridges is not complete. (Subtractive bridges only 640 * track some of their claimed resources, not "the rest of the address space" as 641 * they should, so that allocation to peer non-subtractive PPBs is easier. We 642 * need a fully-capable global resource allocator). 643 */ 644 static void 645 remove_subtractive_res() 646 { 647 int i, j; 648 struct memlist *list; 649 650 for (i = 0; i <= pci_boot_maxbus; i++) { 651 if (pci_bus_res[i].subtractive) { 652 /* remove used io ports */ 653 list = pci_bus_res[i].io_used; 654 while (list) { 655 for (j = 0; j <= pci_boot_maxbus; j++) 656 (void) memlist_remove( 657 &pci_bus_res[j].io_avail, 658 list->ml_address, list->ml_size); 659 list = list->ml_next; 660 } 661 /* remove used mem resource */ 662 list = pci_bus_res[i].mem_used; 663 while (list) { 664 for (j = 0; j <= pci_boot_maxbus; j++) { 665 (void) memlist_remove( 666 &pci_bus_res[j].mem_avail, 667 list->ml_address, list->ml_size); 668 (void) memlist_remove( 669 &pci_bus_res[j].pmem_avail, 670 list->ml_address, list->ml_size); 671 } 672 list = list->ml_next; 673 } 674 /* remove used prefetchable mem resource */ 675 list = pci_bus_res[i].pmem_used; 676 while (list) { 677 for (j = 0; j <= pci_boot_maxbus; j++) { 678 (void) memlist_remove( 679 &pci_bus_res[j].pmem_avail, 680 list->ml_address, list->ml_size); 681 (void) memlist_remove( 682 &pci_bus_res[j].mem_avail, 683 list->ml_address, list->ml_size); 684 } 685 list = list->ml_next; 686 } 687 } 688 } 689 } 690 691 /* 692 * Set up (or complete the setup of) the bus_avail resource list 693 */ 694 static void 695 setup_bus_res(int bus) 696 { 697 uchar_t par_bus; 698 699 if (pci_bus_res[bus].dip == NULL) /* unused bus */ 700 return; 701 702 /* 703 * Set up bus_avail if not already filled in by populate_bus_res() 704 */ 705 if (pci_bus_res[bus].bus_avail == NULL) { 706 ASSERT(pci_bus_res[bus].sub_bus >= bus); 707 memlist_insert(&pci_bus_res[bus].bus_avail, bus, 708 pci_bus_res[bus].sub_bus - bus + 1); 709 } 710 711 ASSERT(pci_bus_res[bus].bus_avail != NULL); 712 713 /* 714 * Remove resources from parent bus node if this is not a 715 * root bus. 716 */ 717 par_bus = pci_bus_res[bus].par_bus; 718 if (par_bus != (uchar_t)-1) { 719 ASSERT(pci_bus_res[par_bus].bus_avail != NULL); 720 memlist_remove_list(&pci_bus_res[par_bus].bus_avail, 721 pci_bus_res[bus].bus_avail); 722 } 723 724 /* remove self from bus_avail */; 725 (void) memlist_remove(&pci_bus_res[bus].bus_avail, bus, 1); 726 } 727 728 /* 729 * Return the bus from which resources should be allocated. A device under a 730 * subtractive PPB can allocate resources from its parent bus if there are no 731 * resources available on its own bus, so iterate up the chain until resources 732 * are found or the root is reached. 733 */ 734 static uchar_t 735 resolve_alloc_bus(uchar_t bus, mem_res_t type) 736 { 737 while (pci_bus_res[bus].subtractive) { 738 if (type == RES_IO && pci_bus_res[bus].io_avail != NULL) 739 break; 740 if (type == RES_MEM && pci_bus_res[bus].mem_avail != NULL) 741 break; 742 if (type == RES_PMEM && pci_bus_res[bus].pmem_avail != NULL) 743 break; 744 /* Has the root bus been reached? */ 745 if (pci_bus_res[bus].par_bus == (uchar_t)-1) 746 break; 747 bus = pci_bus_res[bus].par_bus; 748 } 749 750 return (bus); 751 } 752 753 /* 754 * Each root port has a record of the number of PCIe bridges that is under it 755 * and the amount of memory that is has available which is not otherwise 756 * required for BARs. 757 * 758 * This function finds the root port for a given bus and returns the amount of 759 * spare memory that is available for allocation to any one of its bridges. In 760 * general, not all bridges end up being reprogrammed, so this is usually an 761 * underestimate. A smarter allocator could account for this by building up a 762 * better picture of the topology. 763 */ 764 static uint64_t 765 get_per_bridge_avail(uchar_t bus) 766 { 767 uchar_t par_bus; 768 769 par_bus = pci_bus_res[bus].par_bus; 770 while (par_bus != (uchar_t)-1) { 771 bus = par_bus; 772 par_bus = pci_bus_res[par_bus].par_bus; 773 } 774 775 if (pci_bus_res[bus].mem_buffer == 0 || 776 pci_bus_res[bus].num_bridge == 0) { 777 return (0); 778 } 779 780 return (pci_bus_res[bus].mem_buffer / pci_bus_res[bus].num_bridge); 781 } 782 783 static uint64_t 784 lookup_parbus_res(uchar_t parbus, uint64_t size, uint64_t align, mem_res_t type) 785 { 786 struct memlist **list; 787 uint64_t addr; 788 789 /* 790 * Skip root(peer) buses in multiple-root-bus systems when 791 * ACPI resource discovery was not successfully done; the 792 * initial resources set on each root bus might not be correctly 793 * accounted for in this case. 794 */ 795 if (pci_bus_res[parbus].par_bus == (uchar_t)-1 && 796 num_root_bus > 1 && !pci_prd_multi_root_ok()) { 797 return (0); 798 } 799 800 parbus = resolve_alloc_bus(parbus, type); 801 802 switch (type) { 803 case RES_IO: 804 list = &pci_bus_res[parbus].io_avail; 805 break; 806 case RES_MEM: 807 list = &pci_bus_res[parbus].mem_avail; 808 break; 809 case RES_PMEM: 810 list = &pci_bus_res[parbus].pmem_avail; 811 break; 812 default: 813 panic("Invalid resource type %d", type); 814 } 815 816 if (*list == NULL) 817 return (0); 818 819 addr = memlist_find(list, size, align); 820 821 return (addr); 822 } 823 824 /* 825 * Allocate a resource from the parent bus 826 */ 827 static uint64_t 828 get_parbus_res(uchar_t parbus, uchar_t bus, uint64_t size, uint64_t align, 829 mem_res_t type) 830 { 831 struct memlist **par_avail, **par_used, **avail, **used; 832 uint64_t addr; 833 834 parbus = resolve_alloc_bus(parbus, type); 835 836 switch (type) { 837 case RES_IO: 838 par_avail = &pci_bus_res[parbus].io_avail; 839 par_used = &pci_bus_res[parbus].io_used; 840 avail = &pci_bus_res[bus].io_avail; 841 used = &pci_bus_res[bus].io_used; 842 break; 843 case RES_MEM: 844 par_avail = &pci_bus_res[parbus].mem_avail; 845 par_used = &pci_bus_res[parbus].mem_used; 846 avail = &pci_bus_res[bus].mem_avail; 847 used = &pci_bus_res[bus].mem_used; 848 break; 849 case RES_PMEM: 850 par_avail = &pci_bus_res[parbus].pmem_avail; 851 par_used = &pci_bus_res[parbus].pmem_used; 852 avail = &pci_bus_res[bus].pmem_avail; 853 used = &pci_bus_res[bus].pmem_used; 854 break; 855 default: 856 panic("Invalid resource type %d", type); 857 } 858 859 /* Return any existing resources to the parent bus */ 860 memlist_subsume(used, avail); 861 for (struct memlist *m = *avail; m != NULL; m = m->ml_next) { 862 (void) memlist_remove(par_used, m->ml_address, m->ml_size); 863 memlist_insert(par_avail, m->ml_address, m->ml_size); 864 } 865 memlist_free_all(avail); 866 867 addr = lookup_parbus_res(parbus, size, align, type); 868 869 /* 870 * The system may have provided a 64-bit non-PF memory region to the 871 * parent bus, but we cannot use that for programming a bridge. Since 872 * the memlists are kept sorted by base address and searched in order, 873 * then if we received a 64-bit address here we know that the request 874 * is unsatisfiable from the available 32-bit ranges. 875 */ 876 if (type == RES_MEM && 877 (addr >= UINT32_MAX || addr >= UINT32_MAX - size)) { 878 return (0); 879 } 880 881 if (addr != 0) { 882 memlist_insert(par_used, addr, size); 883 (void) memlist_remove(par_avail, addr, size); 884 memlist_insert(avail, addr, size); 885 } 886 887 return (addr); 888 } 889 890 /* 891 * given a cap_id, return its cap_id location in config space 892 */ 893 static int 894 get_pci_cap(uchar_t bus, uchar_t dev, uchar_t func, uint8_t cap_id) 895 { 896 uint8_t curcap, cap_id_loc; 897 uint16_t status; 898 int location = -1; 899 900 /* 901 * Need to check the Status register for ECP support first. 902 * Also please note that for type 1 devices, the 903 * offset could change. Should support type 1 next. 904 */ 905 status = pci_getw(bus, dev, func, PCI_CONF_STAT); 906 if (!(status & PCI_STAT_CAP)) { 907 return (-1); 908 } 909 cap_id_loc = pci_getb(bus, dev, func, PCI_CONF_CAP_PTR); 910 911 /* Walk the list of capabilities */ 912 while (cap_id_loc && cap_id_loc != (uint8_t)-1) { 913 curcap = pci_getb(bus, dev, func, cap_id_loc); 914 915 if (curcap == cap_id) { 916 location = cap_id_loc; 917 break; 918 } 919 cap_id_loc = pci_getb(bus, dev, func, cap_id_loc + 1); 920 } 921 return (location); 922 } 923 924 /* 925 * Does this resource element live in the legacy VGA range? 926 */ 927 928 static boolean_t 929 is_vga(struct memlist *elem, mem_res_t type) 930 { 931 switch (type) { 932 case RES_IO: 933 if ((elem->ml_address == 0x3b0 && elem->ml_size == 0xc) || 934 (elem->ml_address == 0x3c0 && elem->ml_size == 0x20)) { 935 return (B_TRUE); 936 } 937 break; 938 case RES_MEM: 939 if (elem->ml_address == 0xa0000 && elem->ml_size == 0x20000) 940 return (B_TRUE); 941 break; 942 case RES_PMEM: 943 break; 944 } 945 return (B_FALSE); 946 } 947 948 /* 949 * Does this entire resource list consist only of legacy VGA resources? 950 */ 951 952 static boolean_t 953 list_is_vga_only(struct memlist *l, mem_res_t type) 954 { 955 if (l == NULL) { 956 return (B_FALSE); 957 } 958 959 do { 960 if (!is_vga(l, type)) 961 return (B_FALSE); 962 } while ((l = l->ml_next) != NULL); 963 return (B_TRUE); 964 } 965 966 /* 967 * Find the start and end addresses that cover the range for all list entries, 968 * excluding legacy VGA addresses. Relies on the list being sorted. 969 */ 970 static void 971 pci_memlist_range(struct memlist *list, mem_res_t type, uint64_t *basep, 972 uint64_t *limitp) 973 { 974 *limitp = *basep = 0; 975 976 for (; list != NULL; list = list->ml_next) { 977 if (is_vga(list, type)) 978 continue; 979 980 if (*basep == 0) 981 *basep = list->ml_address; 982 983 if (list->ml_address + list->ml_size >= *limitp) 984 *limitp = list->ml_address + list->ml_size - 1; 985 } 986 } 987 988 static void 989 set_ppb_res(uchar_t bus, uchar_t dev, uchar_t func, mem_res_t type, 990 uint64_t base, uint64_t limit) 991 { 992 char *tag; 993 994 switch (type) { 995 case RES_IO: { 996 VERIFY0(base >> 32); 997 VERIFY0(limit >> 32); 998 999 pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW, 1000 (uint8_t)((base >> PCI_BCNF_IO_SHIFT) & PCI_BCNF_IO_MASK)); 1001 pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW, 1002 (uint8_t)((limit >> PCI_BCNF_IO_SHIFT) & PCI_BCNF_IO_MASK)); 1003 1004 uint8_t val = pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW); 1005 if ((val & PCI_BCNF_ADDR_MASK) == PCI_BCNF_IO_32BIT) { 1006 pci_putw(bus, dev, func, PCI_BCNF_IO_BASE_HI, 1007 base >> 16); 1008 pci_putw(bus, dev, func, PCI_BCNF_IO_LIMIT_HI, 1009 limit >> 16); 1010 } else { 1011 VERIFY0(base >> 16); 1012 VERIFY0(limit >> 16); 1013 } 1014 1015 tag = "I/O"; 1016 break; 1017 } 1018 1019 case RES_MEM: 1020 VERIFY0(base >> 32); 1021 VERIFY0(limit >> 32); 1022 1023 pci_putw(bus, dev, func, PCI_BCNF_MEM_BASE, 1024 (uint16_t)((base >> PCI_BCNF_MEM_SHIFT) & 1025 PCI_BCNF_MEM_MASK)); 1026 pci_putw(bus, dev, func, PCI_BCNF_MEM_LIMIT, 1027 (uint16_t)((limit >> PCI_BCNF_MEM_SHIFT) & 1028 PCI_BCNF_MEM_MASK)); 1029 1030 tag = "MEM"; 1031 break; 1032 1033 case RES_PMEM: { 1034 pci_putw(bus, dev, func, PCI_BCNF_PF_BASE_LOW, 1035 (uint16_t)((base >> PCI_BCNF_MEM_SHIFT) & 1036 PCI_BCNF_MEM_MASK)); 1037 pci_putw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW, 1038 (uint16_t)((limit >> PCI_BCNF_MEM_SHIFT) & 1039 PCI_BCNF_MEM_MASK)); 1040 1041 uint16_t val = pci_getw(bus, dev, func, PCI_BCNF_PF_BASE_LOW); 1042 if ((val & PCI_BCNF_ADDR_MASK) == PCI_BCNF_PF_MEM_64BIT) { 1043 pci_putl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH, 1044 base >> 32); 1045 pci_putl(bus, dev, func, PCI_BCNF_PF_LIMIT_HIGH, 1046 limit >> 32); 1047 } else { 1048 VERIFY0(base >> 32); 1049 VERIFY0(limit >> 32); 1050 } 1051 1052 tag = "PMEM"; 1053 break; 1054 } 1055 1056 default: 1057 panic("Invalid resource type %d", type); 1058 } 1059 1060 if (base > limit) { 1061 cmn_err(CE_NOTE, MSGHDR "DISABLE %4s range", 1062 "ppb", bus, dev, func, tag); 1063 } else { 1064 cmn_err(CE_NOTE, 1065 MSGHDR "PROGRAM %4s range 0x%lx ~ 0x%lx", 1066 "ppb", bus, dev, func, tag, base, limit); 1067 } 1068 } 1069 1070 static void 1071 fetch_ppb_res(uchar_t bus, uchar_t dev, uchar_t func, mem_res_t type, 1072 uint64_t *basep, uint64_t *limitp) 1073 { 1074 uint64_t val, base, limit; 1075 1076 switch (type) { 1077 case RES_IO: 1078 val = pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW); 1079 limit = ((val & PCI_BCNF_IO_MASK) << PCI_BCNF_IO_SHIFT) | 1080 PCI_BCNF_IO_LIMIT_BITS; 1081 val = pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW); 1082 base = ((val & PCI_BCNF_IO_MASK) << PCI_BCNF_IO_SHIFT); 1083 1084 if ((val & PCI_BCNF_ADDR_MASK) == PCI_BCNF_IO_32BIT) { 1085 val = pci_getw(bus, dev, func, PCI_BCNF_IO_BASE_HI); 1086 base |= val << 16; 1087 val = pci_getw(bus, dev, func, PCI_BCNF_IO_LIMIT_HI); 1088 limit |= val << 16; 1089 } 1090 VERIFY0(base >> 32); 1091 break; 1092 1093 case RES_MEM: 1094 val = pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT); 1095 limit = ((val & PCI_BCNF_MEM_MASK) << PCI_BCNF_MEM_SHIFT) | 1096 PCI_BCNF_MEM_LIMIT_BITS; 1097 val = pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE); 1098 base = ((val & PCI_BCNF_MEM_MASK) << PCI_BCNF_MEM_SHIFT); 1099 VERIFY0(base >> 32); 1100 break; 1101 1102 case RES_PMEM: 1103 val = pci_getw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW); 1104 limit = ((val & PCI_BCNF_MEM_MASK) << PCI_BCNF_MEM_SHIFT) | 1105 PCI_BCNF_MEM_LIMIT_BITS; 1106 val = pci_getw(bus, dev, func, PCI_BCNF_PF_BASE_LOW); 1107 base = ((val & PCI_BCNF_MEM_MASK) << PCI_BCNF_MEM_SHIFT); 1108 1109 if ((val & PCI_BCNF_ADDR_MASK) == PCI_BCNF_PF_MEM_64BIT) { 1110 val = pci_getl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH); 1111 base |= val << 32; 1112 val = pci_getl(bus, dev, func, PCI_BCNF_PF_LIMIT_HIGH); 1113 limit |= val << 32; 1114 } 1115 break; 1116 default: 1117 panic("Invalid resource type %d", type); 1118 } 1119 1120 *basep = base; 1121 *limitp = limit; 1122 } 1123 1124 /* 1125 * Assign valid resources to unconfigured pci(e) bridges. We are trying 1126 * to reprogram the bridge when its 1127 * i) SECBUS == SUBBUS || 1128 * ii) IOBASE > IOLIM || 1129 * iii) MEMBASE > MEMLIM && PMEMBASE > PMEMLIM 1130 * This must be done after one full pass through the PCI tree to collect 1131 * all firmware-configured resources, so that we know what resources are 1132 * free and available to assign to the unconfigured PPBs. 1133 */ 1134 static void 1135 fix_ppb_res(uchar_t secbus, boolean_t prog_sub) 1136 { 1137 uchar_t bus, dev, func; 1138 uchar_t parbus, subbus; 1139 struct { 1140 uint64_t base; 1141 uint64_t limit; 1142 uint64_t size; 1143 uint64_t align; 1144 } io, mem, pmem; 1145 uint64_t addr = 0; 1146 int *regp = NULL; 1147 uint_t reglen, buscount; 1148 int rv, cap_ptr, physhi; 1149 dev_info_t *dip; 1150 uint16_t cmd_reg; 1151 struct memlist *scratch_list; 1152 boolean_t reprogram_io, reprogram_mem; 1153 1154 /* skip root (peer) PCI busses */ 1155 if (pci_bus_res[secbus].par_bus == (uchar_t)-1) 1156 return; 1157 1158 /* skip subtractive PPB when prog_sub is not TRUE */ 1159 if (pci_bus_res[secbus].subtractive && !prog_sub) 1160 return; 1161 1162 /* some entries may be empty due to discontiguous bus numbering */ 1163 dip = pci_bus_res[secbus].dip; 1164 if (dip == NULL) 1165 return; 1166 1167 rv = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 1168 "reg", ®p, ®len); 1169 if (rv != DDI_PROP_SUCCESS || reglen == 0) 1170 return; 1171 physhi = regp[0]; 1172 ddi_prop_free(regp); 1173 1174 func = (uchar_t)PCI_REG_FUNC_G(physhi); 1175 dev = (uchar_t)PCI_REG_DEV_G(physhi); 1176 bus = (uchar_t)PCI_REG_BUS_G(physhi); 1177 1178 dump_memlists("fix_ppb_res start bus", bus); 1179 dump_memlists("fix_ppb_res start secbus", secbus); 1180 1181 /* 1182 * If pcie bridge, check to see if link is enabled 1183 */ 1184 cap_ptr = get_pci_cap(bus, dev, func, PCI_CAP_ID_PCI_E); 1185 if (cap_ptr != -1) { 1186 uint16_t reg = pci_getw(bus, dev, func, 1187 (uint16_t)cap_ptr + PCIE_LINKCTL); 1188 if ((reg & PCIE_LINKCTL_LINK_DISABLE) != 0) { 1189 dcmn_err(CE_NOTE, MSGHDR "link is disabled", 1190 "ppb", bus, dev, func); 1191 return; 1192 } 1193 } 1194 1195 subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS); 1196 parbus = pci_bus_res[secbus].par_bus; 1197 ASSERT(parbus == bus); 1198 cmd_reg = pci_getw(bus, dev, func, PCI_CONF_COMM); 1199 1200 /* 1201 * If we have a Cardbus bridge, but no bus space 1202 */ 1203 if (pci_bus_res[secbus].num_cbb != 0 && 1204 pci_bus_res[secbus].bus_avail == NULL) { 1205 uchar_t range; 1206 1207 /* normally there are 2 buses under a cardbus bridge */ 1208 range = pci_bus_res[secbus].num_cbb * 2; 1209 1210 /* 1211 * Try to find and allocate a bus-range starting at subbus+1 1212 * from the parent of the PPB. 1213 */ 1214 for (; range != 0; range--) { 1215 if (memlist_find_with_startaddr( 1216 &pci_bus_res[parbus].bus_avail, 1217 subbus + 1, range, 1) != 0) { 1218 break; /* find bus range resource at parent */ 1219 } 1220 } 1221 if (range != 0) { 1222 memlist_insert(&pci_bus_res[secbus].bus_avail, 1223 subbus + 1, range); 1224 subbus = subbus + range; 1225 pci_bus_res[secbus].sub_bus = subbus; 1226 pci_putb(bus, dev, func, PCI_BCNF_SUBBUS, subbus); 1227 add_bus_range_prop(secbus); 1228 1229 cmn_err(CE_NOTE, 1230 MSGHDR "PROGRAM cardbus buses 0x%x ~ 0x%x", 1231 "cbb", bus, dev, func, secbus, subbus); 1232 } 1233 } 1234 1235 buscount = subbus - secbus + 1; 1236 1237 dcmn_err(CE_NOTE, MSGHDR 1238 "secbus 0x%x existing sizes I/O 0x%x, MEM 0x%lx, PMEM 0x%lx", 1239 "ppb", bus, dev, func, secbus, 1240 pci_bus_res[secbus].io_size, pci_bus_res[secbus].mem_size, 1241 pci_bus_res[secbus].pmem_size); 1242 1243 /* 1244 * If the bridge's I/O range needs to be reprogrammed, then the 1245 * bridge is going to be allocated the greater of: 1246 * - 512 bytes per downstream bus; 1247 * - the amount required by its current children. 1248 * rounded up to the next 4K. 1249 */ 1250 io.size = MAX(pci_bus_res[secbus].io_size, buscount * 0x200); 1251 1252 /* 1253 * Similarly if the memory ranges need to be reprogrammed, then we'd 1254 * like to assign some extra memory to the bridge in case there is 1255 * anything hotplugged underneath later. 1256 * 1257 * We use the information gathered earlier relating to the number of 1258 * bridges that must share the resource of this bus' root port, and how 1259 * much memory is available that isn't already accounted for to 1260 * determine how much to use. 1261 * 1262 * At least the existing `mem_size` must be allocated as that has been 1263 * gleaned from enumeration. 1264 */ 1265 uint64_t avail = get_per_bridge_avail(bus); 1266 1267 if (avail > 0) { 1268 /* Try 32MiB first, then adjust down until it fits */ 1269 for (uint_t i = 32; i > 0; i >>= 1) { 1270 if (avail >= buscount * PPB_MEM_ALIGNMENT * i) { 1271 mem.size = buscount * PPB_MEM_ALIGNMENT * i; 1272 dcmn_err(CE_NOTE, MSGHDR 1273 "Allocating %uMiB", 1274 "ppb", bus, dev, func, i); 1275 break; 1276 } 1277 } 1278 } 1279 mem.size = MAX(pci_bus_res[secbus].mem_size, mem.size); 1280 1281 /* 1282 * For the PF memory range, illumos has not historically handed out 1283 * any additional memory to bridges. However there are some 1284 * hotpluggable devices which need 64-bit PF space and so we now always 1285 * attempt to allocate at least 32 MiB. If there is enough space 1286 * available from a parent then we will increase this to 512MiB. 1287 * If we're later unable to find memory to satisfy this, we just move 1288 * on and are no worse off than before. 1289 */ 1290 pmem.size = MAX(pci_bus_res[secbus].pmem_size, 1291 buscount * PPB_MEM_ALIGNMENT * 32); 1292 1293 /* 1294 * Check if the parent bus could allocate a 64-bit sized PF 1295 * range and bump the minimum pmem.size to 512MB if so. 1296 */ 1297 if (lookup_parbus_res(parbus, 1ULL << 32, PPB_MEM_ALIGNMENT, 1298 RES_PMEM) > 0) { 1299 pmem.size = MAX(pci_bus_res[secbus].pmem_size, 1300 buscount * PPB_MEM_ALIGNMENT * 512); 1301 } 1302 1303 /* 1304 * I/O space needs to be 4KiB aligned, Memory space needs to be 1MiB 1305 * aligned. 1306 * 1307 * We calculate alignment as the largest power of two less than the 1308 * the sum of all children's size requirements, because this will 1309 * align to the size of the largest child request within that size 1310 * (which is always a power of two). 1311 */ 1312 io.size = P2ROUNDUP(io.size, PPB_IO_ALIGNMENT); 1313 mem.size = P2ROUNDUP(mem.size, PPB_MEM_ALIGNMENT); 1314 pmem.size = P2ROUNDUP(pmem.size, PPB_MEM_ALIGNMENT); 1315 1316 io.align = io.size; 1317 P2LE(io.align); 1318 mem.align = mem.size; 1319 P2LE(mem.align); 1320 pmem.align = pmem.size; 1321 P2LE(pmem.align); 1322 1323 /* Subtractive bridge */ 1324 if (pci_bus_res[secbus].subtractive && prog_sub) { 1325 /* 1326 * We program an arbitrary amount of I/O and memory resource 1327 * for the subtractive bridge so that child dynamic-resource- 1328 * allocating devices (such as Cardbus bridges) have a chance 1329 * of success. Until we have full-tree resource rebalancing, 1330 * dynamic resource allocation (thru busra) only looks at the 1331 * parent bridge, so all PPBs must have some allocatable 1332 * resource. For non-subtractive bridges, the resources come 1333 * from the base/limit register "windows", but subtractive 1334 * bridges often don't program those (since they don't need to). 1335 * If we put all the remaining resources on the subtractive 1336 * bridge, then peer non-subtractive bridges can't allocate 1337 * more space (even though this is probably most correct). 1338 * If we put the resources only on the parent, then allocations 1339 * from children of subtractive bridges will fail without 1340 * special-case code for bypassing the subtractive bridge. 1341 * This solution is the middle-ground temporary solution until 1342 * we have fully-capable resource allocation. 1343 */ 1344 1345 /* 1346 * Add an arbitrary I/O resource to the subtractive PPB 1347 */ 1348 if (pci_bus_res[secbus].io_avail == NULL) { 1349 addr = get_parbus_res(parbus, secbus, io.size, 1350 io.align, RES_IO); 1351 if (addr != 0) { 1352 add_ranges_prop(secbus, B_TRUE); 1353 pci_bus_res[secbus].io_reprogram = 1354 pci_bus_res[parbus].io_reprogram; 1355 1356 cmn_err(CE_NOTE, 1357 MSGHDR "PROGRAM I/O range 0x%lx ~ 0x%lx " 1358 "(subtractive bridge)", 1359 "ppb", bus, dev, func, 1360 addr, addr + io.size - 1); 1361 } 1362 } 1363 /* 1364 * Add an arbitrary memory resource to the subtractive PPB 1365 */ 1366 if (pci_bus_res[secbus].mem_avail == NULL) { 1367 addr = get_parbus_res(parbus, secbus, mem.size, 1368 mem.align, RES_MEM); 1369 if (addr != 0) { 1370 add_ranges_prop(secbus, B_TRUE); 1371 pci_bus_res[secbus].mem_reprogram = 1372 pci_bus_res[parbus].mem_reprogram; 1373 1374 cmn_err(CE_NOTE, 1375 MSGHDR "PROGRAM MEM range 0x%lx ~ 0x%lx " 1376 "(subtractive bridge)", 1377 "ppb", bus, dev, func, 1378 addr, addr + mem.size - 1); 1379 } 1380 } 1381 1382 goto cmd_enable; 1383 } 1384 1385 /* 1386 * Retrieve the various configured ranges from the bridge. 1387 */ 1388 1389 fetch_ppb_res(bus, dev, func, RES_IO, &io.base, &io.limit); 1390 fetch_ppb_res(bus, dev, func, RES_MEM, &mem.base, &mem.limit); 1391 fetch_ppb_res(bus, dev, func, RES_PMEM, &pmem.base, &pmem.limit); 1392 1393 /* 1394 * Reprogram IO if: 1395 * 1396 * - The list does not consist entirely of legacy VGA resources; 1397 * 1398 * and any of 1399 * 1400 * - The parent bus is flagged for reprogramming; 1401 * - IO space is currently disabled in the command register; 1402 * - IO space is disabled via base/limit. 1403 */ 1404 scratch_list = memlist_dup(pci_bus_res[secbus].io_avail); 1405 memlist_merge(&pci_bus_res[secbus].io_used, &scratch_list); 1406 1407 reprogram_io = !list_is_vga_only(scratch_list, RES_IO) && 1408 (pci_bus_res[parbus].io_reprogram || 1409 (cmd_reg & PCI_COMM_IO) == 0 || 1410 io.base > io.limit); 1411 1412 memlist_free_all(&scratch_list); 1413 1414 if (reprogram_io) { 1415 if (pci_bus_res[secbus].io_used != NULL) { 1416 memlist_subsume(&pci_bus_res[secbus].io_used, 1417 &pci_bus_res[secbus].io_avail); 1418 } 1419 1420 if (pci_bus_res[secbus].io_avail != NULL && 1421 !pci_bus_res[parbus].io_reprogram && 1422 !pci_bus_res[parbus].subtractive) { 1423 /* re-choose old io ports info */ 1424 1425 uint64_t base, limit; 1426 1427 pci_memlist_range(pci_bus_res[secbus].io_avail, 1428 RES_IO, &base, &limit); 1429 io.base = (uint_t)base; 1430 io.limit = (uint_t)limit; 1431 1432 /* 4K aligned */ 1433 io.base = P2ALIGN(base, PPB_IO_ALIGNMENT); 1434 io.limit = P2ROUNDUP(io.limit, PPB_IO_ALIGNMENT) - 1; 1435 io.size = io.limit - io.base + 1; 1436 ASSERT3U(io.base, <=, io.limit); 1437 memlist_free_all(&pci_bus_res[secbus].io_avail); 1438 memlist_insert(&pci_bus_res[secbus].io_avail, 1439 io.base, io.size); 1440 memlist_insert(&pci_bus_res[parbus].io_used, 1441 io.base, io.size); 1442 (void) memlist_remove(&pci_bus_res[parbus].io_avail, 1443 io.base, io.size); 1444 pci_bus_res[secbus].io_reprogram = B_TRUE; 1445 } else { 1446 /* get new io ports from parent bus */ 1447 addr = get_parbus_res(parbus, secbus, io.size, 1448 io.align, RES_IO); 1449 if (addr != 0) { 1450 io.base = addr; 1451 io.limit = addr + io.size - 1; 1452 pci_bus_res[secbus].io_reprogram = B_TRUE; 1453 } 1454 } 1455 1456 if (pci_bus_res[secbus].io_reprogram) { 1457 /* reprogram PPB regs */ 1458 set_ppb_res(bus, dev, func, RES_IO, io.base, io.limit); 1459 add_ranges_prop(secbus, B_TRUE); 1460 } 1461 } 1462 1463 /* 1464 * Reprogram memory if: 1465 * 1466 * - The list does not consist entirely of legacy VGA resources; 1467 * 1468 * and any of 1469 * 1470 * - The parent bus is flagged for reprogramming; 1471 * - Mem space is currently disabled in the command register; 1472 * - Both mem and pmem space are disabled via base/limit. 1473 * 1474 * Always reprogram both mem and pmem together since this leaves 1475 * resources in the 'avail' list for add_reg_props() to subsequently 1476 * find and assign. 1477 */ 1478 scratch_list = memlist_dup(pci_bus_res[secbus].mem_avail); 1479 memlist_merge(&pci_bus_res[secbus].mem_used, &scratch_list); 1480 1481 reprogram_mem = !list_is_vga_only(scratch_list, RES_MEM) && 1482 (pci_bus_res[parbus].mem_reprogram || 1483 (cmd_reg & PCI_COMM_MAE) == 0 || 1484 (mem.base > mem.limit && pmem.base > pmem.limit)); 1485 1486 memlist_free_all(&scratch_list); 1487 1488 if (reprogram_mem) { 1489 /* Mem range */ 1490 if (pci_bus_res[secbus].mem_used != NULL) { 1491 memlist_subsume(&pci_bus_res[secbus].mem_used, 1492 &pci_bus_res[secbus].mem_avail); 1493 } 1494 1495 /* 1496 * At this point, if the parent bus has not been 1497 * reprogrammed and there is memory in this bus' available 1498 * pool, then it can just be re-used. Otherwise a new range 1499 * is requested from the parent bus - note that 1500 * get_parbus_res() also takes care of constructing new 1501 * avail and used lists for the bus. 1502 * 1503 * For a subtractive parent bus, always request a fresh 1504 * memory range. 1505 */ 1506 if (pci_bus_res[secbus].mem_avail != NULL && 1507 !pci_bus_res[parbus].mem_reprogram && 1508 !pci_bus_res[parbus].subtractive) { 1509 /* re-choose old mem resource */ 1510 pci_memlist_range(pci_bus_res[secbus].mem_avail, 1511 RES_MEM, &mem.base, &mem.limit); 1512 1513 mem.base = P2ALIGN(mem.base, PPB_MEM_ALIGNMENT); 1514 mem.limit = P2ROUNDUP(mem.limit, PPB_MEM_ALIGNMENT) - 1; 1515 mem.size = mem.limit + 1 - mem.base; 1516 ASSERT3U(mem.base, <=, mem.limit); 1517 memlist_free_all(&pci_bus_res[secbus].mem_avail); 1518 memlist_insert(&pci_bus_res[secbus].mem_avail, 1519 mem.base, mem.size); 1520 memlist_insert(&pci_bus_res[parbus].mem_used, 1521 mem.base, mem.size); 1522 (void) memlist_remove(&pci_bus_res[parbus].mem_avail, 1523 mem.base, mem.size); 1524 pci_bus_res[secbus].mem_reprogram = B_TRUE; 1525 } else { 1526 /* get new mem resource from parent bus */ 1527 addr = get_parbus_res(parbus, secbus, mem.size, 1528 mem.align, RES_MEM); 1529 if (addr != 0) { 1530 mem.base = addr; 1531 mem.limit = addr + mem.size - 1; 1532 pci_bus_res[secbus].mem_reprogram = B_TRUE; 1533 } 1534 } 1535 1536 /* Prefetch mem */ 1537 if (pci_bus_res[secbus].pmem_used != NULL) { 1538 memlist_subsume(&pci_bus_res[secbus].pmem_used, 1539 &pci_bus_res[secbus].pmem_avail); 1540 } 1541 1542 /* Same logic as for non-prefetch memory, see above */ 1543 if (pci_bus_res[secbus].pmem_avail != NULL && 1544 !pci_bus_res[parbus].mem_reprogram && 1545 !pci_bus_res[parbus].subtractive) { 1546 /* re-choose old mem resource */ 1547 1548 pci_memlist_range(pci_bus_res[secbus].pmem_avail, 1549 RES_PMEM, &pmem.base, &pmem.limit); 1550 1551 pmem.base = P2ALIGN(pmem.base, PPB_MEM_ALIGNMENT); 1552 pmem.limit = P2ROUNDUP(pmem.limit, PPB_MEM_ALIGNMENT) 1553 - 1; 1554 pmem.size = pmem.limit + 1 - pmem.base; 1555 ASSERT3U(pmem.base, <=, pmem.limit); 1556 memlist_free_all(&pci_bus_res[secbus].pmem_avail); 1557 memlist_insert(&pci_bus_res[secbus].pmem_avail, 1558 pmem.base, pmem.size); 1559 memlist_insert(&pci_bus_res[parbus].pmem_used, 1560 pmem.base, pmem.size); 1561 (void) memlist_remove(&pci_bus_res[parbus].pmem_avail, 1562 pmem.base, pmem.size); 1563 pci_bus_res[secbus].mem_reprogram = B_TRUE; 1564 } else { 1565 /* get new mem resource from parent bus */ 1566 addr = get_parbus_res(parbus, secbus, pmem.size, 1567 pmem.align, RES_PMEM); 1568 if (addr != 0) { 1569 pmem.base = addr; 1570 pmem.limit = addr + pmem.size - 1; 1571 pci_bus_res[secbus].mem_reprogram = B_TRUE; 1572 } 1573 } 1574 1575 if (pci_bus_res[secbus].mem_reprogram) { 1576 set_ppb_res(bus, dev, func, 1577 RES_MEM, mem.base, mem.limit); 1578 set_ppb_res(bus, dev, func, 1579 RES_PMEM, pmem.base, pmem.limit); 1580 add_ranges_prop(secbus, B_TRUE); 1581 } 1582 } 1583 1584 cmd_enable: 1585 dump_memlists("fix_ppb_res end bus", bus); 1586 dump_memlists("fix_ppb_res end secbus", secbus); 1587 1588 if (pci_bus_res[secbus].io_avail != NULL) 1589 cmd_reg |= PCI_COMM_IO | PCI_COMM_ME; 1590 if (pci_bus_res[secbus].mem_avail != NULL || 1591 pci_bus_res[secbus].pmem_avail != NULL) { 1592 cmd_reg |= PCI_COMM_MAE | PCI_COMM_ME; 1593 } 1594 pci_putw(bus, dev, func, PCI_CONF_COMM, cmd_reg); 1595 } 1596 1597 void 1598 pci_reprogram(void) 1599 { 1600 int i, pci_reconfig = 1; 1601 char *onoff; 1602 int bus; 1603 1604 /* 1605 * Ask platform code for all of the root complexes it knows about in 1606 * case we have missed anything in the scan. This is to ensure that we 1607 * have them show up in the devinfo tree. This scan should find any 1608 * existing entries as well. After this, go through each bus and 1609 * ask the platform if it wants to change the name of the slot. 1610 */ 1611 pci_prd_root_complex_iter(pci_rc_scan_cb, NULL); 1612 for (bus = 0; bus <= pci_boot_maxbus; bus++) { 1613 pci_prd_slot_name(bus, pci_bus_res[bus].dip); 1614 } 1615 pci_unitaddr_cache_init(); 1616 1617 /* 1618 * Fix-up unit-address assignments if cache is available 1619 */ 1620 if (pci_unitaddr_cache_valid()) { 1621 int pci_regs[] = {0, 0, 0}; 1622 int new_addr; 1623 int index = 0; 1624 1625 for (bus = 0; bus <= pci_boot_maxbus; bus++) { 1626 /* skip non-root (peer) PCI busses */ 1627 if ((pci_bus_res[bus].par_bus != (uchar_t)-1) || 1628 (pci_bus_res[bus].dip == NULL)) 1629 continue; 1630 1631 new_addr = pci_bus_unitaddr(index); 1632 if (pci_bus_res[bus].root_addr != new_addr) { 1633 /* update reg property for node */ 1634 pci_regs[0] = pci_bus_res[bus].root_addr = 1635 new_addr; 1636 (void) ndi_prop_update_int_array( 1637 DDI_DEV_T_NONE, pci_bus_res[bus].dip, 1638 "reg", (int *)pci_regs, 3); 1639 } 1640 index++; 1641 } 1642 } else { 1643 /* perform legacy processing */ 1644 pci_unitaddr_cache_create(); 1645 } 1646 1647 /* 1648 * Do root-bus resource discovery 1649 */ 1650 for (bus = 0; bus <= pci_boot_maxbus; bus++) { 1651 /* skip non-root (peer) PCI busses */ 1652 if (pci_bus_res[bus].par_bus != (uchar_t)-1) 1653 continue; 1654 1655 /* 1656 * 1. find resources associated with this root bus 1657 */ 1658 populate_bus_res(bus); 1659 1660 /* 1661 * 2. Exclude <1M address range here in case below reserved 1662 * ranges for BIOS data area, ROM area etc are wrongly reported 1663 * in ACPI resource producer entries for PCI root bus. 1664 * 00000000 - 000003FF RAM 1665 * 00000400 - 000004FF BIOS data area 1666 * 00000500 - 0009FFFF RAM 1667 * 000A0000 - 000BFFFF VGA RAM 1668 * 000C0000 - 000FFFFF ROM area 1669 */ 1670 (void) memlist_remove(&pci_bus_res[bus].mem_avail, 0, 0x100000); 1671 (void) memlist_remove(&pci_bus_res[bus].pmem_avail, 1672 0, 0x100000); 1673 1674 /* 1675 * 3. Calculate the amount of "spare" 32-bit memory so that we 1676 * can use that later to determine how much additional memory 1677 * to allocate to bridges in order that they have a better 1678 * chance of supporting a device being hotplugged under them. 1679 * 1680 * This is a root bus and the previous CONFIG_INFO pass has 1681 * populated `mem_size` with the sum of all of the BAR sizes 1682 * for all devices underneath, possibly adjusted up to allow 1683 * for alignment when it is later allocated. This pass has also 1684 * recorded the number of child bridges found under this bus in 1685 * `num_bridge`. To calculate the memory which can be used for 1686 * additional bridge allocations we sum up the contents of the 1687 * `mem_avail` list and subtract `mem_size`. 1688 * 1689 * When programming child bridges later in fix_ppb_res(), the 1690 * bridge count and spare memory values cached against the 1691 * relevant root port are used to determine how much memory to 1692 * be allocated. 1693 */ 1694 if (pci_bus_res[bus].num_bridge > 0) { 1695 uint64_t mem = 0; 1696 1697 for (struct memlist *ml = pci_bus_res[bus].mem_avail; 1698 ml != NULL; ml = ml->ml_next) { 1699 if (ml->ml_address < UINT32_MAX) 1700 mem += ml->ml_size; 1701 } 1702 1703 if (mem > pci_bus_res[bus].mem_size) 1704 mem -= pci_bus_res[bus].mem_size; 1705 else 1706 mem = 0; 1707 1708 pci_bus_res[bus].mem_buffer = mem; 1709 1710 dcmn_err(CE_NOTE, 1711 "Bus 0x%02x, bridges 0x%x, buffer mem 0x%lx", 1712 bus, pci_bus_res[bus].num_bridge, mem); 1713 } 1714 1715 /* 1716 * 4. Remove used PCI and ISA resources from bus resource map 1717 */ 1718 1719 memlist_remove_list(&pci_bus_res[bus].io_avail, 1720 pci_bus_res[bus].io_used); 1721 memlist_remove_list(&pci_bus_res[bus].mem_avail, 1722 pci_bus_res[bus].mem_used); 1723 memlist_remove_list(&pci_bus_res[bus].pmem_avail, 1724 pci_bus_res[bus].pmem_used); 1725 memlist_remove_list(&pci_bus_res[bus].mem_avail, 1726 pci_bus_res[bus].pmem_used); 1727 memlist_remove_list(&pci_bus_res[bus].pmem_avail, 1728 pci_bus_res[bus].mem_used); 1729 1730 memlist_remove_list(&pci_bus_res[bus].io_avail, 1731 isa_res.io_used); 1732 memlist_remove_list(&pci_bus_res[bus].mem_avail, 1733 isa_res.mem_used); 1734 } 1735 1736 memlist_free_all(&isa_res.io_used); 1737 memlist_free_all(&isa_res.mem_used); 1738 1739 /* add bus-range property for root/peer bus nodes */ 1740 for (i = 0; i <= pci_boot_maxbus; i++) { 1741 /* create bus-range property on root/peer buses */ 1742 if (pci_bus_res[i].par_bus == (uchar_t)-1) 1743 add_bus_range_prop(i); 1744 1745 /* setup bus range resource on each bus */ 1746 setup_bus_res(i); 1747 } 1748 1749 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, ddi_root_node(), 1750 DDI_PROP_DONTPASS, "pci-reprog", &onoff) == DDI_SUCCESS) { 1751 if (strcmp(onoff, "off") == 0) { 1752 pci_reconfig = 0; 1753 cmn_err(CE_NOTE, "pci device reprogramming disabled"); 1754 } 1755 ddi_prop_free(onoff); 1756 } 1757 1758 remove_subtractive_res(); 1759 1760 /* reprogram the non-subtractive PPB */ 1761 if (pci_reconfig) 1762 for (i = 0; i <= pci_boot_maxbus; i++) 1763 fix_ppb_res(i, B_FALSE); 1764 1765 for (i = 0; i <= pci_boot_maxbus; i++) { 1766 /* configure devices not configured by firmware */ 1767 if (pci_reconfig) { 1768 /* 1769 * Reprogram the subtractive PPB. At this time, all its 1770 * siblings should have got their resources already. 1771 */ 1772 if (pci_bus_res[i].subtractive) 1773 fix_ppb_res(i, B_TRUE); 1774 enumerate_bus_devs(i, CONFIG_NEW); 1775 } 1776 } 1777 1778 /* All dev programmed, so we can create available prop */ 1779 for (i = 0; i <= pci_boot_maxbus; i++) 1780 add_bus_available_prop(i); 1781 } 1782 1783 /* 1784 * populate bus resources 1785 */ 1786 static void 1787 populate_bus_res(uchar_t bus) 1788 { 1789 pci_bus_res[bus].pmem_avail = pci_prd_find_resource(bus, 1790 PCI_PRD_R_PREFETCH); 1791 pci_bus_res[bus].mem_avail = pci_prd_find_resource(bus, PCI_PRD_R_MMIO); 1792 pci_bus_res[bus].io_avail = pci_prd_find_resource(bus, PCI_PRD_R_IO); 1793 pci_bus_res[bus].bus_avail = pci_prd_find_resource(bus, PCI_PRD_R_BUS); 1794 1795 dump_memlists("populate_bus_res", bus); 1796 1797 /* 1798 * attempt to initialize sub_bus from the largest range-end 1799 * in the bus_avail list 1800 */ 1801 if (pci_bus_res[bus].bus_avail != NULL) { 1802 struct memlist *entry; 1803 int current; 1804 1805 entry = pci_bus_res[bus].bus_avail; 1806 while (entry != NULL) { 1807 current = entry->ml_address + entry->ml_size - 1; 1808 if (current > pci_bus_res[bus].sub_bus) 1809 pci_bus_res[bus].sub_bus = current; 1810 entry = entry->ml_next; 1811 } 1812 } 1813 1814 if (bus == 0) { 1815 /* 1816 * Special treatment of bus 0: 1817 * If no IO/MEM resource from ACPI/MPSPEC/HRT, copy 1818 * pcimem from boot and make I/O space the entire range 1819 * starting at 0x100. 1820 */ 1821 if (pci_bus_res[0].mem_avail == NULL) { 1822 pci_bus_res[0].mem_avail = 1823 memlist_dup(bootops->boot_mem->pcimem); 1824 } 1825 /* Exclude 0x00 to 0xff of the I/O space, used by all PCs */ 1826 if (pci_bus_res[0].io_avail == NULL) 1827 memlist_insert(&pci_bus_res[0].io_avail, 0x100, 0xffff); 1828 } 1829 1830 /* 1831 * Create 'ranges' property here before any resources are 1832 * removed from the resource lists 1833 */ 1834 add_ranges_prop(bus, B_FALSE); 1835 } 1836 1837 /* 1838 * Create top-level bus dips, i.e. /pci@0,0, /pci@1,0... 1839 */ 1840 static void 1841 create_root_bus_dip(uchar_t bus) 1842 { 1843 int pci_regs[] = {0, 0, 0}; 1844 dev_info_t *dip; 1845 1846 ASSERT(pci_bus_res[bus].par_bus == (uchar_t)-1); 1847 1848 num_root_bus++; 1849 ndi_devi_alloc_sleep(ddi_root_node(), "pci", 1850 (pnode_t)DEVI_SID_NODEID, &dip); 1851 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1852 "#address-cells", 3); 1853 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1854 "#size-cells", 2); 1855 pci_regs[0] = pci_bus_res[bus].root_addr; 1856 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1857 "reg", (int *)pci_regs, 3); 1858 1859 /* 1860 * If system has PCIe bus, then create different properties 1861 */ 1862 if (create_pcie_root_bus(bus, dip) == B_FALSE) 1863 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1864 "device_type", "pci"); 1865 1866 (void) ndi_devi_bind_driver(dip, 0); 1867 pci_bus_res[bus].dip = dip; 1868 } 1869 1870 /* 1871 * For any fixed configuration (often compatability) pci devices 1872 * and those with their own expansion rom, create device nodes 1873 * to hold the already configured device details. 1874 */ 1875 void 1876 enumerate_bus_devs(uchar_t bus, int config_op) 1877 { 1878 uchar_t dev, func, nfunc, header; 1879 ushort_t venid; 1880 struct pci_devfunc *devlist = NULL, *entry; 1881 1882 if (bus_debug(bus)) { 1883 if (config_op == CONFIG_NEW) { 1884 dcmn_err(CE_NOTE, "configuring pci bus 0x%x", bus); 1885 } else if (config_op == CONFIG_FIX) { 1886 dcmn_err(CE_NOTE, 1887 "fixing devices on pci bus 0x%x", bus); 1888 } else { 1889 dcmn_err(CE_NOTE, "enumerating pci bus 0x%x", bus); 1890 } 1891 } 1892 1893 if (config_op == CONFIG_NEW) { 1894 devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata; 1895 while (devlist) { 1896 entry = devlist; 1897 devlist = entry->next; 1898 if (entry->reprogram || 1899 pci_bus_res[bus].io_reprogram || 1900 pci_bus_res[bus].mem_reprogram) { 1901 /* reprogram device(s) */ 1902 (void) add_reg_props(entry->dip, bus, 1903 entry->dev, entry->func, CONFIG_NEW, 0); 1904 } 1905 kmem_free(entry, sizeof (*entry)); 1906 } 1907 pci_bus_res[bus].privdata = NULL; 1908 return; 1909 } 1910 1911 for (dev = 0; dev < max_dev_pci; dev++) { 1912 nfunc = 1; 1913 for (func = 0; func < nfunc; func++) { 1914 1915 venid = pci_getw(bus, dev, func, PCI_CONF_VENID); 1916 1917 if ((venid == 0xffff) || (venid == 0)) { 1918 /* no function at this address */ 1919 continue; 1920 } 1921 1922 header = pci_getb(bus, dev, func, PCI_CONF_HEADER); 1923 if (header == 0xff) { 1924 continue; /* illegal value */ 1925 } 1926 1927 /* 1928 * according to some mail from Microsoft posted 1929 * to the pci-drivers alias, their only requirement 1930 * for a multifunction device is for the 1st 1931 * function to have to PCI_HEADER_MULTI bit set. 1932 */ 1933 if ((func == 0) && (header & PCI_HEADER_MULTI)) { 1934 nfunc = 8; 1935 } 1936 1937 if (config_op == CONFIG_FIX || 1938 config_op == CONFIG_INFO) { 1939 /* 1940 * Create the node, unconditionally, on the 1941 * first pass only. It may still need 1942 * resource assignment, which will be 1943 * done on the second, CONFIG_NEW, pass. 1944 */ 1945 process_devfunc(bus, dev, func, header, 1946 venid, config_op); 1947 1948 } 1949 } 1950 } 1951 1952 /* percolate bus used resources up through parents to root */ 1953 if (config_op == CONFIG_INFO) { 1954 int par_bus; 1955 1956 par_bus = pci_bus_res[bus].par_bus; 1957 while (par_bus != (uchar_t)-1) { 1958 pci_bus_res[par_bus].io_size += 1959 pci_bus_res[bus].io_size; 1960 pci_bus_res[par_bus].mem_size += 1961 pci_bus_res[bus].mem_size; 1962 pci_bus_res[par_bus].pmem_size += 1963 pci_bus_res[bus].pmem_size; 1964 1965 if (pci_bus_res[bus].io_used != NULL) { 1966 memlist_merge(&pci_bus_res[bus].io_used, 1967 &pci_bus_res[par_bus].io_used); 1968 } 1969 1970 if (pci_bus_res[bus].mem_used != NULL) { 1971 memlist_merge(&pci_bus_res[bus].mem_used, 1972 &pci_bus_res[par_bus].mem_used); 1973 } 1974 1975 if (pci_bus_res[bus].pmem_used != NULL) { 1976 memlist_merge(&pci_bus_res[bus].pmem_used, 1977 &pci_bus_res[par_bus].pmem_used); 1978 } 1979 1980 pci_bus_res[par_bus].num_bridge += 1981 pci_bus_res[bus].num_bridge; 1982 1983 bus = par_bus; 1984 par_bus = pci_bus_res[par_bus].par_bus; 1985 } 1986 } 1987 } 1988 1989 /* 1990 * As a workaround for devices which is_pciide() (below, which see) would not 1991 * match due to device issues, check an undocumented device tree property 1992 * 'pci-ide', the value of which is a 1275 device identifier. 1993 * 1994 * Should a device matching this (in normal 'compatible' order) be found, and 1995 * the device not otherwise bound, it will be have its node name changed to 1996 * 'pci-ide' so the pci-ide driver will attach. 1997 * 1998 * This can be set via `eeprom pci-ide=pciXXXX,YYYY` (see eeprom(8)) or 1999 * otherwise added to bootenv.rc. 2000 */ 2001 static boolean_t 2002 check_pciide_prop(uchar_t revid, ushort_t venid, ushort_t devid, 2003 ushort_t subvenid, ushort_t subdevid) 2004 { 2005 static int prop_exist = -1; 2006 static char *pciide_str; 2007 char compat[32]; 2008 2009 if (prop_exist == -1) { 2010 prop_exist = (ddi_prop_lookup_string(DDI_DEV_T_ANY, 2011 ddi_root_node(), DDI_PROP_DONTPASS, "pci-ide", 2012 &pciide_str) == DDI_SUCCESS); 2013 } 2014 2015 if (!prop_exist) 2016 return (B_FALSE); 2017 2018 /* compare property value against various forms of compatible */ 2019 if (subvenid) { 2020 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x.%x", 2021 venid, devid, subvenid, subdevid, revid); 2022 if (strcmp(pciide_str, compat) == 0) 2023 return (B_TRUE); 2024 2025 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x", 2026 venid, devid, subvenid, subdevid); 2027 if (strcmp(pciide_str, compat) == 0) 2028 return (B_TRUE); 2029 2030 (void) snprintf(compat, sizeof (compat), "pci%x,%x", 2031 subvenid, subdevid); 2032 if (strcmp(pciide_str, compat) == 0) 2033 return (B_TRUE); 2034 } 2035 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x", 2036 venid, devid, revid); 2037 if (strcmp(pciide_str, compat) == 0) 2038 return (B_TRUE); 2039 2040 (void) snprintf(compat, sizeof (compat), "pci%x,%x", venid, devid); 2041 if (strcmp(pciide_str, compat) == 0) 2042 return (B_TRUE); 2043 2044 return (B_FALSE); 2045 } 2046 2047 static boolean_t 2048 is_pciide(uchar_t basecl, uchar_t subcl, uchar_t revid, 2049 ushort_t venid, ushort_t devid, ushort_t subvenid, ushort_t subdevid) 2050 { 2051 struct ide_table { 2052 ushort_t venid; 2053 ushort_t devid; 2054 } *entry; 2055 2056 /* 2057 * Devices which need to be matched specially as pci-ide because of 2058 * various device issues. Commonly their specification as being 2059 * PCI_MASS_OTHER or PCI_MASS_SATA despite our using them in ATA mode. 2060 */ 2061 static struct ide_table ide_other[] = { 2062 {0x1095, 0x3112}, /* Silicon Image 3112 SATALink/SATARaid */ 2063 {0x1095, 0x3114}, /* Silicon Image 3114 SATALink/SATARaid */ 2064 {0x1095, 0x3512}, /* Silicon Image 3512 SATALink/SATARaid */ 2065 {0x1095, 0x680}, /* Silicon Image PCI0680 Ultra ATA-133 */ 2066 {0x1283, 0x8211}, /* Integrated Technology Express 8211F */ 2067 {0, 0} 2068 }; 2069 2070 if (basecl != PCI_CLASS_MASS) 2071 return (B_FALSE); 2072 2073 if (subcl == PCI_MASS_IDE) { 2074 return (B_TRUE); 2075 } 2076 2077 if (check_pciide_prop(revid, venid, devid, subvenid, subdevid)) 2078 return (B_TRUE); 2079 2080 if (subcl != PCI_MASS_OTHER && subcl != PCI_MASS_SATA) { 2081 return (B_FALSE); 2082 } 2083 2084 entry = &ide_other[0]; 2085 while (entry->venid != 0) { 2086 if (entry->venid == venid && entry->devid == devid) 2087 return (B_TRUE); 2088 entry++; 2089 } 2090 return (B_FALSE); 2091 } 2092 2093 static int 2094 is_display(uint_t classcode) 2095 { 2096 static uint_t disp_classes[] = { 2097 0x000100, /* pre-class code VGA Compatible */ 2098 0x030000, /* VGA Compatible */ 2099 0x030001 /* VGA+8514 Compatible */ 2100 }; 2101 int i, nclasses = sizeof (disp_classes) / sizeof (uint_t); 2102 2103 for (i = 0; i < nclasses; i++) { 2104 if (classcode == disp_classes[i]) 2105 return (1); 2106 } 2107 return (0); 2108 } 2109 2110 static void 2111 add_undofix_entry(uint8_t bus, uint8_t dev, uint8_t fn, 2112 void (*undofn)(uint8_t, uint8_t, uint8_t)) 2113 { 2114 struct pci_fixundo *newundo; 2115 2116 newundo = kmem_alloc(sizeof (struct pci_fixundo), KM_SLEEP); 2117 2118 /* 2119 * Adding an item to this list means that we must turn its NMIENABLE 2120 * bit back on at a later time. 2121 */ 2122 newundo->bus = bus; 2123 newundo->dev = dev; 2124 newundo->fn = fn; 2125 newundo->undofn = undofn; 2126 newundo->next = undolist; 2127 2128 /* add to the undo list in LIFO order */ 2129 undolist = newundo; 2130 } 2131 2132 void 2133 add_pci_fixes(void) 2134 { 2135 int i; 2136 2137 for (i = 0; i <= pci_boot_maxbus; i++) { 2138 /* 2139 * For each bus, apply needed fixes to the appropriate devices. 2140 * This must be done before the main enumeration loop because 2141 * some fixes must be applied to devices normally encountered 2142 * later in the pci scan (e.g. if a fix to device 7 must be 2143 * applied before scanning device 6, applying fixes in the 2144 * normal enumeration loop would obviously be too late). 2145 */ 2146 enumerate_bus_devs(i, CONFIG_FIX); 2147 } 2148 } 2149 2150 void 2151 undo_pci_fixes(void) 2152 { 2153 struct pci_fixundo *nextundo; 2154 uint8_t bus, dev, fn; 2155 2156 /* 2157 * All fixes in the undo list are performed unconditionally. Future 2158 * fixes may require selective undo. 2159 */ 2160 while (undolist != NULL) { 2161 2162 bus = undolist->bus; 2163 dev = undolist->dev; 2164 fn = undolist->fn; 2165 2166 (*(undolist->undofn))(bus, dev, fn); 2167 2168 nextundo = undolist->next; 2169 kmem_free(undolist, sizeof (struct pci_fixundo)); 2170 undolist = nextundo; 2171 } 2172 } 2173 2174 static void 2175 undo_amd8111_pci_fix(uint8_t bus, uint8_t dev, uint8_t fn) 2176 { 2177 uint8_t val8; 2178 2179 val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1); 2180 /* 2181 * The NMIONERR bit is turned back on to allow the SMM BIOS 2182 * to handle more critical PCI errors (e.g. PERR#). 2183 */ 2184 val8 |= AMD8111_ENABLENMI; 2185 pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8); 2186 } 2187 2188 static void 2189 pci_fix_amd8111(uint8_t bus, uint8_t dev, uint8_t fn) 2190 { 2191 uint8_t val8; 2192 2193 val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1); 2194 2195 if ((val8 & AMD8111_ENABLENMI) == 0) 2196 return; 2197 2198 /* 2199 * We reset NMIONERR in the LPC because master-abort on the PCI 2200 * bridge side of the 8111 will cause NMI, which might cause SMI, 2201 * which sometimes prevents all devices from being enumerated. 2202 */ 2203 val8 &= ~AMD8111_ENABLENMI; 2204 2205 pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8); 2206 2207 add_undofix_entry(bus, dev, fn, undo_amd8111_pci_fix); 2208 } 2209 2210 static void 2211 set_devpm_d0(uchar_t bus, uchar_t dev, uchar_t func) 2212 { 2213 uint16_t status; 2214 uint8_t header; 2215 uint8_t cap_ptr; 2216 uint8_t cap_id; 2217 uint16_t pmcsr; 2218 2219 status = pci_getw(bus, dev, func, PCI_CONF_STAT); 2220 if (!(status & PCI_STAT_CAP)) 2221 return; /* No capabilities list */ 2222 2223 header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M; 2224 if (header == PCI_HEADER_CARDBUS) 2225 cap_ptr = pci_getb(bus, dev, func, PCI_CBUS_CAP_PTR); 2226 else 2227 cap_ptr = pci_getb(bus, dev, func, PCI_CONF_CAP_PTR); 2228 /* 2229 * Walk the capabilities list searching for a PM entry. 2230 */ 2231 while (cap_ptr != PCI_CAP_NEXT_PTR_NULL && cap_ptr >= PCI_CAP_PTR_OFF) { 2232 cap_ptr &= PCI_CAP_PTR_MASK; 2233 cap_id = pci_getb(bus, dev, func, cap_ptr + PCI_CAP_ID); 2234 if (cap_id == PCI_CAP_ID_PM) { 2235 pmcsr = pci_getw(bus, dev, func, cap_ptr + PCI_PMCSR); 2236 pmcsr &= ~(PCI_PMCSR_STATE_MASK); 2237 pmcsr |= PCI_PMCSR_D0; /* D0 state */ 2238 pci_putw(bus, dev, func, cap_ptr + PCI_PMCSR, pmcsr); 2239 break; 2240 } 2241 cap_ptr = pci_getb(bus, dev, func, cap_ptr + PCI_CAP_NEXT_PTR); 2242 } 2243 2244 } 2245 2246 #define is_isa(bc, sc) \ 2247 (((bc) == PCI_CLASS_BRIDGE) && ((sc) == PCI_BRIDGE_ISA)) 2248 2249 static void 2250 process_devfunc(uchar_t bus, uchar_t dev, uchar_t func, uchar_t header, 2251 ushort_t vendorid, int config_op) 2252 { 2253 char nodename[32], unitaddr[5]; 2254 dev_info_t *dip; 2255 uchar_t basecl, subcl, progcl, intr, revid; 2256 ushort_t subvenid, subdevid, status; 2257 ushort_t slot_num; 2258 uint_t classcode, revclass; 2259 boolean_t reprogram = B_FALSE; 2260 boolean_t pciide = B_FALSE; 2261 int power[2] = {1, 1}; 2262 int pciex = 0; 2263 ushort_t is_pci_bridge = 0; 2264 struct pci_devfunc *devlist = NULL, *entry = NULL; 2265 boolean_t slot_valid; 2266 gfx_entry_t *gfxp; 2267 pcie_req_id_t bdf; 2268 2269 ushort_t deviceid = pci_getw(bus, dev, func, PCI_CONF_DEVID); 2270 2271 switch (header & PCI_HEADER_TYPE_M) { 2272 case PCI_HEADER_ZERO: 2273 subvenid = pci_getw(bus, dev, func, PCI_CONF_SUBVENID); 2274 subdevid = pci_getw(bus, dev, func, PCI_CONF_SUBSYSID); 2275 break; 2276 case PCI_HEADER_CARDBUS: 2277 subvenid = pci_getw(bus, dev, func, PCI_CBUS_SUBVENID); 2278 subdevid = pci_getw(bus, dev, func, PCI_CBUS_SUBSYSID); 2279 /* Record the # of cardbus bridges found on the bus */ 2280 if (config_op == CONFIG_INFO) 2281 pci_bus_res[bus].num_cbb++; 2282 break; 2283 default: 2284 subvenid = 0; 2285 subdevid = 0; 2286 break; 2287 } 2288 2289 if (config_op == CONFIG_FIX) { 2290 if (vendorid == VENID_AMD && deviceid == DEVID_AMD8111_LPC) { 2291 pci_fix_amd8111(bus, dev, func); 2292 } 2293 return; 2294 } 2295 2296 /* XXX should be use generic names? derive from class? */ 2297 revclass = pci_getl(bus, dev, func, PCI_CONF_REVID); 2298 classcode = revclass >> 8; 2299 revid = revclass & 0xff; 2300 2301 /* figure out if this is pci-ide */ 2302 basecl = classcode >> 16; 2303 subcl = (classcode >> 8) & 0xff; 2304 progcl = classcode & 0xff; 2305 2306 2307 if (is_display(classcode)) 2308 (void) snprintf(nodename, sizeof (nodename), "display"); 2309 else if (!pseudo_isa && is_isa(basecl, subcl)) 2310 (void) snprintf(nodename, sizeof (nodename), "isa"); 2311 else if (subvenid != 0) 2312 (void) snprintf(nodename, sizeof (nodename), 2313 "pci%x,%x", subvenid, subdevid); 2314 else 2315 (void) snprintf(nodename, sizeof (nodename), 2316 "pci%x,%x", vendorid, deviceid); 2317 2318 /* make sure parent bus dip has been created */ 2319 if (pci_bus_res[bus].dip == NULL) 2320 create_root_bus_dip(bus); 2321 2322 ndi_devi_alloc_sleep(pci_bus_res[bus].dip, nodename, 2323 DEVI_SID_NODEID, &dip); 2324 2325 if (check_if_device_is_pciex(dip, bus, dev, func, &slot_valid, 2326 &slot_num, &is_pci_bridge) == B_TRUE) 2327 pciex = 1; 2328 2329 bdf = PCI_GETBDF(bus, dev, func); 2330 /* 2331 * Record BAD AMD bridges which don't support MMIO config access. 2332 */ 2333 if (IS_BAD_AMD_NTBRIDGE(vendorid, deviceid) || 2334 IS_AMD_8132_CHIP(vendorid, deviceid)) { 2335 uchar_t secbus = 0; 2336 uchar_t subbus = 0; 2337 2338 if ((basecl == PCI_CLASS_BRIDGE) && 2339 (subcl == PCI_BRIDGE_PCI)) { 2340 secbus = pci_getb(bus, dev, func, PCI_BCNF_SECBUS); 2341 subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS); 2342 } 2343 pci_cfgacc_add_workaround(bdf, secbus, subbus); 2344 } 2345 2346 /* 2347 * Only populate bus_t if this device is sitting under a PCIE root 2348 * complex. Some particular machines have both a PCIE root complex and 2349 * a PCI hostbridge, in which case only devices under the PCIE root 2350 * complex will have their bus_t populated. 2351 */ 2352 if (pcie_get_rc_dip(dip) != NULL) { 2353 ck804_fix_aer_ptr(dip, bdf); 2354 (void) pcie_init_bus(dip, bdf, PCIE_BUS_INITIAL); 2355 } 2356 2357 /* add properties */ 2358 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "device-id", deviceid); 2359 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "vendor-id", vendorid); 2360 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "revision-id", revid); 2361 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2362 "class-code", classcode); 2363 if (func == 0) 2364 (void) snprintf(unitaddr, sizeof (unitaddr), "%x", dev); 2365 else 2366 (void) snprintf(unitaddr, sizeof (unitaddr), 2367 "%x,%x", dev, func); 2368 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 2369 "unit-address", unitaddr); 2370 2371 /* add device_type for display nodes */ 2372 if (is_display(classcode)) { 2373 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 2374 "device_type", "display"); 2375 } 2376 /* add special stuff for header type */ 2377 if ((header & PCI_HEADER_TYPE_M) == PCI_HEADER_ZERO) { 2378 uchar_t mingrant = pci_getb(bus, dev, func, PCI_CONF_MIN_G); 2379 uchar_t maxlatency = pci_getb(bus, dev, func, PCI_CONF_MAX_L); 2380 2381 if (subvenid != 0) { 2382 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2383 "subsystem-id", subdevid); 2384 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2385 "subsystem-vendor-id", subvenid); 2386 } 2387 if (!pciex) 2388 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2389 "min-grant", mingrant); 2390 if (!pciex) 2391 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2392 "max-latency", maxlatency); 2393 } 2394 2395 /* interrupt, record if not 0 */ 2396 intr = pci_getb(bus, dev, func, PCI_CONF_IPIN); 2397 if (intr != 0) 2398 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2399 "interrupts", intr); 2400 2401 /* 2402 * Add support for 133 mhz pci eventually 2403 */ 2404 status = pci_getw(bus, dev, func, PCI_CONF_STAT); 2405 2406 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2407 "devsel-speed", (status & PCI_STAT_DEVSELT) >> 9); 2408 if (!pciex && (status & PCI_STAT_FBBC)) 2409 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 2410 "fast-back-to-back"); 2411 if (!pciex && (status & PCI_STAT_66MHZ)) 2412 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 2413 "66mhz-capable"); 2414 if (status & PCI_STAT_UDF) 2415 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 2416 "udf-supported"); 2417 if (pciex && slot_valid) { 2418 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2419 "physical-slot#", slot_num); 2420 if (!is_pci_bridge) 2421 pciex_slot_names_prop(dip, slot_num); 2422 } 2423 2424 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 2425 "power-consumption", power, 2); 2426 2427 /* Set the device PM state to D0 */ 2428 set_devpm_d0(bus, dev, func); 2429 2430 if ((basecl == PCI_CLASS_BRIDGE) && (subcl == PCI_BRIDGE_PCI)) 2431 add_ppb_props(dip, bus, dev, func, pciex, is_pci_bridge); 2432 else { 2433 /* 2434 * Record the non-PPB devices on the bus for possible 2435 * reprogramming at 2nd bus enumeration. 2436 * Note: PPB reprogramming is done in fix_ppb_res() 2437 */ 2438 devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata; 2439 entry = kmem_zalloc(sizeof (*entry), KM_SLEEP); 2440 entry->dip = dip; 2441 entry->dev = dev; 2442 entry->func = func; 2443 entry->next = devlist; 2444 pci_bus_res[bus].privdata = entry; 2445 } 2446 2447 if (IS_CLASS_IOAPIC(basecl, subcl, progcl)) { 2448 create_ioapic_node(bus, dev, func, vendorid, deviceid); 2449 } 2450 2451 /* check for NVIDIA CK8-04/MCP55 based LPC bridge */ 2452 if (NVIDIA_IS_LPC_BRIDGE(vendorid, deviceid) && (dev == 1) && 2453 (func == 0)) { 2454 add_nvidia_isa_bridge_props(dip, bus, dev, func); 2455 /* each LPC bridge has an integrated IOAPIC */ 2456 apic_nvidia_io_max++; 2457 } 2458 2459 if (pciex && is_pci_bridge) 2460 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model", 2461 (char *)"PCIe-PCI bridge"); 2462 else 2463 add_model_prop(dip, classcode); 2464 2465 add_compatible(dip, subvenid, subdevid, vendorid, deviceid, 2466 revid, classcode, pciex); 2467 2468 /* 2469 * See if this device is a controller that advertises 2470 * itself to be a standard ATA task file controller, or one that 2471 * has been hard coded. 2472 * 2473 * If it is, check if any other higher precedence driver listed in 2474 * driver_aliases will claim the node by calling 2475 * ddi_compatible_driver_major. If so, clear pciide and do not 2476 * create a pci-ide node or any other special handling. 2477 * 2478 * If another driver does not bind, set the node name to pci-ide 2479 * and then let the special pci-ide handling for registers and 2480 * child pci-ide nodes proceed below. 2481 */ 2482 if (is_pciide(basecl, subcl, revid, vendorid, deviceid, 2483 subvenid, subdevid)) { 2484 if (ddi_compatible_driver_major(dip, NULL) == (major_t)-1) { 2485 (void) ndi_devi_set_nodename(dip, "pci-ide", 0); 2486 pciide = B_TRUE; 2487 } 2488 } 2489 2490 DEVI_SET_PCI(dip); 2491 reprogram = add_reg_props(dip, bus, dev, func, config_op, pciide); 2492 (void) ndi_devi_bind_driver(dip, 0); 2493 2494 /* special handling for pci-ide */ 2495 if (pciide) { 2496 dev_info_t *cdip; 2497 2498 /* 2499 * Create properties specified by P1275 Working Group 2500 * Proposal #414 Version 1 2501 */ 2502 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 2503 "device_type", "pci-ide"); 2504 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2505 "#address-cells", 1); 2506 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2507 "#size-cells", 0); 2508 2509 /* allocate two child nodes */ 2510 ndi_devi_alloc_sleep(dip, "ide", 2511 (pnode_t)DEVI_SID_NODEID, &cdip); 2512 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 2513 "reg", 0); 2514 (void) ndi_devi_bind_driver(cdip, 0); 2515 ndi_devi_alloc_sleep(dip, "ide", 2516 (pnode_t)DEVI_SID_NODEID, &cdip); 2517 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 2518 "reg", 1); 2519 (void) ndi_devi_bind_driver(cdip, 0); 2520 2521 reprogram = B_FALSE; /* don't reprogram pci-ide bridge */ 2522 } 2523 2524 if (is_display(classcode)) { 2525 gfxp = kmem_zalloc(sizeof (*gfxp), KM_SLEEP); 2526 gfxp->g_dip = dip; 2527 gfxp->g_prev = NULL; 2528 gfxp->g_next = gfx_devinfo_list; 2529 gfx_devinfo_list = gfxp; 2530 if (gfxp->g_next) 2531 gfxp->g_next->g_prev = gfxp; 2532 } 2533 2534 /* special handling for isa */ 2535 if (!pseudo_isa && is_isa(basecl, subcl)) { 2536 /* add device_type */ 2537 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 2538 "device_type", "isa"); 2539 } 2540 2541 if (reprogram && (entry != NULL)) 2542 entry->reprogram = B_TRUE; 2543 } 2544 2545 /* 2546 * Some vendors do not use unique subsystem IDs in their products, which 2547 * makes the use of form 2 compatible names (pciSSSS,ssss) inappropriate. 2548 * Allow for these compatible forms to be excluded on a per-device basis. 2549 */ 2550 static boolean_t 2551 subsys_compat_exclude(ushort_t venid, ushort_t devid, ushort_t subvenid, 2552 ushort_t subdevid, uchar_t revid, uint_t classcode) 2553 { 2554 /* Nvidia display adapters */ 2555 if ((venid == 0x10de) && (is_display(classcode))) 2556 return (B_TRUE); 2557 2558 /* 2559 * 8086,166 is the Ivy Bridge built-in graphics controller on some 2560 * models. Unfortunately 8086,2044 is the Skylake Server processor 2561 * memory channel device. The Ivy Bridge device uses the Skylake 2562 * ID as its sub-device ID. The GPU is not a memory controller DIMM 2563 * channel. 2564 */ 2565 if (venid == 0x8086 && devid == 0x166 && subvenid == 0x8086 && 2566 subdevid == 0x2044) { 2567 return (B_TRUE); 2568 } 2569 2570 return (B_FALSE); 2571 } 2572 2573 /* 2574 * Set the compatible property to a value compliant with rev 2.1 of the IEEE1275 2575 * PCI binding. This is also used for PCI express devices and we have our own 2576 * minor additions. 2577 * 2578 * pciVVVV,DDDD.SSSS.ssss.RR (0) 2579 * pciVVVV,DDDD.SSSS.ssss (1) 2580 * pciSSSS,ssss,s (2+) 2581 * pciSSSS,ssss (2) 2582 * pciVVVV,DDDD.RR (3) 2583 * pciVVVV,DDDD,p (4+) 2584 * pciVVVV,DDDD (4) 2585 * pciclass,CCSSPP (5) 2586 * pciclass,CCSS (6) 2587 * 2588 * The Subsystem (SSSS) forms are not inserted if subsystem-vendor-id is 0 or if 2589 * it is a case where we know that the IDs overlap. 2590 * 2591 * NOTE: For PCI-Express devices "pci" is replaced with "pciex" in 0-6 above and 2592 * property 2 is not created as per "1275 bindings for PCI Express 2593 * Interconnect". 2594 * 2595 * Unlike on SPARC, we generate both the "pciex" and "pci" versions of the 2596 * above. The problem with property 2 is that it has an ambiguity with 2597 * property 4. To make sure that drivers can specify either form of 2 or 4 2598 * without ambiguity we add a suffix. The 'p' suffix represents the primary ID, 2599 * meaning that it is guaranteed to be form 4. The 's' suffix means that it is 2600 * sub-vendor and sub-device form, meaning it is guaranteed to be form 2. 2601 * 2602 * Set with setprop and \x00 between each to generate the encoded string array 2603 * form. 2604 */ 2605 void 2606 add_compatible(dev_info_t *dip, ushort_t subvenid, ushort_t subdevid, 2607 ushort_t vendorid, ushort_t deviceid, uchar_t revid, uint_t classcode, 2608 int pciex) 2609 { 2610 int i = 0; 2611 int size = COMPAT_BUFSIZE; 2612 char *compat[15]; 2613 char *buf, *curr; 2614 2615 curr = buf = kmem_alloc(size, KM_SLEEP); 2616 2617 if (pciex) { 2618 if (subvenid) { 2619 compat[i++] = curr; /* form 0 */ 2620 (void) snprintf(curr, size, "pciex%x,%x.%x.%x.%x", 2621 vendorid, deviceid, subvenid, subdevid, revid); 2622 size -= strlen(curr) + 1; 2623 curr += strlen(curr) + 1; 2624 2625 compat[i++] = curr; /* form 1 */ 2626 (void) snprintf(curr, size, "pciex%x,%x.%x.%x", 2627 vendorid, deviceid, subvenid, subdevid); 2628 size -= strlen(curr) + 1; 2629 curr += strlen(curr) + 1; 2630 2631 } 2632 compat[i++] = curr; /* form 3 */ 2633 (void) snprintf(curr, size, "pciex%x,%x.%x", 2634 vendorid, deviceid, revid); 2635 size -= strlen(curr) + 1; 2636 curr += strlen(curr) + 1; 2637 2638 compat[i++] = curr; /* form 4 */ 2639 (void) snprintf(curr, size, "pciex%x,%x", vendorid, deviceid); 2640 size -= strlen(curr) + 1; 2641 curr += strlen(curr) + 1; 2642 2643 compat[i++] = curr; /* form 5 */ 2644 (void) snprintf(curr, size, "pciexclass,%06x", classcode); 2645 size -= strlen(curr) + 1; 2646 curr += strlen(curr) + 1; 2647 2648 compat[i++] = curr; /* form 6 */ 2649 (void) snprintf(curr, size, "pciexclass,%04x", 2650 (classcode >> 8)); 2651 size -= strlen(curr) + 1; 2652 curr += strlen(curr) + 1; 2653 } 2654 2655 if (subvenid) { 2656 compat[i++] = curr; /* form 0 */ 2657 (void) snprintf(curr, size, "pci%x,%x.%x.%x.%x", 2658 vendorid, deviceid, subvenid, subdevid, revid); 2659 size -= strlen(curr) + 1; 2660 curr += strlen(curr) + 1; 2661 2662 compat[i++] = curr; /* form 1 */ 2663 (void) snprintf(curr, size, "pci%x,%x.%x.%x", 2664 vendorid, deviceid, subvenid, subdevid); 2665 size -= strlen(curr) + 1; 2666 curr += strlen(curr) + 1; 2667 2668 if (subsys_compat_exclude(vendorid, deviceid, subvenid, 2669 subdevid, revid, classcode) == B_FALSE) { 2670 compat[i++] = curr; /* form 2+ */ 2671 (void) snprintf(curr, size, "pci%x,%x,s", subvenid, 2672 subdevid); 2673 size -= strlen(curr) + 1; 2674 curr += strlen(curr) + 1; 2675 2676 compat[i++] = curr; /* form 2 */ 2677 (void) snprintf(curr, size, "pci%x,%x", subvenid, 2678 subdevid); 2679 size -= strlen(curr) + 1; 2680 curr += strlen(curr) + 1; 2681 } 2682 } 2683 compat[i++] = curr; /* form 3 */ 2684 (void) snprintf(curr, size, "pci%x,%x.%x", vendorid, deviceid, revid); 2685 size -= strlen(curr) + 1; 2686 curr += strlen(curr) + 1; 2687 2688 compat[i++] = curr; /* form 4+ */ 2689 (void) snprintf(curr, size, "pci%x,%x,p", vendorid, deviceid); 2690 size -= strlen(curr) + 1; 2691 curr += strlen(curr) + 1; 2692 2693 compat[i++] = curr; /* form 4 */ 2694 (void) snprintf(curr, size, "pci%x,%x", vendorid, deviceid); 2695 size -= strlen(curr) + 1; 2696 curr += strlen(curr) + 1; 2697 2698 compat[i++] = curr; /* form 5 */ 2699 (void) snprintf(curr, size, "pciclass,%06x", classcode); 2700 size -= strlen(curr) + 1; 2701 curr += strlen(curr) + 1; 2702 2703 compat[i++] = curr; /* form 6 */ 2704 (void) snprintf(curr, size, "pciclass,%04x", (classcode >> 8)); 2705 size -= strlen(curr) + 1; 2706 curr += strlen(curr) + 1; 2707 2708 (void) ndi_prop_update_string_array(DDI_DEV_T_NONE, dip, 2709 "compatible", compat, i); 2710 kmem_free(buf, COMPAT_BUFSIZE); 2711 } 2712 2713 /* 2714 * Adjust the reg properties for a dual channel PCI-IDE device. 2715 * 2716 * NOTE: don't do anything that changes the order of the hard-decodes 2717 * and programmed BARs. The kernel driver depends on these values 2718 * being in this order regardless of whether they're for a 'native' 2719 * mode BAR or not. 2720 */ 2721 /* 2722 * config info for pci-ide devices 2723 */ 2724 static struct { 2725 uchar_t native_mask; /* 0 == 'compatibility' mode, 1 == native */ 2726 uchar_t bar_offset; /* offset for alt status register */ 2727 ushort_t addr; /* compatibility mode base address */ 2728 ushort_t length; /* number of ports for this BAR */ 2729 } pciide_bar[] = { 2730 { 0x01, 0, 0x1f0, 8 }, /* primary lower BAR */ 2731 { 0x01, 2, 0x3f6, 1 }, /* primary upper BAR */ 2732 { 0x04, 0, 0x170, 8 }, /* secondary lower BAR */ 2733 { 0x04, 2, 0x376, 1 } /* secondary upper BAR */ 2734 }; 2735 2736 static boolean_t 2737 pciide_adjust_bar(uchar_t progcl, uint_t bar, uint_t *basep, uint_t *lenp) 2738 { 2739 boolean_t hard_decode = B_FALSE; 2740 2741 /* 2742 * Adjust the base and len for the BARs of the PCI-IDE 2743 * device's primary and secondary controllers. The first 2744 * two BARs are for the primary controller and the next 2745 * two BARs are for the secondary controller. The fifth 2746 * and sixth bars are never adjusted. 2747 */ 2748 if (bar <= 3) { 2749 *lenp = pciide_bar[bar].length; 2750 2751 if (progcl & pciide_bar[bar].native_mask) { 2752 *basep += pciide_bar[bar].bar_offset; 2753 } else { 2754 *basep = pciide_bar[bar].addr; 2755 hard_decode = B_TRUE; 2756 } 2757 } 2758 2759 /* 2760 * if either base or len is zero make certain both are zero 2761 */ 2762 if (*basep == 0 || *lenp == 0) { 2763 *basep = 0; 2764 *lenp = 0; 2765 hard_decode = B_FALSE; 2766 } 2767 2768 return (hard_decode); 2769 } 2770 2771 /* 2772 * Where op is one of: 2773 * CONFIG_INFO - first pass, gather what is there. 2774 * CONFIG_UPDATE - second pass, adjust/allocate regions. 2775 * CONFIG_NEW - third pass, allocate regions. 2776 * 2777 * Returns: 2778 * -1 Skip this BAR 2779 * 0 Properties have been assigned 2780 * 1 Properties have been assigned, reprogramming required 2781 */ 2782 static int 2783 add_bar_reg_props(int op, uchar_t bus, uchar_t dev, uchar_t func, uint_t bar, 2784 ushort_t offset, pci_regspec_t *regs, pci_regspec_t *assigned, 2785 ushort_t *bar_sz, boolean_t pciide) 2786 { 2787 uint8_t baseclass, subclass, progclass; 2788 uint32_t base, devloc; 2789 uint16_t command = 0; 2790 int reprogram = 0; 2791 uint64_t value; 2792 2793 devloc = PCI_REG_MAKE_BDFR(bus, dev, func, 0); 2794 baseclass = pci_getb(bus, dev, func, PCI_CONF_BASCLASS); 2795 subclass = pci_getb(bus, dev, func, PCI_CONF_SUBCLASS); 2796 progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS); 2797 2798 /* 2799 * Determine the size of the BAR by writing 0xffffffff to the base 2800 * register and reading the value back before restoring the original. 2801 * 2802 * For non-bridges, disable I/O and Memory access while doing this to 2803 * avoid difficulty with USB emulation (see OHCI spec1.0a appendix B 2804 * "Host Controller Mapping"). Doing this for bridges would have the 2805 * side-effect of making the bridge transparent to secondary-bus 2806 * activity (see sections 4.1-4.3 of the PCI-PCI Bridge Spec V1.2). 2807 */ 2808 base = pci_getl(bus, dev, func, offset); 2809 2810 if (baseclass != PCI_CLASS_BRIDGE) { 2811 command = (uint_t)pci_getw(bus, dev, func, PCI_CONF_COMM); 2812 pci_putw(bus, dev, func, PCI_CONF_COMM, 2813 command & ~(PCI_COMM_MAE | PCI_COMM_IO)); 2814 } 2815 2816 pci_putl(bus, dev, func, offset, 0xffffffff); 2817 value = pci_getl(bus, dev, func, offset); 2818 pci_putl(bus, dev, func, offset, base); 2819 2820 if (baseclass != PCI_CLASS_BRIDGE) 2821 pci_putw(bus, dev, func, PCI_CONF_COMM, command); 2822 2823 /* I/O Space */ 2824 if ((pciide && bar < 4) || (base & PCI_BASE_SPACE_IO) != 0) { 2825 struct memlist **io_avail = &pci_bus_res[bus].io_avail; 2826 struct memlist **io_used = &pci_bus_res[bus].io_used; 2827 boolean_t hard_decode = B_FALSE; 2828 uint_t type, len; 2829 2830 *bar_sz = PCI_BAR_SZ_32; 2831 value &= PCI_BASE_IO_ADDR_M; 2832 len = BARMASKTOLEN(value); 2833 2834 /* XXX Adjust first 4 IDE registers */ 2835 if (pciide) { 2836 if (subclass != PCI_MASS_IDE) { 2837 progclass = (PCI_IDE_IF_NATIVE_PRI | 2838 PCI_IDE_IF_NATIVE_SEC); 2839 } 2840 hard_decode = pciide_adjust_bar(progclass, bar, 2841 &base, &len); 2842 } else if (value == 0) { 2843 /* skip base regs with size of 0 */ 2844 return (-1); 2845 } 2846 2847 regs->pci_phys_hi = PCI_ADDR_IO | devloc; 2848 if (hard_decode) { 2849 regs->pci_phys_hi |= PCI_RELOCAT_B; 2850 regs->pci_phys_low = base & PCI_BASE_IO_ADDR_M; 2851 } else { 2852 regs->pci_phys_hi |= offset; 2853 regs->pci_phys_low = 0; 2854 } 2855 assigned->pci_phys_hi = PCI_RELOCAT_B | regs->pci_phys_hi; 2856 regs->pci_size_low = assigned->pci_size_low = len; 2857 2858 /* 2859 * 'type' holds the non-address part of the base to be re-added 2860 * to any new address in the programming step below. 2861 */ 2862 type = base & ~PCI_BASE_IO_ADDR_M; 2863 base &= PCI_BASE_IO_ADDR_M; 2864 2865 /* 2866 * A device under a subtractive PPB can allocate resources from 2867 * its parent bus if there is no resource available on its own 2868 * bus. 2869 */ 2870 if (op == CONFIG_NEW && pci_bus_res[bus].subtractive && 2871 *io_avail == NULL) { 2872 uchar_t res_bus; 2873 2874 res_bus = resolve_alloc_bus(bus, RES_IO); 2875 io_avail = &pci_bus_res[res_bus].io_avail; 2876 } 2877 2878 if (op == CONFIG_INFO) { /* first pass */ 2879 /* take out of the resource map of the bus */ 2880 if (base != 0) { 2881 (void) memlist_remove(io_avail, base, len); 2882 memlist_insert(io_used, base, len); 2883 } else { 2884 reprogram = 1; 2885 } 2886 dcmn_err(CE_NOTE, 2887 MSGHDR "BAR%u I/O FWINIT 0x%x ~ 0x%x", 2888 "pci", bus, dev, func, bar, base, len); 2889 pci_bus_res[bus].io_size += len; 2890 } else if ((*io_avail != NULL && base == 0) || 2891 pci_bus_res[bus].io_reprogram) { 2892 base = memlist_find(io_avail, len, len); 2893 if (base == 0) { 2894 cmn_err(CE_WARN, MSGHDR "BAR%u I/O " 2895 "failed to find length 0x%x", 2896 "pci", bus, dev, func, bar, len); 2897 } else { 2898 uint32_t nbase; 2899 2900 cmn_err(CE_NOTE, "!" MSGHDR "BAR%u " 2901 "I/O REPROG 0x%x ~ 0x%x", 2902 "pci", bus, dev, func, 2903 bar, base, len); 2904 pci_putl(bus, dev, func, offset, base | type); 2905 nbase = pci_getl(bus, dev, func, offset); 2906 nbase &= PCI_BASE_IO_ADDR_M; 2907 2908 if (base != nbase) { 2909 cmn_err(CE_NOTE, "!" MSGHDR "BAR%u " 2910 "I/O REPROG 0x%x ~ 0x%x " 2911 "FAILED READBACK 0x%x", 2912 "pci", bus, dev, func, 2913 bar, base, len, nbase); 2914 pci_putl(bus, dev, func, offset, 0); 2915 if (baseclass != PCI_CLASS_BRIDGE) { 2916 /* Disable PCI_COMM_IO bit */ 2917 command = pci_getw(bus, dev, 2918 func, PCI_CONF_COMM); 2919 command &= ~PCI_COMM_IO; 2920 pci_putw(bus, dev, func, 2921 PCI_CONF_COMM, command); 2922 } 2923 memlist_insert(io_avail, base, len); 2924 base = 0; 2925 } else { 2926 memlist_insert(io_used, base, len); 2927 } 2928 } 2929 } 2930 assigned->pci_phys_low = base; 2931 2932 } else { /* Memory space */ 2933 struct memlist **mem_avail = &pci_bus_res[bus].mem_avail; 2934 struct memlist **mem_used = &pci_bus_res[bus].mem_used; 2935 struct memlist **pmem_avail = &pci_bus_res[bus].pmem_avail; 2936 struct memlist **pmem_used = &pci_bus_res[bus].pmem_used; 2937 uint_t type, base_hi, phys_hi; 2938 uint64_t len, fbase; 2939 2940 if ((base & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) { 2941 *bar_sz = PCI_BAR_SZ_64; 2942 base_hi = pci_getl(bus, dev, func, offset + 4); 2943 pci_putl(bus, dev, func, offset + 4, 2944 0xffffffff); 2945 value |= (uint64_t)pci_getl(bus, dev, func, 2946 offset + 4) << 32; 2947 pci_putl(bus, dev, func, offset + 4, base_hi); 2948 phys_hi = PCI_ADDR_MEM64; 2949 value &= PCI_BASE_M_ADDR64_M; 2950 } else { 2951 *bar_sz = PCI_BAR_SZ_32; 2952 base_hi = 0; 2953 phys_hi = PCI_ADDR_MEM32; 2954 value &= PCI_BASE_M_ADDR_M; 2955 } 2956 2957 /* skip base regs with size of 0 */ 2958 if (value == 0) 2959 return (-1); 2960 2961 len = BARMASKTOLEN(value); 2962 regs->pci_size_low = assigned->pci_size_low = len & 0xffffffff; 2963 regs->pci_size_hi = assigned->pci_size_hi = len >> 32; 2964 2965 phys_hi |= devloc | offset; 2966 if (base & PCI_BASE_PREF_M) 2967 phys_hi |= PCI_PREFETCH_B; 2968 2969 /* 2970 * A device under a subtractive PPB can allocate resources from 2971 * its parent bus if there is no resource available on its own 2972 * bus. 2973 */ 2974 if (op == CONFIG_NEW && pci_bus_res[bus].subtractive) { 2975 uchar_t res_bus = bus; 2976 2977 if ((phys_hi & PCI_PREFETCH_B) != 0 && 2978 *pmem_avail == NULL) { 2979 res_bus = resolve_alloc_bus(bus, RES_PMEM); 2980 pmem_avail = &pci_bus_res[res_bus].pmem_avail; 2981 mem_avail = &pci_bus_res[res_bus].mem_avail; 2982 } else if (*mem_avail == NULL) { 2983 res_bus = resolve_alloc_bus(bus, RES_MEM); 2984 pmem_avail = &pci_bus_res[res_bus].pmem_avail; 2985 mem_avail = &pci_bus_res[res_bus].mem_avail; 2986 } 2987 } 2988 2989 regs->pci_phys_hi = assigned->pci_phys_hi = phys_hi; 2990 assigned->pci_phys_hi |= PCI_RELOCAT_B; 2991 2992 /* 2993 * 'type' holds the non-address part of the base to be re-added 2994 * to any new address in the programming step below. 2995 */ 2996 type = base & ~PCI_BASE_M_ADDR_M; 2997 base &= PCI_BASE_M_ADDR_M; 2998 2999 fbase = (((uint64_t)base_hi) << 32) | base; 3000 3001 if (op == CONFIG_INFO) { 3002 3003 dcmn_err(CE_NOTE, 3004 MSGHDR "BAR%u %sMEM FWINIT 0x%lx ~ 0x%lx%s", 3005 "pci", bus, dev, func, bar, 3006 (phys_hi & PCI_PREFETCH_B) ? "P" : " ", 3007 fbase, len, 3008 *bar_sz == PCI_BAR_SZ_64 ? " (64-bit)" : ""); 3009 3010 /* take out of the resource map of the bus */ 3011 if (fbase != 0) { 3012 /* remove from PMEM and MEM space */ 3013 (void) memlist_remove(mem_avail, fbase, len); 3014 (void) memlist_remove(pmem_avail, fbase, len); 3015 /* only note as used in correct map */ 3016 if ((phys_hi & PCI_PREFETCH_B) != 0) 3017 memlist_insert(pmem_used, fbase, len); 3018 else 3019 memlist_insert(mem_used, fbase, len); 3020 } else { 3021 reprogram = 1; 3022 /* 3023 * If we need to reprogram this because we 3024 * don't have a BAR assigned, we need to 3025 * actually increase the amount of memory that 3026 * we request to take into account alignment. 3027 * This is a bit gross, but by doubling the 3028 * request size we are more likely to get the 3029 * size that we need. A more involved fix would 3030 * require a smarter and more involved 3031 * allocator (something we will need 3032 * eventually). 3033 */ 3034 len *= 2; 3035 } 3036 3037 if (phys_hi & PCI_PREFETCH_B) 3038 pci_bus_res[bus].pmem_size += len; 3039 else 3040 pci_bus_res[bus].mem_size += len; 3041 } else if (pci_bus_res[bus].mem_reprogram || (fbase == 0 && 3042 (*mem_avail != NULL || *pmem_avail != NULL))) { 3043 boolean_t pf = B_FALSE; 3044 fbase = 0; 3045 3046 /* 3047 * When desired, attempt a prefetchable allocation first 3048 */ 3049 if ((phys_hi & PCI_PREFETCH_B) != 0 && 3050 *pmem_avail != NULL) { 3051 fbase = memlist_find(pmem_avail, len, len); 3052 if (fbase != 0) 3053 pf = B_TRUE; 3054 } 3055 /* 3056 * If prefetchable allocation was not desired, or 3057 * failed, attempt ordinary memory allocation. 3058 */ 3059 if (fbase == 0 && *mem_avail != NULL) 3060 fbase = memlist_find(mem_avail, len, len); 3061 3062 base_hi = fbase >> 32; 3063 base = fbase & 0xffffffff; 3064 3065 if (fbase == 0) { 3066 cmn_err(CE_WARN, MSGHDR "BAR%u MEM " 3067 "failed to find length 0x%lx", 3068 "pci", bus, dev, func, bar, len); 3069 } else { 3070 uint64_t nbase, nbase_hi = 0; 3071 3072 cmn_err(CE_NOTE, "!" MSGHDR "BAR%u " 3073 "%s%s REPROG 0x%lx ~ 0x%lx", 3074 "pci", bus, dev, func, bar, 3075 pf ? "PMEM" : "MEM", 3076 *bar_sz == PCI_BAR_SZ_64 ? "64" : "", 3077 fbase, len); 3078 pci_putl(bus, dev, func, offset, base | type); 3079 nbase = pci_getl(bus, dev, func, offset); 3080 3081 if (*bar_sz == PCI_BAR_SZ_64) { 3082 pci_putl(bus, dev, func, 3083 offset + 4, base_hi); 3084 nbase_hi = pci_getl(bus, dev, func, 3085 offset + 4); 3086 } 3087 3088 nbase &= PCI_BASE_M_ADDR_M; 3089 3090 if (base != nbase || base_hi != nbase_hi) { 3091 cmn_err(CE_NOTE, "!" MSGHDR "BAR%u " 3092 "%s%s REPROG 0x%lx ~ 0x%lx " 3093 "FAILED READBACK 0x%lx", 3094 "pci", bus, dev, func, bar, 3095 pf ? "PMEM" : "MEM", 3096 *bar_sz == PCI_BAR_SZ_64 ? 3097 "64" : "", 3098 fbase, len, 3099 nbase_hi << 32 | nbase); 3100 3101 pci_putl(bus, dev, func, offset, 0); 3102 if (*bar_sz == PCI_BAR_SZ_64) { 3103 pci_putl(bus, dev, func, 3104 offset + 4, 0); 3105 } 3106 3107 if (baseclass != PCI_CLASS_BRIDGE) { 3108 /* Disable PCI_COMM_MAE bit */ 3109 command = pci_getw(bus, dev, 3110 func, PCI_CONF_COMM); 3111 command &= ~PCI_COMM_MAE; 3112 pci_putw(bus, dev, func, 3113 PCI_CONF_COMM, command); 3114 } 3115 3116 memlist_insert( 3117 pf ? pmem_avail : mem_avail, 3118 base, len); 3119 base = base_hi = 0; 3120 } else { 3121 if (pf) { 3122 memlist_insert(pmem_used, 3123 fbase, len); 3124 (void) memlist_remove( 3125 pmem_avail, fbase, len); 3126 } else { 3127 memlist_insert(mem_used, 3128 fbase, len); 3129 (void) memlist_remove( 3130 mem_avail, fbase, len); 3131 } 3132 } 3133 } 3134 } 3135 3136 assigned->pci_phys_mid = base_hi; 3137 assigned->pci_phys_low = base; 3138 } 3139 3140 dcmn_err(CE_NOTE, MSGHDR "BAR%u ---- %08x.%x.%x.%x.%x", 3141 "pci", bus, dev, func, bar, 3142 assigned->pci_phys_hi, 3143 assigned->pci_phys_mid, 3144 assigned->pci_phys_low, 3145 assigned->pci_size_hi, 3146 assigned->pci_size_low); 3147 3148 return (reprogram); 3149 } 3150 3151 /* 3152 * Add the "reg" and "assigned-addresses" property 3153 */ 3154 static boolean_t 3155 add_reg_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func, 3156 int op, boolean_t pciide) 3157 { 3158 uchar_t baseclass, subclass, progclass, header; 3159 uint_t bar, value, devloc, base; 3160 ushort_t bar_sz, offset, end; 3161 int max_basereg, reprogram = B_FALSE; 3162 3163 struct memlist **io_avail, **io_used; 3164 struct memlist **mem_avail, **mem_used; 3165 struct memlist **pmem_avail; 3166 3167 pci_regspec_t regs[16] = {{0}}; 3168 pci_regspec_t assigned[15] = {{0}}; 3169 int nreg, nasgn; 3170 3171 io_avail = &pci_bus_res[bus].io_avail; 3172 io_used = &pci_bus_res[bus].io_used; 3173 mem_avail = &pci_bus_res[bus].mem_avail; 3174 mem_used = &pci_bus_res[bus].mem_used; 3175 pmem_avail = &pci_bus_res[bus].pmem_avail; 3176 3177 dump_memlists("add_reg_props start", bus); 3178 3179 devloc = PCI_REG_MAKE_BDFR(bus, dev, func, 0); 3180 regs[0].pci_phys_hi = devloc; 3181 nreg = 1; /* rest of regs[0] is all zero */ 3182 nasgn = 0; 3183 3184 baseclass = pci_getb(bus, dev, func, PCI_CONF_BASCLASS); 3185 subclass = pci_getb(bus, dev, func, PCI_CONF_SUBCLASS); 3186 progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS); 3187 header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M; 3188 3189 switch (header) { 3190 case PCI_HEADER_ZERO: 3191 max_basereg = PCI_BASE_NUM; 3192 break; 3193 case PCI_HEADER_PPB: 3194 max_basereg = PCI_BCNF_BASE_NUM; 3195 break; 3196 case PCI_HEADER_CARDBUS: 3197 max_basereg = PCI_CBUS_BASE_NUM; 3198 reprogram = B_TRUE; 3199 break; 3200 default: 3201 max_basereg = 0; 3202 break; 3203 } 3204 3205 end = PCI_CONF_BASE0 + max_basereg * sizeof (uint_t); 3206 for (bar = 0, offset = PCI_CONF_BASE0; offset < end; 3207 bar++, offset += bar_sz) { 3208 int ret; 3209 3210 ret = add_bar_reg_props(op, bus, dev, func, bar, offset, 3211 ®s[nreg], &assigned[nasgn], &bar_sz, pciide); 3212 3213 if (bar_sz == PCI_BAR_SZ_64) 3214 bar++; 3215 3216 if (ret == -1) /* Skip BAR */ 3217 continue; 3218 3219 if (ret == 1) 3220 reprogram = B_TRUE; 3221 3222 nreg++; 3223 nasgn++; 3224 } 3225 3226 switch (header) { 3227 case PCI_HEADER_ZERO: 3228 offset = PCI_CONF_ROM; 3229 break; 3230 case PCI_HEADER_PPB: 3231 offset = PCI_BCNF_ROM; 3232 break; 3233 default: /* including PCI_HEADER_CARDBUS */ 3234 goto done; 3235 } 3236 3237 /* 3238 * Add the expansion rom memory space 3239 * Determine the size of the ROM base reg; don't write reserved bits 3240 * ROM isn't in the PCI memory space. 3241 */ 3242 base = pci_getl(bus, dev, func, offset); 3243 pci_putl(bus, dev, func, offset, PCI_BASE_ROM_ADDR_M); 3244 value = pci_getl(bus, dev, func, offset); 3245 pci_putl(bus, dev, func, offset, base); 3246 if (value & PCI_BASE_ROM_ENABLE) 3247 value &= PCI_BASE_ROM_ADDR_M; 3248 else 3249 value = 0; 3250 3251 if (value != 0) { 3252 uint_t len; 3253 3254 regs[nreg].pci_phys_hi = (PCI_ADDR_MEM32 | devloc) + offset; 3255 assigned[nasgn].pci_phys_hi = (PCI_RELOCAT_B | 3256 PCI_ADDR_MEM32 | devloc) + offset; 3257 base &= PCI_BASE_ROM_ADDR_M; 3258 assigned[nasgn].pci_phys_low = base; 3259 len = BARMASKTOLEN(value); 3260 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = len; 3261 nreg++, nasgn++; 3262 /* take it out of the memory resource */ 3263 if (base != 0) { 3264 (void) memlist_remove(mem_avail, base, len); 3265 memlist_insert(mem_used, base, len); 3266 pci_bus_res[bus].mem_size += len; 3267 } 3268 } 3269 3270 /* 3271 * Account for "legacy" (alias) video adapter resources 3272 */ 3273 3274 /* add the three hard-decode, aliased address spaces for VGA */ 3275 if ((baseclass == PCI_CLASS_DISPLAY && subclass == PCI_DISPLAY_VGA) || 3276 (baseclass == PCI_CLASS_NONE && subclass == PCI_NONE_VGA)) { 3277 3278 /* VGA hard decode 0x3b0-0x3bb */ 3279 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 3280 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 3281 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3b0; 3282 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0xc; 3283 nreg++, nasgn++; 3284 (void) memlist_remove(io_avail, 0x3b0, 0xc); 3285 memlist_insert(io_used, 0x3b0, 0xc); 3286 pci_bus_res[bus].io_size += 0xc; 3287 3288 /* VGA hard decode 0x3c0-0x3df */ 3289 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 3290 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 3291 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3c0; 3292 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x20; 3293 nreg++, nasgn++; 3294 (void) memlist_remove(io_avail, 0x3c0, 0x20); 3295 memlist_insert(io_used, 0x3c0, 0x20); 3296 pci_bus_res[bus].io_size += 0x20; 3297 3298 /* Video memory */ 3299 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 3300 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_MEM32 | devloc); 3301 regs[nreg].pci_phys_low = 3302 assigned[nasgn].pci_phys_low = 0xa0000; 3303 regs[nreg].pci_size_low = 3304 assigned[nasgn].pci_size_low = 0x20000; 3305 nreg++, nasgn++; 3306 /* remove from MEM and PMEM space */ 3307 (void) memlist_remove(mem_avail, 0xa0000, 0x20000); 3308 (void) memlist_remove(pmem_avail, 0xa0000, 0x20000); 3309 memlist_insert(mem_used, 0xa0000, 0x20000); 3310 pci_bus_res[bus].mem_size += 0x20000; 3311 } 3312 3313 /* add the hard-decode, aliased address spaces for 8514 */ 3314 if ((baseclass == PCI_CLASS_DISPLAY) && 3315 (subclass == PCI_DISPLAY_VGA) && 3316 (progclass & PCI_DISPLAY_IF_8514)) { 3317 3318 /* hard decode 0x2e8 */ 3319 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 3320 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 3321 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2e8; 3322 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x1; 3323 nreg++, nasgn++; 3324 (void) memlist_remove(io_avail, 0x2e8, 0x1); 3325 memlist_insert(io_used, 0x2e8, 0x1); 3326 pci_bus_res[bus].io_size += 0x1; 3327 3328 /* hard decode 0x2ea-0x2ef */ 3329 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 3330 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 3331 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2ea; 3332 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x6; 3333 nreg++, nasgn++; 3334 (void) memlist_remove(io_avail, 0x2ea, 0x6); 3335 memlist_insert(io_used, 0x2ea, 0x6); 3336 pci_bus_res[bus].io_size += 0x6; 3337 } 3338 3339 done: 3340 dump_memlists("add_reg_props end", bus); 3341 3342 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "reg", 3343 (int *)regs, nreg * sizeof (pci_regspec_t) / sizeof (int)); 3344 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 3345 "assigned-addresses", 3346 (int *)assigned, nasgn * sizeof (pci_regspec_t) / sizeof (int)); 3347 3348 return (reprogram); 3349 } 3350 3351 static void 3352 add_ppb_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func, 3353 int pciex, ushort_t is_pci_bridge) 3354 { 3355 char *dev_type; 3356 int i; 3357 uint_t cmd_reg; 3358 struct { 3359 uint64_t base; 3360 uint64_t limit; 3361 } io, mem, pmem; 3362 uchar_t secbus, subbus; 3363 uchar_t progclass; 3364 3365 secbus = pci_getb(bus, dev, func, PCI_BCNF_SECBUS); 3366 subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS); 3367 ASSERT3U(secbus, <=, subbus); 3368 3369 dump_memlists("add_ppb_props start bus", bus); 3370 dump_memlists("add_ppb_props start secbus", secbus); 3371 3372 /* 3373 * Check if it's a subtractive PPB. 3374 */ 3375 progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS); 3376 if (progclass == PCI_BRIDGE_PCI_IF_SUBDECODE) 3377 pci_bus_res[secbus].subtractive = B_TRUE; 3378 3379 /* 3380 * Some firmware lies about max pci busses, we allow for 3381 * such mistakes here 3382 */ 3383 if (subbus > pci_boot_maxbus) { 3384 pci_boot_maxbus = subbus; 3385 alloc_res_array(); 3386 } 3387 3388 ASSERT(pci_bus_res[secbus].dip == NULL); 3389 pci_bus_res[secbus].dip = dip; 3390 pci_bus_res[secbus].par_bus = bus; 3391 3392 dev_type = (pciex && !is_pci_bridge) ? "pciex" : "pci"; 3393 3394 /* set up bus number hierarchy */ 3395 pci_bus_res[secbus].sub_bus = subbus; 3396 /* 3397 * Keep track of the largest subordinate bus number (this is essential 3398 * for peer busses because there is no other way of determining its 3399 * subordinate bus number). 3400 */ 3401 if (subbus > pci_bus_res[bus].sub_bus) 3402 pci_bus_res[bus].sub_bus = subbus; 3403 /* 3404 * Loop through subordinate busses, initializing their parent bus 3405 * field to this bridge's parent. The subordinate busses' parent 3406 * fields may very well be further refined later, as child bridges 3407 * are enumerated. (The value is to note that the subordinate busses 3408 * are not peer busses by changing their par_bus fields to anything 3409 * other than -1.) 3410 */ 3411 for (i = secbus + 1; i <= subbus; i++) 3412 pci_bus_res[i].par_bus = bus; 3413 3414 /* 3415 * Update the number of bridges on the bus. 3416 */ 3417 if (is_pci_bridge == 0) 3418 pci_bus_res[bus].num_bridge++; 3419 3420 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 3421 "device_type", dev_type); 3422 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3423 "#address-cells", 3); 3424 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3425 "#size-cells", 2); 3426 3427 /* 3428 * Collect bridge window specifications, and use them to populate 3429 * the "avail" resources for the bus. Not all of those resources will 3430 * end up being available; this is done top-down, and so the initial 3431 * collection of windows populates the 'ranges' property for the 3432 * bus node. Later, as children are found, resources are removed from 3433 * the 'avail' list, so that it becomes the freelist for 3434 * this point in the tree. ranges may be set again after bridge 3435 * reprogramming in fix_ppb_res(), in which case it's set from 3436 * used + avail. 3437 * 3438 * According to PPB spec, the base register should be programmed 3439 * with a value bigger than the limit register when there are 3440 * no resources available. This applies to io, memory, and 3441 * prefetchable memory. 3442 */ 3443 3444 cmd_reg = (uint_t)pci_getw(bus, dev, func, PCI_CONF_COMM); 3445 fetch_ppb_res(bus, dev, func, RES_IO, &io.base, &io.limit); 3446 fetch_ppb_res(bus, dev, func, RES_MEM, &mem.base, &mem.limit); 3447 fetch_ppb_res(bus, dev, func, RES_PMEM, &pmem.base, &pmem.limit); 3448 3449 if (pci_boot_debug != 0) { 3450 dcmn_err(CE_NOTE, MSGHDR " I/O FWINIT 0x%lx ~ 0x%lx%s", 3451 "ppb", bus, dev, func, io.base, io.limit, 3452 io.base > io.limit ? " (disabled)" : ""); 3453 dcmn_err(CE_NOTE, MSGHDR " MEM FWINIT 0x%lx ~ 0x%lx%s", 3454 "ppb", bus, dev, func, mem.base, mem.limit, 3455 mem.base > mem.limit ? " (disabled)" : ""); 3456 dcmn_err(CE_NOTE, MSGHDR "PMEM FWINIT 0x%lx ~ 0x%lx%s", 3457 "ppb", bus, dev, func, pmem.base, pmem.limit, 3458 pmem.base > pmem.limit ? " (disabled)" : ""); 3459 } 3460 3461 /* 3462 * I/O range 3463 * 3464 * If the command register I/O enable bit is not set then we assume 3465 * that the I/O windows have been left unconfigured by system firmware. 3466 * In that case we leave it disabled and additionally set base > limit 3467 * to indicate there are there are no initial resources available and 3468 * to trigger later reconfiguration. 3469 */ 3470 if ((cmd_reg & PCI_COMM_IO) == 0) { 3471 io.base = PPB_DISABLE_IORANGE_BASE; 3472 io.limit = PPB_DISABLE_IORANGE_LIMIT; 3473 set_ppb_res(bus, dev, func, RES_IO, io.base, io.limit); 3474 } else if (io.base < io.limit) { 3475 uint64_t size = io.limit - io.base + 1; 3476 3477 memlist_insert(&pci_bus_res[secbus].io_avail, io.base, size); 3478 memlist_insert(&pci_bus_res[bus].io_used, io.base, size); 3479 3480 if (pci_bus_res[bus].io_avail != NULL) { 3481 (void) memlist_remove(&pci_bus_res[bus].io_avail, 3482 io.base, size); 3483 } 3484 } 3485 3486 /* 3487 * Memory range 3488 * 3489 * It is possible that the mem range will also have been left 3490 * unconfigured by system firmware. As for the I/O range, we check for 3491 * this by looking at the relevant bit in the command register (Memory 3492 * Access Enable in this case) but we also check if the base address is 3493 * 0, indicating that it is still at PCIe defaults. While 0 technically 3494 * could be a valid base address, it is unlikely. 3495 */ 3496 if ((cmd_reg & PCI_COMM_MAE) == 0 || mem.base == 0) { 3497 mem.base = PPB_DISABLE_MEMRANGE_BASE; 3498 mem.limit = PPB_DISABLE_MEMRANGE_LIMIT; 3499 set_ppb_res(bus, dev, func, RES_MEM, mem.base, mem.limit); 3500 } else if (mem.base < mem.limit) { 3501 uint64_t size = mem.limit - mem.base + 1; 3502 3503 memlist_insert(&pci_bus_res[secbus].mem_avail, mem.base, size); 3504 memlist_insert(&pci_bus_res[bus].mem_used, mem.base, size); 3505 /* remove from parent resource list */ 3506 (void) memlist_remove(&pci_bus_res[bus].mem_avail, 3507 mem.base, size); 3508 (void) memlist_remove(&pci_bus_res[bus].pmem_avail, 3509 mem.base, size); 3510 } 3511 3512 /* 3513 * Prefetchable range - as per MEM range above. 3514 */ 3515 if ((cmd_reg & PCI_COMM_MAE) == 0 || pmem.base == 0) { 3516 pmem.base = PPB_DISABLE_MEMRANGE_BASE; 3517 pmem.limit = PPB_DISABLE_MEMRANGE_LIMIT; 3518 set_ppb_res(bus, dev, func, RES_PMEM, pmem.base, pmem.limit); 3519 } else if (pmem.base < pmem.limit) { 3520 uint64_t size = pmem.limit - pmem.base + 1; 3521 3522 memlist_insert(&pci_bus_res[secbus].pmem_avail, 3523 pmem.base, size); 3524 memlist_insert(&pci_bus_res[bus].pmem_used, pmem.base, size); 3525 /* remove from parent resource list */ 3526 (void) memlist_remove(&pci_bus_res[bus].pmem_avail, 3527 pmem.base, size); 3528 (void) memlist_remove(&pci_bus_res[bus].mem_avail, 3529 pmem.base, size); 3530 } 3531 3532 /* 3533 * Add VGA legacy resources to the bridge's pci_bus_res if it 3534 * has VGA_ENABLE set. Note that we put them in 'avail', 3535 * because that's used to populate the ranges prop; they'll be 3536 * removed from there by the VGA device once it's found. Also, 3537 * remove them from the parent's available list and note them as 3538 * used in the parent. 3539 */ 3540 3541 if (pci_getw(bus, dev, func, PCI_BCNF_BCNTRL) & 3542 PCI_BCNF_BCNTRL_VGA_ENABLE) { 3543 3544 memlist_insert(&pci_bus_res[secbus].io_avail, 0x3b0, 0xc); 3545 3546 memlist_insert(&pci_bus_res[bus].io_used, 0x3b0, 0xc); 3547 if (pci_bus_res[bus].io_avail != NULL) { 3548 (void) memlist_remove(&pci_bus_res[bus].io_avail, 3549 0x3b0, 0xc); 3550 } 3551 3552 memlist_insert(&pci_bus_res[secbus].io_avail, 0x3c0, 0x20); 3553 3554 memlist_insert(&pci_bus_res[bus].io_used, 0x3c0, 0x20); 3555 if (pci_bus_res[bus].io_avail != NULL) { 3556 (void) memlist_remove(&pci_bus_res[bus].io_avail, 3557 0x3c0, 0x20); 3558 } 3559 3560 memlist_insert(&pci_bus_res[secbus].mem_avail, 0xa0000, 3561 0x20000); 3562 3563 memlist_insert(&pci_bus_res[bus].mem_used, 0xa0000, 0x20000); 3564 if (pci_bus_res[bus].mem_avail != NULL) { 3565 (void) memlist_remove(&pci_bus_res[bus].mem_avail, 3566 0xa0000, 0x20000); 3567 } 3568 } 3569 add_bus_range_prop(secbus); 3570 add_ranges_prop(secbus, B_TRUE); 3571 3572 dump_memlists("add_ppb_props end bus", bus); 3573 dump_memlists("add_ppb_props end secbus", secbus); 3574 } 3575 3576 extern const struct pci_class_strings_s class_pci[]; 3577 extern int class_pci_items; 3578 3579 static void 3580 add_model_prop(dev_info_t *dip, uint_t classcode) 3581 { 3582 const char *desc; 3583 int i; 3584 uchar_t baseclass = classcode >> 16; 3585 uchar_t subclass = (classcode >> 8) & 0xff; 3586 uchar_t progclass = classcode & 0xff; 3587 3588 if ((baseclass == PCI_CLASS_MASS) && (subclass == PCI_MASS_IDE)) { 3589 desc = "IDE controller"; 3590 } else { 3591 for (desc = 0, i = 0; i < class_pci_items; i++) { 3592 if ((baseclass == class_pci[i].base_class) && 3593 (subclass == class_pci[i].sub_class) && 3594 (progclass == class_pci[i].prog_class)) { 3595 desc = class_pci[i].actual_desc; 3596 break; 3597 } 3598 } 3599 if (i == class_pci_items) 3600 desc = "Unknown class of pci/pnpbios device"; 3601 } 3602 3603 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model", 3604 (char *)desc); 3605 } 3606 3607 static void 3608 add_bus_range_prop(int bus) 3609 { 3610 int bus_range[2]; 3611 3612 if (pci_bus_res[bus].dip == NULL) 3613 return; 3614 bus_range[0] = bus; 3615 bus_range[1] = pci_bus_res[bus].sub_bus; 3616 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 3617 "bus-range", (int *)bus_range, 2); 3618 } 3619 3620 /* 3621 * Handle both PCI root and PCI-PCI bridge range properties; 3622 * the 'ppb' argument selects PCI-PCI bridges versus root. 3623 */ 3624 static void 3625 memlist_to_ranges(void **rp, struct memlist *list, const int bus, 3626 const uint32_t type, boolean_t ppb) 3627 { 3628 ppb_ranges_t *ppb_rp = *rp; 3629 pci_ranges_t *pci_rp = *rp; 3630 3631 while (list != NULL) { 3632 uint32_t newtype = type; 3633 3634 /* 3635 * If this is in fact a 64-bit address, adjust the address 3636 * type code to match. 3637 */ 3638 if (list->ml_address + (list->ml_size - 1) > UINT32_MAX) { 3639 if ((type & PCI_ADDR_MASK) == PCI_ADDR_IO) { 3640 cmn_err(CE_WARN, "Found invalid 64-bit I/O " 3641 "space address 0x%lx+0x%lx on bus %x", 3642 list->ml_address, list->ml_size, bus); 3643 list = list->ml_next; 3644 continue; 3645 } 3646 newtype &= ~PCI_ADDR_MASK; 3647 newtype |= PCI_ADDR_MEM64; 3648 } 3649 3650 if (ppb) { 3651 ppb_rp->child_high = ppb_rp->parent_high = newtype; 3652 ppb_rp->child_mid = ppb_rp->parent_mid = 3653 (uint32_t)(list->ml_address >> 32); 3654 ppb_rp->child_low = ppb_rp->parent_low = 3655 (uint32_t)list->ml_address; 3656 ppb_rp->size_high = (uint32_t)(list->ml_size >> 32); 3657 ppb_rp->size_low = (uint32_t)list->ml_size; 3658 *rp = ++ppb_rp; 3659 } else { 3660 pci_rp->child_high = newtype; 3661 pci_rp->child_mid = pci_rp->parent_high = 3662 (uint32_t)(list->ml_address >> 32); 3663 pci_rp->child_low = pci_rp->parent_low = 3664 (uint32_t)list->ml_address; 3665 pci_rp->size_high = (uint32_t)(list->ml_size >> 32); 3666 pci_rp->size_low = (uint32_t)list->ml_size; 3667 *rp = ++pci_rp; 3668 } 3669 list = list->ml_next; 3670 } 3671 } 3672 3673 static void 3674 add_ranges_prop(int bus, boolean_t ppb) 3675 { 3676 int total, alloc_size; 3677 void *rp, *next_rp; 3678 struct memlist *iolist, *memlist, *pmemlist; 3679 3680 /* no devinfo node - unused bus, return */ 3681 if (pci_bus_res[bus].dip == NULL) 3682 return; 3683 3684 dump_memlists("add_ranges_prop", bus); 3685 3686 iolist = memlist = pmemlist = (struct memlist *)NULL; 3687 3688 memlist_merge(&pci_bus_res[bus].io_avail, &iolist); 3689 memlist_merge(&pci_bus_res[bus].io_used, &iolist); 3690 memlist_merge(&pci_bus_res[bus].mem_avail, &memlist); 3691 memlist_merge(&pci_bus_res[bus].mem_used, &memlist); 3692 memlist_merge(&pci_bus_res[bus].pmem_avail, &pmemlist); 3693 memlist_merge(&pci_bus_res[bus].pmem_used, &pmemlist); 3694 3695 total = memlist_count(iolist); 3696 total += memlist_count(memlist); 3697 total += memlist_count(pmemlist); 3698 3699 /* no property is created if no ranges are present */ 3700 if (total == 0) 3701 return; 3702 3703 alloc_size = total * 3704 (ppb ? sizeof (ppb_ranges_t) : sizeof (pci_ranges_t)); 3705 3706 next_rp = rp = kmem_alloc(alloc_size, KM_SLEEP); 3707 3708 memlist_to_ranges(&next_rp, iolist, bus, 3709 PCI_ADDR_IO | PCI_RELOCAT_B, ppb); 3710 memlist_to_ranges(&next_rp, memlist, bus, 3711 PCI_ADDR_MEM32 | PCI_RELOCAT_B, ppb); 3712 memlist_to_ranges(&next_rp, pmemlist, bus, 3713 PCI_ADDR_MEM32 | PCI_RELOCAT_B | PCI_PREFETCH_B, ppb); 3714 3715 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 3716 "ranges", (int *)rp, alloc_size / sizeof (int)); 3717 3718 kmem_free(rp, alloc_size); 3719 memlist_free_all(&iolist); 3720 memlist_free_all(&memlist); 3721 memlist_free_all(&pmemlist); 3722 } 3723 3724 static void 3725 memlist_remove_list(struct memlist **list, struct memlist *remove_list) 3726 { 3727 while (list && *list && remove_list) { 3728 (void) memlist_remove(list, remove_list->ml_address, 3729 remove_list->ml_size); 3730 remove_list = remove_list->ml_next; 3731 } 3732 } 3733 3734 static int 3735 memlist_to_spec(struct pci_phys_spec *sp, const int bus, struct memlist *list, 3736 const uint32_t type) 3737 { 3738 uint_t i = 0; 3739 3740 while (list != NULL) { 3741 uint32_t newtype = type; 3742 3743 /* 3744 * If this is in fact a 64-bit address, adjust the address 3745 * type code to match. 3746 */ 3747 if (list->ml_address + (list->ml_size - 1) > UINT32_MAX) { 3748 if ((type & PCI_ADDR_MASK) == PCI_ADDR_IO) { 3749 cmn_err(CE_WARN, "Found invalid 64-bit I/O " 3750 "space address 0x%lx+0x%lx on bus %x", 3751 list->ml_address, list->ml_size, bus); 3752 list = list->ml_next; 3753 continue; 3754 } 3755 newtype &= ~PCI_ADDR_MASK; 3756 newtype |= PCI_ADDR_MEM64; 3757 } 3758 3759 sp->pci_phys_hi = newtype; 3760 sp->pci_phys_mid = (uint32_t)(list->ml_address >> 32); 3761 sp->pci_phys_low = (uint32_t)list->ml_address; 3762 sp->pci_size_hi = (uint32_t)(list->ml_size >> 32); 3763 sp->pci_size_low = (uint32_t)list->ml_size; 3764 3765 list = list->ml_next; 3766 sp++, i++; 3767 } 3768 return (i); 3769 } 3770 3771 static void 3772 add_bus_available_prop(int bus) 3773 { 3774 int i, count; 3775 struct pci_phys_spec *sp; 3776 3777 /* no devinfo node - unused bus, return */ 3778 if (pci_bus_res[bus].dip == NULL) 3779 return; 3780 3781 count = memlist_count(pci_bus_res[bus].io_avail) + 3782 memlist_count(pci_bus_res[bus].mem_avail) + 3783 memlist_count(pci_bus_res[bus].pmem_avail); 3784 3785 if (count == 0) /* nothing available */ 3786 return; 3787 3788 sp = kmem_alloc(count * sizeof (*sp), KM_SLEEP); 3789 i = memlist_to_spec(&sp[0], bus, pci_bus_res[bus].io_avail, 3790 PCI_ADDR_IO | PCI_RELOCAT_B); 3791 i += memlist_to_spec(&sp[i], bus, pci_bus_res[bus].mem_avail, 3792 PCI_ADDR_MEM32 | PCI_RELOCAT_B); 3793 i += memlist_to_spec(&sp[i], bus, pci_bus_res[bus].pmem_avail, 3794 PCI_ADDR_MEM32 | PCI_RELOCAT_B | PCI_PREFETCH_B); 3795 ASSERT(i == count); 3796 3797 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 3798 "available", (int *)sp, 3799 i * sizeof (struct pci_phys_spec) / sizeof (int)); 3800 kmem_free(sp, count * sizeof (*sp)); 3801 } 3802 3803 static void 3804 alloc_res_array(void) 3805 { 3806 static uint_t array_size = 0; 3807 uint_t old_size; 3808 void *old_res; 3809 3810 if (array_size > pci_boot_maxbus + 1) 3811 return; /* array is big enough */ 3812 3813 old_size = array_size; 3814 old_res = pci_bus_res; 3815 3816 if (array_size == 0) 3817 array_size = 16; /* start with a reasonable number */ 3818 3819 while (array_size <= pci_boot_maxbus + 1) 3820 array_size <<= 1; 3821 pci_bus_res = (struct pci_bus_resource *)kmem_zalloc( 3822 array_size * sizeof (struct pci_bus_resource), KM_SLEEP); 3823 3824 if (old_res) { /* copy content and free old array */ 3825 bcopy(old_res, pci_bus_res, 3826 old_size * sizeof (struct pci_bus_resource)); 3827 kmem_free(old_res, old_size * sizeof (struct pci_bus_resource)); 3828 } 3829 } 3830 3831 static void 3832 create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid, 3833 ushort_t deviceid) 3834 { 3835 static dev_info_t *ioapicsnode = NULL; 3836 static int numioapics = 0; 3837 dev_info_t *ioapic_node; 3838 uint64_t physaddr; 3839 uint32_t lobase, hibase = 0; 3840 3841 /* BAR 0 contains the IOAPIC's memory-mapped I/O address */ 3842 lobase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0); 3843 3844 /* We (and the rest of the world) only support memory-mapped IOAPICs */ 3845 if ((lobase & PCI_BASE_SPACE_M) != PCI_BASE_SPACE_MEM) 3846 return; 3847 3848 if ((lobase & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) 3849 hibase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0 + 4); 3850 3851 lobase &= PCI_BASE_M_ADDR_M; 3852 3853 physaddr = (((uint64_t)hibase) << 32) | lobase; 3854 3855 /* 3856 * Create a nexus node for all IOAPICs under the root node. 3857 */ 3858 if (ioapicsnode == NULL) { 3859 if (ndi_devi_alloc(ddi_root_node(), IOAPICS_NODE_NAME, 3860 (pnode_t)DEVI_SID_NODEID, &ioapicsnode) != NDI_SUCCESS) { 3861 return; 3862 } 3863 (void) ndi_devi_online(ioapicsnode, 0); 3864 } 3865 3866 /* 3867 * Create a child node for this IOAPIC 3868 */ 3869 ioapic_node = ddi_add_child(ioapicsnode, IOAPICS_CHILD_NAME, 3870 DEVI_SID_NODEID, numioapics++); 3871 if (ioapic_node == NULL) { 3872 return; 3873 } 3874 3875 /* Vendor and Device ID */ 3876 (void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node, 3877 IOAPICS_PROP_VENID, vendorid); 3878 (void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node, 3879 IOAPICS_PROP_DEVID, deviceid); 3880 3881 /* device_type */ 3882 (void) ndi_prop_update_string(DDI_DEV_T_NONE, ioapic_node, 3883 "device_type", IOAPICS_DEV_TYPE); 3884 3885 /* reg */ 3886 (void) ndi_prop_update_int64(DDI_DEV_T_NONE, ioapic_node, 3887 "reg", physaddr); 3888 } 3889 3890 /* 3891 * NOTE: For PCIe slots, the name is generated from the slot number 3892 * information obtained from Slot Capabilities register. 3893 * For non-PCIe slots, it is generated based on the slot number 3894 * information in the PCI IRQ table. 3895 */ 3896 static void 3897 pciex_slot_names_prop(dev_info_t *dip, ushort_t slot_num) 3898 { 3899 char slotprop[256]; 3900 int len; 3901 3902 bzero(slotprop, sizeof (slotprop)); 3903 3904 /* set mask to 1 as there is only one slot (i.e dev 0) */ 3905 *(uint32_t *)slotprop = 1; 3906 len = 4; 3907 (void) snprintf(slotprop + len, sizeof (slotprop) - len, "pcie%d", 3908 slot_num); 3909 len += strlen(slotprop + len) + 1; 3910 len += len % 4; 3911 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "slot-names", 3912 (int *)slotprop, len / sizeof (int)); 3913 } 3914 3915 /* 3916 * Enable reporting of AER capability next pointer. 3917 * This needs to be done only for CK8-04 devices 3918 * by setting NV_XVR_VEND_CYA1 (offset 0xf40) bit 13 3919 * NOTE: BIOS is disabling this, it needs to be enabled temporarily 3920 * 3921 * This function is adapted from npe_ck804_fix_aer_ptr(), and is 3922 * called from pci_boot.c. 3923 */ 3924 static void 3925 ck804_fix_aer_ptr(dev_info_t *dip, pcie_req_id_t bdf) 3926 { 3927 dev_info_t *rcdip; 3928 ushort_t cya1; 3929 3930 rcdip = pcie_get_rc_dip(dip); 3931 ASSERT(rcdip != NULL); 3932 3933 if ((pci_cfgacc_get16(rcdip, bdf, PCI_CONF_VENID) == 3934 NVIDIA_VENDOR_ID) && 3935 (pci_cfgacc_get16(rcdip, bdf, PCI_CONF_DEVID) == 3936 NVIDIA_CK804_DEVICE_ID) && 3937 (pci_cfgacc_get8(rcdip, bdf, PCI_CONF_REVID) >= 3938 NVIDIA_CK804_AER_VALID_REVID)) { 3939 cya1 = pci_cfgacc_get16(rcdip, bdf, NVIDIA_CK804_VEND_CYA1_OFF); 3940 if (!(cya1 & ~NVIDIA_CK804_VEND_CYA1_ERPT_MASK)) 3941 (void) pci_cfgacc_put16(rcdip, bdf, 3942 NVIDIA_CK804_VEND_CYA1_OFF, 3943 cya1 | NVIDIA_CK804_VEND_CYA1_ERPT_VAL); 3944 } 3945 } 3946