1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _INTEL_NHM_H 28 #define _INTEL_NHM_H 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 #define NHM_EP_CPU 0x2c408086 35 #define NHM_WS_CPU 0x2c418086 36 #define NHM_CPU_RAS 0x2c1a8086 37 38 #define NHM_INTERCONNECT "Intel QuickPath" 39 40 #define MAX_CPU_NODES 2 41 #define CPU_PCI_DEVS 6 42 #define CPU_PCI_FUNCS 6 43 44 #define MAX_BUS_NUMBER max_bus_number 45 46 #define SOCKET_BUS(cpu) (MAX_BUS_NUMBER - (cpu)) 47 #define CPU_ID_RD(cpu) nhm_pci_getl(SOCKET_BUS(cpu), 0, 0, 0, 0) 48 #define MC_CONTROL_RD(cpu) \ 49 nhm_pci_getl(SOCKET_BUS(cpu), 3, 0, 0x48, 0) 50 #define MC_STATUS_RD(cpu) \ 51 nhm_pci_getl(SOCKET_BUS(cpu), 3, 0, 0x4c, 0) 52 #define MC_SMI_SPARE_DIMM_ERROR_STATUS_RD(cpu) \ 53 nhm_pci_getl(SOCKET_BUS(cpu), 3, 0, 0x50, 0) 54 #define MC_CPU_RAS_RD(cpu) \ 55 nhm_pci_getl(SOCKET_BUS(cpu), 3, 2, 0, 0) 56 #define MC_SCRUB_CONTROL_RD(cpu) \ 57 nhm_pci_getl(SOCKET_BUS(cpu), 3, 2, 0x4c, 0) 58 #define MC_SCRUB_CONTROL_WR(cpu, reg) nhm_pci_putl(SOCKET_BUS(cpu), 3, 2, \ 59 0x4c, reg); 60 #define MC_SSR_CONTROL_RD(cpu) nhm_pci_getl(SOCKET_BUS(cpu), 3, 2, 0x48, 0) 61 #define MC_SSR_CONTROL_WR(cpu, reg) nhm_pci_putl(SOCKET_BUS(cpu), 3, 2, 0x48, \ 62 reg); 63 #define MC_SSR_SCRUB_CONTROL_RD(cpu) nhm_pci_getl(SOCKET_BUS(cpu), 3, 2, \ 64 0x4c, 0) 65 #define MC_RAS_ENABLES_RD(cpu) nhm_pci_getl(SOCKET_BUS(cpu), 3, 2, 0x50, 0) 66 #define MC_RAS_STATUS_RD(cpu) nhm_pci_getl(SOCKET_BUS(cpu), 3, 2, 0x54, 0) 67 #define MC_SSR_STATUS_RD(cpu) nhm_pci_getl(SOCKET_BUS(cpu), 3, 2, 0x60, 0) 68 #define MC_CHANNEL_MAPPER_RD(cpu) nhm_pci_getl(SOCKET_BUS(cpu), 3, 0, \ 69 0x60, 0) 70 #define MC_COR_ECC_CNT_RD(cpu, select) \ 71 nhm_pci_getl(SOCKET_BUS(cpu), 3, 2, 0x80 + ((select) * 4), 0) 72 #define MC_CHANNEL_RANK_PRESENT_RD(cpu, channel) \ 73 nhm_pci_getl(SOCKET_BUS(cpu), (channel) + 4, 0, 0x7c, 0) 74 #define MC_DOD_RD(cpu, channel, select) \ 75 nhm_pci_getl(SOCKET_BUS(cpu), (channel) + 4, 1, 0x48 + ((select) * 4), 0) 76 #define MC_SAG_RD(cpu, channel, select) \ 77 nhm_pci_getl(SOCKET_BUS(cpu), (channel) + 4, 1, 0x80 + ((select) * 4), 0) 78 #define MC_RIR_LIMIT_RD(cpu, channel, select) \ 79 nhm_pci_getl(SOCKET_BUS(cpu), (channel) + 4, 2, 0x40 + ((select) * 4), 0) 80 #define MC_RIR_WAY_RD(cpu, channel, select) \ 81 nhm_pci_getl(SOCKET_BUS(cpu), (channel) + 4, 2, 0x80 + ((select) * 4), 0) 82 #define MC_CHANNEL_DIMM_INIT_PARAMS_RD(cpu, channel) \ 83 nhm_pci_getl(SOCKET_BUS(cpu), (channel) + 4, 0, 0x58, 0) 84 #define SAD_DRAM_RULE_RD(cpu, rule) \ 85 nhm_pci_getl(SOCKET_BUS(cpu), 0, 1, 0x80 + (4 * (rule)), 0) 86 #define SAD_INTERLEAVE_LIST_RD(cpu, rule) \ 87 nhm_pci_getl(SOCKET_BUS(cpu), 0, 1, 0xc0 + (4 * (rule)), 0) 88 #define TAD_DRAM_RULE_RD(cpu, rule) \ 89 nhm_pci_getl(SOCKET_BUS(cpu), 3, 1, 0x80 + (4 * (rule)), 0) 90 #define TAD_INTERLEAVE_LIST_RD(cpu, rule) \ 91 nhm_pci_getl(SOCKET_BUS(cpu), 3, 1, 0xc0 + (4 * (rule)), 0) 92 #define MC_DIMM_CLK_RATIO_STATUS(cpu) \ 93 nhm_pci_getl(SOCKET_BUS(cpu), 3, 4, 0x50, 0) 94 95 /* 96 * MC_CONTROL 97 */ 98 #define MC_CONTROL_CHANNEL_ACTIVE(reg, channel) \ 99 ((reg) & (1 << (8 + (channel))) != 0) 100 #define MC_CONTROL_ECCEN(reg) (((reg) >> 1) & 1) 101 #define MC_CONTROL_CLOSED_PAGE(reg) ((reg) & 1) 102 /* 103 * MC_STATUS 104 */ 105 #define CHANNEL_DISABLED(reg, channel) ((reg) & (1 << (channel))) 106 #define WS_ECC_ENABLED 0x10 107 /* 108 * MC_CHANNEL_DIMM_INIT_PARAMS 109 */ 110 #define THREE_DIMMS_PRESENT (1 << 24) /* not quad rank */ 111 #define SINGLE_QUAD_RANK_PRESENT (1 << 23) 112 #define QUAD_RANK_PRESENT (1 << 22) /* 1 or 2 quad rank dimms */ 113 #define REGISTERED_DIMM (1 << 15) 114 115 /* 116 * MC_DOD_CH 117 */ 118 #define RANKOFFSET(reg) (((reg) >> 10) & 7) 119 #define DIMMPRESENT(reg) (((reg) & (1 << 9)) != 0) 120 #define NUMBANK(reg) (((reg) & (3 << 7)) == 0 ? 4 : (((reg) >> 7) & 3) * 8) 121 #define NUMRANK(reg) (((reg) & (3 << 5)) == 0 ? 1 : (((reg) >> 5) & 3) * 2) 122 #define NUMROW(reg) ((((reg) >> 2) & 7) + 12) 123 #define NUMCOL(reg) (((reg) & 3) + 10) 124 #define DIMMWIDTH 8 125 #define DIMMSIZE(reg) ((1ULL << (NUMCOL(reg) + NUMROW(reg))) * NUMRANK(reg) \ 126 * NUMBANK(reg) * DIMMWIDTH) 127 128 /* 129 * MC_SAG_CH 130 */ 131 #define DIVBY3(reg) (((reg) >> 27) & 1) /* 3 or 6 way interleave */ 132 #define REMOVE_6(reg) (((reg) >> 24) & 1) 133 #define REMOVE_7(reg) (((reg) >> 25) & 1) 134 #define REMOVE_8(reg) (((reg) >> 26) & 1) 135 #define CH_ADDRESS_OFFSET(reg) \ 136 ((int64_t)(((uint64_t)(reg) & 0x00ffffff) << 40) >> 40) 137 /* 138 * MC_RIR_LIMIT_CH 139 */ 140 #define RIR_LIMIT(reg) ((((uint64_t)(reg) & 0x000003ff) + 1) << 28) 141 /* 142 * MC_RIR_WAY_CH 143 */ 144 #define RIR_OFFSET(reg) ((int64_t)(((uint64_t)(reg) & 0x3ff0) << 50) >> 54) 145 #define RIR_RANK(reg) ((reg) & 0xf) 146 147 #define MAX_RIR_WAY 4 148 149 /* 150 * MC_RAS_ENABLES 151 */ 152 #define RAS_LOCKSTEP_ENABLE(reg) (((reg) & 2) != 0) 153 #define RAS_MIRROR_MEM_ENABLE(reg) (((reg) & 1) != 0) 154 /* 155 * MC_RAS_STATUS 156 */ 157 #define REDUNDANCY_LOSS(reg) (((reg) & 1) != 0) 158 /* 159 * MC_SSRSTATUS 160 */ 161 #define SPAREING_IN_PROGRESS(reg) (((reg) & 2) != 0) 162 #define SPAREING_COMPLETE(reg) (((reg) & 1) != 0) 163 164 /* 165 * MC_SSR_CONTROL 166 */ 167 #define SSR_MODE(reg) ((reg) & 3) 168 #define SSR_IDLE 0 169 #define SSR_SCRUB 1 170 #define SSR_SPARE 2 171 #define DEMAND_SCRUB_ENABLE (1 << 6) 172 /* 173 * MC_SCRUB_CONTROL 174 */ 175 #define STARTSCRUB (1 << 24) 176 /* 177 * MC_DIMM_CLK_RATIO_STATUS 178 */ 179 #define MAX_DIMM_CLK_RATIO(reg) (((reg) >> 24) & 0x1f) 180 /* 181 * MC_SMI_SPARE_DIMM_ERROR_STATUS_RD 182 */ 183 #define REDUNDANCY_LOSS_FAILING_DIMM(status) (((status) >> 12) & 3) 184 #define DIMM_ERROR_OVERFLOW_STATUS(status) ((status) & 0xfff) 185 186 #define MAX_MEMORY_CONTROLLERS MAX_CPU_NODES 187 #define CHANNELS_PER_MEMORY_CONTROLLER 3 188 #define MAX_DIMMS_PER_CHANNEL 3 189 190 /* 191 * SAD_DRAM_RULE 192 */ 193 #define SAD_DRAM_LIMIT(sad) ((((uint64_t)(sad) & 0x000fffc0ULL) + 0x40) << 20) 194 #define SAD_DRAM_MODE(sad) (((sad) >> 1) & 3) 195 #define SAD_DRAM_RULE_ENABLE(sad) ((sad) & 1) 196 197 #define SAD_INTERLEAVE(list, num) (((list) >> ((num) * 4)) & 0x3) 198 #define INTERLEAVE_NWAY 8 199 #define MAX_SAD_DRAM_RULE 8 200 201 /* 202 * TAD_DRAM_RULE 203 */ 204 #define TAD_DRAM_LIMIT(tad) ((((uint64_t)(tad) & 0x000fffc0ULL) + 0x40) << 20) 205 #define TAD_DRAM_MODE(tad) (((tad) >> 1) & 3) 206 #define TAD_DRAM_RULE_ENABLE(tad) ((tad) & 1) 207 208 #define TAD_INTERLEAVE(list, channel) (((list) >> ((channel) * 4)) & 3) 209 210 #define MAX_TAD_DRAM_RULE 8 211 212 #define VRANK_SZ 0x40000000 213 214 /* 215 * MC_CHANNEL_MAPPER 216 */ 217 #define CHANNEL_MAP(reg, channel, write) (((reg) >> ((channel) * 6 + \ 218 ((write) ? 0 : 3))) & 7) 219 220 extern int max_bus_number; 221 222 #ifdef __cplusplus 223 } 224 #endif 225 226 #endif /* _INTEL_NHM_H */ 227