1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #include <sys/types.h> 28 #include <sys/modctl.h> 29 #include <sys/debug.h> 30 #include <sys/promif.h> 31 #include <sys/pci.h> 32 #include <sys/errno.h> 33 #include <sys/open.h> 34 #include <sys/uio.h> 35 #include <sys/cred.h> 36 #include <sys/cpu.h> 37 #include "ata_common.h" 38 #include "ata_disk.h" 39 #include "atapi.h" 40 #include "ata_blacklist.h" 41 #include "sil3xxx.h" 42 43 /* 44 * Solaris Entry Points. 45 */ 46 47 static int ata_attach(dev_info_t *dip, ddi_attach_cmd_t cmd); 48 static int ata_detach(dev_info_t *dip, ddi_detach_cmd_t cmd); 49 static int ata_bus_ctl(dev_info_t *d, dev_info_t *r, ddi_ctl_enum_t o, 50 void *a, void *v); 51 static uint_t ata_intr(caddr_t arg); 52 53 /* 54 * GHD Entry points 55 */ 56 57 static int ata_get_status(void *hba_handle, void *intr_status); 58 static void ata_process_intr(void *hba_handle, void *intr_status); 59 static int ata_hba_start(void *handle, gcmd_t *gcmdp); 60 static void ata_hba_complete(void *handle, gcmd_t *gcmdp, int do_callback); 61 static int ata_timeout_func(void *hba_handle, gcmd_t *gcmdp, 62 gtgt_t *gtgtp, gact_t action, int calltype); 63 64 /* 65 * Local Function Prototypes 66 */ 67 static int ata_prop_lookup_int(dev_t match_dev, dev_info_t *dip, 68 uint_t flags, char *name, int defvalue); 69 static int ata_ctlr_fsm(uchar_t fsm_func, ata_ctl_t *ata_ctlp, 70 ata_drv_t *ata_drvp, ata_pkt_t *ata_pktp, 71 int *DoneFlgp); 72 static void ata_destroy_controller(dev_info_t *dip); 73 static int ata_drive_type(uchar_t drvhd, 74 ddi_acc_handle_t io_hdl1, caddr_t ioaddr1, 75 ddi_acc_handle_t io_hdl2, caddr_t ioaddr2, 76 struct ata_id *ata_id_bufp); 77 static ata_ctl_t *ata_init_controller(dev_info_t *dip); 78 static ata_drv_t *ata_init_drive(ata_ctl_t *ata_ctlp, 79 uchar_t targ, uchar_t lun); 80 static int ata_init_drive_pcidma(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp, 81 dev_info_t *tdip); 82 static int ata_flush_cache(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp); 83 static void ata_init_pciide(dev_info_t *dip, ata_ctl_t *ata_ctlp); 84 static int ata_reset_bus(ata_ctl_t *ata_ctlp); 85 static int ata_setup_ioaddr(dev_info_t *dip, 86 ddi_acc_handle_t *iohandle1, caddr_t *ioaddr1p, 87 ddi_acc_handle_t *iohandle2, caddr_t *ioaddr2p, 88 ddi_acc_handle_t *bm_hdlp, caddr_t *bm_addrp); 89 static int ata_software_reset(ata_ctl_t *ata_ctlp); 90 static int ata_start_arq(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp, 91 ata_pkt_t *ata_pktp); 92 static int ata_strncmp(char *p1, char *p2, int cnt); 93 static void ata_uninit_drive(ata_drv_t *ata_drvp); 94 95 static int ata_check_pciide_blacklist(dev_info_t *dip, uint_t flags); 96 static int ata_check_revert_to_defaults(ata_drv_t *ata_drvp); 97 static void ata_show_transfer_mode(ata_ctl_t *, ata_drv_t *); 98 static int ata_spec_init_controller(dev_info_t *dip); 99 100 static void ata_init_pm(dev_info_t *); 101 static int ata_suspend(dev_info_t *); 102 static int ata_resume(dev_info_t *); 103 static int ata_power(dev_info_t *, int, int); 104 static int ata_change_power(dev_info_t *, uint8_t); 105 static int ata_is_pci(dev_info_t *); 106 static void ata_disable_DMA(ata_drv_t *ata_drvp); 107 108 /* 109 * Local static data 110 */ 111 static void *ata_state; 112 113 static tmr_t ata_timer_conf; /* single timeout list for all instances */ 114 static int ata_watchdog_usec = 100000; /* check timeouts every 100 ms */ 115 116 int ata_hba_start_watchdog = 1000; 117 int ata_process_intr_watchdog = 1000; 118 int ata_reset_bus_watchdog = 1000; 119 120 121 /* 122 * Use local or framework power management 123 */ 124 125 #ifdef ATA_USE_AUTOPM 126 #define ATA_BUSY_COMPONENT(d, c) ((void)pm_busy_component(d, c)) 127 #define ATA_IDLE_COMPONENT(d, c) ((void)pm_idle_component(d, c)) 128 #define ATA_RAISE_POWER(d, c, l) pm_raise_power(d, c, l) 129 #define ATA_LOWER_POWER(d, c, l) pm_lower_power(d, c, l) 130 #else 131 #define ATA_BUSY_COMPONENT(d, c) 132 #define ATA_IDLE_COMPONENT(d, c) 133 #define ATA_RAISE_POWER(d, c, l) ata_power(d, c, l) 134 #define ATA_LOWER_POWER(d, c, l) ata_power(d, c, l) 135 #endif 136 /* 137 * number of seconds to wait during various operations 138 */ 139 int ata_flush_delay = 5 * 1000000; 140 uint_t ata_set_feature_wait = 4 * 1000000; 141 uint_t ata_flush_cache_wait = 60 * 1000000; /* may take a long time */ 142 143 /* 144 * Change this for SFF-8070i support. Currently SFF-8070i is 145 * using a field in the IDENTIFY PACKET DEVICE response which 146 * already seems to be in use by some vendor's drives. I suspect 147 * SFF will either move their laslun field or provide a reliable 148 * way to validate it. 149 */ 150 int ata_enable_atapi_luns = FALSE; 151 152 /* 153 * set this to disable all DMA requests 154 */ 155 int ata_dma_disabled = FALSE; 156 157 /* 158 * set this to TRUE to enable storing the IDENTIFY DEVICE result in the 159 * "ata" or "atapi" property. 160 */ 161 int ata_id_debug = FALSE; 162 163 /* 164 * set this to TRUE to enable logging device-capability data 165 */ 166 int ata_capability_data = FALSE; 167 168 /* 169 * DMA selection message pointers 170 */ 171 char *ata_cntrl_DMA_sel_msg; 172 char *ata_dev_DMA_sel_msg; 173 174 /* 175 * bus nexus operations 176 */ 177 static struct bus_ops ata_bus_ops; 178 static struct bus_ops *scsa_bus_ops_p; 179 180 /* ARGSUSED */ 181 static int 182 ata_open(dev_t *devp, int flag, int otyp, cred_t *cred_p) 183 { 184 if (ddi_get_soft_state(ata_state, getminor(*devp)) == NULL) 185 return (ENXIO); 186 187 return (0); 188 } 189 190 /* 191 * The purpose of this function is to pass the ioaddress of the controller 192 * to the caller, specifically used for upgrade from pre-pciide 193 * to pciide nodes 194 */ 195 /* ARGSUSED */ 196 static int 197 ata_read(dev_t dev, struct uio *uio_p, cred_t *cred_p) 198 { 199 ata_ctl_t *ata_ctlp; 200 char buf[18]; 201 long len; 202 203 ata_ctlp = ddi_get_soft_state(ata_state, getminor(dev)); 204 205 if (ata_ctlp == NULL) 206 return (ENXIO); 207 208 (void) sprintf(buf, "%p\n", (void *) ata_ctlp->ac_ioaddr1); 209 210 len = strlen(buf) - uio_p->uio_offset; 211 len = min(uio_p->uio_resid, len); 212 if (len <= 0) 213 return (0); 214 215 return (uiomove((caddr_t)(buf + uio_p->uio_offset), len, 216 UIO_READ, uio_p)); 217 } 218 219 int 220 ata_devo_reset( 221 dev_info_t *dip, 222 ddi_reset_cmd_t cmd) 223 { 224 ata_ctl_t *ata_ctlp; 225 ata_drv_t *ata_drvp; 226 int instance; 227 int i; 228 int rc; 229 int flush_okay; 230 231 if (cmd != DDI_RESET_FORCE) 232 return (0); 233 234 instance = ddi_get_instance(dip); 235 ata_ctlp = ddi_get_soft_state(ata_state, instance); 236 237 if (!ata_ctlp) 238 return (0); 239 240 /* 241 * reset ATA drives and flush the write cache of any drives 242 */ 243 flush_okay = TRUE; 244 for (i = 0; i < ATA_MAXTARG; i++) { 245 if ((ata_drvp = CTL2DRV(ata_ctlp, i, 0)) == 0) 246 continue; 247 /* Don't revert to defaults for certain IBM drives */ 248 if ((ata_drvp->ad_flags & AD_DISK) != 0 && 249 ((ata_drvp->ad_flags & AD_NORVRT) == 0)) { 250 /* Enable revert to defaults when reset */ 251 (void) ata_set_feature(ata_ctlp, ata_drvp, 252 ATSF_ENA_REVPOD, 0); 253 } 254 255 /* 256 * skip flush cache if device type is cdrom 257 * 258 * notes: the structure definitions for ata_drvp->ad_id are 259 * defined for the ATA IDENTIFY_DEVICE, but if AD_ATAPI is set 260 * the struct holds data for the ATAPI IDENTIFY_PACKET_DEVICE 261 */ 262 if (!IS_CDROM(ata_drvp)) { 263 264 /* 265 * Try the ATA/ATAPI flush write cache command 266 */ 267 rc = ata_flush_cache(ata_ctlp, ata_drvp); 268 ADBG_WARN(("ata_flush_cache %s\n", 269 rc ? "okay" : "failed")); 270 271 if (!rc) 272 flush_okay = FALSE; 273 } 274 275 276 /* 277 * do something else if flush cache not supported 278 */ 279 } 280 281 /* 282 * just busy wait if any drive doesn't support FLUSH CACHE 283 */ 284 if (!flush_okay) 285 drv_usecwait(ata_flush_delay); 286 return (0); 287 } 288 289 /* 290 * quiesce(9E) entry point. 291 * 292 * This function is called when the system is single-threaded at high 293 * PIL with preemption disabled. Therefore, this function must not be 294 * blocked. 295 * 296 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 297 * DDI_FAILURE indicates an error condition and should almost never happen. 298 */ 299 int 300 ata_quiesce(dev_info_t *dip) 301 { 302 #ifdef ATA_DEBUG 303 /* 304 * Turn off debugging 305 */ 306 ata_debug = 0; 307 #endif 308 309 return (ata_devo_reset(dip, DDI_RESET_FORCE)); 310 } 311 312 313 static struct cb_ops ata_cb_ops = { 314 ata_open, /* open */ 315 nulldev, /* close */ 316 nodev, /* strategy */ 317 nodev, /* print */ 318 nodev, /* dump */ 319 ata_read, /* read */ 320 nodev, /* write */ 321 nodev, /* ioctl */ 322 nodev, /* devmap */ 323 nodev, /* mmap */ 324 nodev, /* segmap */ 325 nochpoll, /* chpoll */ 326 ddi_prop_op, /* prop_op */ 327 NULL, /* stream info */ 328 D_MP, /* driver compatibility flag */ 329 CB_REV, /* cb_ops revision */ 330 nodev, /* aread */ 331 nodev /* awrite */ 332 }; 333 334 static struct dev_ops ata_ops = { 335 DEVO_REV, /* devo_rev, */ 336 0, /* refcnt */ 337 ddi_getinfo_1to1, /* info */ 338 nulldev, /* identify */ 339 NULL, /* probe */ 340 ata_attach, /* attach */ 341 ata_detach, /* detach */ 342 ata_devo_reset, /* reset */ 343 &ata_cb_ops, /* driver operations */ 344 NULL, /* bus operations */ 345 ata_power, /* power */ 346 ata_quiesce /* quiesce */ 347 }; 348 349 /* driver loadable module wrapper */ 350 static struct modldrv modldrv = { 351 &mod_driverops, /* Type of module. This one is a driver */ 352 "ATA AT-bus attachment disk controller Driver", /* module name */ 353 &ata_ops, /* driver ops */ 354 }; 355 356 static struct modlinkage modlinkage = { 357 MODREV_1, (void *)&modldrv, NULL 358 }; 359 360 #ifdef ATA_DEBUG 361 int ata_debug_init = FALSE; 362 int ata_debug_attach = FALSE; 363 364 int ata_debug = ADBG_FLAG_ERROR 365 /* | ADBG_FLAG_ARQ */ 366 /* | ADBG_FLAG_INIT */ 367 /* | ADBG_FLAG_TRACE */ 368 /* | ADBG_FLAG_TRANSPORT */ 369 /* | ADBG_FLAG_WARN */ 370 ; 371 #endif 372 373 int 374 _init(void) 375 { 376 int err; 377 378 #ifdef ATA_DEBUG 379 if (ata_debug_init) 380 debug_enter("\nATA _INIT\n"); 381 #endif 382 383 if ((err = ddi_soft_state_init(&ata_state, sizeof (ata_ctl_t), 0)) != 0) 384 return (err); 385 386 if ((err = scsi_hba_init(&modlinkage)) != 0) { 387 ddi_soft_state_fini(&ata_state); 388 return (err); 389 } 390 391 /* save pointer to SCSA provided bus_ops struct */ 392 scsa_bus_ops_p = ata_ops.devo_bus_ops; 393 394 /* make a copy of SCSA bus_ops */ 395 ata_bus_ops = *(ata_ops.devo_bus_ops); 396 397 /* 398 * Modify our bus_ops to call our routines. Our implementation 399 * will determine if the device is ATA or ATAPI/SCSA and react 400 * accordingly. 401 */ 402 ata_bus_ops.bus_ctl = ata_bus_ctl; 403 404 /* patch our bus_ops into the dev_ops struct */ 405 ata_ops.devo_bus_ops = &ata_bus_ops; 406 407 if ((err = mod_install(&modlinkage)) != 0) { 408 scsi_hba_fini(&modlinkage); 409 ddi_soft_state_fini(&ata_state); 410 } 411 412 /* 413 * Initialize the per driver timer info. 414 */ 415 416 ghd_timer_init(&ata_timer_conf, drv_usectohz(ata_watchdog_usec)); 417 418 return (err); 419 } 420 421 int 422 _fini(void) 423 { 424 int err; 425 426 if ((err = mod_remove(&modlinkage)) == 0) { 427 ghd_timer_fini(&ata_timer_conf); 428 scsi_hba_fini(&modlinkage); 429 ddi_soft_state_fini(&ata_state); 430 } 431 432 return (err); 433 } 434 435 int 436 _info(struct modinfo *modinfop) 437 { 438 return (mod_info(&modlinkage, modinfop)); 439 } 440 441 442 /* 443 * 444 * driver attach entry point 445 * 446 */ 447 448 static int 449 ata_attach( 450 dev_info_t *dip, 451 ddi_attach_cmd_t cmd) 452 { 453 ata_ctl_t *ata_ctlp; 454 ata_drv_t *ata_drvp; 455 ata_drv_t *first_drvp = NULL; 456 uchar_t targ; 457 uchar_t lun; 458 uchar_t lastlun; 459 int atapi_count = 0; 460 int disk_count = 0; 461 462 ADBG_TRACE(("ata_attach entered\n")); 463 #ifdef ATA_DEBUG 464 if (ata_debug_attach) 465 debug_enter("\nATA_ATTACH\n\n"); 466 #endif 467 468 switch (cmd) { 469 case DDI_ATTACH: 470 break; 471 case DDI_RESUME: 472 return (ata_resume(dip)); 473 default: 474 return (DDI_FAILURE); 475 } 476 477 /* initialize controller */ 478 ata_ctlp = ata_init_controller(dip); 479 480 if (ata_ctlp == NULL) 481 goto errout; 482 483 mutex_enter(&ata_ctlp->ac_ccc.ccc_hba_mutex); 484 485 /* initialize drives */ 486 487 for (targ = 0; targ < ATA_MAXTARG; targ++) { 488 489 ata_drvp = ata_init_drive(ata_ctlp, targ, 0); 490 if (ata_drvp == NULL) 491 continue; 492 493 if (first_drvp == NULL) 494 first_drvp = ata_drvp; 495 496 if (ATAPIDRV(ata_drvp)) { 497 atapi_count++; 498 lastlun = ata_drvp->ad_id.ai_lastlun; 499 } else { 500 disk_count++; 501 lastlun = 0; 502 } 503 504 /* 505 * LUN support is currently disabled. Check with SFF-8070i 506 * before enabling. 507 */ 508 if (!ata_enable_atapi_luns) 509 lastlun = 0; 510 511 /* Initialize higher LUNs, if there are any */ 512 for (lun = 1; lun <= lastlun && lun < ATA_MAXLUN; lun++) { 513 if ((ata_drvp = 514 ata_init_drive(ata_ctlp, targ, lun)) != NULL) { 515 ata_show_transfer_mode(ata_ctlp, ata_drvp); 516 } 517 } 518 } 519 520 if ((atapi_count == 0) && (disk_count == 0)) { 521 ADBG_WARN(("ata_attach: no drives detected\n")); 522 goto errout1; 523 } 524 525 /* 526 * Always make certain that a valid drive is selected so 527 * that routines which poll the status register don't get 528 * confused by non-existent drives. 529 */ 530 ddi_put8(ata_ctlp->ac_iohandle1, ata_ctlp->ac_drvhd, 531 first_drvp->ad_drive_bits); 532 ata_nsecwait(400); 533 534 /* 535 * make certain the drive selected 536 */ 537 if (!ata_wait(ata_ctlp->ac_iohandle2, ata_ctlp->ac_ioaddr2, 538 0, ATS_BSY, 5000000)) { 539 ADBG_ERROR(("ata_attach: select failed\n")); 540 } 541 542 /* 543 * initialize atapi/ata_dsk modules if we have at least 544 * one drive of that type. 545 */ 546 547 if (atapi_count) { 548 if (!atapi_attach(ata_ctlp)) 549 goto errout1; 550 ata_ctlp->ac_flags |= AC_ATAPI_INIT; 551 } 552 553 if (disk_count) { 554 if (!ata_disk_attach(ata_ctlp)) 555 goto errout1; 556 ata_ctlp->ac_flags |= AC_DISK_INIT; 557 } 558 559 /* 560 * make certain the interrupt and error latches are clear 561 */ 562 if (ata_ctlp->ac_pciide) { 563 564 int instance = ddi_get_instance(dip); 565 if (ddi_create_minor_node(dip, "control", S_IFCHR, instance, 566 DDI_PSEUDO, 0) != DDI_SUCCESS) { 567 goto errout1; 568 } 569 570 (void) ata_pciide_status_clear(ata_ctlp); 571 572 } 573 574 /* 575 * enable the interrupt handler and drop the mutex 576 */ 577 ata_ctlp->ac_flags |= AC_ATTACHED; 578 mutex_exit(&ata_ctlp->ac_ccc.ccc_hba_mutex); 579 580 ata_init_pm(dip); 581 582 ddi_report_dev(dip); 583 return (DDI_SUCCESS); 584 585 errout1: 586 mutex_exit(&ata_ctlp->ac_ccc.ccc_hba_mutex); 587 errout: 588 (void) ata_detach(dip, DDI_DETACH); 589 return (DDI_FAILURE); 590 } 591 592 /* driver detach entry point */ 593 594 static int 595 ata_detach( 596 dev_info_t *dip, 597 ddi_detach_cmd_t cmd) 598 { 599 ata_ctl_t *ata_ctlp; 600 ata_drv_t *ata_drvp; 601 int instance; 602 int i; 603 int j; 604 605 ADBG_TRACE(("ata_detach entered\n")); 606 607 switch (cmd) { 608 case DDI_DETACH: 609 break; 610 case DDI_SUSPEND: 611 return (ata_suspend(dip)); 612 default: 613 return (DDI_FAILURE); 614 } 615 616 instance = ddi_get_instance(dip); 617 ata_ctlp = ddi_get_soft_state(ata_state, instance); 618 619 if (!ata_ctlp) 620 return (DDI_SUCCESS); 621 622 if (ata_ctlp->ac_pm_support) { 623 ATA_BUSY_COMPONENT(dip, 0); 624 if (ata_ctlp->ac_pm_level != PM_LEVEL_D0) { 625 if (ATA_RAISE_POWER(dip, 0, PM_LEVEL_D0) != 626 DDI_SUCCESS) { 627 ATA_IDLE_COMPONENT(dip, 0); 628 return (DDI_FAILURE); 629 } 630 } 631 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "pm-components"); 632 } 633 ata_ctlp->ac_flags &= ~AC_ATTACHED; 634 635 /* destroy ata module */ 636 if (ata_ctlp->ac_flags & AC_DISK_INIT) 637 ata_disk_detach(ata_ctlp); 638 639 /* destroy atapi module */ 640 if (ata_ctlp->ac_flags & AC_ATAPI_INIT) 641 atapi_detach(ata_ctlp); 642 643 ddi_remove_minor_node(dip, NULL); 644 645 /* destroy drives */ 646 for (i = 0; i < ATA_MAXTARG; i++) { 647 for (j = 0; j < ATA_MAXLUN; j++) { 648 ata_drvp = CTL2DRV(ata_ctlp, i, j); 649 if (ata_drvp != NULL) 650 ata_uninit_drive(ata_drvp); 651 } 652 } 653 654 if (ata_ctlp->ac_iohandle1) 655 ddi_regs_map_free(&ata_ctlp->ac_iohandle1); 656 if (ata_ctlp->ac_iohandle2) 657 ddi_regs_map_free(&ata_ctlp->ac_iohandle2); 658 if (ata_ctlp->ac_bmhandle) 659 ddi_regs_map_free(&ata_ctlp->ac_bmhandle); 660 661 /* destroy controller */ 662 ata_destroy_controller(dip); 663 664 ddi_prop_remove_all(dip); 665 666 return (DDI_SUCCESS); 667 } 668 669 /* 670 * Nexus driver bus_ctl entry point 671 */ 672 /*ARGSUSED*/ 673 static int 674 ata_bus_ctl( 675 dev_info_t *d, 676 dev_info_t *r, 677 ddi_ctl_enum_t o, 678 void *a, 679 void *v) 680 { 681 dev_info_t *tdip; 682 int target_type; 683 int rc; 684 char *bufp; 685 686 ADBG_TRACE(("ata_bus_ctl entered\n")); 687 688 switch (o) { 689 690 case DDI_CTLOPS_SIDDEV: 691 return (DDI_FAILURE); 692 693 case DDI_CTLOPS_IOMIN: 694 695 /* 696 * Since we use PIO, we return a minimum I/O size of 697 * one byte. This will need to be updated when we 698 * implement DMA support 699 */ 700 701 *((int *)v) = 1; 702 return (DDI_SUCCESS); 703 704 case DDI_CTLOPS_DMAPMAPC: 705 case DDI_CTLOPS_REPORTINT: 706 case DDI_CTLOPS_REGSIZE: 707 case DDI_CTLOPS_NREGS: 708 case DDI_CTLOPS_SLAVEONLY: 709 case DDI_CTLOPS_AFFINITY: 710 case DDI_CTLOPS_POKE: 711 case DDI_CTLOPS_PEEK: 712 713 /* These ops shouldn't be called by a target driver */ 714 ADBG_ERROR(("ata_bus_ctl: %s%d: invalid op (%d) from %s%d\n", 715 ddi_driver_name(d), ddi_get_instance(d), o, 716 ddi_driver_name(r), ddi_get_instance(r))); 717 718 return (DDI_FAILURE); 719 720 case DDI_CTLOPS_REPORTDEV: 721 case DDI_CTLOPS_INITCHILD: 722 case DDI_CTLOPS_UNINITCHILD: 723 724 /* these require special handling below */ 725 break; 726 727 default: 728 return (ddi_ctlops(d, r, o, a, v)); 729 } 730 731 /* get targets dip */ 732 733 if (o == DDI_CTLOPS_INITCHILD || o == DDI_CTLOPS_UNINITCHILD) 734 tdip = (dev_info_t *)a; 735 else 736 tdip = r; 737 738 /* 739 * XXX - Get class of target 740 * Before the "class" entry in a conf file becomes 741 * a real property, we use an additional property 742 * tentatively called "class_prop". We will require that 743 * new classes (ie. direct) export "class_prop". 744 * SCSA target drivers will not have this property, so 745 * no property implies SCSA. 746 */ 747 if ((ddi_prop_lookup_string(DDI_DEV_T_ANY, tdip, DDI_PROP_DONTPASS, 748 "class", &bufp) == DDI_PROP_SUCCESS) || 749 (ddi_prop_lookup_string(DDI_DEV_T_ANY, tdip, DDI_PROP_DONTPASS, 750 "class_prop", &bufp) == DDI_PROP_SUCCESS)) { 751 if (strcmp(bufp, "dada") == 0) 752 target_type = ATA_DEV_DISK; 753 else if (strcmp(bufp, "scsi") == 0) 754 target_type = ATA_DEV_ATAPI; 755 else { 756 ADBG_WARN(("ata_bus_ctl: invalid target class %s\n", 757 bufp)); 758 ddi_prop_free(bufp); 759 return (DDI_FAILURE); 760 } 761 ddi_prop_free(bufp); 762 } else { 763 target_type = ATA_DEV_ATAPI; /* no class prop, assume SCSI */ 764 } 765 766 if (o == DDI_CTLOPS_INITCHILD) { 767 int instance = ddi_get_instance(d); 768 ata_ctl_t *ata_ctlp = ddi_get_soft_state(ata_state, instance); 769 ata_drv_t *ata_drvp; 770 int targ; 771 int lun; 772 int drive_type; 773 char *disk_prop; 774 char *class_prop; 775 776 if (ata_ctlp == NULL) { 777 ADBG_WARN(("ata_bus_ctl: failed to find ctl struct\n")); 778 return (DDI_FAILURE); 779 } 780 781 /* get (target,lun) of child device */ 782 783 targ = ddi_prop_get_int(DDI_DEV_T_ANY, tdip, DDI_PROP_DONTPASS, 784 "target", -1); 785 if (targ == -1) { 786 ADBG_WARN(("ata_bus_ctl: failed to get targ num\n")); 787 return (DDI_FAILURE); 788 } 789 790 lun = ddi_prop_get_int(DDI_DEV_T_ANY, tdip, DDI_PROP_DONTPASS, 791 "lun", 0); 792 793 if ((targ < 0) || (targ >= ATA_MAXTARG) || 794 (lun < 0) || (lun >= ATA_MAXLUN)) { 795 return (DDI_FAILURE); 796 } 797 798 ata_drvp = CTL2DRV(ata_ctlp, targ, lun); 799 800 if (ata_drvp == NULL) 801 return (DDI_FAILURE); /* no drive */ 802 803 /* get type of device */ 804 805 if (ATAPIDRV(ata_drvp)) 806 drive_type = ATA_DEV_ATAPI; 807 else 808 drive_type = ATA_DEV_DISK; 809 810 /* 811 * Check for special handling when child driver is 812 * cmdk (which morphs to the correct interface) 813 */ 814 if (strcmp(ddi_get_name(tdip), "cmdk") == 0) { 815 816 if ((target_type == ATA_DEV_DISK) && 817 (target_type != drive_type)) 818 return (DDI_FAILURE); 819 820 target_type = drive_type; 821 822 if (drive_type == ATA_DEV_ATAPI) { 823 class_prop = "scsi"; 824 } else { 825 disk_prop = "dadk"; 826 class_prop = "dada"; 827 828 if (ndi_prop_update_string(DDI_DEV_T_NONE, tdip, 829 "disk", disk_prop) != DDI_PROP_SUCCESS) { 830 ADBG_WARN(("ata_bus_ctl: failed to " 831 "create disk prop\n")); 832 return (DDI_FAILURE); 833 } 834 } 835 836 if (ndi_prop_update_string(DDI_DEV_T_NONE, tdip, 837 "class_prop", class_prop) != DDI_PROP_SUCCESS) { 838 ADBG_WARN(("ata_bus_ctl: failed to " 839 "create class prop\n")); 840 return (DDI_FAILURE); 841 } 842 } 843 844 /* Check that target class matches the device */ 845 846 if (target_type != drive_type) 847 return (DDI_FAILURE); 848 849 /* save pointer to drive struct for ata_disk_bus_ctl */ 850 ddi_set_driver_private(tdip, ata_drvp); 851 852 /* 853 * Determine whether to enable DMA support for this drive. This 854 * check is deferred to this point so that the various dma 855 * properties could reside on the devinfo node should finer 856 * grained dma control be required. 857 */ 858 if (ata_drvp->ad_pciide_dma == ATA_DMA_UNINITIALIZED) { 859 ata_drvp->ad_pciide_dma = 860 ata_init_drive_pcidma(ata_ctlp, ata_drvp, tdip); 861 ata_show_transfer_mode(ata_ctlp, ata_drvp); 862 } 863 } 864 865 if (target_type == ATA_DEV_ATAPI) { 866 rc = scsa_bus_ops_p->bus_ctl(d, r, o, a, v); 867 } else { 868 rc = ata_disk_bus_ctl(d, r, o, a, v); 869 } 870 871 return (rc); 872 } 873 874 /* 875 * 876 * GHD ccc_hba_complete callback 877 * 878 */ 879 880 /* ARGSUSED */ 881 static void 882 ata_hba_complete( 883 void *hba_handle, 884 gcmd_t *gcmdp, 885 int do_callback) 886 { 887 ata_drv_t *ata_drvp; 888 ata_pkt_t *ata_pktp; 889 890 ADBG_TRACE(("ata_hba_complete entered\n")); 891 892 ata_drvp = GCMD2DRV(gcmdp); 893 ata_pktp = GCMD2APKT(gcmdp); 894 if (ata_pktp->ap_complete) 895 (*ata_pktp->ap_complete)(ata_drvp, ata_pktp, 896 do_callback); 897 } 898 899 /* GHD ccc_timeout_func callback */ 900 901 /* ARGSUSED */ 902 static int 903 ata_timeout_func( 904 void *hba_handle, 905 gcmd_t *gcmdp, 906 gtgt_t *gtgtp, 907 gact_t action, 908 int calltype) 909 { 910 ata_ctl_t *ata_ctlp; 911 ata_pkt_t *ata_pktp; 912 ata_drv_t *ata_drvp; 913 914 ADBG_TRACE(("ata_timeout_func entered\n")); 915 916 ata_ctlp = (ata_ctl_t *)hba_handle; 917 918 if (gcmdp != NULL) 919 ata_pktp = GCMD2APKT(gcmdp); 920 else 921 ata_pktp = NULL; 922 923 switch (action) { 924 case GACTION_EARLY_ABORT: 925 /* abort before request was started */ 926 if (ata_pktp != NULL) { 927 ata_pktp->ap_flags |= AP_ABORT; 928 } 929 ghd_complete(&ata_ctlp->ac_ccc, gcmdp); 930 return (TRUE); 931 932 case GACTION_EARLY_TIMEOUT: 933 /* timeout before request was started */ 934 if (ata_pktp != NULL) { 935 ata_pktp->ap_flags |= AP_TIMEOUT; 936 } 937 ghd_complete(&ata_ctlp->ac_ccc, gcmdp); 938 return (TRUE); 939 940 case GACTION_RESET_TARGET: 941 /* 942 * Reset a device is not supported. Resetting a specific 943 * device can't be done at all to an ATA device and if 944 * you send a RESET to an ATAPI device you have to 945 * reset the whole bus to make certain both devices 946 * on the bus stay in sync regarding which device is 947 * the currently selected one. 948 */ 949 return (FALSE); 950 951 case GACTION_RESET_BUS: 952 /* 953 * Issue bus reset and reinitialize both drives. 954 * But only if this is a timed-out request. Target 955 * driver reset requests are ignored because ATA 956 * and ATAPI devices shouldn't be gratuitously reset. 957 * Also disable DMA if it is a CF device. 958 */ 959 if (gcmdp == NULL) 960 break; 961 ata_drvp = GCMD2DRV(gcmdp); 962 if (ata_drvp != NULL) 963 if (ata_drvp->ad_id.ai_config == ATA_ID_CF_TO_ATA) 964 ata_disable_DMA(ata_drvp); 965 return (ata_reset_bus(ata_ctlp)); 966 default: 967 break; 968 } 969 return (FALSE); 970 } 971 972 /* 973 * 974 * Initialize controller's soft-state structure 975 * 976 */ 977 978 static ata_ctl_t * 979 ata_init_controller( 980 dev_info_t *dip) 981 { 982 ata_ctl_t *ata_ctlp; 983 int instance; 984 caddr_t ioaddr1; 985 caddr_t ioaddr2; 986 987 ADBG_TRACE(("ata_init_controller entered\n")); 988 989 instance = ddi_get_instance(dip); 990 991 /* allocate controller structure */ 992 if (ddi_soft_state_zalloc(ata_state, instance) != DDI_SUCCESS) { 993 ADBG_WARN(("ata_init_controller: soft_state_zalloc failed\n")); 994 return (NULL); 995 } 996 997 ata_ctlp = ddi_get_soft_state(ata_state, instance); 998 999 if (ata_ctlp == NULL) { 1000 ADBG_WARN(("ata_init_controller: failed to find " 1001 "controller struct\n")); 1002 return (NULL); 1003 } 1004 1005 /* 1006 * initialize per-controller data 1007 */ 1008 ata_ctlp->ac_dip = dip; 1009 ata_ctlp->ac_arq_pktp = kmem_zalloc(sizeof (ata_pkt_t), KM_SLEEP); 1010 1011 /* 1012 * map the device registers 1013 */ 1014 if (!ata_setup_ioaddr(dip, &ata_ctlp->ac_iohandle1, &ioaddr1, 1015 &ata_ctlp->ac_iohandle2, &ioaddr2, 1016 &ata_ctlp->ac_bmhandle, &ata_ctlp->ac_bmaddr)) { 1017 (void) ata_detach(dip, DDI_DETACH); 1018 return (NULL); 1019 } 1020 1021 ADBG_INIT(("ata_init_controller: ioaddr1 = 0x%p, ioaddr2 = 0x%p\n", 1022 ioaddr1, ioaddr2)); 1023 1024 /* 1025 * Do ARQ setup 1026 */ 1027 atapi_init_arq(ata_ctlp); 1028 1029 /* 1030 * Do PCI-IDE setup 1031 */ 1032 ata_init_pciide(dip, ata_ctlp); 1033 1034 /* 1035 * port addresses associated with ioaddr1 1036 */ 1037 ata_ctlp->ac_ioaddr1 = ioaddr1; 1038 ata_ctlp->ac_data = (ushort_t *)ioaddr1 + AT_DATA; 1039 ata_ctlp->ac_error = (uchar_t *)ioaddr1 + AT_ERROR; 1040 ata_ctlp->ac_feature = (uchar_t *)ioaddr1 + AT_FEATURE; 1041 ata_ctlp->ac_count = (uchar_t *)ioaddr1 + AT_COUNT; 1042 ata_ctlp->ac_sect = (uchar_t *)ioaddr1 + AT_SECT; 1043 ata_ctlp->ac_lcyl = (uchar_t *)ioaddr1 + AT_LCYL; 1044 ata_ctlp->ac_hcyl = (uchar_t *)ioaddr1 + AT_HCYL; 1045 ata_ctlp->ac_drvhd = (uchar_t *)ioaddr1 + AT_DRVHD; 1046 ata_ctlp->ac_status = (uchar_t *)ioaddr1 + AT_STATUS; 1047 ata_ctlp->ac_cmd = (uchar_t *)ioaddr1 + AT_CMD; 1048 1049 /* 1050 * port addresses associated with ioaddr2 1051 */ 1052 ata_ctlp->ac_ioaddr2 = ioaddr2; 1053 ata_ctlp->ac_altstatus = (uchar_t *)ioaddr2 + AT_ALTSTATUS; 1054 ata_ctlp->ac_devctl = (uchar_t *)ioaddr2 + AT_DEVCTL; 1055 1056 /* 1057 * If AC_BSY_WAIT needs to be set for laptops that do 1058 * suspend/resume but do not correctly wait for the busy bit to 1059 * drop after a resume. 1060 */ 1061 ata_ctlp->ac_timing_flags = ddi_prop_get_int(DDI_DEV_T_ANY, 1062 dip, DDI_PROP_DONTPASS, "timing_flags", 0); 1063 /* 1064 * get max transfer size, default to 256 sectors 1065 */ 1066 ata_ctlp->ac_max_transfer = ddi_prop_get_int(DDI_DEV_T_ANY, 1067 dip, DDI_PROP_DONTPASS, "max_transfer", 0x100); 1068 if (ata_ctlp->ac_max_transfer < 1) 1069 ata_ctlp->ac_max_transfer = 1; 1070 if (ata_ctlp->ac_max_transfer > 0x100) 1071 ata_ctlp->ac_max_transfer = 0x100; 1072 1073 /* 1074 * Get the standby timer value 1075 */ 1076 ata_ctlp->ac_standby_time = ddi_prop_get_int(DDI_DEV_T_ANY, 1077 dip, DDI_PROP_DONTPASS, "standby", -1); 1078 1079 /* 1080 * If this is a /pci/pci-ide instance check to see if 1081 * it's supposed to be attached as an /isa/ata 1082 */ 1083 if (ata_ctlp->ac_pciide) { 1084 static char prop_buf[] = "SUNW-ata-ffff-isa"; 1085 int addr1 = (intptr_t)ioaddr1; 1086 1087 1088 if (addr1 < 0 || addr1 > 0xffff) { 1089 (void) ata_detach(dip, DDI_DETACH); 1090 return (NULL); 1091 } 1092 (void) sprintf(prop_buf, "SUNW-ata-%04x-isa", 1093 addr1); 1094 if (ddi_prop_exists(DDI_DEV_T_ANY, ddi_root_node(), 1095 DDI_PROP_DONTPASS, prop_buf)) { 1096 (void) ata_detach(dip, DDI_DETACH); 1097 return (NULL); 1098 } 1099 } 1100 1101 /* Init controller specific stuff */ 1102 (void) ata_spec_init_controller(dip); 1103 1104 /* 1105 * initialize GHD 1106 */ 1107 1108 GHD_WAITQ_INIT(&ata_ctlp->ac_ccc.ccc_waitq, NULL, 1); 1109 1110 if (!ghd_register("ata", &ata_ctlp->ac_ccc, dip, 0, ata_ctlp, 1111 atapi_ccballoc, atapi_ccbfree, 1112 ata_pciide_dma_sg_func, ata_hba_start, 1113 ata_hba_complete, ata_intr, 1114 ata_get_status, ata_process_intr, ata_timeout_func, 1115 &ata_timer_conf, NULL)) { 1116 (void) ata_detach(dip, DDI_DETACH); 1117 return (NULL); 1118 } 1119 1120 ata_ctlp->ac_flags |= AC_GHD_INIT; 1121 return (ata_ctlp); 1122 } 1123 1124 /* destroy a controller */ 1125 1126 static void 1127 ata_destroy_controller( 1128 dev_info_t *dip) 1129 { 1130 ata_ctl_t *ata_ctlp; 1131 int instance; 1132 1133 ADBG_TRACE(("ata_destroy_controller entered\n")); 1134 1135 instance = ddi_get_instance(dip); 1136 ata_ctlp = ddi_get_soft_state(ata_state, instance); 1137 1138 if (ata_ctlp == NULL) 1139 return; 1140 1141 /* destroy ghd */ 1142 if (ata_ctlp->ac_flags & AC_GHD_INIT) 1143 ghd_unregister(&ata_ctlp->ac_ccc); 1144 1145 /* free the pciide buffer (if any) */ 1146 ata_pciide_free(ata_ctlp); 1147 1148 /* destroy controller struct */ 1149 kmem_free(ata_ctlp->ac_arq_pktp, sizeof (ata_pkt_t)); 1150 ddi_soft_state_free(ata_state, instance); 1151 1152 } 1153 1154 1155 /* 1156 * 1157 * initialize a drive 1158 * 1159 */ 1160 1161 static ata_drv_t * 1162 ata_init_drive( 1163 ata_ctl_t *ata_ctlp, 1164 uchar_t targ, 1165 uchar_t lun) 1166 { 1167 static char nec_260[] = "NEC CD-ROM DRIVE"; 1168 ata_drv_t *ata_drvp; 1169 struct ata_id *aidp; 1170 char buf[80]; 1171 int drive_type; 1172 int i; 1173 int valid_version = 0; 1174 1175 ADBG_TRACE(("ata_init_drive entered, targ = %d, lun = %d\n", 1176 targ, lun)); 1177 1178 /* check if device already exists */ 1179 1180 ata_drvp = CTL2DRV(ata_ctlp, targ, lun); 1181 1182 if (ata_drvp != NULL) 1183 return (ata_drvp); 1184 1185 /* allocate new device structure */ 1186 1187 ata_drvp = kmem_zalloc(sizeof (ata_drv_t), KM_SLEEP); 1188 aidp = &ata_drvp->ad_id; 1189 1190 /* 1191 * set up drive struct 1192 */ 1193 ata_drvp->ad_ctlp = ata_ctlp; 1194 ata_drvp->ad_pciide_dma = ATA_DMA_UNINITIALIZED; 1195 ata_drvp->ad_targ = targ; 1196 ata_drvp->ad_drive_bits = 1197 (ata_drvp->ad_targ == 0 ? ATDH_DRIVE0 : ATDH_DRIVE1); 1198 /* 1199 * Add the LUN for SFF-8070i support 1200 */ 1201 ata_drvp->ad_lun = lun; 1202 ata_drvp->ad_drive_bits |= ata_drvp->ad_lun; 1203 1204 /* 1205 * get drive type, side effect is to collect 1206 * IDENTIFY DRIVE data 1207 */ 1208 1209 drive_type = ata_drive_type(ata_drvp->ad_drive_bits, 1210 ata_ctlp->ac_iohandle1, 1211 ata_ctlp->ac_ioaddr1, 1212 ata_ctlp->ac_iohandle2, 1213 ata_ctlp->ac_ioaddr2, 1214 aidp); 1215 1216 switch (drive_type) { 1217 case ATA_DEV_NONE: 1218 /* no drive found */ 1219 goto errout; 1220 case ATA_DEV_ATAPI: 1221 ata_drvp->ad_flags |= AD_ATAPI; 1222 break; 1223 case ATA_DEV_DISK: 1224 ata_drvp->ad_flags |= AD_DISK; 1225 break; 1226 } 1227 1228 /* 1229 * swap bytes of all text fields 1230 */ 1231 if (!ata_strncmp(nec_260, aidp->ai_model, sizeof (aidp->ai_model))) { 1232 swab(aidp->ai_drvser, aidp->ai_drvser, 1233 sizeof (aidp->ai_drvser)); 1234 swab(aidp->ai_fw, aidp->ai_fw, 1235 sizeof (aidp->ai_fw)); 1236 swab(aidp->ai_model, aidp->ai_model, 1237 sizeof (aidp->ai_model)); 1238 } 1239 1240 /* 1241 * Check if this drive has the Single Sector bug 1242 */ 1243 1244 if (ata_check_drive_blacklist(&ata_drvp->ad_id, ATA_BL_1SECTOR)) 1245 ata_drvp->ad_flags |= AD_1SECTOR; 1246 else 1247 ata_drvp->ad_flags &= ~AD_1SECTOR; 1248 1249 if (ata_check_drive_blacklist(&ata_drvp->ad_id, ATA_BL_LBA48)) 1250 ata_drvp->ad_flags |= AD_BLLBA48; 1251 else 1252 ata_drvp->ad_flags &= ~AD_BLLBA48; 1253 1254 /* Check if this drive has the "revert to defaults" bug */ 1255 if (!ata_check_revert_to_defaults(ata_drvp)) 1256 ata_drvp->ad_flags |= AD_NORVRT; 1257 1258 /* Dump the drive info */ 1259 (void) strncpy(buf, aidp->ai_model, sizeof (aidp->ai_model)); 1260 buf[sizeof (aidp->ai_model)-1] = '\0'; 1261 for (i = sizeof (aidp->ai_model) - 2; buf[i] == ' '; i--) 1262 buf[i] = '\0'; 1263 1264 ATAPRT(("?\t%s device at targ %d, lun %d lastlun 0x%x\n", 1265 (ATAPIDRV(ata_drvp) ? "ATAPI":"IDE"), 1266 ata_drvp->ad_targ, ata_drvp->ad_lun, aidp->ai_lastlun)); 1267 1268 ATAPRT(("?\tmodel %s\n", buf)); 1269 1270 if (aidp->ai_majorversion != 0 && aidp->ai_majorversion != 0xffff) { 1271 for (i = 14; i >= 2; i--) { 1272 if (aidp->ai_majorversion & (1 << i)) { 1273 valid_version = i; 1274 break; 1275 } 1276 } 1277 ATAPRT(( 1278 "?\tATA/ATAPI-%d supported, majver 0x%x minver 0x%x\n", 1279 valid_version, 1280 aidp->ai_majorversion, 1281 aidp->ai_minorversion)); 1282 } 1283 1284 if (ata_capability_data) { 1285 1286 ATAPRT(("?\t\tstat %x, err %x\n", 1287 ddi_get8(ata_ctlp->ac_iohandle2, 1288 ata_ctlp->ac_altstatus), 1289 ddi_get8(ata_ctlp->ac_iohandle1, ata_ctlp->ac_error))); 1290 1291 ATAPRT(("?\t\tcfg 0x%x, cap 0x%x\n", 1292 aidp->ai_config, 1293 aidp->ai_cap)); 1294 1295 /* 1296 * Be aware that ATA-6 and later drives may not provide valid 1297 * geometry information and other obsoleted info. 1298 * Select what is printed based on supported ATA model (skip 1299 * anything below ATA/ATAPI-3) 1300 */ 1301 1302 if (valid_version == 0 || aidp->ai_majorversion < 1303 ATAC_MAJVER_6) { 1304 /* 1305 * Supported version less then ATA-6 1306 */ 1307 ATAPRT(("?\t\tcyl %d, hd %d, sec/trk %d\n", 1308 aidp->ai_fixcyls, 1309 aidp->ai_heads, 1310 aidp->ai_sectors)); 1311 } 1312 ATAPRT(("?\t\tmult1 0x%x, mult2 0x%x\n", 1313 aidp->ai_mult1, 1314 aidp->ai_mult2)); 1315 if (valid_version && aidp->ai_majorversion < ATAC_MAJVER_4) { 1316 ATAPRT(( 1317 "?\t\tpiomode 0x%x, dmamode 0x%x, advpiomode 0x%x\n", 1318 aidp->ai_piomode, 1319 aidp->ai_dmamode, 1320 aidp->ai_advpiomode)); 1321 } else { 1322 ATAPRT(("?\t\tadvpiomode 0x%x\n", 1323 aidp->ai_advpiomode)); 1324 } 1325 ATAPRT(("?\t\tminpio %d, minpioflow %d\n", 1326 aidp->ai_minpio, 1327 aidp->ai_minpioflow)); 1328 if (valid_version && aidp->ai_majorversion >= ATAC_MAJVER_4 && 1329 (aidp->ai_validinfo & ATAC_VALIDINFO_83)) { 1330 ATAPRT(("?\t\tdwdma 0x%x, ultradma 0x%x\n", 1331 aidp->ai_dworddma, 1332 aidp->ai_ultradma)); 1333 } else { 1334 ATAPRT(("?\t\tdwdma 0x%x\n", 1335 aidp->ai_dworddma)); 1336 } 1337 } 1338 1339 if (ATAPIDRV(ata_drvp)) { 1340 if (!atapi_init_drive(ata_drvp)) 1341 goto errout; 1342 } else { 1343 if (!ata_disk_init_drive(ata_drvp)) 1344 goto errout; 1345 } 1346 1347 /* 1348 * store pointer in controller struct 1349 */ 1350 CTL2DRV(ata_ctlp, targ, lun) = ata_drvp; 1351 1352 /* 1353 * lock the drive's current settings in case I have to 1354 * reset the drive due to some sort of error 1355 */ 1356 (void) ata_set_feature(ata_ctlp, ata_drvp, ATSF_DIS_REVPOD, 0); 1357 1358 return (ata_drvp); 1359 1360 errout: 1361 ata_uninit_drive(ata_drvp); 1362 return (NULL); 1363 } 1364 1365 /* destroy a drive */ 1366 1367 static void 1368 ata_uninit_drive( 1369 ata_drv_t *ata_drvp) 1370 { 1371 #if 0 1372 ata_ctl_t *ata_ctlp = ata_drvp->ad_ctlp; 1373 #endif 1374 1375 ADBG_TRACE(("ata_uninit_drive entered\n")); 1376 1377 #if 0 1378 /* 1379 * DON'T DO THIS. disabling interrupts floats the IRQ line 1380 * which generates spurious interrupts 1381 */ 1382 1383 /* 1384 * Select the correct drive 1385 */ 1386 ddi_put8(ata_ctlp->ac_iohandle1, ata_ctlp->ac_drvhd, 1387 ata_drvp->ad_drive_bits); 1388 ata_nsecwait(400); 1389 1390 /* 1391 * Disable interrupts from the drive 1392 */ 1393 ddi_put8(ata_ctlp->ac_iohandle2, ata_ctlp->ac_devctl, 1394 (ATDC_D3 | ATDC_NIEN)); 1395 #endif 1396 1397 /* interface specific clean-ups */ 1398 1399 if (ata_drvp->ad_flags & AD_ATAPI) 1400 atapi_uninit_drive(ata_drvp); 1401 else if (ata_drvp->ad_flags & AD_DISK) 1402 ata_disk_uninit_drive(ata_drvp); 1403 1404 /* free drive struct */ 1405 1406 kmem_free(ata_drvp, sizeof (ata_drv_t)); 1407 } 1408 1409 1410 /* 1411 * ata_drive_type() 1412 * 1413 * The timeout values and exact sequence of checking is critical 1414 * especially for atapi device detection, and should not be changed lightly. 1415 * 1416 */ 1417 static int 1418 ata_drive_type( 1419 uchar_t drvhd, 1420 ddi_acc_handle_t io_hdl1, 1421 caddr_t ioaddr1, 1422 ddi_acc_handle_t io_hdl2, 1423 caddr_t ioaddr2, 1424 struct ata_id *ata_id_bufp) 1425 { 1426 uchar_t status; 1427 1428 ADBG_TRACE(("ata_drive_type entered\n")); 1429 1430 /* 1431 * select the appropriate drive and LUN 1432 */ 1433 ddi_put8(io_hdl1, (uchar_t *)ioaddr1 + AT_DRVHD, drvhd); 1434 ata_nsecwait(400); 1435 1436 /* 1437 * make certain the drive is selected, and wait for not busy 1438 */ 1439 (void) ata_wait3(io_hdl2, ioaddr2, 0, ATS_BSY, 0x7f, 0, 0x7f, 0, 1440 5 * 1000000); 1441 1442 status = ddi_get8(io_hdl2, (uchar_t *)ioaddr2 + AT_ALTSTATUS); 1443 1444 if (status & ATS_BSY) { 1445 ADBG_TRACE(("ata_drive_type 0x%p 0x%x\n", ioaddr1, status)); 1446 return (ATA_DEV_NONE); 1447 } 1448 1449 if (ata_disk_id(io_hdl1, ioaddr1, io_hdl2, ioaddr2, ata_id_bufp)) 1450 return (ATA_DEV_DISK); 1451 1452 /* 1453 * No disk, check for atapi unit. 1454 */ 1455 if (!atapi_signature(io_hdl1, ioaddr1)) { 1456 #ifndef ATA_DISABLE_ATAPI_1_7 1457 /* 1458 * Check for old (but prevalent) atapi 1.7B 1459 * spec device, the only known example is the 1460 * NEC CDR-260 (not 260R which is (mostly) ATAPI 1.2 1461 * compliant). This device has no signature 1462 * and requires conversion from hex to BCD 1463 * for some scsi audio commands. 1464 */ 1465 if (atapi_id(io_hdl1, ioaddr1, io_hdl2, ioaddr2, ata_id_bufp)) { 1466 return (ATA_DEV_ATAPI); 1467 } 1468 #endif 1469 return (ATA_DEV_NONE); 1470 } 1471 1472 if (atapi_id(io_hdl1, ioaddr1, io_hdl2, ioaddr2, ata_id_bufp)) { 1473 return (ATA_DEV_ATAPI); 1474 } 1475 1476 return (ATA_DEV_NONE); 1477 1478 } 1479 1480 /* 1481 * nsec-granularity time delay function 1482 */ 1483 void 1484 ata_nsecwait(clock_t count) 1485 { 1486 extern int tsc_gethrtime_initted; 1487 1488 if (tsc_gethrtime_initted) { 1489 hrtime_t end = gethrtime() + count; 1490 1491 while (gethrtime() < end) { 1492 SMT_PAUSE(); 1493 } 1494 } else { 1495 drv_usecwait(1 + (count / 1000)); 1496 } 1497 } 1498 1499 1500 /* 1501 * Wait for a register of a controller to achieve a specific state. 1502 * To return normally, all the bits in the first sub-mask must be ON, 1503 * all the bits in the second sub-mask must be OFF. 1504 * If timeout_usec microseconds pass without the controller achieving 1505 * the desired bit configuration, we return TRUE, else FALSE. 1506 */ 1507 1508 int ata_usec_delay = 10; 1509 1510 int 1511 ata_wait( 1512 ddi_acc_handle_t io_hdl, 1513 caddr_t ioaddr, 1514 uchar_t onbits, 1515 uchar_t offbits, 1516 uint_t timeout_usec) 1517 { 1518 ushort_t val; 1519 hrtime_t deadline = gethrtime() + 1520 (hrtime_t)timeout_usec * (NANOSEC / MICROSEC); 1521 1522 1523 do { 1524 val = ddi_get8(io_hdl, (uchar_t *)ioaddr + AT_ALTSTATUS); 1525 if ((val & onbits) == onbits && (val & offbits) == 0) 1526 return (TRUE); 1527 drv_usecwait(ata_usec_delay); 1528 } while (gethrtime() < deadline); 1529 1530 return (FALSE); 1531 } 1532 1533 1534 /* 1535 * 1536 * This is a slightly more complicated version that checks 1537 * for error conditions and bails-out rather than looping 1538 * until the timeout expires 1539 */ 1540 int 1541 ata_wait3( 1542 ddi_acc_handle_t io_hdl, 1543 caddr_t ioaddr, 1544 uchar_t onbits1, 1545 uchar_t offbits1, 1546 uchar_t failure_onbits2, 1547 uchar_t failure_offbits2, 1548 uchar_t failure_onbits3, 1549 uchar_t failure_offbits3, 1550 uint_t timeout_usec) 1551 { 1552 ushort_t val; 1553 hrtime_t deadline = gethrtime() + 1554 (hrtime_t)timeout_usec * (NANOSEC / MICROSEC); 1555 1556 do { 1557 val = ddi_get8(io_hdl, (uchar_t *)ioaddr + AT_ALTSTATUS); 1558 1559 /* 1560 * check for expected condition 1561 */ 1562 if ((val & onbits1) == onbits1 && (val & offbits1) == 0) 1563 return (TRUE); 1564 1565 /* 1566 * check for error conditions 1567 */ 1568 if ((val & failure_onbits2) == failure_onbits2 && 1569 (val & failure_offbits2) == 0) { 1570 return (FALSE); 1571 } 1572 1573 if ((val & failure_onbits3) == failure_onbits3 && 1574 (val & failure_offbits3) == 0) { 1575 return (FALSE); 1576 } 1577 1578 drv_usecwait(ata_usec_delay); 1579 } while (gethrtime() < deadline); 1580 1581 return (FALSE); 1582 } 1583 1584 1585 /* 1586 * 1587 * low level routine for ata_disk_id() and atapi_id() 1588 * 1589 */ 1590 1591 int 1592 ata_id_common( 1593 uchar_t id_cmd, 1594 int expect_drdy, 1595 ddi_acc_handle_t io_hdl1, 1596 caddr_t ioaddr1, 1597 ddi_acc_handle_t io_hdl2, 1598 caddr_t ioaddr2, 1599 struct ata_id *aidp) 1600 { 1601 uchar_t status; 1602 1603 ADBG_TRACE(("ata_id_common entered\n")); 1604 1605 bzero(aidp, sizeof (struct ata_id)); 1606 1607 /* 1608 * clear the features register 1609 */ 1610 ddi_put8(io_hdl1, (uchar_t *)ioaddr1 + AT_FEATURE, 0); 1611 1612 /* 1613 * Disable interrupts from the device. When the ata 1614 * hardware is sharing its interrupt with another 1615 * device, the shared interrupt might have already been 1616 * unmasked in the interrupt controller and 1617 * triggering ata device interrupts will result in an 1618 * interrupt storm and a hung system. 1619 */ 1620 ddi_put8(io_hdl2, (uchar_t *)ioaddr2 + AT_DEVCTL, ATDC_D3 | ATDC_NIEN); 1621 1622 /* 1623 * issue IDENTIFY DEVICE or IDENTIFY PACKET DEVICE command 1624 */ 1625 ddi_put8(io_hdl1, (uchar_t *)ioaddr1 + AT_CMD, id_cmd); 1626 1627 /* wait for the busy bit to settle */ 1628 ata_nsecwait(400); 1629 1630 /* 1631 * read alternate status and check for conditions which 1632 * may indicate the drive is not present, to prevent getting 1633 * stuck in ata_wait3() below. 1634 */ 1635 status = ddi_get8(io_hdl2, (uchar_t *)ioaddr2 + AT_ALTSTATUS); 1636 1637 /* 1638 * 0x0, 0x7f, or ATS_DF can happen when no drive is present 1639 */ 1640 if ((status == 0x0) || (status == 0x7f) || 1641 ((status & (ATS_BSY|ATS_DF)) == ATS_DF)) { 1642 /* invalid status, can't be an ATA or ATAPI device */ 1643 return (FALSE); 1644 } 1645 1646 /* 1647 * According to the ATA specification, some drives may have 1648 * to read the media to complete this command. We need to 1649 * make sure we give them enough time to respond. 1650 */ 1651 (void) ata_wait3(io_hdl2, ioaddr2, 0, ATS_BSY, 1652 ATS_ERR, ATS_BSY, 0x7f, 0, 5 * 1000000); 1653 1654 /* 1655 * read the status byte and clear the pending interrupt 1656 */ 1657 status = ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_STATUS); 1658 1659 /* 1660 * this happens if there's no drive present 1661 */ 1662 if (status == 0xff || status == 0x7f) { 1663 /* invalid status, can't be an ATA or ATAPI device */ 1664 return (FALSE); 1665 } 1666 1667 if (status & ATS_BSY) { 1668 ADBG_ERROR(("ata_id_common: BUSY status 0x%x error 0x%x\n", 1669 ddi_get8(io_hdl2, (uchar_t *)ioaddr2 +AT_ALTSTATUS), 1670 ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_ERROR))); 1671 return (FALSE); 1672 } 1673 1674 if (!(status & ATS_DRQ)) { 1675 if (status & (ATS_ERR | ATS_DF)) { 1676 return (FALSE); 1677 } 1678 /* 1679 * Give the drive another second to assert DRQ. Some older 1680 * drives de-assert BSY before asserting DRQ. 1681 */ 1682 if (!ata_wait(io_hdl2, ioaddr2, ATS_DRQ, ATS_BSY, 1000000)) { 1683 ADBG_WARN(("ata_id_common: !DRQ status 0x%x error 0x%x\n", 1684 ddi_get8(io_hdl2, (uchar_t *)ioaddr2 +AT_ALTSTATUS), 1685 ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_ERROR))); 1686 return (FALSE); 1687 } 1688 } 1689 1690 /* 1691 * transfer the data 1692 */ 1693 ddi_rep_get16(io_hdl1, (ushort_t *)aidp, (ushort_t *)ioaddr1 + AT_DATA, 1694 NBPSCTR >> 1, DDI_DEV_NO_AUTOINCR); 1695 1696 /* wait for the busy bit to settle */ 1697 ata_nsecwait(400); 1698 1699 1700 /* 1701 * Wait for the drive to recognize I've read all the data. 1702 * Some drives have been observed to take as much as 3msec to 1703 * deassert DRQ after reading the data; allow 10 msec just in case. 1704 * 1705 * Note: some non-compliant ATAPI drives (e.g., NEC Multispin 6V, 1706 * CDR-1350A) don't assert DRDY. If we've made it this far we can 1707 * safely ignore the DRDY bit since the ATAPI Packet command 1708 * actually doesn't require it to ever be asserted. 1709 * 1710 */ 1711 if (!ata_wait(io_hdl2, ioaddr2, (uchar_t)(expect_drdy ? ATS_DRDY : 0), 1712 (ATS_BSY | ATS_DRQ), 1000000)) { 1713 ADBG_WARN(("ata_id_common: bad status 0x%x error 0x%x\n", 1714 ddi_get8(io_hdl2, (uchar_t *)ioaddr2 + AT_ALTSTATUS), 1715 ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_ERROR))); 1716 return (FALSE); 1717 } 1718 1719 /* 1720 * Check to see if the command aborted. This happens if 1721 * an IDENTIFY DEVICE command is issued to an ATAPI PACKET device, 1722 * or if an IDENTIFY PACKET DEVICE command is issued to an ATA 1723 * (non-PACKET) device. 1724 */ 1725 if (status & (ATS_DF | ATS_ERR)) { 1726 ADBG_WARN(("ata_id_common: status 0x%x error 0x%x \n", 1727 ddi_get8(io_hdl2, (uchar_t *)ioaddr2 + AT_ALTSTATUS), 1728 ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_ERROR))); 1729 return (FALSE); 1730 } 1731 return (TRUE); 1732 } 1733 1734 1735 /* 1736 * Low level routine to issue a non-data command and busy wait for 1737 * the completion status. 1738 */ 1739 1740 int 1741 ata_command( 1742 ata_ctl_t *ata_ctlp, 1743 ata_drv_t *ata_drvp, 1744 int expect_drdy, 1745 int silent, 1746 uint_t busy_wait, 1747 uchar_t cmd, 1748 uchar_t feature, 1749 uchar_t count, 1750 uchar_t sector, 1751 uchar_t head, 1752 uchar_t cyl_low, 1753 uchar_t cyl_hi) 1754 { 1755 ddi_acc_handle_t io_hdl1 = ata_ctlp->ac_iohandle1; 1756 ddi_acc_handle_t io_hdl2 = ata_ctlp->ac_iohandle2; 1757 uchar_t status; 1758 1759 /* select the drive */ 1760 ddi_put8(io_hdl1, ata_ctlp->ac_drvhd, ata_drvp->ad_drive_bits); 1761 ata_nsecwait(400); 1762 1763 /* make certain the drive selected */ 1764 if (!ata_wait(io_hdl2, ata_ctlp->ac_ioaddr2, 1765 (uchar_t)(expect_drdy ? ATS_DRDY : 0), 1766 ATS_BSY, busy_wait)) { 1767 ADBG_ERROR(("ata_command: select failed " 1768 "DRDY 0x%x CMD 0x%x F 0x%x N 0x%x " 1769 "S 0x%x H 0x%x CL 0x%x CH 0x%x\n", 1770 expect_drdy, cmd, feature, count, 1771 sector, head, cyl_low, cyl_hi)); 1772 return (FALSE); 1773 } 1774 1775 /* 1776 * set all the regs 1777 */ 1778 ddi_put8(io_hdl1, ata_ctlp->ac_drvhd, (head | ata_drvp->ad_drive_bits)); 1779 ddi_put8(io_hdl1, ata_ctlp->ac_sect, sector); 1780 ddi_put8(io_hdl1, ata_ctlp->ac_count, count); 1781 ddi_put8(io_hdl1, ata_ctlp->ac_lcyl, cyl_low); 1782 ddi_put8(io_hdl1, ata_ctlp->ac_hcyl, cyl_hi); 1783 ddi_put8(io_hdl1, ata_ctlp->ac_feature, feature); 1784 1785 /* send the command */ 1786 ddi_put8(io_hdl1, ata_ctlp->ac_cmd, cmd); 1787 1788 /* wait for the busy bit to settle */ 1789 ata_nsecwait(400); 1790 1791 /* wait for not busy */ 1792 if (!ata_wait(io_hdl2, ata_ctlp->ac_ioaddr2, 0, ATS_BSY, busy_wait)) { 1793 ADBG_ERROR(("ata_command: BSY too long!" 1794 "DRDY 0x%x CMD 0x%x F 0x%x N 0x%x " 1795 "S 0x%x H 0x%x CL 0x%x CH 0x%x\n", 1796 expect_drdy, cmd, feature, count, 1797 sector, head, cyl_low, cyl_hi)); 1798 return (FALSE); 1799 } 1800 1801 /* 1802 * wait for DRDY before continuing 1803 */ 1804 (void) ata_wait3(io_hdl2, ata_ctlp->ac_ioaddr2, 1805 ATS_DRDY, ATS_BSY, /* okay */ 1806 ATS_ERR, ATS_BSY, /* cmd failed */ 1807 ATS_DF, ATS_BSY, /* drive failed */ 1808 busy_wait); 1809 1810 /* read status to clear IRQ, and check for error */ 1811 status = ddi_get8(io_hdl1, ata_ctlp->ac_status); 1812 1813 if ((status & (ATS_BSY | ATS_DF | ATS_ERR)) == 0) 1814 return (TRUE); 1815 1816 if (!silent) { 1817 ADBG_ERROR(("ata_command status 0x%x error 0x%x " 1818 "DRDY 0x%x CMD 0x%x F 0x%x N 0x%x " 1819 "S 0x%x H 0x%x CL 0x%x CH 0x%x\n", 1820 ddi_get8(io_hdl1, ata_ctlp->ac_status), 1821 ddi_get8(io_hdl1, ata_ctlp->ac_error), 1822 expect_drdy, cmd, feature, count, 1823 sector, head, cyl_low, cyl_hi)); 1824 } 1825 return (FALSE); 1826 } 1827 1828 1829 1830 /* 1831 * 1832 * Issue a SET FEATURES command 1833 * 1834 */ 1835 1836 int 1837 ata_set_feature( 1838 ata_ctl_t *ata_ctlp, 1839 ata_drv_t *ata_drvp, 1840 uchar_t feature, 1841 uchar_t value) 1842 { 1843 int rc; 1844 1845 rc = ata_command(ata_ctlp, ata_drvp, TRUE, TRUE, ata_set_feature_wait, 1846 ATC_SET_FEAT, feature, value, 0, 0, 0, 0); 1847 /* feature, count, sector, head, cyl_low, cyl_hi */ 1848 1849 if (rc) { 1850 return (TRUE); 1851 } 1852 1853 ADBG_ERROR(("?ata_set_feature: (0x%x,0x%x) failed\n", feature, value)); 1854 return (FALSE); 1855 } 1856 1857 1858 1859 /* 1860 * 1861 * Issue a FLUSH CACHE command 1862 * 1863 */ 1864 1865 static int 1866 ata_flush_cache( 1867 ata_ctl_t *ata_ctlp, 1868 ata_drv_t *ata_drvp) 1869 { 1870 /* this command is optional so fail silently */ 1871 return (ata_command(ata_ctlp, ata_drvp, TRUE, TRUE, 1872 ata_flush_cache_wait, 1873 ATC_FLUSH_CACHE, 0, 0, 0, 0, 0, 0)); 1874 } 1875 1876 /* 1877 * ata_setup_ioaddr() 1878 * 1879 * Map the device registers and return the handles. 1880 * 1881 * If this is a ISA-ATA controller then only two handles are 1882 * initialized and returned. 1883 * 1884 * If this is a PCI-IDE controller than a third handle (for the 1885 * PCI-IDE Bus Mastering registers) is initialized and returned. 1886 * 1887 */ 1888 1889 static int 1890 ata_setup_ioaddr( 1891 dev_info_t *dip, 1892 ddi_acc_handle_t *handle1p, 1893 caddr_t *addr1p, 1894 ddi_acc_handle_t *handle2p, 1895 caddr_t *addr2p, 1896 ddi_acc_handle_t *bm_hdlp, 1897 caddr_t *bm_addrp) 1898 { 1899 ddi_device_acc_attr_t dev_attr; 1900 int rnumber; 1901 int rc; 1902 off_t regsize; 1903 1904 /* 1905 * Make certain the controller is enabled and its regs are map-able 1906 * 1907 */ 1908 rc = ddi_dev_regsize(dip, 0, ®size); 1909 if (rc != DDI_SUCCESS || regsize <= AT_CMD) { 1910 ADBG_INIT(("ata_setup_ioaddr(1): rc %d regsize %lld\n", 1911 rc, (long long)regsize)); 1912 return (FALSE); 1913 } 1914 1915 rc = ddi_dev_regsize(dip, 1, ®size); 1916 if (rc != DDI_SUCCESS || regsize <= AT_ALTSTATUS) { 1917 ADBG_INIT(("ata_setup_ioaddr(2): rc %d regsize %lld\n", 1918 rc, (long long)regsize)); 1919 return (FALSE); 1920 } 1921 1922 /* 1923 * setup the device attribute structure for little-endian, 1924 * strict ordering access. 1925 */ 1926 dev_attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 1927 dev_attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 1928 dev_attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 1929 1930 *handle1p = NULL; 1931 *handle2p = NULL; 1932 *bm_hdlp = NULL; 1933 1934 /* 1935 * Determine whether this is a ISA, PNP-ISA, or PCI-IDE device 1936 */ 1937 if (ddi_prop_exists(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, "pnp-csn")) { 1938 /* it's PNP-ISA, skip over the extra reg tuple */ 1939 rnumber = 1; 1940 goto not_pciide; 1941 } 1942 1943 /* else, it's ISA or PCI-IDE, check further */ 1944 rnumber = 0; 1945 1946 if (!ata_is_pci(dip)) { 1947 /* 1948 * If it's not a PCI-IDE, there are only two reg tuples 1949 * and the first one contains the I/O base (170 or 1f0) 1950 * rather than the controller instance number. 1951 */ 1952 ADBG_TRACE(("ata_setup_ioaddr !pci-ide\n")); 1953 goto not_pciide; 1954 } 1955 1956 1957 /* 1958 * Map the correct half of the PCI-IDE Bus Master registers. 1959 * There's a single BAR that maps these registers for both 1960 * controller's in a dual-controller chip and it's upto my 1961 * parent nexus, pciide, to adjust which (based on my instance 1962 * number) half this call maps. 1963 */ 1964 rc = ddi_dev_regsize(dip, 2, ®size); 1965 if (rc != DDI_SUCCESS || regsize < 8) { 1966 ADBG_INIT(("ata_setup_ioaddr(3): rc %d regsize %lld\n", 1967 rc, (long long)regsize)); 1968 goto not_pciide; 1969 } 1970 1971 rc = ddi_regs_map_setup(dip, 2, bm_addrp, 0, 0, &dev_attr, bm_hdlp); 1972 1973 if (rc != DDI_SUCCESS) { 1974 /* map failed, try to use in non-pci-ide mode */ 1975 ADBG_WARN(("ata_setup_ioaddr bus master map failed, rc=0x%x\n", 1976 rc)); 1977 *bm_hdlp = NULL; 1978 } 1979 1980 not_pciide: 1981 /* 1982 * map the lower command block registers 1983 */ 1984 1985 rc = ddi_regs_map_setup(dip, rnumber, addr1p, 0, 0, &dev_attr, 1986 handle1p); 1987 1988 if (rc != DDI_SUCCESS) { 1989 cmn_err(CE_WARN, "ata: reg tuple 0 map failed, rc=0x%x\n", rc); 1990 goto out1; 1991 } 1992 1993 /* 1994 * If the controller is being used in compatibility mode 1995 * via /devices/isa/ata@1,{1f0,1f0}/..., the reg property 1996 * will specify zeros for the I/O ports for the PCI 1997 * instance. 1998 */ 1999 if (*addr1p == 0) { 2000 ADBG_TRACE(("ata_setup_ioaddr ioaddr1 0\n")); 2001 goto out2; 2002 } 2003 2004 /* 2005 * map the upper control block registers 2006 */ 2007 rc = ddi_regs_map_setup(dip, rnumber + 1, addr2p, 0, 0, &dev_attr, 2008 handle2p); 2009 if (rc == DDI_SUCCESS) 2010 return (TRUE); 2011 2012 cmn_err(CE_WARN, "ata: reg tuple 1 map failed, rc=0x%x", rc); 2013 2014 out2: 2015 if (*handle1p != NULL) { 2016 ddi_regs_map_free(handle1p); 2017 *handle1p = NULL; 2018 } 2019 2020 out1: 2021 if (*bm_hdlp != NULL) { 2022 ddi_regs_map_free(bm_hdlp); 2023 *bm_hdlp = NULL; 2024 } 2025 return (FALSE); 2026 2027 } 2028 2029 /* 2030 * 2031 * Currently, the only supported controllers are ones which 2032 * support the SFF-8038 Bus Mastering spec. 2033 * 2034 * Check the parent node's IEEE 1275 class-code property to 2035 * determine if it's an PCI-IDE instance which supports SFF-8038 2036 * Bus Mastering. It's perfectly valid to have a PCI-IDE controller 2037 * that doesn't do Bus Mastering. In that case, my interrupt handler 2038 * only uses the interrupt latch bit in PCI-IDE status register. 2039 * The assumption is that the programming interface byte of the 2040 * class-code property reflects the bus master DMA capability of 2041 * the controller. 2042 * 2043 * Whether the drive support supports the DMA option still needs 2044 * to be checked later. Each individual request also has to be 2045 * checked for alignment and size to decide whether to use the 2046 * DMA transfer mode. 2047 */ 2048 2049 static void 2050 ata_init_pciide( 2051 dev_info_t *dip, 2052 ata_ctl_t *ata_ctlp) 2053 { 2054 uint_t class_code; 2055 uchar_t status; 2056 2057 ata_cntrl_DMA_sel_msg = NULL; 2058 2059 if (ata_ctlp->ac_bmhandle == NULL) { 2060 ata_ctlp->ac_pciide = FALSE; 2061 ata_ctlp->ac_pciide_bm = FALSE; 2062 ata_cntrl_DMA_sel_msg = "cntrl not Bus Master DMA capable"; 2063 return; 2064 } 2065 2066 /* 2067 * check if it's a known bogus PCI-IDE chip 2068 */ 2069 if (ata_check_pciide_blacklist(dip, ATA_BL_BOGUS)) { 2070 ADBG_WARN(("ata_setup_ioaddr pci-ide blacklist\n")); 2071 ata_ctlp->ac_pciide = FALSE; 2072 ata_ctlp->ac_pciide_bm = FALSE; 2073 ata_cntrl_DMA_sel_msg = "cntrl blacklisted"; 2074 return; 2075 } 2076 ata_ctlp->ac_pciide = TRUE; 2077 2078 if (ata_check_pciide_blacklist(dip, ATA_BL_BMSTATREG_PIO_BROKEN)) { 2079 ata_ctlp->ac_flags |= AC_BMSTATREG_PIO_BROKEN; 2080 } 2081 2082 /* 2083 * check for a PCI-IDE chip with a broken DMA engine 2084 */ 2085 if (ata_check_pciide_blacklist(dip, ATA_BL_NODMA)) { 2086 ata_ctlp->ac_pciide_bm = FALSE; 2087 ata_cntrl_DMA_sel_msg = 2088 "cntrl blacklisted/DMA engine broken"; 2089 return; 2090 } 2091 2092 /* 2093 * Check the Programming Interface register to determine 2094 * if this device supports PCI-IDE Bus Mastering. Some PCI-IDE 2095 * devices don't support Bus Mastering or DMA. 2096 * Since we are dealing with pre-qualified pci-ide controller, 2097 * check programming interface byte only. 2098 */ 2099 2100 class_code = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip), 2101 DDI_PROP_DONTPASS, "class-code", 0); 2102 if ((class_code & PCIIDE_BM_CAP_MASK) != PCIIDE_BM_CAP_MASK) { 2103 ata_ctlp->ac_pciide_bm = FALSE; 2104 ata_cntrl_DMA_sel_msg = 2105 "cntrl not Bus Master DMA capable"; 2106 return; 2107 } 2108 2109 /* 2110 * Avoid doing DMA on "simplex" chips which share hardware 2111 * between channels 2112 */ 2113 status = ddi_get8(ata_ctlp->ac_bmhandle, 2114 (uchar_t *)ata_ctlp->ac_bmaddr + PCIIDE_BMISX_REG); 2115 /* 2116 * Some motherboards have CSB5's that are wired "to emulate CSB4 mode". 2117 * In such a mode, the simplex bit is asserted, but in fact testing 2118 * on such a motherboard has shown that the devices are not simplex 2119 * -- DMA can be used on both channels concurrently with no special 2120 * considerations. For chips like this, we have the ATA_BL_NO_SIMPLEX 2121 * flag set to indicate that the value of the simplex bit can be 2122 * ignored. 2123 */ 2124 2125 if (status & PCIIDE_BMISX_SIMPLEX) { 2126 if (ata_check_pciide_blacklist(dip, ATA_BL_NO_SIMPLEX)) { 2127 cmn_err(CE_WARN, "Ignoring false simplex bit \n"); 2128 2129 } else { 2130 2131 int simplex_dma_channel, *rp, proplen, channel; 2132 int dma_on = FALSE; 2133 2134 /* 2135 * By default,use DMA on channel 0 and PIO on channel 2136 * 1. This can be switched by setting 2137 * ata-simplex-dma-channel to: 2138 * 0 DMA on channel 0 (default without this 2139 * property) 2140 * 1 DMA on channel 1 2141 * any other value: DMA off on both channels. 2142 */ 2143 simplex_dma_channel = ata_prop_lookup_int(DDI_DEV_T_ANY, 2144 ata_ctlp->ac_dip, 0, "ata-simplex-dma-channel", 0); 2145 2146 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, 2147 ata_ctlp->ac_dip, DDI_PROP_DONTPASS, "reg", &rp, 2148 (uint_t *)&proplen) == DDI_PROP_SUCCESS) { 2149 2150 channel = *rp; 2151 ddi_prop_free(rp); 2152 2153 if (simplex_dma_channel == channel) { 2154 cmn_err(CE_CONT, "?ata: simplex " 2155 "controller. DMA on channel" 2156 " %d PIO on channel %d", 2157 channel, channel ? 0:1); 2158 dma_on = TRUE; 2159 } else { 2160 ata_cntrl_DMA_sel_msg = 2161 "simplex controller"; 2162 } 2163 } 2164 2165 if (dma_on == FALSE) { 2166 ata_ctlp->ac_pciide_bm = FALSE; 2167 2168 return; 2169 } 2170 } 2171 } 2172 2173 /* 2174 * It's a compatible PCI-IDE Bus Mastering controller, 2175 * allocate and map the DMA Scatter/Gather list (PRDE table). 2176 */ 2177 if (ata_pciide_alloc(dip, ata_ctlp)) 2178 ata_ctlp->ac_pciide_bm = TRUE; 2179 else { 2180 ata_ctlp->ac_pciide_bm = FALSE; 2181 ata_cntrl_DMA_sel_msg = "unable to init DMA S/G list"; 2182 } 2183 } 2184 2185 /* 2186 * 2187 * Determine whether to enable DMA support for this drive. 2188 * The controller and the drive both have to support DMA. 2189 * The controller's capabilities were already checked in 2190 * ata_init_pciide(), now just check the drive's capabilities. 2191 * 2192 */ 2193 2194 static int 2195 ata_init_drive_pcidma( 2196 ata_ctl_t *ata_ctlp, 2197 ata_drv_t *ata_drvp, 2198 dev_info_t *tdip) 2199 { 2200 boolean_t dma; 2201 boolean_t cd_dma; 2202 boolean_t disk_dma; 2203 boolean_t atapi_dma; 2204 int ata_options; 2205 2206 ata_dev_DMA_sel_msg = NULL; 2207 2208 if (ata_ctlp->ac_pciide_bm != TRUE) { 2209 ata_dev_DMA_sel_msg = 2210 "controller is not Bus Master capable"; 2211 2212 return (ATA_DMA_OFF); 2213 } 2214 2215 ata_options = ddi_prop_get_int(DDI_DEV_T_ANY, ata_ctlp->ac_dip, 2216 0, "ata-options", 0); 2217 2218 if (!(ata_options & ATA_OPTIONS_DMA)) { 2219 /* 2220 * Either the ata-options property was not found or 2221 * DMA is not enabled by this property 2222 */ 2223 ata_dev_DMA_sel_msg = 2224 "disabled by \"ata-options\" property"; 2225 2226 return (ATA_DMA_OFF); 2227 } 2228 2229 if (ata_check_drive_blacklist(&ata_drvp->ad_id, ATA_BL_NODMA)) { 2230 ata_dev_DMA_sel_msg = "device not DMA capable; blacklisted"; 2231 2232 return (ATA_DMA_OFF); 2233 } 2234 2235 /* 2236 * DMA mode is mandatory on ATA-3 (or newer) drives but is 2237 * optional on ATA-2 (or older) drives. 2238 * 2239 * On ATA-2 drives the ai_majorversion word will probably 2240 * be 0xffff or 0x0000, check the (now obsolete) DMA bit in 2241 * the capabilities word instead. The order of these tests 2242 * is important since an ATA-3 drive doesn't have to set 2243 * the DMA bit in the capabilities word. 2244 * 2245 */ 2246 2247 if (!((ata_drvp->ad_id.ai_majorversion & 0x8000) == 0 && 2248 ata_drvp->ad_id.ai_majorversion >= (1 << 2)) && 2249 !(ata_drvp->ad_id.ai_cap & ATAC_DMA_SUPPORT)) { 2250 ata_dev_DMA_sel_msg = "device not DMA capable"; 2251 2252 return (ATA_DMA_OFF); 2253 } 2254 2255 /* 2256 * Disable DMA for ATAPI devices on controllers known to 2257 * have trouble with ATAPI DMA 2258 */ 2259 2260 if (ATAPIDRV(ata_drvp)) { 2261 if (ata_check_pciide_blacklist(ata_ctlp->ac_dip, 2262 ATA_BL_ATAPI_NODMA)) { 2263 ata_dev_DMA_sel_msg = 2264 "controller incapable of DMA for ATAPI device"; 2265 2266 return (ATA_DMA_OFF); 2267 } 2268 } 2269 dma = ata_prop_lookup_int(DDI_DEV_T_ANY, tdip, 2270 0, "ata-dma-enabled", TRUE); 2271 disk_dma = ata_prop_lookup_int(DDI_DEV_T_ANY, tdip, 2272 0, "ata-disk-dma-enabled", TRUE); 2273 cd_dma = ata_prop_lookup_int(DDI_DEV_T_ANY, tdip, 2274 0, "atapi-cd-dma-enabled", FALSE); 2275 atapi_dma = ata_prop_lookup_int(DDI_DEV_T_ANY, tdip, 2276 0, "atapi-other-dma-enabled", TRUE); 2277 2278 if (dma == FALSE) { 2279 cmn_err(CE_CONT, "?ata_init_drive_pcidma: " 2280 "DMA disabled by \"ata-dma-enabled\" property"); 2281 ata_dev_DMA_sel_msg = "disabled by prop ata-dma-enabled"; 2282 2283 return (ATA_DMA_OFF); 2284 } 2285 2286 if (IS_CDROM(ata_drvp) == TRUE) { 2287 if (cd_dma == FALSE) { 2288 ata_dev_DMA_sel_msg = 2289 "disabled. Control with \"atapi-cd-dma-enabled\"" 2290 " property"; 2291 2292 return (ATA_DMA_OFF); 2293 } 2294 2295 } else if (ATAPIDRV(ata_drvp) == FALSE) { 2296 if (disk_dma == FALSE) { 2297 ata_dev_DMA_sel_msg = 2298 "disabled by \"ata-disk-dma-enabled\" property"; 2299 2300 return (ATA_DMA_OFF); 2301 } 2302 2303 } else if (atapi_dma == FALSE) { 2304 ata_dev_DMA_sel_msg = 2305 "disabled by \"atapi-other-dma-enabled\" property"; 2306 2307 return (ATA_DMA_OFF); 2308 } 2309 2310 return (ATA_DMA_ON); 2311 } 2312 2313 2314 2315 /* 2316 * this compare routine squeezes out extra blanks and 2317 * returns TRUE if p1 matches the leftmost substring of p2 2318 */ 2319 2320 static int 2321 ata_strncmp( 2322 char *p1, 2323 char *p2, 2324 int cnt) 2325 { 2326 2327 for (;;) { 2328 /* 2329 * skip over any extra blanks in both strings 2330 */ 2331 while (*p1 != '\0' && *p1 == ' ') 2332 p1++; 2333 2334 while (cnt != 0 && *p2 == ' ') { 2335 p2++; 2336 cnt--; 2337 } 2338 2339 /* 2340 * compare the two strings 2341 */ 2342 2343 if (cnt == 0 || *p1 != *p2) 2344 break; 2345 2346 while (cnt > 0 && *p1 == *p2) { 2347 p1++; 2348 p2++; 2349 cnt--; 2350 } 2351 2352 } 2353 2354 /* return TRUE if both strings ended at same point */ 2355 return ((*p1 == '\0') ? TRUE : FALSE); 2356 } 2357 2358 /* 2359 * Per PSARC/1997/281 create variant="atapi" property (if necessary) 2360 * on the target's dev_info node. Currently, the sd target driver 2361 * is the only driver which refers to this property. 2362 * 2363 * If the flag ata_id_debug is set also create the 2364 * the "ata" or "atapi" property on the target's dev_info node 2365 * 2366 */ 2367 2368 int 2369 ata_prop_create( 2370 dev_info_t *tgt_dip, 2371 ata_drv_t *ata_drvp, 2372 char *name) 2373 { 2374 int rc; 2375 2376 ADBG_TRACE(("ata_prop_create 0x%p 0x%p %s\n", tgt_dip, ata_drvp, name)); 2377 2378 if (strcmp("atapi", name) == 0) { 2379 rc = ndi_prop_update_string(DDI_DEV_T_NONE, tgt_dip, 2380 "variant", name); 2381 if (rc != DDI_PROP_SUCCESS) 2382 return (FALSE); 2383 } 2384 2385 if (!ata_id_debug) 2386 return (TRUE); 2387 2388 rc = ndi_prop_update_byte_array(DDI_DEV_T_NONE, tgt_dip, name, 2389 (uchar_t *)&ata_drvp->ad_id, sizeof (ata_drvp->ad_id)); 2390 if (rc != DDI_PROP_SUCCESS) { 2391 ADBG_ERROR(("ata_prop_create failed, rc=%d\n", rc)); 2392 } 2393 return (TRUE); 2394 } 2395 2396 2397 /* *********************************************************************** */ 2398 /* *********************************************************************** */ 2399 /* *********************************************************************** */ 2400 2401 /* 2402 * This state machine doesn't implement the ATAPI Optional Overlap 2403 * feature. You need that feature to efficiently support ATAPI 2404 * tape drives. See the 1394-ATA Tailgate spec (D97107), Figure 24, 2405 * for an example of how to add the necessary additional NextActions 2406 * and NextStates to this FSM and the atapi_fsm, in order to support 2407 * the Overlap Feature. 2408 */ 2409 2410 2411 uchar_t ata_ctlr_fsm_NextAction[ATA_CTLR_NSTATES][ATA_CTLR_NFUNCS] = { 2412 /* --------------------- next action --------------------- | - current - */ 2413 /* start0 --- start1 ---- intr ------ fini --- reset --- */ 2414 { AC_START, AC_START, AC_NADA, AC_NADA, AC_RESET_I }, /* idle */ 2415 { AC_BUSY, AC_BUSY, AC_INTR, AC_FINI, AC_RESET_A }, /* active0 */ 2416 { AC_BUSY, AC_BUSY, AC_INTR, AC_FINI, AC_RESET_A }, /* active1 */ 2417 }; 2418 2419 uchar_t ata_ctlr_fsm_NextState[ATA_CTLR_NSTATES][ATA_CTLR_NFUNCS] = { 2420 2421 /* --------------------- next state --------------------- | - current - */ 2422 /* start0 --- start1 ---- intr ------ fini --- reset --- */ 2423 { AS_ACTIVE0, AS_ACTIVE1, AS_IDLE, AS_IDLE, AS_IDLE }, /* idle */ 2424 { AS_ACTIVE0, AS_ACTIVE0, AS_ACTIVE0, AS_IDLE, AS_ACTIVE0 }, /* active0 */ 2425 { AS_ACTIVE1, AS_ACTIVE1, AS_ACTIVE1, AS_IDLE, AS_ACTIVE1 }, /* active1 */ 2426 }; 2427 2428 2429 static int 2430 ata_ctlr_fsm( 2431 uchar_t fsm_func, 2432 ata_ctl_t *ata_ctlp, 2433 ata_drv_t *ata_drvp, 2434 ata_pkt_t *ata_pktp, 2435 int *DoneFlgp) 2436 { 2437 uchar_t action; 2438 uchar_t current_state; 2439 uchar_t next_state; 2440 int rc; 2441 2442 current_state = ata_ctlp->ac_state; 2443 action = ata_ctlr_fsm_NextAction[current_state][fsm_func]; 2444 next_state = ata_ctlr_fsm_NextState[current_state][fsm_func]; 2445 2446 /* 2447 * Set the controller's new state 2448 */ 2449 ata_ctlp->ac_state = next_state; 2450 switch (action) { 2451 2452 case AC_BUSY: 2453 return (ATA_FSM_RC_BUSY); 2454 2455 case AC_NADA: 2456 return (ATA_FSM_RC_OKAY); 2457 2458 case AC_START: 2459 ASSERT(ata_ctlp->ac_active_pktp == NULL); 2460 ASSERT(ata_ctlp->ac_active_drvp == NULL); 2461 2462 ata_ctlp->ac_active_pktp = ata_pktp; 2463 ata_ctlp->ac_active_drvp = ata_drvp; 2464 2465 rc = (*ata_pktp->ap_start)(ata_ctlp, ata_drvp, ata_pktp); 2466 2467 if (rc == ATA_FSM_RC_BUSY) { 2468 /* the request didn't start, GHD will requeue it */ 2469 ata_ctlp->ac_state = AS_IDLE; 2470 ata_ctlp->ac_active_pktp = NULL; 2471 ata_ctlp->ac_active_drvp = NULL; 2472 } 2473 return (rc); 2474 2475 case AC_INTR: 2476 ASSERT(ata_ctlp->ac_active_pktp != NULL); 2477 ASSERT(ata_ctlp->ac_active_drvp != NULL); 2478 2479 ata_drvp = ata_ctlp->ac_active_drvp; 2480 ata_pktp = ata_ctlp->ac_active_pktp; 2481 return ((*ata_pktp->ap_intr)(ata_ctlp, ata_drvp, ata_pktp)); 2482 2483 case AC_RESET_A: /* Reset, controller active */ 2484 ASSERT(ata_ctlp->ac_active_pktp != NULL); 2485 ASSERT(ata_ctlp->ac_active_drvp != NULL); 2486 2487 /* clean up the active request */ 2488 ata_pktp = ata_ctlp->ac_active_pktp; 2489 ata_pktp->ap_flags |= AP_DEV_RESET | AP_BUS_RESET; 2490 2491 /* halt the DMA engine */ 2492 if (ata_pktp->ap_pciide_dma) { 2493 ata_pciide_dma_stop(ata_ctlp); 2494 (void) ata_pciide_status_clear(ata_ctlp); 2495 } 2496 2497 /* Do a Software Reset to unwedge the bus */ 2498 if (!ata_software_reset(ata_ctlp)) { 2499 return (ATA_FSM_RC_BUSY); 2500 } 2501 2502 /* Then send a DEVICE RESET cmd to each ATAPI device */ 2503 atapi_fsm_reset(ata_ctlp); 2504 return (ATA_FSM_RC_FINI); 2505 2506 case AC_RESET_I: /* Reset, controller idle */ 2507 /* Do a Software Reset to unwedge the bus */ 2508 if (!ata_software_reset(ata_ctlp)) { 2509 return (ATA_FSM_RC_BUSY); 2510 } 2511 2512 /* Then send a DEVICE RESET cmd to each ATAPI device */ 2513 atapi_fsm_reset(ata_ctlp); 2514 return (ATA_FSM_RC_OKAY); 2515 2516 case AC_FINI: 2517 break; 2518 } 2519 2520 /* 2521 * AC_FINI, check ARQ needs to be started or finished 2522 */ 2523 2524 ASSERT(action == AC_FINI); 2525 ASSERT(ata_ctlp->ac_active_pktp != NULL); 2526 ASSERT(ata_ctlp->ac_active_drvp != NULL); 2527 2528 /* 2529 * The active request is done now. 2530 * Disconnect the request from the controller and 2531 * add it to the done queue. 2532 */ 2533 ata_drvp = ata_ctlp->ac_active_drvp; 2534 ata_pktp = ata_ctlp->ac_active_pktp; 2535 2536 /* 2537 * If ARQ pkt is done, get ptr to original pkt and wrap it up. 2538 */ 2539 if (ata_pktp == ata_ctlp->ac_arq_pktp) { 2540 ata_pkt_t *arq_pktp; 2541 2542 ADBG_ARQ(("ata_ctlr_fsm 0x%p ARQ done\n", ata_ctlp)); 2543 2544 arq_pktp = ata_pktp; 2545 ata_pktp = ata_ctlp->ac_fault_pktp; 2546 ata_ctlp->ac_fault_pktp = NULL; 2547 if (arq_pktp->ap_flags & (AP_ERROR | AP_BUS_RESET)) 2548 ata_pktp->ap_flags |= AP_ARQ_ERROR; 2549 else 2550 ata_pktp->ap_flags |= AP_ARQ_OKAY; 2551 goto all_done; 2552 } 2553 2554 2555 #define AP_ARQ_NEEDED (AP_ARQ_ON_ERROR | AP_GOT_STATUS | AP_ERROR) 2556 2557 /* 2558 * Start ARQ pkt if necessary 2559 */ 2560 if ((ata_pktp->ap_flags & AP_ARQ_NEEDED) == AP_ARQ_NEEDED && 2561 (ata_pktp->ap_status & ATS_ERR)) { 2562 2563 /* set controller state back to active */ 2564 ata_ctlp->ac_state = current_state; 2565 2566 /* try to start the ARQ pkt */ 2567 rc = ata_start_arq(ata_ctlp, ata_drvp, ata_pktp); 2568 2569 if (rc == ATA_FSM_RC_BUSY) { 2570 ADBG_ARQ(("ata_ctlr_fsm 0x%p ARQ BUSY\n", ata_ctlp)); 2571 /* let the target driver handle the problem */ 2572 ata_ctlp->ac_state = AS_IDLE; 2573 ata_ctlp->ac_active_pktp = NULL; 2574 ata_ctlp->ac_active_drvp = NULL; 2575 ata_ctlp->ac_fault_pktp = NULL; 2576 goto all_done; 2577 } 2578 2579 ADBG_ARQ(("ata_ctlr_fsm 0x%p ARQ started\n", ata_ctlp)); 2580 return (rc); 2581 } 2582 2583 /* 2584 * Normal completion, no error status, and not an ARQ pkt, 2585 * just fall through. 2586 */ 2587 2588 all_done: 2589 2590 /* 2591 * wrap everything up and tie a ribbon around it 2592 */ 2593 ata_ctlp->ac_active_pktp = NULL; 2594 ata_ctlp->ac_active_drvp = NULL; 2595 if (APKT2GCMD(ata_pktp) != (gcmd_t *)0) { 2596 ghd_complete(&ata_ctlp->ac_ccc, APKT2GCMD(ata_pktp)); 2597 if (DoneFlgp) 2598 *DoneFlgp = TRUE; 2599 } 2600 2601 return (ATA_FSM_RC_OKAY); 2602 } 2603 2604 2605 static int 2606 ata_start_arq( 2607 ata_ctl_t *ata_ctlp, 2608 ata_drv_t *ata_drvp, 2609 ata_pkt_t *ata_pktp) 2610 { 2611 ata_pkt_t *arq_pktp; 2612 int bytes; 2613 uint_t senselen; 2614 2615 ADBG_ARQ(("ata_start_arq 0x%p ARQ needed\n", ata_ctlp)); 2616 2617 /* 2618 * Determine just the size of the Request Sense Data buffer within 2619 * the scsi_arq_status structure. 2620 */ 2621 #define SIZEOF_ARQ_HEADER (sizeof (struct scsi_arq_status) \ 2622 - sizeof (struct scsi_extended_sense)) 2623 senselen = ata_pktp->ap_statuslen - SIZEOF_ARQ_HEADER; 2624 ASSERT(senselen > 0); 2625 2626 2627 /* save ptr to original pkt */ 2628 ata_ctlp->ac_fault_pktp = ata_pktp; 2629 2630 /* switch the controller's active pkt to the ARQ pkt */ 2631 arq_pktp = ata_ctlp->ac_arq_pktp; 2632 ata_ctlp->ac_active_pktp = arq_pktp; 2633 2634 /* finish initializing the ARQ CDB */ 2635 ata_ctlp->ac_arq_cdb[1] = ata_drvp->ad_lun << 4; 2636 ata_ctlp->ac_arq_cdb[4] = (uchar_t)senselen; 2637 2638 /* finish initializing the ARQ pkt */ 2639 arq_pktp->ap_v_addr = (caddr_t)&ata_pktp->ap_scbp->sts_sensedata; 2640 2641 arq_pktp->ap_resid = senselen; 2642 arq_pktp->ap_flags = AP_ATAPI | AP_READ; 2643 arq_pktp->ap_cdb_pad = 2644 ((unsigned)(ata_drvp->ad_cdb_len - arq_pktp->ap_cdb_len)) >> 1; 2645 2646 bytes = min(senselen, ATAPI_MAX_BYTES_PER_DRQ); 2647 arq_pktp->ap_hicyl = (uchar_t)(bytes >> 8); 2648 arq_pktp->ap_lwcyl = (uchar_t)bytes; 2649 2650 /* 2651 * This packet is shared by all drives on this controller 2652 * therefore we need to init the drive number on every ARQ. 2653 */ 2654 arq_pktp->ap_hd = ata_drvp->ad_drive_bits; 2655 2656 /* start it up */ 2657 return ((*arq_pktp->ap_start)(ata_ctlp, ata_drvp, arq_pktp)); 2658 } 2659 2660 /* 2661 * 2662 * reset the bus 2663 * 2664 */ 2665 2666 static int 2667 ata_reset_bus( 2668 ata_ctl_t *ata_ctlp) 2669 { 2670 int watchdog; 2671 uchar_t drive; 2672 int rc = FALSE; 2673 uchar_t fsm_func; 2674 int DoneFlg = FALSE; 2675 2676 /* 2677 * Do a Software Reset to unwedge the bus, and send 2678 * ATAPI DEVICE RESET to each ATAPI drive. 2679 */ 2680 fsm_func = ATA_FSM_RESET; 2681 for (watchdog = ata_reset_bus_watchdog; watchdog > 0; watchdog--) { 2682 switch (ata_ctlr_fsm(fsm_func, ata_ctlp, NULL, NULL, 2683 &DoneFlg)) { 2684 case ATA_FSM_RC_OKAY: 2685 rc = TRUE; 2686 goto fsm_done; 2687 2688 case ATA_FSM_RC_BUSY: 2689 return (FALSE); 2690 2691 case ATA_FSM_RC_INTR: 2692 fsm_func = ATA_FSM_INTR; 2693 rc = TRUE; 2694 continue; 2695 2696 case ATA_FSM_RC_FINI: 2697 fsm_func = ATA_FSM_FINI; 2698 rc = TRUE; 2699 continue; 2700 } 2701 } 2702 ADBG_WARN(("ata_reset_bus: watchdog\n")); 2703 2704 fsm_done: 2705 2706 /* 2707 * Reinitialize the ATA drives 2708 */ 2709 for (drive = 0; drive < ATA_MAXTARG; drive++) { 2710 ata_drv_t *ata_drvp; 2711 2712 if ((ata_drvp = CTL2DRV(ata_ctlp, drive, 0)) == NULL) 2713 continue; 2714 2715 if (ATAPIDRV(ata_drvp)) 2716 continue; 2717 2718 /* 2719 * Reprogram the Read/Write Multiple block factor 2720 * and current geometry into the drive. 2721 */ 2722 if (!ata_disk_setup_parms(ata_ctlp, ata_drvp)) 2723 rc = FALSE; 2724 } 2725 2726 /* If DoneFlg is TRUE, it means that ghd_complete() function */ 2727 /* has been already called. In this case ignore any errors and */ 2728 /* return TRUE to the caller, otherwise return the value of rc */ 2729 /* to the caller */ 2730 if (DoneFlg) 2731 return (TRUE); 2732 else 2733 return (rc); 2734 } 2735 2736 2737 /* 2738 * 2739 * Low level routine to toggle the Software Reset bit 2740 * 2741 */ 2742 2743 static int 2744 ata_software_reset( 2745 ata_ctl_t *ata_ctlp) 2746 { 2747 ddi_acc_handle_t io_hdl1 = ata_ctlp->ac_iohandle1; 2748 ddi_acc_handle_t io_hdl2 = ata_ctlp->ac_iohandle2; 2749 hrtime_t deadline; 2750 uint_t usecs_left; 2751 2752 ADBG_TRACE(("ata_reset_bus entered\n")); 2753 2754 /* disable interrupts and turn the software reset bit on */ 2755 ddi_put8(io_hdl2, ata_ctlp->ac_devctl, (ATDC_D3 | ATDC_SRST)); 2756 2757 /* why 30 milliseconds, the ATA/ATAPI-4 spec says 5 usec. */ 2758 drv_usecwait(30000); 2759 2760 /* turn the software reset bit back off */ 2761 ddi_put8(io_hdl2, ata_ctlp->ac_devctl, ATDC_D3); 2762 2763 /* 2764 * Wait for the controller to assert BUSY status. 2765 * I don't think 300 msecs is correct. The ATA/ATAPI-4 2766 * spec says 400 nsecs, (and 2 msecs if device 2767 * was in sleep mode; but we don't put drives to sleep 2768 * so it probably doesn't matter). 2769 */ 2770 drv_usecwait(300000); 2771 2772 /* 2773 * If drive 0 exists the test for completion is simple 2774 */ 2775 deadline = gethrtime() + ((hrtime_t)31 * NANOSEC); 2776 2777 if (CTL2DRV(ata_ctlp, 0, 0)) { 2778 goto wait_for_not_busy; 2779 } 2780 2781 ASSERT(CTL2DRV(ata_ctlp, 1, 0) != NULL); 2782 2783 /* 2784 * This must be a single device configuration, with drive 1 2785 * only. This complicates the test for completion because 2786 * issuing the software reset just caused drive 1 to 2787 * deselect. With drive 1 deselected, if I just read the 2788 * status register to test the BSY bit I get garbage, but 2789 * I can't re-select drive 1 until I'm certain the BSY bit 2790 * is de-asserted. Catch-22. 2791 * 2792 * In ATA/ATAPI-4, rev 15, section 9.16.2, it says to handle 2793 * this situation like this: 2794 */ 2795 2796 /* give up if the drive doesn't settle within 31 seconds */ 2797 while (gethrtime() < deadline) { 2798 /* 2799 * delay 10msec each time around the loop 2800 */ 2801 drv_usecwait(10000); 2802 2803 /* 2804 * try to select drive 1 2805 */ 2806 ddi_put8(io_hdl1, ata_ctlp->ac_drvhd, ATDH_DRIVE1); 2807 2808 ddi_put8(io_hdl1, ata_ctlp->ac_sect, 0x55); 2809 ddi_put8(io_hdl1, ata_ctlp->ac_sect, 0xaa); 2810 if (ddi_get8(io_hdl1, ata_ctlp->ac_sect) != 0xaa) 2811 continue; 2812 2813 ddi_put8(io_hdl1, ata_ctlp->ac_count, 0x55); 2814 ddi_put8(io_hdl1, ata_ctlp->ac_count, 0xaa); 2815 if (ddi_get8(io_hdl1, ata_ctlp->ac_count) != 0xaa) 2816 continue; 2817 2818 goto wait_for_not_busy; 2819 } 2820 return (FALSE); 2821 2822 wait_for_not_busy: 2823 2824 /* 2825 * Now wait up to 31 seconds for BUSY to clear. 2826 */ 2827 usecs_left = (deadline - gethrtime()) / 1000; 2828 (void) ata_wait3(io_hdl2, ata_ctlp->ac_ioaddr2, 0, ATS_BSY, 2829 ATS_ERR, ATS_BSY, ATS_DF, ATS_BSY, usecs_left); 2830 2831 return (TRUE); 2832 } 2833 2834 /* 2835 * 2836 * DDI interrupt handler 2837 * 2838 */ 2839 2840 static uint_t 2841 ata_intr( 2842 caddr_t arg) 2843 { 2844 ata_ctl_t *ata_ctlp; 2845 int one_shot = 1; 2846 2847 ata_ctlp = (ata_ctl_t *)arg; 2848 2849 return (ghd_intr(&ata_ctlp->ac_ccc, (void *)&one_shot)); 2850 } 2851 2852 2853 /* 2854 * 2855 * GHD ccc_get_status callback 2856 * 2857 */ 2858 2859 static int 2860 ata_get_status( 2861 void *hba_handle, 2862 void *intr_status) 2863 { 2864 ata_ctl_t *ata_ctlp = (ata_ctl_t *)hba_handle; 2865 uchar_t status; 2866 2867 ADBG_TRACE(("ata_get_status entered\n")); 2868 2869 /* 2870 * ignore interrupts before ata_attach completes 2871 */ 2872 if (!(ata_ctlp->ac_flags & AC_ATTACHED)) 2873 return (FALSE); 2874 2875 /* 2876 * can't be interrupt pending if nothing active 2877 */ 2878 switch (ata_ctlp->ac_state) { 2879 case AS_IDLE: 2880 return (FALSE); 2881 case AS_ACTIVE0: 2882 case AS_ACTIVE1: 2883 ASSERT(ata_ctlp->ac_active_drvp != NULL); 2884 ASSERT(ata_ctlp->ac_active_pktp != NULL); 2885 break; 2886 } 2887 2888 /* 2889 * If this is a PCI-IDE controller, check the PCI-IDE controller's 2890 * interrupt status latch. But don't clear it yet. 2891 * 2892 * AC_BMSTATREG_PIO_BROKEN flag is used currently for 2893 * CMD chips with device id 0x646. Since the interrupt bit on 2894 * Bus master IDE register is not usable when in PIO mode, 2895 * this chip is treated as a legacy device for interrupt 2896 * indication. The following code for CMD 2897 * chips may need to be revisited when we enable support for dma. 2898 * 2899 * CHANGE: DMA is not disabled for these devices. BM intr bit is 2900 * checked only if there was DMA used or BM intr is useable on PIO, 2901 * else treat it as before - as legacy device. 2902 */ 2903 2904 if ((ata_ctlp->ac_pciide) && 2905 ((ata_ctlp->ac_pciide_bm != FALSE) && 2906 ((ata_ctlp->ac_active_pktp->ap_pciide_dma == TRUE) || 2907 !(ata_ctlp->ac_flags & AC_BMSTATREG_PIO_BROKEN)))) { 2908 2909 if (!ata_pciide_status_pending(ata_ctlp)) 2910 return (FALSE); 2911 } else { 2912 /* 2913 * Interrupts from legacy ATA/IDE controllers are 2914 * edge-triggered but the dumb legacy ATA/IDE controllers 2915 * and drives don't have an interrupt status bit. 2916 * 2917 * Use a one_shot variable to make sure we only return 2918 * one status per interrupt. 2919 */ 2920 if (intr_status != NULL) { 2921 int *one_shot = (int *)intr_status; 2922 2923 if (*one_shot == 1) 2924 *one_shot = 0; 2925 else 2926 return (FALSE); 2927 } 2928 } 2929 2930 /* check if device is still busy */ 2931 2932 status = ddi_get8(ata_ctlp->ac_iohandle2, ata_ctlp->ac_altstatus); 2933 if (status & ATS_BSY) 2934 return (FALSE); 2935 return (TRUE); 2936 } 2937 2938 2939 /* 2940 * 2941 * get the current status and clear the IRQ 2942 * 2943 */ 2944 2945 int 2946 ata_get_status_clear_intr( 2947 ata_ctl_t *ata_ctlp, 2948 ata_pkt_t *ata_pktp) 2949 { 2950 uchar_t status; 2951 2952 /* 2953 * Here's where we clear the PCI-IDE interrupt latch. If this 2954 * request used DMA mode then we also have to check and clear 2955 * the DMA error latch at the same time. 2956 */ 2957 2958 if (ata_pktp->ap_pciide_dma) { 2959 if (ata_pciide_status_dmacheck_clear(ata_ctlp)) 2960 ata_pktp->ap_flags |= AP_ERROR | AP_TRAN_ERROR; 2961 } else if ((ata_ctlp->ac_pciide) && 2962 !(ata_ctlp->ac_flags & AC_BMSTATREG_PIO_BROKEN)) { 2963 /* 2964 * Some requests don't use DMA mode and therefore won't 2965 * set the DMA error latch, but we still have to clear 2966 * the interrupt latch. 2967 * Controllers with broken BM intr in PIO mode do not go 2968 * through this path. 2969 */ 2970 (void) ata_pciide_status_clear(ata_ctlp); 2971 } 2972 2973 /* 2974 * this clears the drive's interrupt 2975 */ 2976 status = ddi_get8(ata_ctlp->ac_iohandle1, ata_ctlp->ac_status); 2977 ADBG_TRACE(("ata_get_status_clear_intr: 0x%x\n", status)); 2978 return (status); 2979 } 2980 2981 2982 2983 /* 2984 * 2985 * GHD interrupt handler 2986 * 2987 */ 2988 2989 /* ARGSUSED */ 2990 static void 2991 ata_process_intr( 2992 void *hba_handle, 2993 void *intr_status) 2994 { 2995 ata_ctl_t *ata_ctlp = (ata_ctl_t *)hba_handle; 2996 int watchdog; 2997 uchar_t fsm_func; 2998 int rc; 2999 3000 ADBG_TRACE(("ata_process_intr entered\n")); 3001 3002 /* 3003 * process the ATA or ATAPI interrupt 3004 */ 3005 3006 fsm_func = ATA_FSM_INTR; 3007 for (watchdog = ata_process_intr_watchdog; watchdog > 0; watchdog--) { 3008 rc = ata_ctlr_fsm(fsm_func, ata_ctlp, NULL, NULL, NULL); 3009 3010 switch (rc) { 3011 case ATA_FSM_RC_OKAY: 3012 return; 3013 3014 case ATA_FSM_RC_BUSY: /* wait for the next interrupt */ 3015 return; 3016 3017 case ATA_FSM_RC_INTR: /* re-invoke the FSM */ 3018 fsm_func = ATA_FSM_INTR; 3019 break; 3020 3021 case ATA_FSM_RC_FINI: /* move a request to done Q */ 3022 fsm_func = ATA_FSM_FINI; 3023 break; 3024 } 3025 } 3026 ADBG_WARN(("ata_process_intr: watchdog\n")); 3027 } 3028 3029 3030 3031 /* 3032 * 3033 * GHD ccc_hba_start callback 3034 * 3035 */ 3036 3037 static int 3038 ata_hba_start( 3039 void *hba_handle, 3040 gcmd_t *gcmdp) 3041 { 3042 ata_ctl_t *ata_ctlp; 3043 ata_drv_t *ata_drvp; 3044 ata_pkt_t *ata_pktp; 3045 uchar_t fsm_func; 3046 int request_started; 3047 int watchdog; 3048 3049 ADBG_TRACE(("ata_hba_start entered\n")); 3050 3051 ata_ctlp = (ata_ctl_t *)hba_handle; 3052 3053 if (ata_ctlp->ac_active_drvp != NULL) { 3054 ADBG_WARN(("ata_hba_start drvp not null\n")); 3055 return (FALSE); 3056 } 3057 if (ata_ctlp->ac_active_pktp != NULL) { 3058 ADBG_WARN(("ata_hba_start pktp not null\n")); 3059 return (FALSE); 3060 } 3061 3062 ata_pktp = GCMD2APKT(gcmdp); 3063 ata_drvp = GCMD2DRV(gcmdp); 3064 3065 /* 3066 * which drive? 3067 */ 3068 if (ata_drvp->ad_targ == 0) 3069 fsm_func = ATA_FSM_START0; 3070 else 3071 fsm_func = ATA_FSM_START1; 3072 3073 /* 3074 * start the request 3075 */ 3076 request_started = FALSE; 3077 for (watchdog = ata_hba_start_watchdog; watchdog > 0; watchdog--) { 3078 switch (ata_ctlr_fsm(fsm_func, ata_ctlp, ata_drvp, ata_pktp, 3079 NULL)) { 3080 case ATA_FSM_RC_OKAY: 3081 request_started = TRUE; 3082 goto fsm_done; 3083 3084 case ATA_FSM_RC_BUSY: 3085 /* if first time, tell GHD to requeue the request */ 3086 goto fsm_done; 3087 3088 case ATA_FSM_RC_INTR: 3089 /* 3090 * The start function polled for the next 3091 * bus phase, now fake an interrupt to process 3092 * the next action. 3093 */ 3094 request_started = TRUE; 3095 fsm_func = ATA_FSM_INTR; 3096 ata_drvp = NULL; 3097 ata_pktp = NULL; 3098 break; 3099 3100 case ATA_FSM_RC_FINI: /* move request to the done queue */ 3101 request_started = TRUE; 3102 fsm_func = ATA_FSM_FINI; 3103 ata_drvp = NULL; 3104 ata_pktp = NULL; 3105 break; 3106 } 3107 } 3108 ADBG_WARN(("ata_hba_start: watchdog\n")); 3109 3110 fsm_done: 3111 return (request_started); 3112 3113 } 3114 3115 static int 3116 ata_check_pciide_blacklist( 3117 dev_info_t *dip, 3118 uint_t flags) 3119 { 3120 ushort_t vendorid; 3121 ushort_t deviceid; 3122 pcibl_t *blp; 3123 int *propp; 3124 uint_t count; 3125 int rc; 3126 3127 3128 vendorid = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip), 3129 DDI_PROP_DONTPASS, "vendor-id", 0); 3130 deviceid = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip), 3131 DDI_PROP_DONTPASS, "device-id", 0); 3132 3133 /* 3134 * first check for a match in the "pci-ide-blacklist" property 3135 */ 3136 rc = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, 3137 "pci-ide-blacklist", &propp, &count); 3138 3139 if (rc == DDI_PROP_SUCCESS) { 3140 count = (count * sizeof (uint_t)) / sizeof (pcibl_t); 3141 blp = (pcibl_t *)propp; 3142 while (count--) { 3143 /* check for matching ID */ 3144 if ((vendorid & blp->b_vmask) 3145 != (blp->b_vendorid & blp->b_vmask)) { 3146 blp++; 3147 continue; 3148 } 3149 if ((deviceid & blp->b_dmask) 3150 != (blp->b_deviceid & blp->b_dmask)) { 3151 blp++; 3152 continue; 3153 } 3154 3155 /* got a match */ 3156 if (blp->b_flags & flags) { 3157 ddi_prop_free(propp); 3158 return (TRUE); 3159 } else { 3160 ddi_prop_free(propp); 3161 return (FALSE); 3162 } 3163 } 3164 ddi_prop_free(propp); 3165 } 3166 3167 /* 3168 * then check the built-in blacklist 3169 */ 3170 for (blp = ata_pciide_blacklist; blp->b_vendorid; blp++) { 3171 if ((vendorid & blp->b_vmask) != blp->b_vendorid) 3172 continue; 3173 if ((deviceid & blp->b_dmask) != blp->b_deviceid) 3174 continue; 3175 if (!(blp->b_flags & flags)) 3176 continue; 3177 return (TRUE); 3178 } 3179 return (FALSE); 3180 } 3181 3182 int 3183 ata_check_drive_blacklist( 3184 struct ata_id *aidp, 3185 uint_t flags) 3186 { 3187 atabl_t *blp; 3188 3189 for (blp = ata_drive_blacklist; blp->b_model != NULL; blp++) { 3190 if (!ata_strncmp(blp->b_model, aidp->ai_model, 3191 sizeof (aidp->ai_model))) 3192 continue; 3193 if (blp->b_fw != NULL) { 3194 if (!ata_strncmp(blp->b_fw, aidp->ai_fw, 3195 sizeof (aidp->ai_fw))) 3196 continue; 3197 } 3198 if (blp->b_flags & flags) 3199 return (TRUE); 3200 return (FALSE); 3201 } 3202 return (FALSE); 3203 } 3204 3205 /* 3206 * Queue a request to perform some sort of internally 3207 * generated command. When this request packet reaches 3208 * the front of the queue (*func)() is invoked. 3209 * 3210 */ 3211 3212 int 3213 ata_queue_cmd( 3214 int (*func)(ata_ctl_t *, ata_drv_t *, ata_pkt_t *), 3215 void *arg, 3216 ata_ctl_t *ata_ctlp, 3217 ata_drv_t *ata_drvp, 3218 gtgt_t *gtgtp) 3219 { 3220 ata_pkt_t *ata_pktp; 3221 gcmd_t *gcmdp; 3222 int rc; 3223 3224 if (!(gcmdp = ghd_gcmd_alloc(gtgtp, sizeof (*ata_pktp), TRUE))) { 3225 ADBG_ERROR(("atapi_id_update alloc failed\n")); 3226 return (FALSE); 3227 } 3228 3229 3230 /* set the back ptr from the ata_pkt to the gcmd_t */ 3231 ata_pktp = GCMD2APKT(gcmdp); 3232 ata_pktp->ap_gcmdp = gcmdp; 3233 ata_pktp->ap_hd = ata_drvp->ad_drive_bits; 3234 ata_pktp->ap_bytes_per_block = ata_drvp->ad_bytes_per_block; 3235 3236 /* 3237 * over-ride the default start function 3238 */ 3239 ata_pktp = GCMD2APKT(gcmdp); 3240 ata_pktp->ap_start = func; 3241 ata_pktp->ap_complete = NULL; 3242 ata_pktp->ap_v_addr = (caddr_t)arg; 3243 3244 /* 3245 * add it to the queue, when it gets to the front the 3246 * ap_start function is called. 3247 */ 3248 rc = ghd_transport(&ata_ctlp->ac_ccc, gcmdp, gcmdp->cmd_gtgtp, 3249 0, TRUE, NULL); 3250 3251 if (rc != TRAN_ACCEPT) { 3252 /* this should never, ever happen */ 3253 return (FALSE); 3254 } 3255 3256 if (ata_pktp->ap_flags & AP_ERROR) 3257 return (FALSE); 3258 return (TRUE); 3259 } 3260 3261 /* 3262 * Check if this drive has the "revert to defaults" bug 3263 * PSARC 2001/500 and 2001/xxx - check for the properties 3264 * ata-revert-to-defaults and atarvrt-<diskmodel> before 3265 * examining the blacklist. 3266 * <diskmodel> is made from the model number reported by Identify Drive 3267 * with uppercase letters converted to lowercase and all characters 3268 * except letters, digits, ".", "_", and "-" deleted. 3269 * Return value: 3270 * TRUE: enable revert to defaults 3271 * FALSE: disable revert to defaults 3272 * 3273 * NOTE: revert to power on defaults that includes reverting to MDMA 3274 * mode is allowed by ATA-6 & ATA-7 specs. 3275 * Therefore drives exhibiting this behaviour are not violating the spec. 3276 * Furthermore, the spec explicitly says that after the soft reset 3277 * host should check the current setting of the device features. 3278 * Correctly working BIOS would therefore reprogram either the drive 3279 * and/or the host controller to match transfer modes. 3280 * Devices with ATA_BL_NORVRT flag will be removed from 3281 * the ata_blacklist. 3282 * The default behaviour will be - no revert to power-on defaults 3283 * for all devices. The property is retained in case the user 3284 * explicitly requests revert-to-defaults before reboot. 3285 */ 3286 3287 #define ATA_REVERT_PROP_PREFIX "revert-" 3288 #define ATA_REVERT_PROP_GLOBAL "ata-revert-to-defaults" 3289 /* room for prefix + model number + terminating NUL character */ 3290 #define PROP_BUF_SIZE (sizeof (ATA_REVERT_PROP_PREFIX) + \ 3291 sizeof (aidp->ai_model) + 1) 3292 #define PROP_LEN_MAX (31) 3293 3294 static int 3295 ata_check_revert_to_defaults( 3296 ata_drv_t *ata_drvp) 3297 { 3298 struct ata_id *aidp = &ata_drvp->ad_id; 3299 ata_ctl_t *ata_ctlp = ata_drvp->ad_ctlp; 3300 char prop_buf[PROP_BUF_SIZE]; 3301 int i, j; 3302 int propval; 3303 3304 /* put prefix into the buffer */ 3305 (void) strcpy(prop_buf, ATA_REVERT_PROP_PREFIX); 3306 j = strlen(prop_buf); 3307 3308 /* append the model number, leaving out invalid characters */ 3309 for (i = 0; i < sizeof (aidp->ai_model); ++i) { 3310 char c = aidp->ai_model[i]; 3311 if (c >= 'A' && c <= 'Z') /* uppercase -> lower */ 3312 c = c - 'A' + 'a'; 3313 if (c >= 'a' && c <= 'z' || c >= '0' && c <= '9' || 3314 c == '.' || c == '_' || c == '-') 3315 prop_buf[j++] = c; 3316 if (c == '\0') 3317 break; 3318 } 3319 3320 /* make sure there's a terminating NUL character */ 3321 if (j >= PROP_LEN_MAX) 3322 j = PROP_LEN_MAX; 3323 prop_buf[j] = '\0'; 3324 3325 /* look for a disk-specific "revert" property" */ 3326 propval = ddi_getprop(DDI_DEV_T_ANY, ata_ctlp->ac_dip, 3327 DDI_PROP_DONTPASS, prop_buf, -1); 3328 if (propval == 0) 3329 return (FALSE); 3330 else if (propval != -1) 3331 return (TRUE); 3332 3333 /* look for a global "revert" property" */ 3334 propval = ddi_getprop(DDI_DEV_T_ANY, ata_ctlp->ac_dip, 3335 0, ATA_REVERT_PROP_GLOBAL, -1); 3336 if (propval == 0) 3337 return (FALSE); 3338 else if (propval != -1) 3339 return (TRUE); 3340 3341 return (FALSE); 3342 } 3343 3344 void 3345 ata_show_transfer_mode(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp) 3346 { 3347 int i; 3348 3349 if (ata_ctlp->ac_pciide_bm == FALSE || 3350 ata_drvp->ad_pciide_dma != ATA_DMA_ON) { 3351 if (ata_cntrl_DMA_sel_msg) { 3352 ATAPRT(( 3353 "?\tATA DMA off: %s\n", ata_cntrl_DMA_sel_msg)); 3354 } else if (ata_dev_DMA_sel_msg) { 3355 ATAPRT(("?\tATA DMA off: %s\n", ata_dev_DMA_sel_msg)); 3356 } 3357 ATAPRT(("?\tPIO mode %d selected\n", 3358 (ata_drvp->ad_id.ai_advpiomode & ATAC_ADVPIO_4_SUP) == 3359 ATAC_ADVPIO_4_SUP ? 4 : 3)); 3360 } else { 3361 /* Using DMA */ 3362 if (ata_drvp->ad_id.ai_dworddma & ATAC_MDMA_SEL_MASK) { 3363 /* 3364 * Rely on the fact that either dwdma or udma is 3365 * selected, not both. 3366 */ 3367 ATAPRT(("?\tMultiwordDMA mode %d selected\n", 3368 (ata_drvp->ad_id.ai_dworddma & ATAC_MDMA_2_SEL) == 3369 ATAC_MDMA_2_SEL ? 2 : 3370 (ata_drvp->ad_id.ai_dworddma & ATAC_MDMA_1_SEL) == 3371 ATAC_MDMA_1_SEL ? 1 : 0)); 3372 } else { 3373 for (i = 0; i <= 6; i++) { 3374 if (ata_drvp->ad_id.ai_ultradma & 3375 (1 << (i + 8))) { 3376 ATAPRT(( 3377 "?\tUltraDMA mode %d selected\n", 3378 i)); 3379 break; 3380 } 3381 } 3382 } 3383 } 3384 } 3385 3386 /* 3387 * Controller-specific operation pointers. 3388 * Should be extended as needed - init only for now 3389 */ 3390 struct ata_ctl_spec_ops { 3391 uint_t (*cs_init)(dev_info_t *, ushort_t, ushort_t); /* ctlr init */ 3392 }; 3393 3394 3395 struct ata_ctl_spec { 3396 ushort_t cs_vendor_id; 3397 ushort_t cs_device_id; 3398 struct ata_ctl_spec_ops *cs_ops; 3399 }; 3400 3401 /* Sil3XXX-specific functions (init only for now) */ 3402 struct ata_ctl_spec_ops sil3xxx_ops = { 3403 &sil3xxx_init_controller /* Sil3XXX cntrl initialization */ 3404 }; 3405 3406 3407 struct ata_ctl_spec ata_cntrls_spec[] = { 3408 {0x1095, 0x3114, &sil3xxx_ops}, 3409 {0x1095, 0x3512, &sil3xxx_ops}, 3410 {0x1095, 0x3112, &sil3xxx_ops}, 3411 {0, 0, NULL} /* List must end with cs_ops set to NULL */ 3412 }; 3413 3414 /* 3415 * Do controller specific initialization if necessary. 3416 * Pick-up controller specific functions. 3417 */ 3418 3419 int 3420 ata_spec_init_controller(dev_info_t *dip) 3421 { 3422 ushort_t vendor_id; 3423 ushort_t device_id; 3424 struct ata_ctl_spec *ctlsp; 3425 3426 vendor_id = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip), 3427 DDI_PROP_DONTPASS, "vendor-id", 0); 3428 device_id = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip), 3429 DDI_PROP_DONTPASS, "device-id", 0); 3430 3431 /* Locate controller specific ops, if they exist */ 3432 ctlsp = ata_cntrls_spec; 3433 while (ctlsp->cs_ops != NULL) { 3434 if (ctlsp->cs_vendor_id == vendor_id && 3435 ctlsp->cs_device_id == device_id) 3436 break; 3437 ctlsp++; 3438 } 3439 3440 if (ctlsp->cs_ops != NULL) { 3441 if (ctlsp->cs_ops->cs_init != NULL) { 3442 /* Initialize controller */ 3443 if ((*(ctlsp->cs_ops->cs_init)) 3444 (dip, vendor_id, device_id) != TRUE) { 3445 cmn_err(CE_WARN, 3446 "pci%4x,%4x cntrl specific " 3447 "initialization failed", 3448 vendor_id, device_id); 3449 return (FALSE); 3450 } 3451 } 3452 } 3453 return (TRUE); 3454 } 3455 3456 /* 3457 * this routine works like ddi_prop_get_int, except that it works on 3458 * a string property that contains ascii representations 3459 * of an integer. 3460 * If the property is not found, the default value is returned. 3461 */ 3462 static int 3463 ata_prop_lookup_int(dev_t match_dev, dev_info_t *dip, 3464 uint_t flags, char *name, int defvalue) 3465 { 3466 3467 char *bufp, *cp; 3468 int rc = defvalue; 3469 int proprc; 3470 3471 proprc = ddi_prop_lookup_string(match_dev, dip, 3472 flags, name, &bufp); 3473 3474 if (proprc == DDI_PROP_SUCCESS) { 3475 cp = bufp; 3476 rc = stoi(&cp); 3477 ddi_prop_free(bufp); 3478 } else { 3479 /* 3480 * see if property is encoded as an int instead of string. 3481 */ 3482 rc = ddi_prop_get_int(match_dev, dip, flags, name, defvalue); 3483 } 3484 3485 return (rc); 3486 } 3487 3488 /* 3489 * Initialize the power management components 3490 */ 3491 static void 3492 ata_init_pm(dev_info_t *dip) 3493 { 3494 char pmc_name[16]; 3495 char *pmc[] = { 3496 NULL, 3497 "0=Sleep (PCI D3 State)", 3498 "3=PowerOn (PCI D0 State)", 3499 NULL 3500 }; 3501 int instance; 3502 ata_ctl_t *ata_ctlp; 3503 3504 3505 instance = ddi_get_instance(dip); 3506 ata_ctlp = ddi_get_soft_state(ata_state, instance); 3507 ata_ctlp->ac_pm_support = 0; 3508 3509 /* check PCI capabilities */ 3510 if (!ata_is_pci(dip)) 3511 return; 3512 3513 (void) sprintf(pmc_name, "NAME=ata%d", instance); 3514 pmc[0] = pmc_name; 3515 3516 #ifdef ATA_USE_AUTOPM 3517 if (ddi_prop_update_string_array(DDI_DEV_T_NONE, dip, 3518 "pm-components", pmc, 3) != DDI_PROP_SUCCESS) { 3519 return; 3520 } 3521 #endif 3522 3523 ata_ctlp->ac_pm_support = 1; 3524 ata_ctlp->ac_pm_level = PM_LEVEL_D0; 3525 3526 ATA_BUSY_COMPONENT(dip, 0); 3527 if (ATA_RAISE_POWER(dip, 0, PM_LEVEL_D0) != DDI_SUCCESS) { 3528 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "pm-components"); 3529 } 3530 ATA_IDLE_COMPONENT(dip, 0); 3531 } 3532 3533 /* 3534 * resume the hard drive 3535 */ 3536 static void 3537 ata_resume_drive(ata_drv_t *ata_drvp) 3538 { 3539 ata_ctl_t *ata_ctlp = ata_drvp->ad_ctlp; 3540 int drive_type; 3541 struct ata_id id; 3542 3543 ADBG_TRACE(("ata_resume_drive entered\n")); 3544 3545 drive_type = ata_drive_type(ata_drvp->ad_drive_bits, 3546 ata_ctlp->ac_iohandle1, ata_ctlp->ac_ioaddr1, 3547 ata_ctlp->ac_iohandle2, ata_ctlp->ac_ioaddr2, 3548 &id); 3549 if (drive_type == ATA_DEV_NONE) 3550 return; 3551 3552 if (!ATAPIDRV(ata_drvp)) { 3553 /* Reset Ultra DMA mode */ 3554 ata_reset_dma_mode(ata_drvp); 3555 if (!ata_disk_setup_parms(ata_ctlp, ata_drvp)) 3556 return; 3557 } else { 3558 (void) atapi_init_drive(ata_drvp); 3559 atapi_reset_dma_mode(ata_drvp); 3560 } 3561 (void) ata_set_feature(ata_ctlp, ata_drvp, ATSF_DIS_REVPOD, 0); 3562 3563 } 3564 3565 /* 3566 * resume routine, it will be run when get the command 3567 * DDI_RESUME at attach(9E) from system power management 3568 */ 3569 static int 3570 ata_resume(dev_info_t *dip) 3571 { 3572 int instance; 3573 ata_ctl_t *ata_ctlp; 3574 ddi_acc_handle_t io_hdl2; 3575 caddr_t ioaddr2; 3576 3577 instance = ddi_get_instance(dip); 3578 ata_ctlp = ddi_get_soft_state(ata_state, instance); 3579 3580 if (!ata_ctlp->ac_pm_support) 3581 return (DDI_FAILURE); 3582 if (ata_ctlp->ac_pm_level == PM_LEVEL_D0) 3583 return (DDI_SUCCESS); 3584 3585 ATA_BUSY_COMPONENT(dip, 0); 3586 if (ATA_RAISE_POWER(dip, 0, PM_LEVEL_D0) == DDI_FAILURE) 3587 return (DDI_FAILURE); 3588 ATA_IDLE_COMPONENT(dip, 0); 3589 3590 /* enable interrupts from the device */ 3591 io_hdl2 = ata_ctlp->ac_iohandle2; 3592 ioaddr2 = ata_ctlp->ac_ioaddr2; 3593 ddi_put8(io_hdl2, (uchar_t *)ioaddr2 + AT_DEVCTL, ATDC_D3); 3594 ata_ctlp->ac_pm_level = PM_LEVEL_D0; 3595 3596 return (DDI_SUCCESS); 3597 } 3598 3599 /* 3600 * suspend routine, it will be run when get the command 3601 * DDI_SUSPEND at detach(9E) from system power management 3602 */ 3603 static int 3604 ata_suspend(dev_info_t *dip) 3605 { 3606 int instance; 3607 ata_ctl_t *ata_ctlp; 3608 ddi_acc_handle_t io_hdl2; 3609 3610 instance = ddi_get_instance(dip); 3611 ata_ctlp = ddi_get_soft_state(ata_state, instance); 3612 3613 if (!ata_ctlp->ac_pm_support) 3614 return (DDI_FAILURE); 3615 if (ata_ctlp->ac_pm_level == PM_LEVEL_D3) 3616 return (DDI_SUCCESS); 3617 3618 /* disable interrupts and turn the software reset bit on */ 3619 io_hdl2 = ata_ctlp->ac_iohandle2; 3620 ddi_put8(io_hdl2, ata_ctlp->ac_devctl, (ATDC_D3 | ATDC_SRST)); 3621 3622 (void) ata_reset_bus(ata_ctlp); 3623 (void) ata_change_power(dip, ATC_SLEEP); 3624 ata_ctlp->ac_pm_level = PM_LEVEL_D3; 3625 return (DDI_SUCCESS); 3626 } 3627 3628 int ata_save_pci_config = 0; 3629 /* 3630 * ata specific power management entry point, it was 3631 * used to change the power management component 3632 */ 3633 static int 3634 ata_power(dev_info_t *dip, int component, int level) 3635 { 3636 int instance; 3637 ata_ctl_t *ata_ctlp; 3638 uint8_t cmd; 3639 3640 ADBG_TRACE(("ata_power entered, component = %d, level = %d\n", 3641 component, level)); 3642 3643 instance = ddi_get_instance(dip); 3644 ata_ctlp = ddi_get_soft_state(ata_state, instance); 3645 if (ata_ctlp == NULL || component != 0) 3646 return (DDI_FAILURE); 3647 3648 if (!ata_ctlp->ac_pm_support) 3649 return (DDI_FAILURE); 3650 3651 if (ata_ctlp->ac_pm_level == level) 3652 return (DDI_SUCCESS); 3653 3654 switch (level) { 3655 case PM_LEVEL_D0: 3656 if (ata_save_pci_config) 3657 (void) pci_restore_config_regs(dip); 3658 ata_ctlp->ac_pm_level = PM_LEVEL_D0; 3659 cmd = ATC_IDLE_IMMED; 3660 break; 3661 case PM_LEVEL_D3: 3662 if (ata_save_pci_config) 3663 (void) pci_save_config_regs(dip); 3664 ata_ctlp->ac_pm_level = PM_LEVEL_D3; 3665 cmd = ATC_SLEEP; 3666 break; 3667 default: 3668 return (DDI_FAILURE); 3669 } 3670 return (ata_change_power(dip, cmd)); 3671 } 3672 3673 /* 3674 * sent commands to ata controller to change the power level 3675 */ 3676 static int 3677 ata_change_power(dev_info_t *dip, uint8_t cmd) 3678 { 3679 int instance; 3680 ata_ctl_t *ata_ctlp; 3681 ata_drv_t *ata_drvp; 3682 uchar_t targ; 3683 struct ata_id id; 3684 uchar_t lun; 3685 uchar_t lastlun; 3686 struct ata_id *aidp; 3687 3688 ADBG_TRACE(("ata_change_power entered, cmd = %d\n", cmd)); 3689 3690 instance = ddi_get_instance(dip); 3691 ata_ctlp = ddi_get_soft_state(ata_state, instance); 3692 3693 /* 3694 * Issue command on each disk device on the bus. 3695 */ 3696 if (cmd == ATC_SLEEP) { 3697 for (targ = 0; targ < ATA_MAXTARG; targ++) { 3698 ata_drvp = CTL2DRV(ata_ctlp, targ, 0); 3699 if (ata_drvp == NULL) 3700 continue; 3701 aidp = &ata_drvp->ad_id; 3702 if ((aidp->ai_validinfo & ATAC_VALIDINFO_83) && 3703 (aidp->ai_ultradma & ATAC_UDMA_SEL_MASK)) { 3704 ata_drvp->ad_dma_cap = ATA_DMA_ULTRAMODE; 3705 ata_drvp->ad_dma_mode = aidp->ai_ultradma; 3706 } else if (aidp->ai_dworddma & ATAC_MDMA_SEL_MASK) { 3707 ata_drvp->ad_dma_cap = ATA_DMA_MWORDMODE; 3708 ata_drvp->ad_dma_mode = aidp->ai_dworddma; 3709 } 3710 if (ata_drive_type(ata_drvp->ad_drive_bits, 3711 ata_ctlp->ac_iohandle1, ata_ctlp->ac_ioaddr1, 3712 ata_ctlp->ac_iohandle2, ata_ctlp->ac_ioaddr2, 3713 &id) != ATA_DEV_DISK) 3714 continue; 3715 (void) ata_flush_cache(ata_ctlp, ata_drvp); 3716 if (!ata_command(ata_ctlp, ata_drvp, TRUE, TRUE, 3717 5 * 1000000, cmd, 0, 0, 0, 0, 0, 0)) { 3718 cmn_err(CE_WARN, "!ata_controller - Can not " 3719 "put drive %d in to power mode %u", 3720 targ, cmd); 3721 (void) ata_devo_reset(dip, DDI_RESET_FORCE); 3722 return (DDI_FAILURE); 3723 } 3724 } 3725 return (DDI_SUCCESS); 3726 } 3727 3728 (void) ata_software_reset(ata_ctlp); 3729 for (targ = 0; targ < ATA_MAXTARG; targ++) { 3730 ata_drvp = CTL2DRV(ata_ctlp, targ, 0); 3731 if (ata_drvp == NULL) 3732 continue; 3733 ata_resume_drive(ata_drvp); 3734 3735 if (ATAPIDRV(ata_drvp)) 3736 lastlun = ata_drvp->ad_id.ai_lastlun; 3737 else 3738 lastlun = 0; 3739 if (!ata_enable_atapi_luns) 3740 lastlun = 0; 3741 for (lun = 1; lun <= lastlun && lun < ATA_MAXLUN; lun++) { 3742 ata_drvp = CTL2DRV(ata_ctlp, targ, lun); 3743 if (ata_drvp != NULL) 3744 ata_resume_drive(ata_drvp); 3745 } 3746 } 3747 3748 return (DDI_SUCCESS); 3749 } 3750 3751 /* 3752 * return 1 when ata controller is a pci device, 3753 * otherwise return 0 3754 */ 3755 static int 3756 ata_is_pci(dev_info_t *dip) 3757 { 3758 int rc; 3759 char *bufp; 3760 int ispci; 3761 3762 rc = ddi_prop_lookup_string(DDI_DEV_T_ANY, ddi_get_parent(dip), 3763 DDI_PROP_DONTPASS, "device_type", &bufp); 3764 3765 if (rc != DDI_PROP_SUCCESS) { 3766 ADBG_ERROR(("ata_is_pci !device_type\n")); 3767 return (0); 3768 } 3769 3770 ispci = (strcmp(bufp, "pci-ide") == 0); 3771 3772 ddi_prop_free(bufp); 3773 3774 return (ispci); 3775 } 3776 3777 /* 3778 * Disable DMA for this drive 3779 */ 3780 static void 3781 ata_disable_DMA(ata_drv_t *ata_drvp) 3782 { 3783 struct ata_id *aidp; 3784 char buf[sizeof (aidp->ai_model) +2]; 3785 int i; 3786 3787 if (ata_drvp == NULL) 3788 return; 3789 3790 if (ata_drvp->ad_pciide_dma == ATA_DMA_OFF) 3791 return; 3792 3793 ata_drvp->ad_pciide_dma = ATA_DMA_OFF; 3794 3795 /* Print the message */ 3796 buf[0] = '\0'; 3797 aidp = &ata_drvp->ad_id; 3798 if (aidp != NULL) { 3799 (void) strncpy(buf, aidp->ai_model, sizeof (aidp->ai_model)); 3800 buf[sizeof (aidp->ai_model) -1] = '\0'; 3801 for (i = sizeof (aidp->ai_model) - 2; buf[i] == ' '; i--) 3802 buf[i] = '\0'; 3803 } 3804 cmn_err(CE_CONT, 3805 "?DMA disabled on %s target=%d, lun=%d due to DMA errors,", 3806 buf, ata_drvp->ad_targ, ata_drvp->ad_lun); 3807 cmn_err(CE_CONT, "?most likely due to the CF-to-IDE adapter."); 3808 } 3809 3810 /* 3811 * Check and select DMA mode 3812 * 3813 * TRUE is returned when set feature is called successfully, 3814 * otherwise return FALSE 3815 */ 3816 int 3817 ata_set_dma_mode(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp) 3818 { 3819 struct ata_id *aidp; 3820 int mode, rval = FALSE; 3821 uint8_t subcmd; 3822 3823 aidp = &ata_drvp->ad_id; 3824 3825 /* Return directly if DMA is not supported */ 3826 if (!(aidp->ai_cap & ATAC_DMA_SUPPORT)) 3827 return (rval); 3828 3829 /* Return if DMA mode is already selected */ 3830 if (((aidp->ai_validinfo & ATAC_VALIDINFO_83) && 3831 (aidp->ai_ultradma & ATAC_UDMA_SEL_MASK)) || 3832 (aidp->ai_dworddma & ATAC_MDMA_SEL_MASK)) 3833 return (rval); 3834 3835 /* First check Ultra DMA mode if no DMA is selected */ 3836 if ((aidp->ai_validinfo & ATAC_VALIDINFO_83) && 3837 (aidp->ai_ultradma & ATAC_UDMA_SUP_MASK)) { 3838 for (mode = 6; mode >= 0; --mode) { 3839 if (aidp->ai_ultradma & (1 << mode)) 3840 break; 3841 } 3842 subcmd = ATF_XFRMOD_UDMA; 3843 3844 } else if (aidp->ai_dworddma & ATAC_MDMA_SUP_MASK) { 3845 /* Then check multi-word DMA mode */ 3846 for (mode = 2; mode >= 0; --mode) { 3847 if (aidp->ai_dworddma & (1 << mode)) 3848 break; 3849 } 3850 subcmd = ATF_XFRMOD_MDMA; 3851 3852 } else { 3853 return (rval); 3854 } 3855 3856 rval = ata_set_feature(ata_ctlp, ata_drvp, ATSF_SET_XFRMOD, 3857 subcmd|mode); 3858 3859 return (rval); 3860 } 3861 3862 /* 3863 * Reset Ultra DMA mode / MWDMA mode 3864 */ 3865 void 3866 ata_reset_dma_mode(ata_drv_t *ata_drvp) 3867 { 3868 uint8_t subcmd; 3869 int mode; 3870 ata_ctl_t *ata_ctlp = ata_drvp->ad_ctlp; 3871 3872 switch (ata_drvp->ad_dma_cap) { 3873 case ATA_DMA_ULTRAMODE: 3874 subcmd = ATF_XFRMOD_UDMA; 3875 for (mode = 0; mode <= 6; mode++) { 3876 if (ata_drvp->ad_dma_mode & (1 << (mode + 8))) 3877 break; 3878 } 3879 break; 3880 case ATA_DMA_MWORDMODE: 3881 subcmd = ATF_XFRMOD_MDMA; 3882 mode = ((ata_drvp->ad_dma_mode & ATAC_MDMA_2_SEL) == 3883 ATAC_MDMA_2_SEL ? 2 : 3884 (ata_drvp->ad_dma_mode & ATAC_MDMA_1_SEL) == 3885 ATAC_MDMA_1_SEL ? 1 : 0); 3886 break; 3887 default: 3888 return; 3889 } 3890 3891 (void) ata_set_feature(ata_ctlp, ata_drvp, ATSF_SET_XFRMOD, 3892 (subcmd | mode)); 3893 } 3894