1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 1993, 2010, Oracle and/or its affiliates. All rights reserved. 24 */ 25 /* 26 * Copyright (c) 2010, Intel Corporation. 27 * All rights reserved. 28 * Copyright 2019 Joyent, Inc. 29 * Copyright 2020 Oxide Computer Company 30 */ 31 32 /* 33 * To understand how the pcplusmp module interacts with the interrupt subsystem 34 * read the theory statement in uts/i86pc/os/intr.c. 35 */ 36 37 /* 38 * PSMI 1.1 extensions are supported only in 2.6 and later versions. 39 * PSMI 1.2 extensions are supported only in 2.7 and later versions. 40 * PSMI 1.3 and 1.4 extensions are supported in Solaris 10. 41 * PSMI 1.5 extensions are supported in Solaris Nevada. 42 * PSMI 1.6 extensions are supported in Solaris Nevada. 43 * PSMI 1.7 extensions are supported in Solaris Nevada. 44 */ 45 #define PSMI_1_7 46 47 #include <sys/processor.h> 48 #include <sys/time.h> 49 #include <sys/psm.h> 50 #include <sys/smp_impldefs.h> 51 #include <sys/cram.h> 52 #include <sys/acpi/acpi.h> 53 #include <sys/acpica.h> 54 #include <sys/psm_common.h> 55 #include <sys/apic.h> 56 #include <sys/pit.h> 57 #include <sys/ddi.h> 58 #include <sys/sunddi.h> 59 #include <sys/ddi_impldefs.h> 60 #include <sys/pci.h> 61 #include <sys/promif.h> 62 #include <sys/prom_debug.h> 63 #include <sys/x86_archext.h> 64 #include <sys/cpc_impl.h> 65 #include <sys/uadmin.h> 66 #include <sys/panic.h> 67 #include <sys/debug.h> 68 #include <sys/archsystm.h> 69 #include <sys/trap.h> 70 #include <sys/machsystm.h> 71 #include <sys/sysmacros.h> 72 #include <sys/cpuvar.h> 73 #include <sys/rm_platter.h> 74 #include <sys/privregs.h> 75 #include <sys/note.h> 76 #include <sys/pci_intr_lib.h> 77 #include <sys/spl.h> 78 #include <sys/clock.h> 79 #include <sys/cyclic.h> 80 #include <sys/dditypes.h> 81 #include <sys/sunddi.h> 82 #include <sys/x_call.h> 83 #include <sys/reboot.h> 84 #include <sys/hpet.h> 85 #include <sys/apic_common.h> 86 #include <sys/apic_timer.h> 87 #include <sys/smt.h> 88 89 /* 90 * Local Function Prototypes 91 */ 92 static void apic_init_intr(void); 93 94 /* 95 * standard MP entries 96 */ 97 static int apic_probe(void); 98 static int apic_getclkirq(int ipl); 99 static void apic_init(void); 100 static void apic_picinit(void); 101 static int apic_post_cpu_start(void); 102 static int apic_intr_enter(int ipl, int *vect); 103 static void apic_setspl(int ipl); 104 static int apic_addspl(int ipl, int vector, int min_ipl, int max_ipl); 105 static int apic_delspl(int ipl, int vector, int min_ipl, int max_ipl); 106 static int apic_disable_intr(processorid_t cpun); 107 static void apic_enable_intr(processorid_t cpun); 108 static int apic_get_ipivect(int ipl, int type); 109 static void apic_post_cyclic_setup(void *arg); 110 111 #define UCHAR_MAX UINT8_MAX 112 113 /* 114 * The following vector assignments influence the value of ipltopri and 115 * vectortoipl. Note that vectors 0 - 0x1f are not used. We can program 116 * idle to 0 and IPL 0 to 0xf to differentiate idle in case 117 * we care to do so in future. Note some IPLs which are rarely used 118 * will share the vector ranges and heavily used IPLs (5 and 6) have 119 * a wide range. 120 * 121 * This array is used to initialize apic_ipls[] (in apic_init()). 122 * 123 * IPL Vector range. as passed to intr_enter 124 * 0 none. 125 * 1,2,3 0x20-0x2f 0x0-0xf 126 * 4 0x30-0x3f 0x10-0x1f 127 * 5 0x40-0x5f 0x20-0x3f 128 * 6 0x60-0x7f 0x40-0x5f 129 * 7,8,9 0x80-0x8f 0x60-0x6f 130 * 10 0x90-0x9f 0x70-0x7f 131 * 11 0xa0-0xaf 0x80-0x8f 132 * ... ... 133 * 15 0xe0-0xef 0xc0-0xcf 134 * 15 0xf0-0xff 0xd0-0xdf 135 */ 136 uchar_t apic_vectortoipl[APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL] = { 137 3, 4, 5, 5, 6, 6, 9, 10, 11, 12, 13, 14, 15, 15 138 }; 139 /* 140 * The ipl of an ISR at vector X is apic_vectortoipl[X>>4] 141 * NOTE that this is vector as passed into intr_enter which is 142 * programmed vector - 0x20 (APIC_BASE_VECT) 143 */ 144 145 uchar_t apic_ipltopri[MAXIPL + 1]; /* unix ipl to apic pri */ 146 /* The taskpri to be programmed into apic to mask given ipl */ 147 148 /* 149 * Correlation of the hardware vector to the IPL in use, initialized 150 * from apic_vectortoipl[] in apic_init(). The final IPLs may not correlate 151 * to the IPLs in apic_vectortoipl on some systems that share interrupt lines 152 * connected to errata-stricken IOAPICs 153 */ 154 uchar_t apic_ipls[APIC_AVAIL_VECTOR]; 155 156 /* 157 * Patchable global variables. 158 */ 159 int apic_enable_hwsoftint = 0; /* 0 - disable, 1 - enable */ 160 int apic_enable_bind_log = 1; /* 1 - display interrupt binding log */ 161 162 /* 163 * Local static data 164 */ 165 static struct psm_ops apic_ops = { 166 apic_probe, 167 168 apic_init, 169 apic_picinit, 170 apic_intr_enter, 171 apic_intr_exit, 172 apic_setspl, 173 apic_addspl, 174 apic_delspl, 175 apic_disable_intr, 176 apic_enable_intr, 177 (int (*)(int))NULL, /* psm_softlvl_to_irq */ 178 (void (*)(int))NULL, /* psm_set_softintr */ 179 180 apic_set_idlecpu, 181 apic_unset_idlecpu, 182 183 apic_clkinit, 184 apic_getclkirq, 185 (void (*)(void))NULL, /* psm_hrtimeinit */ 186 apic_gethrtime, 187 188 apic_get_next_processorid, 189 apic_cpu_start, 190 apic_post_cpu_start, 191 apic_shutdown, 192 apic_get_ipivect, 193 apic_send_ipi, 194 195 (int (*)(dev_info_t *, int))NULL, /* psm_translate_irq */ 196 (void (*)(int, char *))NULL, /* psm_notify_error */ 197 (void (*)(int))NULL, /* psm_notify_func */ 198 apic_timer_reprogram, 199 apic_timer_enable, 200 apic_timer_disable, 201 apic_post_cyclic_setup, 202 apic_preshutdown, 203 apic_intr_ops, /* Advanced DDI Interrupt framework */ 204 apic_state, /* save, restore apic state for S3 */ 205 apic_cpu_ops, /* CPU control interface. */ 206 207 apic_get_pir_ipivect, 208 apic_send_pir_ipi, 209 apic_cmci_setup, 210 }; 211 212 struct psm_ops *psmops = &apic_ops; 213 214 static struct psm_info apic_psm_info = { 215 PSM_INFO_VER01_7, /* version */ 216 PSM_OWN_EXCLUSIVE, /* ownership */ 217 (struct psm_ops *)&apic_ops, /* operation */ 218 APIC_PCPLUSMP_NAME, /* machine name */ 219 "pcplusmp v1.4 compatible", 220 }; 221 222 static void *apic_hdlp; 223 224 /* to gather intr data and redistribute */ 225 static void apic_redistribute_compute(void); 226 227 /* 228 * This is the loadable module wrapper 229 */ 230 231 int 232 _init(void) 233 { 234 if (apic_coarse_hrtime) 235 apic_ops.psm_gethrtime = &apic_gettime; 236 return (psm_mod_init(&apic_hdlp, &apic_psm_info)); 237 } 238 239 int 240 _fini(void) 241 { 242 return (psm_mod_fini(&apic_hdlp, &apic_psm_info)); 243 } 244 245 int 246 _info(struct modinfo *modinfop) 247 { 248 return (psm_mod_info(&apic_hdlp, &apic_psm_info, modinfop)); 249 } 250 251 static int 252 apic_probe(void) 253 { 254 PRM_POINT("apic_probe()"); 255 256 /* check if apix is initialized */ 257 if (apix_enable && apix_loaded()) { 258 PRM_POINT("apic_probe FAILURE: apix is loaded"); 259 return (PSM_FAILURE); 260 } 261 262 /* 263 * Check whether x2APIC mode was activated by BIOS. We don't support 264 * that in pcplusmp as apix normally handles that. 265 */ 266 PRM_POINT("apic_local_mode()"); 267 if (apic_local_mode() == LOCAL_X2APIC) { 268 PRM_POINT("apic_probe FAILURE: in x2apic mode"); 269 return (PSM_FAILURE); 270 } 271 272 /* continue using pcplusmp PSM */ 273 apix_enable = 0; 274 275 return (apic_probe_common(apic_psm_info.p_mach_idstring)); 276 } 277 278 static uchar_t 279 apic_xlate_vector_by_irq(uchar_t irq) 280 { 281 if (apic_irq_table[irq] == NULL) 282 return (0); 283 284 return (apic_irq_table[irq]->airq_vector); 285 } 286 287 void 288 apic_init(void) 289 { 290 int i; 291 int j = 1; 292 293 psm_get_ioapicid = apic_get_ioapicid; 294 psm_get_localapicid = apic_get_localapicid; 295 psm_xlate_vector_by_irq = apic_xlate_vector_by_irq; 296 297 apic_ipltopri[0] = APIC_VECTOR_PER_IPL; /* leave 0 for idle */ 298 for (i = 0; i < (APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL); i++) { 299 if ((i < ((APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL) - 1)) && 300 (apic_vectortoipl[i + 1] == apic_vectortoipl[i])) 301 /* get to highest vector at the same ipl */ 302 continue; 303 for (; j <= apic_vectortoipl[i]; j++) { 304 apic_ipltopri[j] = (i << APIC_IPL_SHIFT) + 305 APIC_BASE_VECT; 306 } 307 } 308 for (; j < MAXIPL + 1; j++) 309 /* fill up any empty ipltopri slots */ 310 apic_ipltopri[j] = (i << APIC_IPL_SHIFT) + APIC_BASE_VECT; 311 apic_init_common(); 312 313 /* 314 * For pcplusmp, we'll keep things simple and always disable this. 315 */ 316 smt_intr_alloc_pil(XC_CPUPOKE_PIL); 317 318 apic_pir_vect = apic_get_ipivect(XC_CPUPOKE_PIL, -1); 319 320 #if !defined(__amd64) 321 if (cpuid_have_cr8access(CPU)) 322 apic_have_32bit_cr8 = 1; 323 #endif 324 } 325 326 static void 327 apic_init_intr(void) 328 { 329 processorid_t cpun = psm_get_cpu_id(); 330 uint_t nlvt; 331 uint32_t svr = AV_UNIT_ENABLE | APIC_SPUR_INTR; 332 333 apic_reg_ops->apic_write_task_reg(APIC_MASK_ALL); 334 335 ASSERT(apic_mode == LOCAL_APIC); 336 337 /* 338 * We are running APIC in MMIO mode. 339 */ 340 if (apic_flat_model) { 341 apic_reg_ops->apic_write(APIC_FORMAT_REG, APIC_FLAT_MODEL); 342 } else { 343 apic_reg_ops->apic_write(APIC_FORMAT_REG, APIC_CLUSTER_MODEL); 344 } 345 346 apic_reg_ops->apic_write(APIC_DEST_REG, AV_HIGH_ORDER >> cpun); 347 348 if (apic_directed_EOI_supported()) { 349 /* 350 * Setting the 12th bit in the Spurious Interrupt Vector 351 * Register suppresses broadcast EOIs generated by the local 352 * APIC. The suppression of broadcast EOIs happens only when 353 * interrupts are level-triggered. 354 */ 355 svr |= APIC_SVR_SUPPRESS_BROADCAST_EOI; 356 } 357 358 /* need to enable APIC before unmasking NMI */ 359 apic_reg_ops->apic_write(APIC_SPUR_INT_REG, svr); 360 361 /* 362 * Presence of an invalid vector with delivery mode AV_FIXED can 363 * cause an error interrupt, even if the entry is masked...so 364 * write a valid vector to LVT entries along with the mask bit 365 */ 366 367 /* All APICs have timer and LINT0/1 */ 368 apic_reg_ops->apic_write(APIC_LOCAL_TIMER, AV_MASK|APIC_RESV_IRQ); 369 apic_reg_ops->apic_write(APIC_INT_VECT0, AV_MASK|APIC_RESV_IRQ); 370 apic_reg_ops->apic_write(APIC_INT_VECT1, AV_NMI); /* enable NMI */ 371 372 /* 373 * On integrated APICs, the number of LVT entries is 374 * 'Max LVT entry' + 1; on 82489DX's (non-integrated 375 * APICs), nlvt is "3" (LINT0, LINT1, and timer) 376 */ 377 378 if (apic_cpus[cpun].aci_local_ver < APIC_INTEGRATED_VERS) { 379 nlvt = 3; 380 } else { 381 nlvt = ((apic_reg_ops->apic_read(APIC_VERS_REG) >> 16) & 382 0xFF) + 1; 383 } 384 385 if (nlvt >= 5) { 386 /* Enable performance counter overflow interrupt */ 387 388 if (!is_x86_feature(x86_featureset, X86FSET_MSR)) 389 apic_enable_cpcovf_intr = 0; 390 if (apic_enable_cpcovf_intr) { 391 if (apic_cpcovf_vect == 0) { 392 int ipl = APIC_PCINT_IPL; 393 int irq = apic_get_ipivect(ipl, -1); 394 395 ASSERT(irq != -1); 396 apic_cpcovf_vect = 397 apic_irq_table[irq]->airq_vector; 398 ASSERT(apic_cpcovf_vect); 399 (void) add_avintr(NULL, ipl, 400 (avfunc)kcpc_hw_overflow_intr, 401 "apic pcint", irq, NULL, NULL, NULL, NULL); 402 kcpc_hw_overflow_intr_installed = 1; 403 kcpc_hw_enable_cpc_intr = 404 apic_cpcovf_mask_clear; 405 } 406 apic_reg_ops->apic_write(APIC_PCINT_VECT, 407 apic_cpcovf_vect); 408 } 409 } 410 411 if (nlvt >= 6) { 412 /* Only mask TM intr if the BIOS apparently doesn't use it */ 413 414 uint32_t lvtval; 415 416 lvtval = apic_reg_ops->apic_read(APIC_THERM_VECT); 417 if (((lvtval & AV_MASK) == AV_MASK) || 418 ((lvtval & AV_DELIV_MODE) != AV_SMI)) { 419 apic_reg_ops->apic_write(APIC_THERM_VECT, 420 AV_MASK|APIC_RESV_IRQ); 421 } 422 } 423 424 /* Enable error interrupt */ 425 426 if (nlvt >= 4 && apic_enable_error_intr) { 427 if (apic_errvect == 0) { 428 int ipl = 0xf; /* get highest priority intr */ 429 int irq = apic_get_ipivect(ipl, -1); 430 431 ASSERT(irq != -1); 432 apic_errvect = apic_irq_table[irq]->airq_vector; 433 ASSERT(apic_errvect); 434 /* 435 * Not PSMI compliant, but we are going to merge 436 * with ON anyway 437 */ 438 (void) add_avintr((void *)NULL, ipl, 439 (avfunc)apic_error_intr, "apic error intr", 440 irq, NULL, NULL, NULL, NULL); 441 } 442 apic_reg_ops->apic_write(APIC_ERR_VECT, apic_errvect); 443 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0); 444 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0); 445 } 446 447 /* 448 * Ensure a CMCI interrupt is allocated, regardless of whether it is 449 * enabled or not. 450 */ 451 if (apic_cmci_vect == 0) { 452 const int ipl = 0x2; 453 int irq = apic_get_ipivect(ipl, -1); 454 455 ASSERT(irq != -1); 456 apic_cmci_vect = apic_irq_table[irq]->airq_vector; 457 ASSERT(apic_cmci_vect); 458 459 (void) add_avintr(NULL, ipl, 460 (avfunc)cmi_cmci_trap, 461 "apic cmci intr", irq, NULL, NULL, NULL, NULL); 462 } 463 } 464 465 static void 466 apic_picinit(void) 467 { 468 int i, j; 469 uint_t isr; 470 471 /* 472 * Initialize and enable interrupt remapping before apic 473 * hardware initialization 474 */ 475 apic_intrmap_init(apic_mode); 476 477 /* 478 * On UniSys Model 6520, the BIOS leaves vector 0x20 isr 479 * bit on without clearing it with EOI. Since softint 480 * uses vector 0x20 to interrupt itself, so softint will 481 * not work on this machine. In order to fix this problem 482 * a check is made to verify all the isr bits are clear. 483 * If not, EOIs are issued to clear the bits. 484 */ 485 for (i = 7; i >= 1; i--) { 486 isr = apic_reg_ops->apic_read(APIC_ISR_REG + (i * 4)); 487 if (isr != 0) 488 for (j = 0; ((j < 32) && (isr != 0)); j++) 489 if (isr & (1 << j)) { 490 apic_reg_ops->apic_write( 491 APIC_EOI_REG, 0); 492 isr &= ~(1 << j); 493 apic_error |= APIC_ERR_BOOT_EOI; 494 } 495 } 496 497 /* set a flag so we know we have run apic_picinit() */ 498 apic_picinit_called = 1; 499 LOCK_INIT_CLEAR(&apic_gethrtime_lock); 500 LOCK_INIT_CLEAR(&apic_ioapic_lock); 501 LOCK_INIT_CLEAR(&apic_error_lock); 502 LOCK_INIT_CLEAR(&apic_mode_switch_lock); 503 504 picsetup(); /* initialise the 8259 */ 505 506 /* add nmi handler - least priority nmi handler */ 507 LOCK_INIT_CLEAR(&apic_nmi_lock); 508 509 if (!psm_add_nmintr(0, (avfunc) apic_nmi_intr, 510 "pcplusmp NMI handler", (caddr_t)NULL)) 511 cmn_err(CE_WARN, "pcplusmp: Unable to add nmi handler"); 512 513 /* 514 * Check for directed-EOI capability in the local APIC. 515 */ 516 if (apic_directed_EOI_supported() == 1) { 517 apic_set_directed_EOI_handler(); 518 } 519 520 apic_init_intr(); 521 522 /* enable apic mode if imcr present */ 523 if (apic_imcrp) { 524 outb(APIC_IMCR_P1, (uchar_t)APIC_IMCR_SELECT); 525 outb(APIC_IMCR_P2, (uchar_t)APIC_IMCR_APIC); 526 } 527 528 ioapic_init_intr(IOAPIC_MASK); 529 } 530 531 #ifdef DEBUG 532 void 533 apic_break(void) 534 { 535 } 536 #endif /* DEBUG */ 537 538 /* 539 * platform_intr_enter 540 * 541 * Called at the beginning of the interrupt service routine to 542 * mask all level equal to and below the interrupt priority 543 * of the interrupting vector. An EOI should be given to 544 * the interrupt controller to enable other HW interrupts. 545 * 546 * Return -1 for spurious interrupts 547 * 548 */ 549 /*ARGSUSED*/ 550 static int 551 apic_intr_enter(int ipl, int *vectorp) 552 { 553 uchar_t vector; 554 int nipl; 555 int irq; 556 ulong_t iflag; 557 apic_cpus_info_t *cpu_infop; 558 559 /* 560 * The real vector delivered is (*vectorp + 0x20), but our caller 561 * subtracts 0x20 from the vector before passing it to us. 562 * (That's why APIC_BASE_VECT is 0x20.) 563 */ 564 vector = (uchar_t)*vectorp; 565 566 /* if interrupted by the clock, increment apic_nsec_since_boot */ 567 if (vector == apic_clkvect) { 568 if (!apic_oneshot) { 569 /* NOTE: this is not MT aware */ 570 apic_hrtime_stamp++; 571 apic_nsec_since_boot += apic_nsec_per_intr; 572 apic_hrtime_stamp++; 573 last_count_read = apic_hertz_count; 574 apic_redistribute_compute(); 575 } 576 577 /* We will avoid all the book keeping overhead for clock */ 578 nipl = apic_ipls[vector]; 579 580 *vectorp = apic_vector_to_irq[vector + APIC_BASE_VECT]; 581 582 apic_reg_ops->apic_write_task_reg(apic_ipltopri[nipl]); 583 apic_reg_ops->apic_send_eoi(0); 584 585 return (nipl); 586 } 587 588 cpu_infop = &apic_cpus[psm_get_cpu_id()]; 589 590 if (vector == (APIC_SPUR_INTR - APIC_BASE_VECT)) { 591 cpu_infop->aci_spur_cnt++; 592 return (APIC_INT_SPURIOUS); 593 } 594 595 /* Check if the vector we got is really what we need */ 596 if (apic_revector_pending) { 597 /* 598 * Disable interrupts for the duration of 599 * the vector translation to prevent a self-race for 600 * the apic_revector_lock. This cannot be done 601 * in apic_xlate_vector because it is recursive and 602 * we want the vector translation to be atomic with 603 * respect to other (higher-priority) interrupts. 604 */ 605 iflag = intr_clear(); 606 vector = apic_xlate_vector(vector + APIC_BASE_VECT) - 607 APIC_BASE_VECT; 608 intr_restore(iflag); 609 } 610 611 nipl = apic_ipls[vector]; 612 *vectorp = irq = apic_vector_to_irq[vector + APIC_BASE_VECT]; 613 614 apic_reg_ops->apic_write_task_reg(apic_ipltopri[nipl]); 615 616 cpu_infop->aci_current[nipl] = (uchar_t)irq; 617 cpu_infop->aci_curipl = (uchar_t)nipl; 618 cpu_infop->aci_ISR_in_progress |= 1 << nipl; 619 620 /* 621 * apic_level_intr could have been assimilated into the irq struct. 622 * but, having it as a character array is more efficient in terms of 623 * cache usage. So, we leave it as is. 624 */ 625 if (!apic_level_intr[irq]) { 626 apic_reg_ops->apic_send_eoi(0); 627 } 628 629 #ifdef DEBUG 630 APIC_DEBUG_BUF_PUT(vector); 631 APIC_DEBUG_BUF_PUT(irq); 632 APIC_DEBUG_BUF_PUT(nipl); 633 APIC_DEBUG_BUF_PUT(psm_get_cpu_id()); 634 if ((apic_stretch_interrupts) && (apic_stretch_ISR & (1 << nipl))) 635 drv_usecwait(apic_stretch_interrupts); 636 637 if (apic_break_on_cpu == psm_get_cpu_id()) 638 apic_break(); 639 #endif /* DEBUG */ 640 return (nipl); 641 } 642 643 void 644 apic_intr_exit(int prev_ipl, int irq) 645 { 646 apic_cpus_info_t *cpu_infop; 647 648 apic_reg_ops->apic_write_task_reg(apic_ipltopri[prev_ipl]); 649 650 cpu_infop = &apic_cpus[psm_get_cpu_id()]; 651 if (apic_level_intr[irq]) 652 apic_reg_ops->apic_send_eoi(irq); 653 cpu_infop->aci_curipl = (uchar_t)prev_ipl; 654 /* ISR above current pri could not be in progress */ 655 cpu_infop->aci_ISR_in_progress &= (2 << prev_ipl) - 1; 656 } 657 658 intr_exit_fn_t 659 psm_intr_exit_fn(void) 660 { 661 return (apic_intr_exit); 662 } 663 664 /* 665 * Mask all interrupts below or equal to the given IPL. 666 */ 667 static void 668 apic_setspl(int ipl) 669 { 670 apic_reg_ops->apic_write_task_reg(apic_ipltopri[ipl]); 671 672 /* interrupts at ipl above this cannot be in progress */ 673 apic_cpus[psm_get_cpu_id()].aci_ISR_in_progress &= (2 << ipl) - 1; 674 /* 675 * this is a patch fix for the ALR QSMP P5 machine, so that interrupts 676 * have enough time to come in before the priority is raised again 677 * during the idle() loop. 678 */ 679 if (apic_setspl_delay) 680 (void) apic_reg_ops->apic_get_pri(); 681 } 682 683 /*ARGSUSED*/ 684 static int 685 apic_addspl(int irqno, int ipl, int min_ipl, int max_ipl) 686 { 687 return (apic_addspl_common(irqno, ipl, min_ipl, max_ipl)); 688 } 689 690 static int 691 apic_delspl(int irqno, int ipl, int min_ipl, int max_ipl) 692 { 693 return (apic_delspl_common(irqno, ipl, min_ipl, max_ipl)); 694 } 695 696 static int 697 apic_post_cpu_start(void) 698 { 699 int cpun; 700 static int cpus_started = 1; 701 702 /* We know this CPU + BSP started successfully. */ 703 cpus_started++; 704 705 splx(ipltospl(LOCK_LEVEL)); 706 apic_init_intr(); 707 708 /* 709 * since some systems don't enable the internal cache on the non-boot 710 * cpus, so we have to enable them here 711 */ 712 setcr0(getcr0() & ~(CR0_CD | CR0_NW)); 713 714 APIC_AV_PENDING_SET(); 715 716 /* 717 * We may be booting, or resuming from suspend; aci_status will 718 * be APIC_CPU_INTR_ENABLE if coming from suspend, so we add the 719 * APIC_CPU_ONLINE flag here rather than setting aci_status completely. 720 */ 721 cpun = psm_get_cpu_id(); 722 apic_cpus[cpun].aci_status |= APIC_CPU_ONLINE; 723 724 apic_reg_ops->apic_write(APIC_DIVIDE_REG, apic_divide_reg_init); 725 return (PSM_SUCCESS); 726 } 727 728 /* 729 * type == -1 indicates it is an internal request. Do not change 730 * resv_vector for these requests 731 */ 732 static int 733 apic_get_ipivect(int ipl, int type) 734 { 735 uchar_t vector; 736 int irq; 737 738 if ((irq = apic_allocate_irq(APIC_VECTOR(ipl))) != -1) { 739 if ((vector = apic_allocate_vector(ipl, irq, 1))) { 740 apic_irq_table[irq]->airq_mps_intr_index = 741 RESERVE_INDEX; 742 apic_irq_table[irq]->airq_vector = vector; 743 if (type != -1) { 744 apic_resv_vector[ipl] = vector; 745 } 746 return (irq); 747 } 748 } 749 apic_error |= APIC_ERR_GET_IPIVECT_FAIL; 750 return (-1); /* shouldn't happen */ 751 } 752 753 static int 754 apic_getclkirq(int ipl) 755 { 756 int irq; 757 758 if ((irq = apic_get_ipivect(ipl, -1)) == -1) 759 return (-1); 760 /* 761 * Note the vector in apic_clkvect for per clock handling. 762 */ 763 apic_clkvect = apic_irq_table[irq]->airq_vector - APIC_BASE_VECT; 764 APIC_VERBOSE_IOAPIC((CE_NOTE, "get_clkirq: vector = %x\n", 765 apic_clkvect)); 766 return (irq); 767 } 768 769 /* 770 * Try and disable all interrupts. We just assign interrupts to other 771 * processors based on policy. If any were bound by user request, we 772 * let them continue and return failure. We do not bother to check 773 * for cache affinity while rebinding. 774 */ 775 776 static int 777 apic_disable_intr(processorid_t cpun) 778 { 779 int bind_cpu = 0, i, hardbound = 0; 780 apic_irq_t *irq_ptr; 781 ulong_t iflag; 782 783 iflag = intr_clear(); 784 lock_set(&apic_ioapic_lock); 785 786 for (i = 0; i <= APIC_MAX_VECTOR; i++) { 787 if (apic_reprogram_info[i].done == B_FALSE) { 788 if (apic_reprogram_info[i].bindcpu == cpun) { 789 /* 790 * CPU is busy -- it's the target of 791 * a pending reprogramming attempt 792 */ 793 lock_clear(&apic_ioapic_lock); 794 intr_restore(iflag); 795 return (PSM_FAILURE); 796 } 797 } 798 } 799 800 apic_cpus[cpun].aci_status &= ~APIC_CPU_INTR_ENABLE; 801 802 apic_cpus[cpun].aci_curipl = 0; 803 804 i = apic_min_device_irq; 805 for (; i <= apic_max_device_irq; i++) { 806 /* 807 * If there are bound interrupts on this cpu, then 808 * rebind them to other processors. 809 */ 810 if ((irq_ptr = apic_irq_table[i]) != NULL) { 811 ASSERT((irq_ptr->airq_temp_cpu == IRQ_UNBOUND) || 812 (irq_ptr->airq_temp_cpu == IRQ_UNINIT) || 813 (apic_cpu_in_range(irq_ptr->airq_temp_cpu))); 814 815 if (irq_ptr->airq_temp_cpu == (cpun | IRQ_USER_BOUND)) { 816 hardbound = 1; 817 continue; 818 } 819 820 if (irq_ptr->airq_temp_cpu == cpun) { 821 do { 822 bind_cpu = 823 apic_find_cpu(APIC_CPU_INTR_ENABLE); 824 } while (apic_rebind_all(irq_ptr, bind_cpu)); 825 } 826 } 827 } 828 829 lock_clear(&apic_ioapic_lock); 830 intr_restore(iflag); 831 832 if (hardbound) { 833 cmn_err(CE_WARN, "Could not disable interrupts on %d" 834 "due to user bound interrupts", cpun); 835 return (PSM_FAILURE); 836 } 837 else 838 return (PSM_SUCCESS); 839 } 840 841 /* 842 * Bind interrupts to the CPU's local APIC. 843 * Interrupts should not be bound to a CPU's local APIC until the CPU 844 * is ready to receive interrupts. 845 */ 846 static void 847 apic_enable_intr(processorid_t cpun) 848 { 849 int i; 850 apic_irq_t *irq_ptr; 851 ulong_t iflag; 852 853 iflag = intr_clear(); 854 lock_set(&apic_ioapic_lock); 855 856 apic_cpus[cpun].aci_status |= APIC_CPU_INTR_ENABLE; 857 858 i = apic_min_device_irq; 859 for (i = apic_min_device_irq; i <= apic_max_device_irq; i++) { 860 if ((irq_ptr = apic_irq_table[i]) != NULL) { 861 if ((irq_ptr->airq_cpu & ~IRQ_USER_BOUND) == cpun) { 862 (void) apic_rebind_all(irq_ptr, 863 irq_ptr->airq_cpu); 864 } 865 } 866 } 867 868 if (apic_cpus[cpun].aci_status & APIC_CPU_SUSPEND) 869 apic_cpus[cpun].aci_status &= ~APIC_CPU_SUSPEND; 870 871 lock_clear(&apic_ioapic_lock); 872 intr_restore(iflag); 873 } 874 875 /* 876 * If this module needs a periodic handler for the interrupt distribution, it 877 * can be added here. The argument to the periodic handler is not currently 878 * used, but is reserved for future. 879 */ 880 static void 881 apic_post_cyclic_setup(void *arg) 882 { 883 _NOTE(ARGUNUSED(arg)) 884 885 cyc_handler_t cyh; 886 cyc_time_t cyt; 887 888 /* cpu_lock is held */ 889 /* set up a periodic handler for intr redistribution */ 890 891 /* 892 * In peridoc mode intr redistribution processing is done in 893 * apic_intr_enter during clk intr processing 894 */ 895 if (!apic_oneshot) 896 return; 897 898 /* 899 * Register a periodical handler for the redistribution processing. 900 * Though we would generally prefer to use the DDI interface for 901 * periodic handler invocation, ddi_periodic_add(9F), we are 902 * unfortunately already holding cpu_lock, which ddi_periodic_add will 903 * attempt to take for us. Thus, we add our own cyclic directly: 904 */ 905 cyh.cyh_func = (void (*)(void *))apic_redistribute_compute; 906 cyh.cyh_arg = NULL; 907 cyh.cyh_level = CY_LOW_LEVEL; 908 909 cyt.cyt_when = 0; 910 cyt.cyt_interval = apic_redistribute_sample_interval; 911 912 apic_cyclic_id = cyclic_add(&cyh, &cyt); 913 } 914 915 static void 916 apic_redistribute_compute(void) 917 { 918 int i, j, max_busy; 919 920 if (apic_enable_dynamic_migration) { 921 if (++apic_nticks == apic_sample_factor_redistribution) { 922 /* 923 * Time to call apic_intr_redistribute(). 924 * reset apic_nticks. This will cause max_busy 925 * to be calculated below and if it is more than 926 * apic_int_busy, we will do the whole thing 927 */ 928 apic_nticks = 0; 929 } 930 max_busy = 0; 931 for (i = 0; i < apic_nproc; i++) { 932 if (!apic_cpu_in_range(i)) 933 continue; 934 935 /* 936 * Check if curipl is non zero & if ISR is in 937 * progress 938 */ 939 if (((j = apic_cpus[i].aci_curipl) != 0) && 940 (apic_cpus[i].aci_ISR_in_progress & (1 << j))) { 941 942 int irq; 943 apic_cpus[i].aci_busy++; 944 irq = apic_cpus[i].aci_current[j]; 945 apic_irq_table[irq]->airq_busy++; 946 } 947 948 if (!apic_nticks && 949 (apic_cpus[i].aci_busy > max_busy)) 950 max_busy = apic_cpus[i].aci_busy; 951 } 952 if (!apic_nticks) { 953 if (max_busy > apic_int_busy_mark) { 954 /* 955 * We could make the following check be 956 * skipped > 1 in which case, we get a 957 * redistribution at half the busy mark (due to 958 * double interval). Need to be able to collect 959 * more empirical data to decide if that is a 960 * good strategy. Punt for now. 961 */ 962 if (apic_skipped_redistribute) { 963 apic_cleanup_busy(); 964 apic_skipped_redistribute = 0; 965 } else { 966 apic_intr_redistribute(); 967 } 968 } else 969 apic_skipped_redistribute++; 970 } 971 } 972 } 973 974 975 /* 976 * The following functions are in the platform specific file so that they 977 * can be different functions depending on whether we are running on 978 * bare metal or a hypervisor. 979 */ 980 981 /* 982 * Check to make sure there are enough irq slots 983 */ 984 int 985 apic_check_free_irqs(int count) 986 { 987 int i, avail; 988 989 avail = 0; 990 for (i = APIC_FIRST_FREE_IRQ; i < APIC_RESV_IRQ; i++) { 991 if ((apic_irq_table[i] == NULL) || 992 apic_irq_table[i]->airq_mps_intr_index == FREE_INDEX) { 993 if (++avail >= count) 994 return (PSM_SUCCESS); 995 } 996 } 997 return (PSM_FAILURE); 998 } 999 1000 /* 1001 * This function allocates "count" MSI vector(s) for the given "dip/pri/type" 1002 */ 1003 int 1004 apic_alloc_msi_vectors(dev_info_t *dip, int inum, int count, int pri, 1005 int behavior) 1006 { 1007 int rcount, i; 1008 uchar_t start, irqno; 1009 uint32_t cpu = 0; 1010 major_t major; 1011 apic_irq_t *irqptr; 1012 1013 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: dip=0x%p " 1014 "inum=0x%x pri=0x%x count=0x%x behavior=%d\n", 1015 (void *)dip, inum, pri, count, behavior)); 1016 1017 if (count > 1) { 1018 if (behavior == DDI_INTR_ALLOC_STRICT && 1019 apic_multi_msi_enable == 0) 1020 return (0); 1021 if (apic_multi_msi_enable == 0) 1022 count = 1; 1023 } 1024 1025 if ((rcount = apic_navail_vector(dip, pri)) > count) 1026 rcount = count; 1027 else if (rcount == 0 || (rcount < count && 1028 behavior == DDI_INTR_ALLOC_STRICT)) 1029 return (0); 1030 1031 /* if not ISP2, then round it down */ 1032 if (!ISP2(rcount)) 1033 rcount = 1 << (highbit(rcount) - 1); 1034 1035 mutex_enter(&airq_mutex); 1036 1037 for (start = 0; rcount > 0; rcount >>= 1) { 1038 if ((start = apic_find_multi_vectors(pri, rcount)) != 0 || 1039 behavior == DDI_INTR_ALLOC_STRICT) 1040 break; 1041 } 1042 1043 if (start == 0) { 1044 /* no vector available */ 1045 mutex_exit(&airq_mutex); 1046 return (0); 1047 } 1048 1049 if (apic_check_free_irqs(rcount) == PSM_FAILURE) { 1050 /* not enough free irq slots available */ 1051 mutex_exit(&airq_mutex); 1052 return (0); 1053 } 1054 1055 major = (dip != NULL) ? ddi_driver_major(dip) : 0; 1056 for (i = 0; i < rcount; i++) { 1057 if ((irqno = apic_allocate_irq(apic_first_avail_irq)) == 1058 (uchar_t)-1) { 1059 /* 1060 * shouldn't happen because of the 1061 * apic_check_free_irqs() check earlier 1062 */ 1063 mutex_exit(&airq_mutex); 1064 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: " 1065 "apic_allocate_irq failed\n")); 1066 return (i); 1067 } 1068 apic_max_device_irq = max(irqno, apic_max_device_irq); 1069 apic_min_device_irq = min(irqno, apic_min_device_irq); 1070 irqptr = apic_irq_table[irqno]; 1071 #ifdef DEBUG 1072 if (apic_vector_to_irq[start + i] != APIC_RESV_IRQ) 1073 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: " 1074 "apic_vector_to_irq is not APIC_RESV_IRQ\n")); 1075 #endif 1076 apic_vector_to_irq[start + i] = (uchar_t)irqno; 1077 1078 irqptr->airq_vector = (uchar_t)(start + i); 1079 irqptr->airq_ioapicindex = (uchar_t)inum; /* start */ 1080 irqptr->airq_intin_no = (uchar_t)rcount; 1081 ASSERT(pri >= 0 && pri <= UCHAR_MAX); 1082 irqptr->airq_ipl = (uchar_t)pri; 1083 irqptr->airq_vector = start + i; 1084 irqptr->airq_origirq = (uchar_t)(inum + i); 1085 irqptr->airq_share_id = 0; 1086 irqptr->airq_mps_intr_index = MSI_INDEX; 1087 irqptr->airq_dip = dip; 1088 irqptr->airq_major = major; 1089 if (i == 0) /* they all bound to the same cpu */ 1090 cpu = irqptr->airq_cpu = apic_bind_intr(dip, irqno, 1091 0xff, 0xff); 1092 else 1093 irqptr->airq_cpu = cpu; 1094 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: irq=0x%x " 1095 "dip=0x%p vector=0x%x origirq=0x%x pri=0x%x\n", irqno, 1096 (void *)irqptr->airq_dip, irqptr->airq_vector, 1097 irqptr->airq_origirq, pri)); 1098 } 1099 mutex_exit(&airq_mutex); 1100 return (rcount); 1101 } 1102 1103 /* 1104 * This function allocates "count" MSI-X vector(s) for the given "dip/pri/type" 1105 */ 1106 int 1107 apic_alloc_msix_vectors(dev_info_t *dip, int inum, int count, int pri, 1108 int behavior) 1109 { 1110 int rcount, i; 1111 major_t major; 1112 1113 mutex_enter(&airq_mutex); 1114 1115 if ((rcount = apic_navail_vector(dip, pri)) > count) 1116 rcount = count; 1117 else if (rcount == 0 || (rcount < count && 1118 behavior == DDI_INTR_ALLOC_STRICT)) { 1119 rcount = 0; 1120 goto out; 1121 } 1122 1123 if (apic_check_free_irqs(rcount) == PSM_FAILURE) { 1124 /* not enough free irq slots available */ 1125 rcount = 0; 1126 goto out; 1127 } 1128 1129 major = (dip != NULL) ? ddi_driver_major(dip) : 0; 1130 for (i = 0; i < rcount; i++) { 1131 uchar_t vector, irqno; 1132 apic_irq_t *irqptr; 1133 1134 if ((irqno = apic_allocate_irq(apic_first_avail_irq)) == 1135 (uchar_t)-1) { 1136 /* 1137 * shouldn't happen because of the 1138 * apic_check_free_irqs() check earlier 1139 */ 1140 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msix_vectors: " 1141 "apic_allocate_irq failed\n")); 1142 rcount = i; 1143 goto out; 1144 } 1145 if ((vector = apic_allocate_vector(pri, irqno, 1)) == 0) { 1146 /* 1147 * shouldn't happen because of the 1148 * apic_navail_vector() call earlier 1149 */ 1150 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msix_vectors: " 1151 "apic_allocate_vector failed\n")); 1152 rcount = i; 1153 goto out; 1154 } 1155 apic_max_device_irq = max(irqno, apic_max_device_irq); 1156 apic_min_device_irq = min(irqno, apic_min_device_irq); 1157 irqptr = apic_irq_table[irqno]; 1158 irqptr->airq_vector = (uchar_t)vector; 1159 ASSERT(pri >= 0 && pri <= UCHAR_MAX); 1160 irqptr->airq_ipl = (uchar_t)pri; 1161 irqptr->airq_origirq = (uchar_t)(inum + i); 1162 irqptr->airq_share_id = 0; 1163 irqptr->airq_mps_intr_index = MSIX_INDEX; 1164 irqptr->airq_dip = dip; 1165 irqptr->airq_major = major; 1166 irqptr->airq_cpu = apic_bind_intr(dip, irqno, 0xff, 0xff); 1167 } 1168 out: 1169 mutex_exit(&airq_mutex); 1170 return (rcount); 1171 } 1172 1173 /* 1174 * Allocate a free vector for irq at ipl. Takes care of merging of multiple 1175 * IPLs into a single APIC level as well as stretching some IPLs onto multiple 1176 * levels. APIC_HI_PRI_VECTS interrupts are reserved for high priority 1177 * requests and allocated only when pri is set. 1178 */ 1179 uchar_t 1180 apic_allocate_vector(int ipl, int irq, int pri) 1181 { 1182 int lowest, highest, i; 1183 1184 highest = apic_ipltopri[ipl] + APIC_VECTOR_MASK; 1185 lowest = apic_ipltopri[ipl - 1] + APIC_VECTOR_PER_IPL; 1186 1187 if (highest < lowest) /* Both ipl and ipl - 1 map to same pri */ 1188 lowest -= APIC_VECTOR_PER_IPL; 1189 1190 #ifdef DEBUG 1191 if (apic_restrict_vector) /* for testing shared interrupt logic */ 1192 highest = lowest + apic_restrict_vector + APIC_HI_PRI_VECTS; 1193 #endif /* DEBUG */ 1194 if (pri == 0) 1195 highest -= APIC_HI_PRI_VECTS; 1196 1197 for (i = lowest; i <= highest; i++) { 1198 if (APIC_CHECK_RESERVE_VECTORS(i)) 1199 continue; 1200 if (apic_vector_to_irq[i] == APIC_RESV_IRQ) { 1201 apic_vector_to_irq[i] = (uchar_t)irq; 1202 ASSERT(i >= 0 && i <= UCHAR_MAX); 1203 return ((uchar_t)i); 1204 } 1205 } 1206 1207 return (0); 1208 } 1209 1210 /* Mark vector as not being used by any irq */ 1211 void 1212 apic_free_vector(uchar_t vector) 1213 { 1214 apic_vector_to_irq[vector] = APIC_RESV_IRQ; 1215 } 1216 1217 /* 1218 * Call rebind to do the actual programming. 1219 * Must be called with interrupts disabled and apic_ioapic_lock held 1220 * 'p' is polymorphic -- if this function is called to process a deferred 1221 * reprogramming, p is of type 'struct ioapic_reprogram_data *', from which 1222 * the irq pointer is retrieved. If not doing deferred reprogramming, 1223 * p is of the type 'apic_irq_t *'. 1224 * 1225 * apic_ioapic_lock must be held across this call, as it protects apic_rebind 1226 * and it protects apic_get_next_bind_cpu() from a race in which a CPU can be 1227 * taken offline after a cpu is selected, but before apic_rebind is called to 1228 * bind interrupts to it. 1229 */ 1230 int 1231 apic_setup_io_intr(void *p, int irq, boolean_t deferred) 1232 { 1233 apic_irq_t *irqptr; 1234 struct ioapic_reprogram_data *drep = NULL; 1235 int rv; 1236 1237 if (deferred) { 1238 drep = (struct ioapic_reprogram_data *)p; 1239 ASSERT(drep != NULL); 1240 irqptr = drep->irqp; 1241 } else 1242 irqptr = (apic_irq_t *)p; 1243 1244 ASSERT(irqptr != NULL); 1245 1246 rv = apic_rebind(irqptr, apic_irq_table[irq]->airq_cpu, drep); 1247 if (rv) { 1248 /* 1249 * CPU is not up or interrupts are disabled. Fall back to 1250 * the first available CPU 1251 */ 1252 rv = apic_rebind(irqptr, apic_find_cpu(APIC_CPU_INTR_ENABLE), 1253 drep); 1254 } 1255 1256 return (rv); 1257 } 1258 1259 1260 uchar_t 1261 apic_modify_vector(uchar_t vector, int irq) 1262 { 1263 apic_vector_to_irq[vector] = (uchar_t)irq; 1264 return (vector); 1265 } 1266 1267 char * 1268 apic_get_apic_type(void) 1269 { 1270 return (apic_psm_info.p_mach_idstring); 1271 } 1272 1273 void 1274 apic_switch_ipi_callback(boolean_t enter) 1275 { 1276 ASSERT(enter == B_TRUE); 1277 } 1278 1279 int 1280 apic_detect_x2apic(void) 1281 { 1282 return (0); 1283 } 1284 1285 void 1286 apic_enable_x2apic(void) 1287 { 1288 cmn_err(CE_PANIC, "apic_enable_x2apic() called in pcplusmp"); 1289 } 1290 1291 void 1292 x2apic_update_psm(void) 1293 { 1294 cmn_err(CE_PANIC, "x2apic_update_psm() called in pcplusmp"); 1295 } 1296