1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright (c) 2007, 2010, Oracle and/or its affiliates. All rights reserved. 23 * Copyright 2016 Nexenta Systems, Inc. 24 * Copyright (c) 2017 by Delphix. All rights reserved. 25 * Copyright 2017 Joyent, Inc. 26 */ 27 /* 28 * Copyright (c) 2010, Intel Corporation. 29 * All rights reserved. 30 */ 31 32 /* 33 * PSMI 1.1 extensions are supported only in 2.6 and later versions. 34 * PSMI 1.2 extensions are supported only in 2.7 and later versions. 35 * PSMI 1.3 and 1.4 extensions are supported in Solaris 10. 36 * PSMI 1.5 extensions are supported in Solaris Nevada. 37 * PSMI 1.6 extensions are supported in Solaris Nevada. 38 * PSMI 1.7 extensions are supported in Solaris Nevada. 39 */ 40 #define PSMI_1_7 41 42 #include <sys/processor.h> 43 #include <sys/time.h> 44 #include <sys/psm.h> 45 #include <sys/smp_impldefs.h> 46 #include <sys/cram.h> 47 #include <sys/acpi/acpi.h> 48 #include <sys/acpica.h> 49 #include <sys/psm_common.h> 50 #include <sys/apic.h> 51 #include <sys/apic_timer.h> 52 #include <sys/pit.h> 53 #include <sys/ddi.h> 54 #include <sys/sunddi.h> 55 #include <sys/ddi_impldefs.h> 56 #include <sys/pci.h> 57 #include <sys/promif.h> 58 #include <sys/x86_archext.h> 59 #include <sys/cpc_impl.h> 60 #include <sys/uadmin.h> 61 #include <sys/panic.h> 62 #include <sys/debug.h> 63 #include <sys/archsystm.h> 64 #include <sys/trap.h> 65 #include <sys/machsystm.h> 66 #include <sys/cpuvar.h> 67 #include <sys/rm_platter.h> 68 #include <sys/privregs.h> 69 #include <sys/cyclic.h> 70 #include <sys/note.h> 71 #include <sys/pci_intr_lib.h> 72 #include <sys/sunndi.h> 73 #if !defined(__xpv) 74 #include <sys/hpet.h> 75 #include <sys/clock.h> 76 #endif 77 78 /* 79 * Local Function Prototypes 80 */ 81 static int apic_handle_defconf(); 82 static int apic_parse_mpct(caddr_t mpct, int bypass); 83 static struct apic_mpfps_hdr *apic_find_fps_sig(caddr_t fptr, int size); 84 static int apic_checksum(caddr_t bptr, int len); 85 static int apic_find_bus_type(char *bus); 86 static int apic_find_bus(int busid); 87 static struct apic_io_intr *apic_find_io_intr(int irqno); 88 static int apic_find_free_irq(int start, int end); 89 struct apic_io_intr *apic_find_io_intr_w_busid(int irqno, int busid); 90 static void apic_set_pwroff_method_from_mpcnfhdr(struct apic_mp_cnf_hdr *hdrp); 91 static void apic_free_apic_cpus(void); 92 static boolean_t apic_is_ioapic_AMD_813x(uint32_t physaddr); 93 static int apic_acpi_enter_apicmode(void); 94 95 int apic_handle_pci_pci_bridge(dev_info_t *idip, int child_devno, 96 int child_ipin, struct apic_io_intr **intrp); 97 int apic_find_bus_id(int bustype); 98 int apic_find_intin(uchar_t ioapic, uchar_t intin); 99 void apic_record_rdt_entry(apic_irq_t *irqptr, int irq); 100 101 int apic_debug_mps_id = 0; /* 1 - print MPS ID strings */ 102 103 /* ACPI SCI interrupt configuration; -1 if SCI not used */ 104 int apic_sci_vect = -1; 105 iflag_t apic_sci_flags; 106 107 #if !defined(__xpv) 108 /* ACPI HPET interrupt configuration; -1 if HPET not used */ 109 int apic_hpet_vect = -1; 110 iflag_t apic_hpet_flags; 111 #endif 112 113 /* 114 * psm name pointer 115 */ 116 char *psm_name; 117 118 /* ACPI support routines */ 119 static int acpi_probe(char *); 120 static int apic_acpi_irq_configure(acpi_psm_lnk_t *acpipsmlnkp, dev_info_t *dip, 121 int *pci_irqp, iflag_t *intr_flagp); 122 123 int apic_acpi_translate_pci_irq(dev_info_t *dip, int busid, int devid, 124 int ipin, int *pci_irqp, iflag_t *intr_flagp); 125 uchar_t acpi_find_ioapic(int irq); 126 static int acpi_intr_compatible(iflag_t iflag1, iflag_t iflag2); 127 128 /* Max wait time (in repetitions) for flags to clear in an RDT entry. */ 129 int apic_max_reps_clear_pending = 1000; 130 131 int apic_intr_policy = INTR_ROUND_ROBIN; 132 133 int apic_next_bind_cpu = 1; /* For round robin assignment */ 134 /* start with cpu 1 */ 135 136 /* 137 * If enabled, the distribution works as follows: 138 * On every interrupt entry, the current ipl for the CPU is set in cpu_info 139 * and the irq corresponding to the ipl is also set in the aci_current array. 140 * interrupt exit and setspl (due to soft interrupts) will cause the current 141 * ipl to be be changed. This is cache friendly as these frequently used 142 * paths write into a per cpu structure. 143 * 144 * Sampling is done by checking the structures for all CPUs and incrementing 145 * the busy field of the irq (if any) executing on each CPU and the busy field 146 * of the corresponding CPU. 147 * In periodic mode this is done on every clock interrupt. 148 * In one-shot mode, this is done thru a cyclic with an interval of 149 * apic_redistribute_sample_interval (default 10 milli sec). 150 * 151 * Every apic_sample_factor_redistribution times we sample, we do computations 152 * to decide which interrupt needs to be migrated (see comments 153 * before apic_intr_redistribute(). 154 */ 155 156 /* 157 * Following 3 variables start as % and can be patched or set using an 158 * API to be defined in future. They will be scaled to 159 * sample_factor_redistribution which is in turn set to hertz+1 (in periodic 160 * mode), or 101 in one-shot mode to stagger it away from one sec processing 161 */ 162 163 int apic_int_busy_mark = 60; 164 int apic_int_free_mark = 20; 165 int apic_diff_for_redistribution = 10; 166 167 /* sampling interval for interrupt redistribution for dynamic migration */ 168 int apic_redistribute_sample_interval = NANOSEC / 100; /* 10 millisec */ 169 170 /* 171 * number of times we sample before deciding to redistribute interrupts 172 * for dynamic migration 173 */ 174 int apic_sample_factor_redistribution = 101; 175 176 int apic_redist_cpu_skip = 0; 177 int apic_num_imbalance = 0; 178 int apic_num_rebind = 0; 179 180 /* 181 * Maximum number of APIC CPUs in the system, -1 indicates that dynamic 182 * allocation of CPU ids is disabled. 183 */ 184 int apic_max_nproc = -1; 185 int apic_nproc = 0; 186 size_t apic_cpus_size = 0; 187 int apic_defconf = 0; 188 int apic_irq_translate = 0; 189 int apic_spec_rev = 0; 190 int apic_imcrp = 0; 191 192 int apic_use_acpi = 1; /* 1 = use ACPI, 0 = don't use ACPI */ 193 int apic_use_acpi_madt_only = 0; /* 1=ONLY use MADT from ACPI */ 194 195 /* 196 * For interrupt link devices, if apic_unconditional_srs is set, an irq resource 197 * will be assigned (via _SRS). If it is not set, use the current 198 * irq setting (via _CRS), but only if that irq is in the set of possible 199 * irqs (returned by _PRS) for the device. 200 */ 201 int apic_unconditional_srs = 1; 202 203 /* 204 * For interrupt link devices, if apic_prefer_crs is set when we are 205 * assigning an IRQ resource to a device, prefer the current IRQ setting 206 * over other possible irq settings under same conditions. 207 */ 208 209 int apic_prefer_crs = 1; 210 211 uchar_t apic_io_id[MAX_IO_APIC]; 212 volatile uint32_t *apicioadr[MAX_IO_APIC]; 213 uchar_t apic_io_ver[MAX_IO_APIC]; 214 uchar_t apic_io_vectbase[MAX_IO_APIC]; 215 uchar_t apic_io_vectend[MAX_IO_APIC]; 216 uchar_t apic_reserved_irqlist[MAX_ISA_IRQ + 1]; 217 uint32_t apic_physaddr[MAX_IO_APIC]; 218 219 boolean_t ioapic_mask_workaround[MAX_IO_APIC]; 220 221 /* 222 * First available slot to be used as IRQ index into the apic_irq_table 223 * for those interrupts (like MSI/X) that don't have a physical IRQ. 224 */ 225 int apic_first_avail_irq = APIC_FIRST_FREE_IRQ; 226 227 /* 228 * apic_ioapic_lock protects the ioapics (reg select), the status, temp_bound 229 * and bound elements of cpus_info and the temp_cpu element of irq_struct 230 */ 231 lock_t apic_ioapic_lock; 232 233 int apic_io_max = 0; /* no. of i/o apics enabled */ 234 235 struct apic_io_intr *apic_io_intrp = NULL; 236 static struct apic_bus *apic_busp; 237 238 uchar_t apic_resv_vector[MAXIPL+1]; 239 240 char apic_level_intr[APIC_MAX_VECTOR+1]; 241 242 uint32_t eisa_level_intr_mask = 0; 243 /* At least MSB will be set if EISA bus */ 244 245 int apic_pci_bus_total = 0; 246 uchar_t apic_single_pci_busid = 0; 247 248 /* 249 * airq_mutex protects additions to the apic_irq_table - the first 250 * pointer and any airq_nexts off of that one. It also protects 251 * apic_max_device_irq & apic_min_device_irq. It also guarantees 252 * that share_id is unique as new ids are generated only when new 253 * irq_t structs are linked in. Once linked in the structs are never 254 * deleted. temp_cpu & mps_intr_index field indicate if it is programmed 255 * or allocated. Note that there is a slight gap between allocating in 256 * apic_introp_xlate and programming in addspl. 257 */ 258 kmutex_t airq_mutex; 259 apic_irq_t *apic_irq_table[APIC_MAX_VECTOR+1]; 260 int apic_max_device_irq = 0; 261 int apic_min_device_irq = APIC_MAX_VECTOR; 262 263 typedef struct prs_irq_list_ent { 264 int list_prio; 265 int32_t irq; 266 iflag_t intrflags; 267 acpi_prs_private_t prsprv; 268 struct prs_irq_list_ent *next; 269 } prs_irq_list_t; 270 271 272 /* 273 * ACPI variables 274 */ 275 /* 1 = acpi is enabled & working, 0 = acpi is not enabled or not there */ 276 int apic_enable_acpi = 0; 277 278 /* ACPI Multiple APIC Description Table ptr */ 279 static ACPI_TABLE_MADT *acpi_mapic_dtp = NULL; 280 281 /* ACPI Interrupt Source Override Structure ptr */ 282 ACPI_MADT_INTERRUPT_OVERRIDE *acpi_isop = NULL; 283 int acpi_iso_cnt = 0; 284 285 /* ACPI Non-maskable Interrupt Sources ptr */ 286 static ACPI_MADT_NMI_SOURCE *acpi_nmi_sp = NULL; 287 static int acpi_nmi_scnt = 0; 288 static ACPI_MADT_LOCAL_APIC_NMI *acpi_nmi_cp = NULL; 289 static int acpi_nmi_ccnt = 0; 290 291 static boolean_t acpi_found_smp_config = B_FALSE; 292 293 /* 294 * The following added to identify a software poweroff method if available. 295 */ 296 297 static struct { 298 int poweroff_method; 299 char oem_id[APIC_MPS_OEM_ID_LEN + 1]; /* MAX + 1 for NULL */ 300 char prod_id[APIC_MPS_PROD_ID_LEN + 1]; /* MAX + 1 for NULL */ 301 } apic_mps_ids[] = { 302 { APIC_POWEROFF_VIA_RTC, "INTEL", "ALDER" }, /* 4300 */ 303 { APIC_POWEROFF_VIA_RTC, "NCR", "AMC" }, /* 4300 */ 304 { APIC_POWEROFF_VIA_ASPEN_BMC, "INTEL", "A450NX" }, /* 4400? */ 305 { APIC_POWEROFF_VIA_ASPEN_BMC, "INTEL", "AD450NX" }, /* 4400 */ 306 { APIC_POWEROFF_VIA_ASPEN_BMC, "INTEL", "AC450NX" }, /* 4400R */ 307 { APIC_POWEROFF_VIA_SITKA_BMC, "INTEL", "S450NX" }, /* S50 */ 308 { APIC_POWEROFF_VIA_SITKA_BMC, "INTEL", "SC450NX" } /* S50? */ 309 }; 310 311 int apic_poweroff_method = APIC_POWEROFF_NONE; 312 313 /* 314 * Auto-configuration routines 315 */ 316 317 /* 318 * Look at MPSpec 1.4 (Intel Order # 242016-005) for details of what we do here 319 * May work with 1.1 - but not guaranteed. 320 * According to the MP Spec, the MP floating pointer structure 321 * will be searched in the order described below: 322 * 1. In the first kilobyte of Extended BIOS Data Area (EBDA) 323 * 2. Within the last kilobyte of system base memory 324 * 3. In the BIOS ROM address space between 0F0000h and 0FFFFh 325 * Once we find the right signature with proper checksum, we call 326 * either handle_defconf or parse_mpct to get all info necessary for 327 * subsequent operations. 328 */ 329 int 330 apic_probe_common(char *modname) 331 { 332 uint32_t mpct_addr, ebda_start = 0, base_mem_end; 333 caddr_t biosdatap; 334 caddr_t mpct = NULL; 335 caddr_t fptr; 336 int i, mpct_size = 0, mapsize, retval = PSM_FAILURE; 337 ushort_t ebda_seg, base_mem_size; 338 struct apic_mpfps_hdr *fpsp; 339 struct apic_mp_cnf_hdr *hdrp; 340 int bypass_cpu_and_ioapics_in_mptables; 341 int acpi_user_options; 342 343 if (apic_forceload < 0) 344 return (retval); 345 346 /* 347 * Remember who we are 348 */ 349 psm_name = modname; 350 351 /* Allow override for MADT-only mode */ 352 acpi_user_options = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_root_node(), 0, 353 "acpi-user-options", 0); 354 apic_use_acpi_madt_only = ((acpi_user_options & ACPI_OUSER_MADT) != 0); 355 356 /* Allow apic_use_acpi to override MADT-only mode */ 357 if (!apic_use_acpi) 358 apic_use_acpi_madt_only = 0; 359 360 retval = acpi_probe(modname); 361 362 /* in UEFI system, there is no BIOS data */ 363 if (ddi_prop_exists(DDI_DEV_T_ANY, ddi_root_node(), 0, "efi-systab")) 364 goto apic_ret; 365 366 /* 367 * mapin the bios data area 40:0 368 * 40:13h - two-byte location reports the base memory size 369 * 40:0Eh - two-byte location for the exact starting address of 370 * the EBDA segment for EISA 371 */ 372 biosdatap = psm_map_phys(0x400, 0x20, PROT_READ); 373 if (!biosdatap) 374 goto apic_ret; 375 fpsp = (struct apic_mpfps_hdr *)NULL; 376 mapsize = MPFPS_RAM_WIN_LEN; 377 /*LINTED: pointer cast may result in improper alignment */ 378 ebda_seg = *((ushort_t *)(biosdatap+0xe)); 379 /* check the 1k of EBDA */ 380 if (ebda_seg) { 381 ebda_start = ((uint32_t)ebda_seg) << 4; 382 fptr = psm_map_phys(ebda_start, MPFPS_RAM_WIN_LEN, PROT_READ); 383 if (fptr) { 384 if (!(fpsp = 385 apic_find_fps_sig(fptr, MPFPS_RAM_WIN_LEN))) 386 psm_unmap_phys(fptr, MPFPS_RAM_WIN_LEN); 387 } 388 } 389 /* If not in EBDA, check the last k of system base memory */ 390 if (!fpsp) { 391 /*LINTED: pointer cast may result in improper alignment */ 392 base_mem_size = *((ushort_t *)(biosdatap + 0x13)); 393 394 if (base_mem_size > 512) 395 base_mem_end = 639 * 1024; 396 else 397 base_mem_end = 511 * 1024; 398 /* if ebda == last k of base mem, skip to check BIOS ROM */ 399 if (base_mem_end != ebda_start) { 400 401 fptr = psm_map_phys(base_mem_end, MPFPS_RAM_WIN_LEN, 402 PROT_READ); 403 404 if (fptr) { 405 if (!(fpsp = apic_find_fps_sig(fptr, 406 MPFPS_RAM_WIN_LEN))) 407 psm_unmap_phys(fptr, MPFPS_RAM_WIN_LEN); 408 } 409 } 410 } 411 psm_unmap_phys(biosdatap, 0x20); 412 413 /* If still cannot find it, check the BIOS ROM space */ 414 if (!fpsp) { 415 mapsize = MPFPS_ROM_WIN_LEN; 416 fptr = psm_map_phys(MPFPS_ROM_WIN_START, 417 MPFPS_ROM_WIN_LEN, PROT_READ); 418 if (fptr) { 419 if (!(fpsp = 420 apic_find_fps_sig(fptr, MPFPS_ROM_WIN_LEN))) { 421 psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN); 422 goto apic_ret; 423 } 424 } 425 } 426 427 if (apic_checksum((caddr_t)fpsp, fpsp->mpfps_length * 16) != 0) { 428 psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN); 429 goto apic_ret; 430 } 431 432 apic_spec_rev = fpsp->mpfps_spec_rev; 433 if ((apic_spec_rev != 04) && (apic_spec_rev != 01)) { 434 psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN); 435 goto apic_ret; 436 } 437 438 /* check IMCR is present or not */ 439 apic_imcrp = fpsp->mpfps_featinfo2 & MPFPS_FEATINFO2_IMCRP; 440 441 /* check default configuration (dual CPUs) */ 442 if ((apic_defconf = fpsp->mpfps_featinfo1) != 0) { 443 psm_unmap_phys(fptr, mapsize); 444 if ((retval = apic_handle_defconf()) != PSM_SUCCESS) 445 return (retval); 446 447 goto apic_ret; 448 } 449 450 /* MP Configuration Table */ 451 mpct_addr = (uint32_t)(fpsp->mpfps_mpct_paddr); 452 453 psm_unmap_phys(fptr, mapsize); /* unmap floating ptr struct */ 454 455 /* 456 * Map in enough memory for the MP Configuration Table Header. 457 * Use this table to read the total length of the BIOS data and 458 * map in all the info 459 */ 460 /*LINTED: pointer cast may result in improper alignment */ 461 hdrp = (struct apic_mp_cnf_hdr *)psm_map_phys(mpct_addr, 462 sizeof (struct apic_mp_cnf_hdr), PROT_READ); 463 if (!hdrp) 464 goto apic_ret; 465 466 /* check mp configuration table signature PCMP */ 467 if (hdrp->mpcnf_sig != 0x504d4350) { 468 psm_unmap_phys((caddr_t)hdrp, sizeof (struct apic_mp_cnf_hdr)); 469 goto apic_ret; 470 } 471 mpct_size = (int)hdrp->mpcnf_tbl_length; 472 473 apic_set_pwroff_method_from_mpcnfhdr(hdrp); 474 475 psm_unmap_phys((caddr_t)hdrp, sizeof (struct apic_mp_cnf_hdr)); 476 477 if ((retval == PSM_SUCCESS) && !apic_use_acpi_madt_only) { 478 /* This is an ACPI machine No need for further checks */ 479 goto apic_ret; 480 } 481 482 /* 483 * Map in the entries for this machine, ie. Processor 484 * Entry Tables, Bus Entry Tables, etc. 485 * They are in fixed order following one another 486 */ 487 mpct = psm_map_phys(mpct_addr, mpct_size, PROT_READ); 488 if (!mpct) 489 goto apic_ret; 490 491 if (apic_checksum(mpct, mpct_size) != 0) 492 goto apic_fail1; 493 494 /*LINTED: pointer cast may result in improper alignment */ 495 hdrp = (struct apic_mp_cnf_hdr *)mpct; 496 apicadr = (uint32_t *)mapin_apic((uint32_t)hdrp->mpcnf_local_apic, 497 APIC_LOCAL_MEMLEN, PROT_READ | PROT_WRITE); 498 if (!apicadr) 499 goto apic_fail1; 500 501 /* Parse all information in the tables */ 502 bypass_cpu_and_ioapics_in_mptables = (retval == PSM_SUCCESS); 503 if (apic_parse_mpct(mpct, bypass_cpu_and_ioapics_in_mptables) == 504 PSM_SUCCESS) { 505 retval = PSM_SUCCESS; 506 goto apic_ret; 507 } 508 509 apic_fail1: 510 psm_unmap_phys(mpct, mpct_size); 511 mpct = NULL; 512 513 apic_ret: 514 if (retval == PSM_SUCCESS) { 515 extern int apic_ioapic_method_probe(); 516 517 if ((retval = apic_ioapic_method_probe()) == PSM_SUCCESS) 518 return (PSM_SUCCESS); 519 } 520 521 for (i = 0; i < apic_io_max; i++) 522 mapout_ioapic((caddr_t)apicioadr[i], APIC_IO_MEMLEN); 523 if (apic_cpus) { 524 kmem_free(apic_cpus, apic_cpus_size); 525 apic_cpus = NULL; 526 } 527 if (apicadr) { 528 mapout_apic((caddr_t)apicadr, APIC_LOCAL_MEMLEN); 529 apicadr = NULL; 530 } 531 if (mpct) 532 psm_unmap_phys(mpct, mpct_size); 533 534 return (retval); 535 } 536 537 static void 538 apic_set_pwroff_method_from_mpcnfhdr(struct apic_mp_cnf_hdr *hdrp) 539 { 540 int i; 541 542 for (i = 0; i < (sizeof (apic_mps_ids) / sizeof (apic_mps_ids[0])); 543 i++) { 544 if ((strncmp(hdrp->mpcnf_oem_str, apic_mps_ids[i].oem_id, 545 strlen(apic_mps_ids[i].oem_id)) == 0) && 546 (strncmp(hdrp->mpcnf_prod_str, apic_mps_ids[i].prod_id, 547 strlen(apic_mps_ids[i].prod_id)) == 0)) { 548 549 apic_poweroff_method = apic_mps_ids[i].poweroff_method; 550 break; 551 } 552 } 553 554 if (apic_debug_mps_id != 0) { 555 cmn_err(CE_CONT, "%s: MPS OEM ID = '%c%c%c%c%c%c%c%c'" 556 "Product ID = '%c%c%c%c%c%c%c%c%c%c%c%c'\n", 557 psm_name, 558 hdrp->mpcnf_oem_str[0], 559 hdrp->mpcnf_oem_str[1], 560 hdrp->mpcnf_oem_str[2], 561 hdrp->mpcnf_oem_str[3], 562 hdrp->mpcnf_oem_str[4], 563 hdrp->mpcnf_oem_str[5], 564 hdrp->mpcnf_oem_str[6], 565 hdrp->mpcnf_oem_str[7], 566 hdrp->mpcnf_prod_str[0], 567 hdrp->mpcnf_prod_str[1], 568 hdrp->mpcnf_prod_str[2], 569 hdrp->mpcnf_prod_str[3], 570 hdrp->mpcnf_prod_str[4], 571 hdrp->mpcnf_prod_str[5], 572 hdrp->mpcnf_prod_str[6], 573 hdrp->mpcnf_prod_str[7], 574 hdrp->mpcnf_prod_str[8], 575 hdrp->mpcnf_prod_str[9], 576 hdrp->mpcnf_prod_str[10], 577 hdrp->mpcnf_prod_str[11]); 578 } 579 } 580 581 static void 582 apic_free_apic_cpus(void) 583 { 584 if (apic_cpus != NULL) { 585 kmem_free(apic_cpus, apic_cpus_size); 586 apic_cpus = NULL; 587 apic_cpus_size = 0; 588 } 589 } 590 591 static int 592 acpi_probe(char *modname) 593 { 594 int i, intmax, index; 595 uint32_t id, ver; 596 int acpi_verboseflags = 0; 597 int madt_seen, madt_size; 598 ACPI_SUBTABLE_HEADER *ap; 599 ACPI_MADT_LOCAL_APIC *mpa; 600 ACPI_MADT_LOCAL_X2APIC *mpx2a; 601 ACPI_MADT_IO_APIC *mia; 602 ACPI_MADT_IO_SAPIC *misa; 603 ACPI_MADT_INTERRUPT_OVERRIDE *mio; 604 ACPI_MADT_NMI_SOURCE *mns; 605 ACPI_MADT_INTERRUPT_SOURCE *mis; 606 ACPI_MADT_LOCAL_APIC_NMI *mlan; 607 ACPI_MADT_LOCAL_X2APIC_NMI *mx2alan; 608 ACPI_MADT_LOCAL_APIC_OVERRIDE *mao; 609 int sci; 610 iflag_t sci_flags; 611 volatile uint32_t *ioapic; 612 int ioapic_ix; 613 uint32_t *local_ids; 614 uint32_t *proc_ids; 615 uchar_t hid; 616 int warned = 0; 617 618 if (!apic_use_acpi) 619 return (PSM_FAILURE); 620 621 if (AcpiGetTable(ACPI_SIG_MADT, 1, 622 (ACPI_TABLE_HEADER **) &acpi_mapic_dtp) != AE_OK) { 623 cmn_err(CE_WARN, "!acpi_probe: No MADT found!"); 624 return (PSM_FAILURE); 625 } 626 627 apicadr = mapin_apic((uint32_t)acpi_mapic_dtp->Address, 628 APIC_LOCAL_MEMLEN, PROT_READ | PROT_WRITE); 629 if (!apicadr) 630 return (PSM_FAILURE); 631 632 if ((local_ids = (uint32_t *)kmem_zalloc(NCPU * sizeof (uint32_t), 633 KM_NOSLEEP)) == NULL) 634 return (PSM_FAILURE); 635 636 if ((proc_ids = (uint32_t *)kmem_zalloc(NCPU * sizeof (uint32_t), 637 KM_NOSLEEP)) == NULL) { 638 kmem_free(local_ids, NCPU * sizeof (uint32_t)); 639 return (PSM_FAILURE); 640 } 641 642 id = apic_reg_ops->apic_read(APIC_LID_REG); 643 local_ids[0] = (uchar_t)(id >> 24); 644 apic_nproc = index = 1; 645 apic_io_max = 0; 646 647 ap = (ACPI_SUBTABLE_HEADER *) (acpi_mapic_dtp + 1); 648 madt_size = acpi_mapic_dtp->Header.Length; 649 madt_seen = sizeof (*acpi_mapic_dtp); 650 651 while (madt_seen < madt_size) { 652 switch (ap->Type) { 653 case ACPI_MADT_TYPE_LOCAL_APIC: 654 mpa = (ACPI_MADT_LOCAL_APIC *) ap; 655 if (mpa->LapicFlags & ACPI_MADT_ENABLED) { 656 if (mpa->Id == 255) { 657 cmn_err(CE_WARN, "!%s: encountered " 658 "invalid entry in MADT: CPU %d " 659 "has Local APIC Id equal to 255 ", 660 psm_name, mpa->ProcessorId); 661 } 662 if (mpa->Id == local_ids[0]) { 663 ASSERT(index == 1); 664 proc_ids[0] = mpa->ProcessorId; 665 } else if (apic_nproc < NCPU && use_mp && 666 apic_nproc < boot_ncpus) { 667 local_ids[index] = mpa->Id; 668 proc_ids[index] = mpa->ProcessorId; 669 index++; 670 apic_nproc++; 671 } else if (apic_nproc == NCPU && !warned) { 672 cmn_err(CE_WARN, "%s: CPU limit " 673 "exceeded" 674 #if !defined(__amd64) 675 " for 32-bit mode" 676 #endif 677 "; Solaris will use %d CPUs.", 678 psm_name, NCPU); 679 warned = 1; 680 } 681 } 682 break; 683 684 case ACPI_MADT_TYPE_IO_APIC: 685 mia = (ACPI_MADT_IO_APIC *) ap; 686 if (apic_io_max < MAX_IO_APIC) { 687 ioapic_ix = apic_io_max; 688 apic_io_id[apic_io_max] = mia->Id; 689 apic_io_vectbase[apic_io_max] = 690 mia->GlobalIrqBase; 691 apic_physaddr[apic_io_max] = 692 (uint32_t)mia->Address; 693 ioapic = apicioadr[apic_io_max] = 694 mapin_ioapic((uint32_t)mia->Address, 695 APIC_IO_MEMLEN, PROT_READ | PROT_WRITE); 696 if (!ioapic) 697 goto cleanup; 698 ioapic_mask_workaround[apic_io_max] = 699 apic_is_ioapic_AMD_813x(mia->Address); 700 apic_io_max++; 701 } 702 break; 703 704 case ACPI_MADT_TYPE_INTERRUPT_OVERRIDE: 705 mio = (ACPI_MADT_INTERRUPT_OVERRIDE *) ap; 706 if (acpi_isop == NULL) 707 acpi_isop = mio; 708 acpi_iso_cnt++; 709 break; 710 711 case ACPI_MADT_TYPE_NMI_SOURCE: 712 /* UNIMPLEMENTED */ 713 mns = (ACPI_MADT_NMI_SOURCE *) ap; 714 if (acpi_nmi_sp == NULL) 715 acpi_nmi_sp = mns; 716 acpi_nmi_scnt++; 717 718 cmn_err(CE_NOTE, "!apic: nmi source: %d 0x%x\n", 719 mns->GlobalIrq, mns->IntiFlags); 720 break; 721 722 case ACPI_MADT_TYPE_LOCAL_APIC_NMI: 723 /* UNIMPLEMENTED */ 724 mlan = (ACPI_MADT_LOCAL_APIC_NMI *) ap; 725 if (acpi_nmi_cp == NULL) 726 acpi_nmi_cp = mlan; 727 acpi_nmi_ccnt++; 728 729 cmn_err(CE_NOTE, "!apic: local nmi: %d 0x%x %d\n", 730 mlan->ProcessorId, mlan->IntiFlags, 731 mlan->Lint); 732 break; 733 734 case ACPI_MADT_TYPE_LOCAL_APIC_OVERRIDE: 735 /* UNIMPLEMENTED */ 736 mao = (ACPI_MADT_LOCAL_APIC_OVERRIDE *) ap; 737 cmn_err(CE_NOTE, "!apic: address override: %lx\n", 738 (long)mao->Address); 739 break; 740 741 case ACPI_MADT_TYPE_IO_SAPIC: 742 /* UNIMPLEMENTED */ 743 misa = (ACPI_MADT_IO_SAPIC *) ap; 744 745 cmn_err(CE_NOTE, "!apic: io sapic: %d %d %lx\n", 746 misa->Id, misa->GlobalIrqBase, 747 (long)misa->Address); 748 break; 749 750 case ACPI_MADT_TYPE_INTERRUPT_SOURCE: 751 /* UNIMPLEMENTED */ 752 mis = (ACPI_MADT_INTERRUPT_SOURCE *) ap; 753 754 cmn_err(CE_NOTE, 755 "!apic: irq source: %d %d %d 0x%x %d %d\n", 756 mis->Id, mis->Eid, mis->GlobalIrq, 757 mis->IntiFlags, mis->Type, 758 mis->IoSapicVector); 759 break; 760 761 case ACPI_MADT_TYPE_LOCAL_X2APIC: 762 mpx2a = (ACPI_MADT_LOCAL_X2APIC *) ap; 763 764 if (mpx2a->LapicFlags & ACPI_MADT_ENABLED) { 765 if (mpx2a->LocalApicId == local_ids[0]) { 766 ASSERT(index == 1); 767 proc_ids[0] = mpx2a->Uid; 768 } else if (apic_nproc < NCPU && use_mp && 769 apic_nproc < boot_ncpus) { 770 local_ids[index] = mpx2a->LocalApicId; 771 proc_ids[index] = mpx2a->Uid; 772 index++; 773 apic_nproc++; 774 } else if (apic_nproc == NCPU && !warned) { 775 cmn_err(CE_WARN, "%s: CPU limit " 776 "exceeded" 777 #if !defined(__amd64) 778 " for 32-bit mode" 779 #endif 780 "; Solaris will use %d CPUs.", 781 psm_name, NCPU); 782 warned = 1; 783 } 784 } 785 786 break; 787 788 case ACPI_MADT_TYPE_LOCAL_X2APIC_NMI: 789 /* UNIMPLEMENTED */ 790 mx2alan = (ACPI_MADT_LOCAL_X2APIC_NMI *) ap; 791 if (mx2alan->Uid >> 8) 792 acpi_nmi_ccnt++; 793 794 #ifdef DEBUG 795 cmn_err(CE_NOTE, 796 "!apic: local x2apic nmi: %d 0x%x %d\n", 797 mx2alan->Uid, mx2alan->IntiFlags, mx2alan->Lint); 798 #endif 799 800 break; 801 802 case ACPI_MADT_TYPE_RESERVED: 803 default: 804 break; 805 } 806 807 /* advance to next entry */ 808 madt_seen += ap->Length; 809 ap = (ACPI_SUBTABLE_HEADER *)(((char *)ap) + ap->Length); 810 } 811 812 /* We found multiple enabled cpus via MADT */ 813 if ((apic_nproc > 1) && (apic_io_max > 0)) { 814 acpi_found_smp_config = B_TRUE; 815 cmn_err(CE_NOTE, 816 "!apic: Using ACPI (MADT) for SMP configuration"); 817 } 818 819 /* 820 * allocate enough space for possible hot-adding of CPUs. 821 * max_ncpus may be less than apic_nproc if it's set by user. 822 */ 823 if (plat_dr_support_cpu()) { 824 apic_max_nproc = max_ncpus; 825 } 826 apic_cpus_size = max(apic_nproc, max_ncpus) * sizeof (*apic_cpus); 827 if ((apic_cpus = kmem_zalloc(apic_cpus_size, KM_NOSLEEP)) == NULL) 828 goto cleanup; 829 830 /* 831 * ACPI doesn't provide the local apic ver, get it directly from the 832 * local apic 833 */ 834 ver = apic_reg_ops->apic_read(APIC_VERS_REG); 835 for (i = 0; i < apic_nproc; i++) { 836 apic_cpus[i].aci_local_id = local_ids[i]; 837 apic_cpus[i].aci_local_ver = (uchar_t)(ver & 0xFF); 838 apic_cpus[i].aci_processor_id = proc_ids[i]; 839 /* Only build mapping info for CPUs present at boot. */ 840 if (i < boot_ncpus) 841 (void) acpica_map_cpu(i, proc_ids[i]); 842 } 843 844 /* 845 * To support CPU dynamic reconfiguration, the apic CPU info structure 846 * for each possible CPU will be pre-allocated at boot time. 847 * The state for each apic CPU info structure will be assigned according 848 * to the following rules: 849 * Rule 1: 850 * Slot index range: [0, min(apic_nproc, boot_ncpus)) 851 * State flags: 0 852 * Note: cpu exists and will be configured/enabled at boot time 853 * Rule 2: 854 * Slot index range: [boot_ncpus, apic_nproc) 855 * State flags: APIC_CPU_FREE | APIC_CPU_DIRTY 856 * Note: cpu exists but won't be configured/enabled at boot time 857 * Rule 3: 858 * Slot index range: [apic_nproc, boot_ncpus) 859 * State flags: APIC_CPU_FREE 860 * Note: cpu doesn't exist at boot time 861 * Rule 4: 862 * Slot index range: [max(apic_nproc, boot_ncpus), max_ncpus) 863 * State flags: APIC_CPU_FREE 864 * Note: cpu doesn't exist at boot time 865 */ 866 CPUSET_ZERO(apic_cpumask); 867 for (i = 0; i < min(boot_ncpus, apic_nproc); i++) { 868 CPUSET_ADD(apic_cpumask, i); 869 apic_cpus[i].aci_status = 0; 870 } 871 for (i = boot_ncpus; i < apic_nproc; i++) { 872 apic_cpus[i].aci_status = APIC_CPU_FREE | APIC_CPU_DIRTY; 873 } 874 for (i = apic_nproc; i < boot_ncpus; i++) { 875 apic_cpus[i].aci_status = APIC_CPU_FREE; 876 } 877 for (i = max(boot_ncpus, apic_nproc); i < max_ncpus; i++) { 878 apic_cpus[i].aci_status = APIC_CPU_FREE; 879 } 880 881 for (i = 0; i < apic_io_max; i++) { 882 ioapic_ix = i; 883 884 /* 885 * need to check Sitka on the following acpi problem 886 * On the Sitka, the ioapic's apic_id field isn't reporting 887 * the actual io apic id. We have reported this problem 888 * to Intel. Until they fix the problem, we will get the 889 * actual id directly from the ioapic. 890 */ 891 id = ioapic_read(ioapic_ix, APIC_ID_CMD); 892 hid = (uchar_t)(id >> 24); 893 894 if (hid != apic_io_id[i]) { 895 if (apic_io_id[i] == 0) 896 apic_io_id[i] = hid; 897 else { /* set ioapic id to whatever reported by ACPI */ 898 id = ((uint32_t)apic_io_id[i]) << 24; 899 ioapic_write(ioapic_ix, APIC_ID_CMD, id); 900 } 901 } 902 ver = ioapic_read(ioapic_ix, APIC_VERS_CMD); 903 apic_io_ver[i] = (uchar_t)(ver & 0xff); 904 intmax = (ver >> 16) & 0xff; 905 apic_io_vectend[i] = apic_io_vectbase[i] + intmax; 906 if (apic_first_avail_irq <= apic_io_vectend[i]) 907 apic_first_avail_irq = apic_io_vectend[i] + 1; 908 } 909 910 911 /* 912 * Process SCI configuration here 913 * An error may be returned here if 914 * acpi-user-options specifies legacy mode 915 * (no SCI, no ACPI mode) 916 */ 917 if (acpica_get_sci(&sci, &sci_flags) != AE_OK) 918 sci = -1; 919 920 /* 921 * Now call acpi_init() to generate namespaces 922 * If this fails, we don't attempt to use ACPI 923 * even if we were able to get a MADT above 924 */ 925 if (acpica_init() != AE_OK) { 926 cmn_err(CE_WARN, "!apic: Failed to initialize acpica!"); 927 goto cleanup; 928 } 929 930 /* 931 * Call acpica_build_processor_map() now that we have 932 * ACPI namesspace access 933 */ 934 (void) acpica_build_processor_map(); 935 936 /* 937 * Squirrel away the SCI and flags for later on 938 * in apic_picinit() when we're ready 939 */ 940 apic_sci_vect = sci; 941 apic_sci_flags = sci_flags; 942 943 if (apic_verbose & APIC_VERBOSE_IRQ_FLAG) 944 acpi_verboseflags |= PSM_VERBOSE_IRQ_FLAG; 945 946 if (apic_verbose & APIC_VERBOSE_POWEROFF_FLAG) 947 acpi_verboseflags |= PSM_VERBOSE_POWEROFF_FLAG; 948 949 if (apic_verbose & APIC_VERBOSE_POWEROFF_PAUSE_FLAG) 950 acpi_verboseflags |= PSM_VERBOSE_POWEROFF_PAUSE_FLAG; 951 952 if (acpi_psm_init(modname, acpi_verboseflags) == ACPI_PSM_FAILURE) 953 goto cleanup; 954 955 /* Enable ACPI APIC interrupt routing */ 956 if (apic_acpi_enter_apicmode() != PSM_FAILURE) { 957 cmn_err(CE_NOTE, "!apic: Using APIC interrupt routing mode"); 958 build_reserved_irqlist((uchar_t *)apic_reserved_irqlist); 959 apic_enable_acpi = 1; 960 if (apic_sci_vect > 0) { 961 acpica_set_core_feature(ACPI_FEATURE_SCI_EVENT); 962 } 963 if (apic_use_acpi_madt_only) { 964 cmn_err(CE_CONT, 965 "?Using ACPI for CPU/IOAPIC information ONLY\n"); 966 } 967 968 #if !defined(__xpv) 969 /* 970 * probe ACPI for hpet information here which is used later 971 * in apic_picinit(). 972 */ 973 if (hpet_acpi_init(&apic_hpet_vect, &apic_hpet_flags) < 0) { 974 cmn_err(CE_NOTE, "!ACPI HPET table query failed\n"); 975 } 976 #endif 977 978 kmem_free(local_ids, NCPU * sizeof (uint32_t)); 979 kmem_free(proc_ids, NCPU * sizeof (uint32_t)); 980 return (PSM_SUCCESS); 981 } 982 /* if setting APIC mode failed above, we fall through to cleanup */ 983 984 cleanup: 985 cmn_err(CE_WARN, "!apic: Failed acpi_probe, SMP config was %s", 986 acpi_found_smp_config ? "found" : "not found"); 987 apic_free_apic_cpus(); 988 if (apicadr != NULL) { 989 mapout_apic((caddr_t)apicadr, APIC_LOCAL_MEMLEN); 990 apicadr = NULL; 991 } 992 apic_max_nproc = -1; 993 apic_nproc = 0; 994 for (i = 0; i < apic_io_max; i++) { 995 mapout_ioapic((caddr_t)apicioadr[i], APIC_IO_MEMLEN); 996 apicioadr[i] = NULL; 997 } 998 apic_io_max = 0; 999 acpi_isop = NULL; 1000 acpi_iso_cnt = 0; 1001 acpi_nmi_sp = NULL; 1002 acpi_nmi_scnt = 0; 1003 acpi_nmi_cp = NULL; 1004 acpi_nmi_ccnt = 0; 1005 acpi_found_smp_config = B_FALSE; 1006 kmem_free(local_ids, NCPU * sizeof (uint32_t)); 1007 kmem_free(proc_ids, NCPU * sizeof (uint32_t)); 1008 return (PSM_FAILURE); 1009 } 1010 1011 /* 1012 * Handle default configuration. Fill in reqd global variables & tables 1013 * Fill all details as MP table does not give any more info 1014 */ 1015 static int 1016 apic_handle_defconf() 1017 { 1018 uint_t lid; 1019 1020 /* Failed to probe ACPI MADT tables, disable CPU DR. */ 1021 apic_max_nproc = -1; 1022 apic_free_apic_cpus(); 1023 plat_dr_disable_cpu(); 1024 1025 apicioadr[0] = (void *)mapin_ioapic(APIC_IO_ADDR, 1026 APIC_IO_MEMLEN, PROT_READ | PROT_WRITE); 1027 apicadr = (void *)psm_map_phys(APIC_LOCAL_ADDR, 1028 APIC_LOCAL_MEMLEN, PROT_READ); 1029 apic_cpus_size = 2 * sizeof (*apic_cpus); 1030 apic_cpus = (apic_cpus_info_t *) 1031 kmem_zalloc(apic_cpus_size, KM_NOSLEEP); 1032 if ((!apicadr) || (!apicioadr[0]) || (!apic_cpus)) 1033 goto apic_handle_defconf_fail; 1034 CPUSET_ONLY(apic_cpumask, 0); 1035 CPUSET_ADD(apic_cpumask, 1); 1036 apic_nproc = 2; 1037 lid = apic_reg_ops->apic_read(APIC_LID_REG); 1038 apic_cpus[0].aci_local_id = (uchar_t)(lid >> APIC_ID_BIT_OFFSET); 1039 /* 1040 * According to the PC+MP spec 1.1, the local ids 1041 * for the default configuration has to be 0 or 1 1042 */ 1043 if (apic_cpus[0].aci_local_id == 1) 1044 apic_cpus[1].aci_local_id = 0; 1045 else if (apic_cpus[0].aci_local_id == 0) 1046 apic_cpus[1].aci_local_id = 1; 1047 else 1048 goto apic_handle_defconf_fail; 1049 1050 apic_io_id[0] = 2; 1051 apic_io_max = 1; 1052 if (apic_defconf >= 5) { 1053 apic_cpus[0].aci_local_ver = APIC_INTEGRATED_VERS; 1054 apic_cpus[1].aci_local_ver = APIC_INTEGRATED_VERS; 1055 apic_io_ver[0] = APIC_INTEGRATED_VERS; 1056 } else { 1057 apic_cpus[0].aci_local_ver = 0; /* 82489 DX */ 1058 apic_cpus[1].aci_local_ver = 0; 1059 apic_io_ver[0] = 0; 1060 } 1061 if (apic_defconf == 2 || apic_defconf == 3 || apic_defconf == 6) 1062 eisa_level_intr_mask = (inb(EISA_LEVEL_CNTL + 1) << 8) | 1063 inb(EISA_LEVEL_CNTL) | ((uint_t)INT32_MAX + 1); 1064 return (PSM_SUCCESS); 1065 1066 apic_handle_defconf_fail: 1067 if (apicadr) 1068 mapout_apic((caddr_t)apicadr, APIC_LOCAL_MEMLEN); 1069 if (apicioadr[0]) 1070 mapout_ioapic((caddr_t)apicioadr[0], APIC_IO_MEMLEN); 1071 return (PSM_FAILURE); 1072 } 1073 1074 /* Parse the entries in MP configuration table and collect info that we need */ 1075 static int 1076 apic_parse_mpct(caddr_t mpct, int bypass_cpus_and_ioapics) 1077 { 1078 struct apic_procent *procp; 1079 struct apic_bus *busp; 1080 struct apic_io_entry *ioapicp; 1081 struct apic_io_intr *intrp; 1082 int ioapic_ix; 1083 uint_t lid; 1084 uint32_t id; 1085 uchar_t hid; 1086 int warned = 0; 1087 1088 /*LINTED: pointer cast may result in improper alignment */ 1089 procp = (struct apic_procent *)(mpct + sizeof (struct apic_mp_cnf_hdr)); 1090 1091 /* No need to count cpu entries if we won't use them */ 1092 if (!bypass_cpus_and_ioapics) { 1093 1094 /* Find max # of CPUS and allocate structure accordingly */ 1095 apic_nproc = 0; 1096 CPUSET_ZERO(apic_cpumask); 1097 while (procp->proc_entry == APIC_CPU_ENTRY) { 1098 if (procp->proc_cpuflags & CPUFLAGS_EN) { 1099 if (apic_nproc < NCPU && use_mp && 1100 apic_nproc < boot_ncpus) { 1101 CPUSET_ADD(apic_cpumask, apic_nproc); 1102 apic_nproc++; 1103 } else if (apic_nproc == NCPU && !warned) { 1104 cmn_err(CE_WARN, "%s: CPU limit " 1105 "exceeded" 1106 #if !defined(__amd64) 1107 " for 32-bit mode" 1108 #endif 1109 "; Solaris will use %d CPUs.", 1110 psm_name, NCPU); 1111 warned = 1; 1112 } 1113 1114 } 1115 procp++; 1116 } 1117 apic_cpus_size = apic_nproc * sizeof (*apic_cpus); 1118 if (!apic_nproc || !(apic_cpus = (apic_cpus_info_t *) 1119 kmem_zalloc(apic_cpus_size, KM_NOSLEEP))) 1120 return (PSM_FAILURE); 1121 } 1122 1123 /*LINTED: pointer cast may result in improper alignment */ 1124 procp = (struct apic_procent *)(mpct + sizeof (struct apic_mp_cnf_hdr)); 1125 1126 /* 1127 * start with index 1 as 0 needs to be filled in with Boot CPU, but 1128 * if we're bypassing this information, it has already been filled 1129 * in by acpi_probe(), so don't overwrite it. 1130 */ 1131 if (!bypass_cpus_and_ioapics) 1132 apic_nproc = 1; 1133 1134 while (procp->proc_entry == APIC_CPU_ENTRY) { 1135 /* check whether the cpu exists or not */ 1136 if (!bypass_cpus_and_ioapics && 1137 procp->proc_cpuflags & CPUFLAGS_EN) { 1138 if (procp->proc_cpuflags & CPUFLAGS_BP) { /* Boot CPU */ 1139 lid = apic_reg_ops->apic_read(APIC_LID_REG); 1140 apic_cpus[0].aci_local_id = procp->proc_apicid; 1141 if (apic_cpus[0].aci_local_id != 1142 (uchar_t)(lid >> APIC_ID_BIT_OFFSET)) { 1143 return (PSM_FAILURE); 1144 } 1145 apic_cpus[0].aci_local_ver = 1146 procp->proc_version; 1147 } else if (apic_nproc < NCPU && use_mp && 1148 apic_nproc < boot_ncpus) { 1149 apic_cpus[apic_nproc].aci_local_id = 1150 procp->proc_apicid; 1151 1152 apic_cpus[apic_nproc].aci_local_ver = 1153 procp->proc_version; 1154 apic_nproc++; 1155 1156 } 1157 } 1158 procp++; 1159 } 1160 1161 /* 1162 * Save start of bus entries for later use. 1163 * Get EISA level cntrl if EISA bus is present. 1164 * Also get the CPI bus id for single CPI bus case 1165 */ 1166 apic_busp = busp = (struct apic_bus *)procp; 1167 while (busp->bus_entry == APIC_BUS_ENTRY) { 1168 lid = apic_find_bus_type((char *)&busp->bus_str1); 1169 if (lid == BUS_EISA) { 1170 eisa_level_intr_mask = (inb(EISA_LEVEL_CNTL + 1) << 8) | 1171 inb(EISA_LEVEL_CNTL) | ((uint_t)INT32_MAX + 1); 1172 } else if (lid == BUS_PCI) { 1173 /* 1174 * apic_single_pci_busid will be used only if 1175 * apic_pic_bus_total is equal to 1 1176 */ 1177 apic_pci_bus_total++; 1178 apic_single_pci_busid = busp->bus_id; 1179 } 1180 busp++; 1181 } 1182 1183 ioapicp = (struct apic_io_entry *)busp; 1184 1185 if (!bypass_cpus_and_ioapics) 1186 apic_io_max = 0; 1187 do { 1188 if (!bypass_cpus_and_ioapics && apic_io_max < MAX_IO_APIC) { 1189 if (ioapicp->io_flags & IOAPIC_FLAGS_EN) { 1190 apic_io_id[apic_io_max] = ioapicp->io_apicid; 1191 apic_io_ver[apic_io_max] = ioapicp->io_version; 1192 apicioadr[apic_io_max] = 1193 (void *)mapin_ioapic( 1194 (uint32_t)ioapicp->io_apic_addr, 1195 APIC_IO_MEMLEN, PROT_READ | PROT_WRITE); 1196 1197 if (!apicioadr[apic_io_max]) 1198 return (PSM_FAILURE); 1199 1200 ioapic_mask_workaround[apic_io_max] = 1201 apic_is_ioapic_AMD_813x( 1202 ioapicp->io_apic_addr); 1203 1204 ioapic_ix = apic_io_max; 1205 id = ioapic_read(ioapic_ix, APIC_ID_CMD); 1206 hid = (uchar_t)(id >> 24); 1207 1208 if (hid != apic_io_id[apic_io_max]) { 1209 if (apic_io_id[apic_io_max] == 0) 1210 apic_io_id[apic_io_max] = hid; 1211 else { 1212 /* 1213 * set ioapic id to whatever 1214 * reported by MPS 1215 * 1216 * may not need to set index 1217 * again ??? 1218 * take it out and try 1219 */ 1220 1221 id = ((uint32_t) 1222 apic_io_id[apic_io_max]) << 1223 24; 1224 1225 ioapic_write(ioapic_ix, 1226 APIC_ID_CMD, id); 1227 } 1228 } 1229 apic_io_max++; 1230 } 1231 } 1232 ioapicp++; 1233 } while (ioapicp->io_entry == APIC_IO_ENTRY); 1234 1235 apic_io_intrp = (struct apic_io_intr *)ioapicp; 1236 1237 intrp = apic_io_intrp; 1238 while (intrp->intr_entry == APIC_IO_INTR_ENTRY) { 1239 if ((intrp->intr_irq > APIC_MAX_ISA_IRQ) || 1240 (apic_find_bus(intrp->intr_busid) == BUS_PCI)) { 1241 apic_irq_translate = 1; 1242 break; 1243 } 1244 intrp++; 1245 } 1246 1247 return (PSM_SUCCESS); 1248 } 1249 1250 boolean_t 1251 apic_cpu_in_range(int cpu) 1252 { 1253 cpu &= ~IRQ_USER_BOUND; 1254 /* Check whether cpu id is in valid range. */ 1255 if (cpu < 0 || cpu >= apic_nproc) { 1256 return (B_FALSE); 1257 } else if (apic_max_nproc != -1 && cpu >= apic_max_nproc) { 1258 /* 1259 * Check whether cpuid is in valid range if CPU DR is enabled. 1260 */ 1261 return (B_FALSE); 1262 } else if (!CPU_IN_SET(apic_cpumask, cpu)) { 1263 return (B_FALSE); 1264 } 1265 1266 return (B_TRUE); 1267 } 1268 1269 processorid_t 1270 apic_get_next_bind_cpu(void) 1271 { 1272 int i, count; 1273 processorid_t cpuid = 0; 1274 1275 for (count = 0; count < apic_nproc; count++) { 1276 if (apic_next_bind_cpu >= apic_nproc) { 1277 apic_next_bind_cpu = 0; 1278 } 1279 i = apic_next_bind_cpu++; 1280 if (apic_cpu_in_range(i)) { 1281 cpuid = i; 1282 break; 1283 } 1284 } 1285 1286 return (cpuid); 1287 } 1288 1289 uint16_t 1290 apic_get_apic_version() 1291 { 1292 int i; 1293 uchar_t min_io_apic_ver = 0; 1294 static uint16_t version; /* Cache as value is constant */ 1295 static boolean_t found = B_FALSE; /* Accomodate zero version */ 1296 1297 if (found == B_FALSE) { 1298 found = B_TRUE; 1299 1300 /* 1301 * Don't assume all IO APICs in the system are the same. 1302 * 1303 * Set to the minimum version. 1304 */ 1305 for (i = 0; i < apic_io_max; i++) { 1306 if ((apic_io_ver[i] != 0) && 1307 ((min_io_apic_ver == 0) || 1308 (min_io_apic_ver >= apic_io_ver[i]))) 1309 min_io_apic_ver = apic_io_ver[i]; 1310 } 1311 1312 /* Assume all local APICs are of the same version. */ 1313 version = (min_io_apic_ver << 8) | apic_cpus[0].aci_local_ver; 1314 } 1315 return (version); 1316 } 1317 1318 static struct apic_mpfps_hdr * 1319 apic_find_fps_sig(caddr_t cptr, int len) 1320 { 1321 int i; 1322 1323 /* Look for the pattern "_MP_" */ 1324 for (i = 0; i < len; i += 16) { 1325 if ((*(cptr+i) == '_') && 1326 (*(cptr+i+1) == 'M') && 1327 (*(cptr+i+2) == 'P') && 1328 (*(cptr+i+3) == '_')) 1329 /*LINTED: pointer cast may result in improper alignment */ 1330 return ((struct apic_mpfps_hdr *)(cptr + i)); 1331 } 1332 return (NULL); 1333 } 1334 1335 static int 1336 apic_checksum(caddr_t bptr, int len) 1337 { 1338 int i; 1339 uchar_t cksum; 1340 1341 cksum = 0; 1342 for (i = 0; i < len; i++) 1343 cksum += *bptr++; 1344 return ((int)cksum); 1345 } 1346 1347 /* 1348 * On machines with PCI-PCI bridges, a device behind a PCI-PCI bridge 1349 * needs special handling. We may need to chase up the device tree, 1350 * using the PCI-PCI Bridge specification's "rotating IPIN assumptions", 1351 * to find the IPIN at the root bus that relates to the IPIN on the 1352 * subsidiary bus (for ACPI or MP). We may, however, have an entry 1353 * in the MP table or the ACPI namespace for this device itself. 1354 * We handle both cases in the search below. 1355 */ 1356 /* this is the non-acpi version */ 1357 int 1358 apic_handle_pci_pci_bridge(dev_info_t *idip, int child_devno, int child_ipin, 1359 struct apic_io_intr **intrp) 1360 { 1361 dev_info_t *dipp, *dip; 1362 int pci_irq; 1363 ddi_acc_handle_t cfg_handle; 1364 int bridge_devno, bridge_bus; 1365 int ipin; 1366 1367 dip = idip; 1368 1369 /*CONSTCOND*/ 1370 while (1) { 1371 if (((dipp = ddi_get_parent(dip)) == (dev_info_t *)NULL) || 1372 (pci_config_setup(dipp, &cfg_handle) != DDI_SUCCESS)) 1373 return (-1); 1374 if ((pci_config_get8(cfg_handle, PCI_CONF_BASCLASS) == 1375 PCI_CLASS_BRIDGE) && (pci_config_get8(cfg_handle, 1376 PCI_CONF_SUBCLASS) == PCI_BRIDGE_PCI)) { 1377 pci_config_teardown(&cfg_handle); 1378 if (acpica_get_bdf(dipp, &bridge_bus, &bridge_devno, 1379 NULL) != 0) 1380 return (-1); 1381 /* 1382 * This is the rotating scheme documented in the 1383 * PCI-to-PCI spec. If the PCI-to-PCI bridge is 1384 * behind another PCI-to-PCI bridge, then it needs 1385 * to keep ascending until an interrupt entry is 1386 * found or the root is reached. 1387 */ 1388 ipin = (child_devno + child_ipin) % PCI_INTD; 1389 if (bridge_bus == 0 && apic_pci_bus_total == 1) 1390 bridge_bus = (int)apic_single_pci_busid; 1391 pci_irq = ((bridge_devno & 0x1f) << 2) | 1392 (ipin & 0x3); 1393 if ((*intrp = apic_find_io_intr_w_busid(pci_irq, 1394 bridge_bus)) != NULL) { 1395 return (pci_irq); 1396 } 1397 dip = dipp; 1398 child_devno = bridge_devno; 1399 child_ipin = ipin; 1400 } else { 1401 pci_config_teardown(&cfg_handle); 1402 return (-1); 1403 } 1404 } 1405 /*LINTED: function will not fall off the bottom */ 1406 } 1407 1408 uchar_t 1409 acpi_find_ioapic(int irq) 1410 { 1411 int i; 1412 1413 for (i = 0; i < apic_io_max; i++) { 1414 if (irq >= apic_io_vectbase[i] && irq <= apic_io_vectend[i]) 1415 return ((uchar_t)i); 1416 } 1417 return (0xFF); /* shouldn't happen */ 1418 } 1419 1420 /* 1421 * See if two irqs are compatible for sharing a vector. 1422 * Currently we only support sharing of PCI devices. 1423 */ 1424 static int 1425 acpi_intr_compatible(iflag_t iflag1, iflag_t iflag2) 1426 { 1427 uint_t level1, po1; 1428 uint_t level2, po2; 1429 1430 /* Assume active high by default */ 1431 po1 = 0; 1432 po2 = 0; 1433 1434 if (iflag1.bustype != iflag2.bustype || iflag1.bustype != BUS_PCI) 1435 return (0); 1436 1437 if (iflag1.intr_el == INTR_EL_CONFORM) 1438 level1 = AV_LEVEL; 1439 else 1440 level1 = (iflag1.intr_el == INTR_EL_LEVEL) ? AV_LEVEL : 0; 1441 1442 if (level1 && ((iflag1.intr_po == INTR_PO_ACTIVE_LOW) || 1443 (iflag1.intr_po == INTR_PO_CONFORM))) 1444 po1 = AV_ACTIVE_LOW; 1445 1446 if (iflag2.intr_el == INTR_EL_CONFORM) 1447 level2 = AV_LEVEL; 1448 else 1449 level2 = (iflag2.intr_el == INTR_EL_LEVEL) ? AV_LEVEL : 0; 1450 1451 if (level2 && ((iflag2.intr_po == INTR_PO_ACTIVE_LOW) || 1452 (iflag2.intr_po == INTR_PO_CONFORM))) 1453 po2 = AV_ACTIVE_LOW; 1454 1455 if ((level1 == level2) && (po1 == po2)) 1456 return (1); 1457 1458 return (0); 1459 } 1460 1461 struct apic_io_intr * 1462 apic_find_io_intr_w_busid(int irqno, int busid) 1463 { 1464 struct apic_io_intr *intrp; 1465 1466 /* 1467 * It can have more than 1 entry with same source bus IRQ, 1468 * but unique with the source bus id 1469 */ 1470 intrp = apic_io_intrp; 1471 if (intrp != NULL) { 1472 while (intrp->intr_entry == APIC_IO_INTR_ENTRY) { 1473 if (intrp->intr_irq == irqno && 1474 intrp->intr_busid == busid && 1475 intrp->intr_type == IO_INTR_INT) 1476 return (intrp); 1477 intrp++; 1478 } 1479 } 1480 APIC_VERBOSE_IOAPIC((CE_NOTE, "Did not find io intr for irqno:" 1481 "busid %x:%x\n", irqno, busid)); 1482 return ((struct apic_io_intr *)NULL); 1483 } 1484 1485 1486 struct mps_bus_info { 1487 char *bus_name; 1488 int bus_id; 1489 } bus_info_array[] = { 1490 "ISA ", BUS_ISA, 1491 "PCI ", BUS_PCI, 1492 "EISA ", BUS_EISA, 1493 "XPRESS", BUS_XPRESS, 1494 "PCMCIA", BUS_PCMCIA, 1495 "VL ", BUS_VL, 1496 "CBUS ", BUS_CBUS, 1497 "CBUSII", BUS_CBUSII, 1498 "FUTURE", BUS_FUTURE, 1499 "INTERN", BUS_INTERN, 1500 "MBI ", BUS_MBI, 1501 "MBII ", BUS_MBII, 1502 "MPI ", BUS_MPI, 1503 "MPSA ", BUS_MPSA, 1504 "NUBUS ", BUS_NUBUS, 1505 "TC ", BUS_TC, 1506 "VME ", BUS_VME, 1507 "PCI-E ", BUS_PCIE 1508 }; 1509 1510 static int 1511 apic_find_bus_type(char *bus) 1512 { 1513 int i = 0; 1514 1515 for (; i < sizeof (bus_info_array)/sizeof (struct mps_bus_info); i++) 1516 if (strncmp(bus, bus_info_array[i].bus_name, 1517 strlen(bus_info_array[i].bus_name)) == 0) 1518 return (bus_info_array[i].bus_id); 1519 APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus type for bus %s", bus)); 1520 return (0); 1521 } 1522 1523 static int 1524 apic_find_bus(int busid) 1525 { 1526 struct apic_bus *busp; 1527 1528 busp = apic_busp; 1529 while (busp->bus_entry == APIC_BUS_ENTRY) { 1530 if (busp->bus_id == busid) 1531 return (apic_find_bus_type((char *)&busp->bus_str1)); 1532 busp++; 1533 } 1534 APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus for bus id %x", busid)); 1535 return (0); 1536 } 1537 1538 int 1539 apic_find_bus_id(int bustype) 1540 { 1541 struct apic_bus *busp; 1542 1543 busp = apic_busp; 1544 while (busp->bus_entry == APIC_BUS_ENTRY) { 1545 if (apic_find_bus_type((char *)&busp->bus_str1) == bustype) 1546 return (busp->bus_id); 1547 busp++; 1548 } 1549 APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus id for bustype %x", 1550 bustype)); 1551 return (-1); 1552 } 1553 1554 /* 1555 * Check if a particular irq need to be reserved for any io_intr 1556 */ 1557 static struct apic_io_intr * 1558 apic_find_io_intr(int irqno) 1559 { 1560 struct apic_io_intr *intrp; 1561 1562 intrp = apic_io_intrp; 1563 if (intrp != NULL) { 1564 while (intrp->intr_entry == APIC_IO_INTR_ENTRY) { 1565 if (intrp->intr_irq == irqno && 1566 intrp->intr_type == IO_INTR_INT) 1567 return (intrp); 1568 intrp++; 1569 } 1570 } 1571 return ((struct apic_io_intr *)NULL); 1572 } 1573 1574 /* 1575 * Check if the given ioapicindex intin combination has already been assigned 1576 * an irq. If so return irqno. Else -1 1577 */ 1578 int 1579 apic_find_intin(uchar_t ioapic, uchar_t intin) 1580 { 1581 apic_irq_t *irqptr; 1582 int i; 1583 1584 /* find ioapic and intin in the apic_irq_table[] and return the index */ 1585 for (i = apic_min_device_irq; i <= apic_max_device_irq; i++) { 1586 irqptr = apic_irq_table[i]; 1587 while (irqptr) { 1588 if ((irqptr->airq_mps_intr_index >= 0) && 1589 (irqptr->airq_intin_no == intin) && 1590 (irqptr->airq_ioapicindex == ioapic)) { 1591 APIC_VERBOSE_IOAPIC((CE_NOTE, "!Found irq " 1592 "entry for ioapic:intin %x:%x " 1593 "shared interrupts ?", ioapic, intin)); 1594 return (i); 1595 } 1596 irqptr = irqptr->airq_next; 1597 } 1598 } 1599 return (-1); 1600 } 1601 1602 int 1603 apic_allocate_irq(int irq) 1604 { 1605 int freeirq, i; 1606 1607 if ((freeirq = apic_find_free_irq(irq, (APIC_RESV_IRQ - 1))) == -1) 1608 if ((freeirq = apic_find_free_irq(APIC_FIRST_FREE_IRQ, 1609 (irq - 1))) == -1) { 1610 /* 1611 * if BIOS really defines every single irq in the mps 1612 * table, then don't worry about conflicting with 1613 * them, just use any free slot in apic_irq_table 1614 */ 1615 for (i = APIC_FIRST_FREE_IRQ; i < APIC_RESV_IRQ; i++) { 1616 if ((apic_irq_table[i] == NULL) || 1617 apic_irq_table[i]->airq_mps_intr_index == 1618 FREE_INDEX) { 1619 freeirq = i; 1620 break; 1621 } 1622 } 1623 if (freeirq == -1) { 1624 /* This shouldn't happen, but just in case */ 1625 cmn_err(CE_WARN, "%s: NO available IRQ", psm_name); 1626 return (-1); 1627 } 1628 } 1629 if (apic_irq_table[freeirq] == NULL) { 1630 apic_irq_table[freeirq] = 1631 kmem_zalloc(sizeof (apic_irq_t), KM_NOSLEEP); 1632 if (apic_irq_table[freeirq] == NULL) { 1633 cmn_err(CE_WARN, "%s: NO memory to allocate IRQ", 1634 psm_name); 1635 return (-1); 1636 } 1637 apic_irq_table[freeirq]->airq_temp_cpu = IRQ_UNINIT; 1638 apic_irq_table[freeirq]->airq_mps_intr_index = FREE_INDEX; 1639 } 1640 return (freeirq); 1641 } 1642 1643 static int 1644 apic_find_free_irq(int start, int end) 1645 { 1646 int i; 1647 1648 for (i = start; i <= end; i++) 1649 /* Check if any I/O entry needs this IRQ */ 1650 if (apic_find_io_intr(i) == NULL) { 1651 /* Then see if it is free */ 1652 if ((apic_irq_table[i] == NULL) || 1653 (apic_irq_table[i]->airq_mps_intr_index == 1654 FREE_INDEX)) { 1655 return (i); 1656 } 1657 } 1658 return (-1); 1659 } 1660 1661 /* 1662 * compute the polarity, trigger mode and vector for programming into 1663 * the I/O apic and record in airq_rdt_entry. 1664 */ 1665 void 1666 apic_record_rdt_entry(apic_irq_t *irqptr, int irq) 1667 { 1668 int ioapicindex, bus_type, vector; 1669 short intr_index; 1670 uint_t level, po, io_po; 1671 struct apic_io_intr *iointrp; 1672 1673 intr_index = irqptr->airq_mps_intr_index; 1674 DDI_INTR_IMPLDBG((CE_CONT, "apic_record_rdt_entry: intr_index=%d " 1675 "irq = 0x%x dip = 0x%p vector = 0x%x\n", intr_index, irq, 1676 (void *)irqptr->airq_dip, irqptr->airq_vector)); 1677 1678 if (intr_index == RESERVE_INDEX) { 1679 apic_error |= APIC_ERR_INVALID_INDEX; 1680 return; 1681 } else if (APIC_IS_MSI_OR_MSIX_INDEX(intr_index)) { 1682 return; 1683 } 1684 1685 vector = irqptr->airq_vector; 1686 ioapicindex = irqptr->airq_ioapicindex; 1687 /* Assume edge triggered by default */ 1688 level = 0; 1689 /* Assume active high by default */ 1690 po = 0; 1691 1692 if (intr_index == DEFAULT_INDEX || intr_index == FREE_INDEX) { 1693 ASSERT(irq < 16); 1694 if (eisa_level_intr_mask & (1 << irq)) 1695 level = AV_LEVEL; 1696 if (intr_index == FREE_INDEX && apic_defconf == 0) 1697 apic_error |= APIC_ERR_INVALID_INDEX; 1698 } else if (intr_index == ACPI_INDEX) { 1699 bus_type = irqptr->airq_iflag.bustype; 1700 if (irqptr->airq_iflag.intr_el == INTR_EL_CONFORM) { 1701 if (bus_type == BUS_PCI) 1702 level = AV_LEVEL; 1703 } else 1704 level = (irqptr->airq_iflag.intr_el == INTR_EL_LEVEL) ? 1705 AV_LEVEL : 0; 1706 if (level && 1707 ((irqptr->airq_iflag.intr_po == INTR_PO_ACTIVE_LOW) || 1708 (irqptr->airq_iflag.intr_po == INTR_PO_CONFORM && 1709 bus_type == BUS_PCI))) 1710 po = AV_ACTIVE_LOW; 1711 } else { 1712 iointrp = apic_io_intrp + intr_index; 1713 bus_type = apic_find_bus(iointrp->intr_busid); 1714 if (iointrp->intr_el == INTR_EL_CONFORM) { 1715 if ((irq < 16) && (eisa_level_intr_mask & (1 << irq))) 1716 level = AV_LEVEL; 1717 else if (bus_type == BUS_PCI) 1718 level = AV_LEVEL; 1719 } else 1720 level = (iointrp->intr_el == INTR_EL_LEVEL) ? 1721 AV_LEVEL : 0; 1722 if (level && ((iointrp->intr_po == INTR_PO_ACTIVE_LOW) || 1723 (iointrp->intr_po == INTR_PO_CONFORM && 1724 bus_type == BUS_PCI))) 1725 po = AV_ACTIVE_LOW; 1726 } 1727 if (level) 1728 apic_level_intr[irq] = 1; 1729 /* 1730 * The 82489DX External APIC cannot do active low polarity interrupts. 1731 */ 1732 if (po && (apic_io_ver[ioapicindex] != IOAPIC_VER_82489DX)) 1733 io_po = po; 1734 else 1735 io_po = 0; 1736 1737 if (apic_verbose & APIC_VERBOSE_IOAPIC_FLAG) 1738 prom_printf("setio: ioapic=0x%x intin=0x%x level=0x%x po=0x%x " 1739 "vector=0x%x cpu=0x%x\n\n", ioapicindex, 1740 irqptr->airq_intin_no, level, io_po, vector, 1741 irqptr->airq_cpu); 1742 1743 irqptr->airq_rdt_entry = level|io_po|vector; 1744 } 1745 1746 int 1747 apic_acpi_translate_pci_irq(dev_info_t *dip, int busid, int devid, 1748 int ipin, int *pci_irqp, iflag_t *intr_flagp) 1749 { 1750 1751 int status; 1752 acpi_psm_lnk_t acpipsmlnk; 1753 1754 if ((status = acpi_get_irq_cache_ent(busid, devid, ipin, pci_irqp, 1755 intr_flagp)) == ACPI_PSM_SUCCESS) { 1756 APIC_VERBOSE_IRQ((CE_CONT, "!%s: Found irqno %d " 1757 "from cache for device %s, instance #%d\n", psm_name, 1758 *pci_irqp, ddi_get_name(dip), ddi_get_instance(dip))); 1759 return (status); 1760 } 1761 1762 bzero(&acpipsmlnk, sizeof (acpi_psm_lnk_t)); 1763 1764 if ((status = acpi_translate_pci_irq(dip, ipin, pci_irqp, intr_flagp, 1765 &acpipsmlnk)) == ACPI_PSM_FAILURE) { 1766 APIC_VERBOSE_IRQ((CE_WARN, "%s: " 1767 " acpi_translate_pci_irq failed for device %s, instance" 1768 " #%d", psm_name, ddi_get_name(dip), 1769 ddi_get_instance(dip))); 1770 return (status); 1771 } 1772 1773 if (status == ACPI_PSM_PARTIAL && acpipsmlnk.lnkobj != NULL) { 1774 status = apic_acpi_irq_configure(&acpipsmlnk, dip, pci_irqp, 1775 intr_flagp); 1776 if (status != ACPI_PSM_SUCCESS) { 1777 status = acpi_get_current_irq_resource(&acpipsmlnk, 1778 pci_irqp, intr_flagp); 1779 } 1780 } 1781 1782 if (status == ACPI_PSM_SUCCESS) { 1783 acpi_new_irq_cache_ent(busid, devid, ipin, *pci_irqp, 1784 intr_flagp, &acpipsmlnk); 1785 1786 APIC_VERBOSE_IRQ((CE_CONT, "%s: [ACPI] " 1787 "new irq %d for device %s, instance #%d\n", psm_name, 1788 *pci_irqp, ddi_get_name(dip), ddi_get_instance(dip))); 1789 } 1790 1791 return (status); 1792 } 1793 1794 /* 1795 * Adds an entry to the irq list passed in, and returns the new list. 1796 * Entries are added in priority order (lower numerical priorities are 1797 * placed closer to the head of the list) 1798 */ 1799 static prs_irq_list_t * 1800 acpi_insert_prs_irq_ent(prs_irq_list_t *listp, int priority, int irq, 1801 iflag_t *iflagp, acpi_prs_private_t *prsprvp) 1802 { 1803 struct prs_irq_list_ent *newent, *prevp = NULL, *origlistp; 1804 1805 newent = kmem_zalloc(sizeof (struct prs_irq_list_ent), KM_SLEEP); 1806 1807 newent->list_prio = priority; 1808 newent->irq = irq; 1809 newent->intrflags = *iflagp; 1810 newent->prsprv = *prsprvp; 1811 /* ->next is NULL from kmem_zalloc */ 1812 1813 /* 1814 * New list -- return the new entry as the list. 1815 */ 1816 if (listp == NULL) 1817 return (newent); 1818 1819 /* 1820 * Save original list pointer for return (since we're not modifying 1821 * the head) 1822 */ 1823 origlistp = listp; 1824 1825 /* 1826 * Insertion sort, with entries with identical keys stored AFTER 1827 * existing entries (the less-than-or-equal test of priority does 1828 * this for us). 1829 */ 1830 while (listp != NULL && listp->list_prio <= priority) { 1831 prevp = listp; 1832 listp = listp->next; 1833 } 1834 1835 newent->next = listp; 1836 1837 if (prevp == NULL) { /* Add at head of list (newent is the new head) */ 1838 return (newent); 1839 } else { 1840 prevp->next = newent; 1841 return (origlistp); 1842 } 1843 } 1844 1845 /* 1846 * Frees the list passed in, deallocating all memory and leaving *listpp 1847 * set to NULL. 1848 */ 1849 static void 1850 acpi_destroy_prs_irq_list(prs_irq_list_t **listpp) 1851 { 1852 struct prs_irq_list_ent *nextp; 1853 1854 ASSERT(listpp != NULL); 1855 1856 while (*listpp != NULL) { 1857 nextp = (*listpp)->next; 1858 kmem_free(*listpp, sizeof (struct prs_irq_list_ent)); 1859 *listpp = nextp; 1860 } 1861 } 1862 1863 /* 1864 * apic_choose_irqs_from_prs returns a list of irqs selected from the list of 1865 * irqs returned by the link device's _PRS method. The irqs are chosen 1866 * to minimize contention in situations where the interrupt link device 1867 * can be programmed to steer interrupts to different interrupt controller 1868 * inputs (some of which may already be in use). The list is sorted in order 1869 * of irqs to use, with the highest priority given to interrupt controller 1870 * inputs that are not shared. When an interrupt controller input 1871 * must be shared, apic_choose_irqs_from_prs adds the possible irqs to the 1872 * returned list in the order that minimizes sharing (thereby ensuring lowest 1873 * possible latency from interrupt trigger time to ISR execution time). 1874 */ 1875 static prs_irq_list_t * 1876 apic_choose_irqs_from_prs(acpi_irqlist_t *irqlistent, dev_info_t *dip, 1877 int crs_irq) 1878 { 1879 int32_t irq; 1880 int i; 1881 prs_irq_list_t *prsirqlistp = NULL; 1882 iflag_t iflags; 1883 1884 while (irqlistent != NULL) { 1885 irqlistent->intr_flags.bustype = BUS_PCI; 1886 1887 for (i = 0; i < irqlistent->num_irqs; i++) { 1888 1889 irq = irqlistent->irqs[i]; 1890 1891 if (irq <= 0) { 1892 /* invalid irq number */ 1893 continue; 1894 } 1895 1896 if ((irq < 16) && (apic_reserved_irqlist[irq])) 1897 continue; 1898 1899 if ((apic_irq_table[irq] == NULL) || 1900 (apic_irq_table[irq]->airq_dip == dip)) { 1901 1902 prsirqlistp = acpi_insert_prs_irq_ent( 1903 prsirqlistp, 0 /* Highest priority */, irq, 1904 &irqlistent->intr_flags, 1905 &irqlistent->acpi_prs_prv); 1906 1907 /* 1908 * If we do not prefer the current irq from _CRS 1909 * or if we do and this irq is the same as the 1910 * current irq from _CRS, this is the one 1911 * to pick. 1912 */ 1913 if (!(apic_prefer_crs) || (irq == crs_irq)) { 1914 return (prsirqlistp); 1915 } 1916 continue; 1917 } 1918 1919 /* 1920 * Edge-triggered interrupts cannot be shared 1921 */ 1922 if (irqlistent->intr_flags.intr_el == INTR_EL_EDGE) 1923 continue; 1924 1925 /* 1926 * To work around BIOSes that contain incorrect 1927 * interrupt polarity information in interrupt 1928 * descriptors returned by _PRS, we assume that 1929 * the polarity of the other device sharing this 1930 * interrupt controller input is compatible. 1931 * If it's not, the caller will catch it when 1932 * the caller invokes the link device's _CRS method 1933 * (after invoking its _SRS method). 1934 */ 1935 iflags = irqlistent->intr_flags; 1936 iflags.intr_po = 1937 apic_irq_table[irq]->airq_iflag.intr_po; 1938 1939 if (!acpi_intr_compatible(iflags, 1940 apic_irq_table[irq]->airq_iflag)) { 1941 APIC_VERBOSE_IRQ((CE_CONT, "!%s: irq %d " 1942 "not compatible [%x:%x:%x !~ %x:%x:%x]", 1943 psm_name, irq, 1944 iflags.intr_po, 1945 iflags.intr_el, 1946 iflags.bustype, 1947 apic_irq_table[irq]->airq_iflag.intr_po, 1948 apic_irq_table[irq]->airq_iflag.intr_el, 1949 apic_irq_table[irq]->airq_iflag.bustype)); 1950 continue; 1951 } 1952 1953 /* 1954 * If we prefer the irq from _CRS, no need 1955 * to search any further (and make sure 1956 * to add this irq with the highest priority 1957 * so it's tried first). 1958 */ 1959 if (crs_irq == irq && apic_prefer_crs) { 1960 1961 return (acpi_insert_prs_irq_ent( 1962 prsirqlistp, 1963 0 /* Highest priority */, 1964 irq, &iflags, 1965 &irqlistent->acpi_prs_prv)); 1966 } 1967 1968 /* 1969 * Priority is equal to the share count (lower 1970 * share count is higher priority). Note that 1971 * the intr flags passed in here are the ones we 1972 * changed above -- if incorrect, it will be 1973 * caught by the caller's _CRS flags comparison. 1974 */ 1975 prsirqlistp = acpi_insert_prs_irq_ent( 1976 prsirqlistp, 1977 apic_irq_table[irq]->airq_share, irq, 1978 &iflags, &irqlistent->acpi_prs_prv); 1979 } 1980 1981 /* Go to the next irqlist entry */ 1982 irqlistent = irqlistent->next; 1983 } 1984 1985 return (prsirqlistp); 1986 } 1987 1988 /* 1989 * Configures the irq for the interrupt link device identified by 1990 * acpipsmlnkp. 1991 * 1992 * Gets the current and the list of possible irq settings for the 1993 * device. If apic_unconditional_srs is not set, and the current 1994 * resource setting is in the list of possible irq settings, 1995 * current irq resource setting is passed to the caller. 1996 * 1997 * Otherwise, picks an irq number from the list of possible irq 1998 * settings, and sets the irq of the device to this value. 1999 * If prefer_crs is set, among a set of irq numbers in the list that have 2000 * the least number of devices sharing the interrupt, we pick current irq 2001 * resource setting if it is a member of this set. 2002 * 2003 * Passes the irq number in the value pointed to by pci_irqp, and 2004 * polarity and sensitivity in the structure pointed to by dipintrflagp 2005 * to the caller. 2006 * 2007 * Note that if setting the irq resource failed, but successfuly obtained 2008 * the current irq resource settings, passes the current irq resources 2009 * and considers it a success. 2010 * 2011 * Returns: 2012 * ACPI_PSM_SUCCESS on success. 2013 * 2014 * ACPI_PSM_FAILURE if an error occured during the configuration or 2015 * if a suitable irq was not found for this device, or if setting the 2016 * irq resource and obtaining the current resource fails. 2017 * 2018 */ 2019 static int 2020 apic_acpi_irq_configure(acpi_psm_lnk_t *acpipsmlnkp, dev_info_t *dip, 2021 int *pci_irqp, iflag_t *dipintr_flagp) 2022 { 2023 int32_t irq; 2024 int cur_irq = -1; 2025 acpi_irqlist_t *irqlistp; 2026 prs_irq_list_t *prs_irq_listp, *prs_irq_entp; 2027 boolean_t found_irq = B_FALSE; 2028 2029 dipintr_flagp->bustype = BUS_PCI; 2030 2031 if ((acpi_get_possible_irq_resources(acpipsmlnkp, &irqlistp)) 2032 == ACPI_PSM_FAILURE) { 2033 APIC_VERBOSE_IRQ((CE_WARN, "!%s: Unable to determine " 2034 "or assign IRQ for device %s, instance #%d: The system was " 2035 "unable to get the list of potential IRQs from ACPI.", 2036 psm_name, ddi_get_name(dip), ddi_get_instance(dip))); 2037 2038 return (ACPI_PSM_FAILURE); 2039 } 2040 2041 if ((acpi_get_current_irq_resource(acpipsmlnkp, &cur_irq, 2042 dipintr_flagp) == ACPI_PSM_SUCCESS) && (!apic_unconditional_srs) && 2043 (cur_irq > 0)) { 2044 /* 2045 * If an IRQ is set in CRS and that IRQ exists in the set 2046 * returned from _PRS, return that IRQ, otherwise print 2047 * a warning 2048 */ 2049 2050 if (acpi_irqlist_find_irq(irqlistp, cur_irq, NULL) 2051 == ACPI_PSM_SUCCESS) { 2052 2053 ASSERT(pci_irqp != NULL); 2054 *pci_irqp = cur_irq; 2055 acpi_free_irqlist(irqlistp); 2056 return (ACPI_PSM_SUCCESS); 2057 } 2058 2059 APIC_VERBOSE_IRQ((CE_WARN, "!%s: Could not find the " 2060 "current irq %d for device %s, instance #%d in ACPI's " 2061 "list of possible irqs for this device. Picking one from " 2062 " the latter list.", psm_name, cur_irq, ddi_get_name(dip), 2063 ddi_get_instance(dip))); 2064 } 2065 2066 if ((prs_irq_listp = apic_choose_irqs_from_prs(irqlistp, dip, 2067 cur_irq)) == NULL) { 2068 2069 APIC_VERBOSE_IRQ((CE_WARN, "!%s: Could not find a " 2070 "suitable irq from the list of possible irqs for device " 2071 "%s, instance #%d in ACPI's list of possible irqs", 2072 psm_name, ddi_get_name(dip), ddi_get_instance(dip))); 2073 2074 acpi_free_irqlist(irqlistp); 2075 return (ACPI_PSM_FAILURE); 2076 } 2077 2078 acpi_free_irqlist(irqlistp); 2079 2080 for (prs_irq_entp = prs_irq_listp; 2081 prs_irq_entp != NULL && found_irq == B_FALSE; 2082 prs_irq_entp = prs_irq_entp->next) { 2083 2084 acpipsmlnkp->acpi_prs_prv = prs_irq_entp->prsprv; 2085 irq = prs_irq_entp->irq; 2086 2087 APIC_VERBOSE_IRQ((CE_CONT, "!%s: Setting irq %d for " 2088 "device %s instance #%d\n", psm_name, irq, 2089 ddi_get_name(dip), ddi_get_instance(dip))); 2090 2091 if ((acpi_set_irq_resource(acpipsmlnkp, irq)) 2092 == ACPI_PSM_SUCCESS) { 2093 /* 2094 * setting irq was successful, check to make sure CRS 2095 * reflects that. If CRS does not agree with what we 2096 * set, return the irq that was set. 2097 */ 2098 2099 if (acpi_get_current_irq_resource(acpipsmlnkp, &cur_irq, 2100 dipintr_flagp) == ACPI_PSM_SUCCESS) { 2101 2102 if (cur_irq != irq) 2103 APIC_VERBOSE_IRQ((CE_WARN, 2104 "!%s: IRQ resource set " 2105 "(irqno %d) for device %s " 2106 "instance #%d, differs from " 2107 "current setting irqno %d", 2108 psm_name, irq, ddi_get_name(dip), 2109 ddi_get_instance(dip), cur_irq)); 2110 } else { 2111 /* 2112 * On at least one system, there was a bug in 2113 * a DSDT method called by _STA, causing _STA to 2114 * indicate that the link device was disabled 2115 * (when, in fact, it was enabled). Since _SRS 2116 * succeeded, assume that _CRS is lying and use 2117 * the iflags from this _PRS interrupt choice. 2118 * If we're wrong about the flags, the polarity 2119 * will be incorrect and we may get an interrupt 2120 * storm, but there's not much else we can do 2121 * at this point. 2122 */ 2123 *dipintr_flagp = prs_irq_entp->intrflags; 2124 } 2125 2126 /* 2127 * Return the irq that was set, and not what _CRS 2128 * reports, since _CRS has been seen to return 2129 * different IRQs than what was passed to _SRS on some 2130 * systems (and just not return successfully on others). 2131 */ 2132 cur_irq = irq; 2133 found_irq = B_TRUE; 2134 } else { 2135 APIC_VERBOSE_IRQ((CE_WARN, "!%s: set resource " 2136 "irq %d failed for device %s instance #%d", 2137 psm_name, irq, ddi_get_name(dip), 2138 ddi_get_instance(dip))); 2139 2140 if (cur_irq == -1) { 2141 acpi_destroy_prs_irq_list(&prs_irq_listp); 2142 return (ACPI_PSM_FAILURE); 2143 } 2144 } 2145 } 2146 2147 acpi_destroy_prs_irq_list(&prs_irq_listp); 2148 2149 if (!found_irq) 2150 return (ACPI_PSM_FAILURE); 2151 2152 ASSERT(pci_irqp != NULL); 2153 *pci_irqp = cur_irq; 2154 return (ACPI_PSM_SUCCESS); 2155 } 2156 2157 void 2158 ioapic_disable_redirection() 2159 { 2160 int ioapic_ix; 2161 int intin_max; 2162 int intin_ix; 2163 2164 /* Disable the I/O APIC redirection entries */ 2165 for (ioapic_ix = 0; ioapic_ix < apic_io_max; ioapic_ix++) { 2166 2167 /* Bits 23-16 define the maximum redirection entries */ 2168 intin_max = (ioapic_read(ioapic_ix, APIC_VERS_CMD) >> 16) 2169 & 0xff; 2170 2171 for (intin_ix = 0; intin_ix <= intin_max; intin_ix++) { 2172 /* 2173 * The assumption here is that this is safe, even for 2174 * systems with IOAPICs that suffer from the hardware 2175 * erratum because all devices have been quiesced before 2176 * this function is called from apic_shutdown() 2177 * (or equivalent). If that assumption turns out to be 2178 * false, this mask operation can induce the same 2179 * erratum result we're trying to avoid. 2180 */ 2181 ioapic_write(ioapic_ix, APIC_RDT_CMD + 2 * intin_ix, 2182 AV_MASK); 2183 } 2184 } 2185 } 2186 2187 /* 2188 * Looks for an IOAPIC with the specified physical address in the /ioapics 2189 * node in the device tree (created by the PCI enumerator). 2190 */ 2191 static boolean_t 2192 apic_is_ioapic_AMD_813x(uint32_t physaddr) 2193 { 2194 /* 2195 * Look in /ioapics, for the ioapic with 2196 * the physical address given 2197 */ 2198 dev_info_t *ioapicsnode = ddi_find_devinfo(IOAPICS_NODE_NAME, -1, 0); 2199 dev_info_t *ioapic_child; 2200 boolean_t rv = B_FALSE; 2201 int vid, did; 2202 uint64_t ioapic_paddr; 2203 boolean_t done = B_FALSE; 2204 2205 if (ioapicsnode == NULL) 2206 return (B_FALSE); 2207 2208 /* Load first child: */ 2209 ioapic_child = ddi_get_child(ioapicsnode); 2210 while (!done && ioapic_child != 0) { /* Iterate over children */ 2211 2212 if ((ioapic_paddr = (uint64_t)ddi_prop_get_int64(DDI_DEV_T_ANY, 2213 ioapic_child, DDI_PROP_DONTPASS, "reg", 0)) 2214 != 0 && physaddr == ioapic_paddr) { 2215 2216 vid = ddi_prop_get_int(DDI_DEV_T_ANY, ioapic_child, 2217 DDI_PROP_DONTPASS, IOAPICS_PROP_VENID, 0); 2218 2219 if (vid == VENID_AMD) { 2220 2221 did = ddi_prop_get_int(DDI_DEV_T_ANY, 2222 ioapic_child, DDI_PROP_DONTPASS, 2223 IOAPICS_PROP_DEVID, 0); 2224 2225 if (did == DEVID_8131_IOAPIC || 2226 did == DEVID_8132_IOAPIC) { 2227 rv = B_TRUE; 2228 done = B_TRUE; 2229 } 2230 } 2231 } 2232 2233 if (!done) 2234 ioapic_child = ddi_get_next_sibling(ioapic_child); 2235 } 2236 2237 /* The ioapics node was held by ddi_find_devinfo, so release it */ 2238 ndi_rele_devi(ioapicsnode); 2239 return (rv); 2240 } 2241 2242 struct apic_state { 2243 int32_t as_task_reg; 2244 int32_t as_dest_reg; 2245 int32_t as_format_reg; 2246 int32_t as_local_timer; 2247 int32_t as_pcint_vect; 2248 int32_t as_int_vect0; 2249 int32_t as_int_vect1; 2250 int32_t as_err_vect; 2251 int32_t as_init_count; 2252 int32_t as_divide_reg; 2253 int32_t as_spur_int_reg; 2254 uint32_t as_ioapic_ids[MAX_IO_APIC]; 2255 }; 2256 2257 2258 static int 2259 apic_acpi_enter_apicmode(void) 2260 { 2261 ACPI_OBJECT_LIST arglist; 2262 ACPI_OBJECT arg; 2263 ACPI_STATUS status; 2264 2265 /* Setup parameter object */ 2266 arglist.Count = 1; 2267 arglist.Pointer = &arg; 2268 arg.Type = ACPI_TYPE_INTEGER; 2269 arg.Integer.Value = ACPI_APIC_MODE; 2270 2271 status = AcpiEvaluateObject(NULL, "\\_PIC", &arglist, NULL); 2272 /* 2273 * Per ACPI spec - section 5.8.1 _PIC Method 2274 * calling the \_PIC control method is optional for the OS 2275 * and might not be found. It's ok to not fail in such cases. 2276 * This is the case on linux KVM and qemu (status AE_NOT_FOUND) 2277 */ 2278 if (ACPI_FAILURE(status) && (status != AE_NOT_FOUND)) { 2279 cmn_err(CE_NOTE, 2280 "!apic: Reporting APIC mode failed (via _PIC), err: 0x%x", 2281 ACPI_FAILURE(status)); 2282 return (PSM_FAILURE); 2283 } else { 2284 return (PSM_SUCCESS); 2285 } 2286 } 2287 2288 2289 static void 2290 apic_save_state(struct apic_state *sp) 2291 { 2292 int i, cpuid; 2293 ulong_t iflag; 2294 2295 PMD(PMD_SX, ("apic_save_state %p\n", (void *)sp)) 2296 /* 2297 * First the local APIC. 2298 */ 2299 sp->as_task_reg = apic_reg_ops->apic_get_pri(); 2300 sp->as_dest_reg = apic_reg_ops->apic_read(APIC_DEST_REG); 2301 if (apic_mode == LOCAL_APIC) 2302 sp->as_format_reg = apic_reg_ops->apic_read(APIC_FORMAT_REG); 2303 sp->as_local_timer = apic_reg_ops->apic_read(APIC_LOCAL_TIMER); 2304 sp->as_pcint_vect = apic_reg_ops->apic_read(APIC_PCINT_VECT); 2305 sp->as_int_vect0 = apic_reg_ops->apic_read(APIC_INT_VECT0); 2306 sp->as_int_vect1 = apic_reg_ops->apic_read(APIC_INT_VECT1); 2307 sp->as_err_vect = apic_reg_ops->apic_read(APIC_ERR_VECT); 2308 sp->as_init_count = apic_reg_ops->apic_read(APIC_INIT_COUNT); 2309 sp->as_divide_reg = apic_reg_ops->apic_read(APIC_DIVIDE_REG); 2310 sp->as_spur_int_reg = apic_reg_ops->apic_read(APIC_SPUR_INT_REG); 2311 2312 /* 2313 * If on the boot processor then save the IOAPICs' IDs 2314 */ 2315 if ((cpuid = psm_get_cpu_id()) == 0) { 2316 2317 iflag = intr_clear(); 2318 lock_set(&apic_ioapic_lock); 2319 2320 for (i = 0; i < apic_io_max; i++) 2321 sp->as_ioapic_ids[i] = ioapic_read(i, APIC_ID_CMD); 2322 2323 lock_clear(&apic_ioapic_lock); 2324 intr_restore(iflag); 2325 } 2326 2327 /* apic_state() is currently invoked only in Suspend/Resume */ 2328 apic_cpus[cpuid].aci_status |= APIC_CPU_SUSPEND; 2329 } 2330 2331 static void 2332 apic_restore_state(struct apic_state *sp) 2333 { 2334 int i; 2335 ulong_t iflag; 2336 2337 /* 2338 * First the local APIC. 2339 */ 2340 apic_reg_ops->apic_write_task_reg(sp->as_task_reg); 2341 if (apic_mode == LOCAL_APIC) { 2342 apic_reg_ops->apic_write(APIC_DEST_REG, sp->as_dest_reg); 2343 apic_reg_ops->apic_write(APIC_FORMAT_REG, sp->as_format_reg); 2344 } 2345 apic_reg_ops->apic_write(APIC_LOCAL_TIMER, sp->as_local_timer); 2346 apic_reg_ops->apic_write(APIC_PCINT_VECT, sp->as_pcint_vect); 2347 apic_reg_ops->apic_write(APIC_INT_VECT0, sp->as_int_vect0); 2348 apic_reg_ops->apic_write(APIC_INT_VECT1, sp->as_int_vect1); 2349 apic_reg_ops->apic_write(APIC_ERR_VECT, sp->as_err_vect); 2350 apic_reg_ops->apic_write(APIC_INIT_COUNT, sp->as_init_count); 2351 apic_reg_ops->apic_write(APIC_DIVIDE_REG, sp->as_divide_reg); 2352 apic_reg_ops->apic_write(APIC_SPUR_INT_REG, sp->as_spur_int_reg); 2353 2354 /* 2355 * the following only needs to be done once, so we do it on the 2356 * boot processor, since we know that we only have one of those 2357 */ 2358 if (psm_get_cpu_id() == 0) { 2359 2360 iflag = intr_clear(); 2361 lock_set(&apic_ioapic_lock); 2362 2363 /* Restore IOAPICs' APIC IDs */ 2364 for (i = 0; i < apic_io_max; i++) { 2365 ioapic_write(i, APIC_ID_CMD, sp->as_ioapic_ids[i]); 2366 } 2367 2368 lock_clear(&apic_ioapic_lock); 2369 intr_restore(iflag); 2370 2371 /* 2372 * Reenter APIC mode before restoring LNK devices 2373 */ 2374 (void) apic_acpi_enter_apicmode(); 2375 2376 /* 2377 * restore acpi link device mappings 2378 */ 2379 acpi_restore_link_devices(); 2380 } 2381 } 2382 2383 /* 2384 * Returns 0 on success 2385 */ 2386 int 2387 apic_state(psm_state_request_t *rp) 2388 { 2389 PMD(PMD_SX, ("apic_state ")) 2390 switch (rp->psr_cmd) { 2391 case PSM_STATE_ALLOC: 2392 rp->req.psm_state_req.psr_state = 2393 kmem_zalloc(sizeof (struct apic_state), KM_NOSLEEP); 2394 if (rp->req.psm_state_req.psr_state == NULL) 2395 return (ENOMEM); 2396 rp->req.psm_state_req.psr_state_size = 2397 sizeof (struct apic_state); 2398 PMD(PMD_SX, (":STATE_ALLOC: state %p, size %lx\n", 2399 rp->req.psm_state_req.psr_state, 2400 rp->req.psm_state_req.psr_state_size)) 2401 return (0); 2402 2403 case PSM_STATE_FREE: 2404 kmem_free(rp->req.psm_state_req.psr_state, 2405 rp->req.psm_state_req.psr_state_size); 2406 PMD(PMD_SX, (" STATE_FREE: state %p, size %lx\n", 2407 rp->req.psm_state_req.psr_state, 2408 rp->req.psm_state_req.psr_state_size)) 2409 return (0); 2410 2411 case PSM_STATE_SAVE: 2412 PMD(PMD_SX, (" STATE_SAVE: state %p, size %lx\n", 2413 rp->req.psm_state_req.psr_state, 2414 rp->req.psm_state_req.psr_state_size)) 2415 apic_save_state(rp->req.psm_state_req.psr_state); 2416 return (0); 2417 2418 case PSM_STATE_RESTORE: 2419 apic_restore_state(rp->req.psm_state_req.psr_state); 2420 PMD(PMD_SX, (" STATE_RESTORE: state %p, size %lx\n", 2421 rp->req.psm_state_req.psr_state, 2422 rp->req.psm_state_req.psr_state_size)) 2423 return (0); 2424 2425 default: 2426 return (EINVAL); 2427 } 2428 } 2429