1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #include <sys/sunddi.h> 28 #include <sys/iommulib.h> 29 #include <sys/amd_iommu.h> 30 #include <sys/pci_cap.h> 31 #include <sys/bootconf.h> 32 #include <sys/ddidmareq.h> 33 34 #include "amd_iommu_impl.h" 35 #include "amd_iommu_acpi.h" 36 #include "amd_iommu_page_tables.h" 37 38 static int amd_iommu_fini(amd_iommu_t *iommu, int type); 39 static void amd_iommu_teardown_interrupts(amd_iommu_t *iommu); 40 static void amd_iommu_stop(amd_iommu_t *iommu); 41 42 static int amd_iommu_probe(iommulib_handle_t handle, dev_info_t *rdip); 43 static int amd_iommu_allochdl(iommulib_handle_t handle, 44 dev_info_t *dip, dev_info_t *rdip, ddi_dma_attr_t *attr, 45 int (*waitfp)(caddr_t), caddr_t arg, ddi_dma_handle_t *dma_handlep); 46 static int amd_iommu_freehdl(iommulib_handle_t handle, 47 dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t dma_handle); 48 static int amd_iommu_bindhdl(iommulib_handle_t handle, dev_info_t *dip, 49 dev_info_t *rdip, ddi_dma_handle_t dma_handle, 50 struct ddi_dma_req *dmareq, ddi_dma_cookie_t *cookiep, 51 uint_t *ccountp); 52 static int amd_iommu_unbindhdl(iommulib_handle_t handle, 53 dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t dma_handle); 54 static int amd_iommu_sync(iommulib_handle_t handle, dev_info_t *dip, 55 dev_info_t *rdip, ddi_dma_handle_t dma_handle, off_t off, 56 size_t len, uint_t cache_flags); 57 static int amd_iommu_win(iommulib_handle_t handle, dev_info_t *dip, 58 dev_info_t *rdip, ddi_dma_handle_t dma_handle, uint_t win, 59 off_t *offp, size_t *lenp, ddi_dma_cookie_t *cookiep, 60 uint_t *ccountp); 61 static int amd_iommu_map(iommulib_handle_t handle, dev_info_t *dip, 62 dev_info_t *rdip, struct ddi_dma_req *dmareq, 63 ddi_dma_handle_t *dma_handle); 64 static int amd_iommu_mctl(iommulib_handle_t handle, dev_info_t *dip, 65 dev_info_t *rdip, ddi_dma_handle_t dma_handle, 66 enum ddi_dma_ctlops request, off_t *offp, size_t *lenp, 67 caddr_t *objpp, uint_t cache_flags); 68 69 static int unmap_current_window(amd_iommu_t *iommu, dev_info_t *rdip, 70 ddi_dma_cookie_t *cookie_array, uint_t ccount, int ncookies, int locked); 71 72 extern void *device_arena_alloc(size_t size, int vm_flag); 73 extern void device_arena_free(void * vaddr, size_t size); 74 75 ddi_dma_attr_t amd_iommu_dma_attr = { 76 DMA_ATTR_V0, 77 0U, /* dma_attr_addr_lo */ 78 0xffffffffffffffffULL, /* dma_attr_addr_hi */ 79 0xffffffffU, /* dma_attr_count_max */ 80 (uint64_t)4096, /* dma_attr_align */ 81 1, /* dma_attr_burstsizes */ 82 64, /* dma_attr_minxfer */ 83 0xffffffffU, /* dma_attr_maxxfer */ 84 0xffffffffU, /* dma_attr_seg */ 85 1, /* dma_attr_sgllen, variable */ 86 64, /* dma_attr_granular */ 87 0 /* dma_attr_flags */ 88 }; 89 90 ddi_device_acc_attr_t amd_iommu_devacc = { 91 DDI_DEVICE_ATTR_V0, 92 DDI_NEVERSWAP_ACC, 93 DDI_STRICTORDER_ACC 94 }; 95 96 struct iommulib_ops amd_iommulib_ops = { 97 IOMMU_OPS_VERSION, 98 AMD_IOMMU, 99 "AMD IOMMU Vers. 1", 100 NULL, 101 amd_iommu_probe, 102 amd_iommu_allochdl, 103 amd_iommu_freehdl, 104 amd_iommu_bindhdl, 105 amd_iommu_unbindhdl, 106 amd_iommu_sync, 107 amd_iommu_win, 108 amd_iommu_map, 109 amd_iommu_mctl 110 }; 111 112 static kmutex_t amd_iommu_pgtable_lock; 113 114 static int 115 amd_iommu_register(amd_iommu_t *iommu) 116 { 117 dev_info_t *dip = iommu->aiomt_dip; 118 const char *driver = ddi_driver_name(dip); 119 int instance = ddi_get_instance(dip); 120 iommulib_ops_t *iommulib_ops; 121 iommulib_handle_t handle; 122 const char *f = "amd_iommu_register"; 123 124 iommulib_ops = kmem_zalloc(sizeof (iommulib_ops_t), KM_SLEEP); 125 126 *iommulib_ops = amd_iommulib_ops; 127 128 iommulib_ops->ilops_data = (void *)iommu; 129 iommu->aiomt_iommulib_ops = iommulib_ops; 130 131 if (iommulib_iommu_register(dip, iommulib_ops, &handle) 132 != DDI_SUCCESS) { 133 cmn_err(CE_WARN, "%s: %s%d: Register with iommulib " 134 "failed idx=%d", f, driver, instance, iommu->aiomt_idx); 135 kmem_free(iommulib_ops, sizeof (iommulib_ops_t)); 136 return (DDI_FAILURE); 137 } 138 139 iommu->aiomt_iommulib_handle = handle; 140 141 return (DDI_SUCCESS); 142 } 143 144 static int 145 amd_iommu_unregister(amd_iommu_t *iommu) 146 { 147 if (iommu->aiomt_iommulib_handle == NULL) { 148 /* we never registered */ 149 return (DDI_SUCCESS); 150 } 151 152 if (iommulib_iommu_unregister(iommu->aiomt_iommulib_handle) 153 != DDI_SUCCESS) { 154 return (DDI_FAILURE); 155 } 156 157 kmem_free(iommu->aiomt_iommulib_ops, sizeof (iommulib_ops_t)); 158 iommu->aiomt_iommulib_ops = NULL; 159 iommu->aiomt_iommulib_handle = NULL; 160 161 return (DDI_SUCCESS); 162 } 163 164 static int 165 amd_iommu_setup_passthru(amd_iommu_t *iommu) 166 { 167 gfx_entry_t *gfxp; 168 dev_info_t *dip; 169 170 /* 171 * Setup passthru mapping for "special" devices 172 */ 173 amd_iommu_set_passthru(iommu, NULL); 174 175 for (gfxp = gfx_devinfo_list; gfxp; gfxp = gfxp->g_next) { 176 gfxp->g_ref++; 177 dip = gfxp->g_dip; 178 if (dip) { 179 amd_iommu_set_passthru(iommu, dip); 180 } 181 gfxp->g_ref--; 182 } 183 184 return (DDI_SUCCESS); 185 } 186 187 static int 188 amd_iommu_start(amd_iommu_t *iommu) 189 { 190 dev_info_t *dip = iommu->aiomt_dip; 191 int instance = ddi_get_instance(dip); 192 const char *driver = ddi_driver_name(dip); 193 amd_iommu_acpi_ivhd_t *hinfop; 194 const char *f = "amd_iommu_start"; 195 196 hinfop = amd_iommu_lookup_all_ivhd(); 197 198 /* 199 * Disable HT tunnel translation. 200 * XXX use ACPI 201 */ 202 AMD_IOMMU_REG_SET64(REGADDR64(iommu->aiomt_reg_ctrl_va), 203 AMD_IOMMU_HT_TUN_ENABLE, 0); 204 205 if (hinfop) { 206 if (amd_iommu_debug) { 207 cmn_err(CE_NOTE, 208 "amd_iommu: using ACPI for CTRL registers"); 209 } 210 AMD_IOMMU_REG_SET64(REGADDR64(iommu->aiomt_reg_ctrl_va), 211 AMD_IOMMU_ISOC, hinfop->ach_Isoc); 212 AMD_IOMMU_REG_SET64(REGADDR64(iommu->aiomt_reg_ctrl_va), 213 AMD_IOMMU_RESPASSPW, hinfop->ach_ResPassPW); 214 AMD_IOMMU_REG_SET64(REGADDR64(iommu->aiomt_reg_ctrl_va), 215 AMD_IOMMU_PASSPW, hinfop->ach_PassPW); 216 } 217 218 AMD_IOMMU_REG_SET64(REGADDR64(iommu->aiomt_reg_ctrl_va), 219 AMD_IOMMU_INVTO, 5); 220 221 222 /* 223 * The Device table entry bit 0 (V) controls whether the device 224 * table entry is valid for address translation and Device table 225 * entry bit 128 (IV) controls whether interrupt remapping is valid. 226 * By setting both to zero we are essentially doing pass-thru. Since 227 * this table is zeroed on allocation, essentially we will have 228 * pass-thru when IOMMU is enabled. 229 */ 230 231 /* Finally enable the IOMMU ... */ 232 AMD_IOMMU_REG_SET64(REGADDR64(iommu->aiomt_reg_ctrl_va), 233 AMD_IOMMU_ENABLE, 1); 234 235 if (amd_iommu_debug) { 236 cmn_err(CE_NOTE, "%s: %s%d: AMD IOMMU idx=%d. " 237 "Successfully started AMD IOMMU", f, driver, instance, 238 iommu->aiomt_idx); 239 } 240 cmn_err(CE_NOTE, "AMD IOMMU (%d,%d) enabled", 241 instance, iommu->aiomt_idx); 242 243 return (DDI_SUCCESS); 244 } 245 246 static void 247 amd_iommu_stop(amd_iommu_t *iommu) 248 { 249 dev_info_t *dip = iommu->aiomt_dip; 250 int instance = ddi_get_instance(dip); 251 const char *driver = ddi_driver_name(dip); 252 const char *f = "amd_iommu_stop"; 253 254 AMD_IOMMU_REG_SET64(REGADDR64(iommu->aiomt_reg_ctrl_va), 255 AMD_IOMMU_ENABLE, 0); 256 AMD_IOMMU_REG_SET64(REGADDR64(iommu->aiomt_reg_ctrl_va), 257 AMD_IOMMU_EVENTINT_ENABLE, 0); 258 AMD_IOMMU_REG_SET64(REGADDR64(iommu->aiomt_reg_ctrl_va), 259 AMD_IOMMU_COMWAITINT_ENABLE, 0); 260 AMD_IOMMU_REG_SET64(REGADDR64(iommu->aiomt_reg_ctrl_va), 261 AMD_IOMMU_EVENTLOG_ENABLE, 0); 262 263 /* 264 * Disable translation on HT tunnel traffic 265 */ 266 AMD_IOMMU_REG_SET64(REGADDR64(iommu->aiomt_reg_ctrl_va), 267 AMD_IOMMU_HT_TUN_ENABLE, 0); 268 AMD_IOMMU_REG_SET64(REGADDR64(iommu->aiomt_reg_ctrl_va), 269 AMD_IOMMU_CMDBUF_ENABLE, 0); 270 271 cmn_err(CE_NOTE, "%s: %s%d: AMD IOMMYU idx=%d. " 272 "Successfully stopped AMD IOMMU", f, driver, instance, 273 iommu->aiomt_idx); 274 } 275 276 static int 277 amd_iommu_setup_tables_and_buffers(amd_iommu_t *iommu) 278 { 279 dev_info_t *dip = iommu->aiomt_dip; 280 int instance = ddi_get_instance(dip); 281 const char *driver = ddi_driver_name(dip); 282 uint32_t dma_bufsz; 283 caddr_t addr; 284 uint32_t sz; 285 uint32_t p2sz; 286 int i; 287 uint64_t *dentry; 288 int err; 289 const char *f = "amd_iommu_setup_tables_and_buffers"; 290 291 /* 292 * We will put the Device Table, Command Buffer and 293 * Event Log in contiguous memory. Allocate the maximum 294 * size allowed for such structures 295 * Device Table: 256b * 64K = 32B * 64K 296 * Command Buffer: 128b * 32K = 16B * 32K 297 * Event Log: 128b * 32K = 16B * 32K 298 */ 299 iommu->aiomt_devtbl_sz = (1<<AMD_IOMMU_DEVTBL_SZ) * AMD_IOMMU_DEVENT_SZ; 300 iommu->aiomt_cmdbuf_sz = (1<<AMD_IOMMU_CMDBUF_SZ) * AMD_IOMMU_CMD_SZ; 301 iommu->aiomt_eventlog_sz = 302 (1<<AMD_IOMMU_EVENTLOG_SZ) * AMD_IOMMU_EVENT_SZ; 303 304 dma_bufsz = iommu->aiomt_devtbl_sz + iommu->aiomt_cmdbuf_sz 305 + iommu->aiomt_eventlog_sz; 306 307 /* 308 * Alloc a DMA handle. 309 */ 310 err = ddi_dma_alloc_handle(dip, &amd_iommu_dma_attr, 311 DDI_DMA_SLEEP, NULL, &iommu->aiomt_dmahdl); 312 if (err != DDI_SUCCESS) { 313 cmn_err(CE_WARN, "%s: %s%d: Cannot alloc DMA handle for " 314 "AMD IOMMU tables and buffers", f, driver, instance); 315 return (DDI_FAILURE); 316 } 317 318 /* 319 * Alloc memory for tables and buffers 320 * XXX remove cast to size_t 321 */ 322 err = ddi_dma_mem_alloc(iommu->aiomt_dmahdl, dma_bufsz, 323 &amd_iommu_devacc, DDI_DMA_CONSISTENT|IOMEM_DATA_UNCACHED, 324 DDI_DMA_SLEEP, NULL, (caddr_t *)&iommu->aiomt_dma_bufva, 325 (size_t *)&iommu->aiomt_dma_mem_realsz, &iommu->aiomt_dma_mem_hdl); 326 if (err != DDI_SUCCESS) { 327 cmn_err(CE_WARN, "%s: %s%d: Cannot alloc memory for DMA " 328 "to AMD IOMMU tables and buffers", f, driver, instance); 329 iommu->aiomt_dma_bufva = NULL; 330 iommu->aiomt_dma_mem_realsz = 0; 331 ddi_dma_free_handle(&iommu->aiomt_dmahdl); 332 iommu->aiomt_dmahdl = NULL; 333 return (DDI_FAILURE); 334 } 335 336 /* 337 * The VA must be 4K aligned and >= table size 338 */ 339 ASSERT(((uintptr_t)iommu->aiomt_dma_bufva & 340 AMD_IOMMU_TABLE_ALIGN) == 0); 341 ASSERT(iommu->aiomt_dma_mem_realsz >= dma_bufsz); 342 343 /* 344 * Now bind the handle 345 */ 346 err = ddi_dma_addr_bind_handle(iommu->aiomt_dmahdl, NULL, 347 iommu->aiomt_dma_bufva, iommu->aiomt_dma_mem_realsz, 348 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, 349 NULL, &iommu->aiomt_buf_dma_cookie, &iommu->aiomt_buf_dma_ncookie); 350 if (err != DDI_DMA_MAPPED) { 351 cmn_err(CE_WARN, "%s: %s%d: Cannot bind memory for DMA " 352 "to AMD IOMMU tables and buffers. bufrealsz=%p", 353 f, driver, instance, 354 (void *)(uintptr_t)iommu->aiomt_dma_mem_realsz); 355 iommu->aiomt_buf_dma_cookie.dmac_laddress = 0; 356 iommu->aiomt_buf_dma_cookie.dmac_size = 0; 357 iommu->aiomt_buf_dma_cookie.dmac_type = 0; 358 iommu->aiomt_buf_dma_ncookie = 0; 359 ddi_dma_mem_free(&iommu->aiomt_dma_mem_hdl); 360 iommu->aiomt_dma_mem_hdl = NULL; 361 iommu->aiomt_dma_bufva = NULL; 362 iommu->aiomt_dma_mem_realsz = 0; 363 ddi_dma_free_handle(&iommu->aiomt_dmahdl); 364 iommu->aiomt_dmahdl = NULL; 365 return (DDI_FAILURE); 366 } 367 368 /* 369 * We assume the DMA engine on the IOMMU is capable of handling the 370 * whole table buffer in a single cookie. If not and multiple cookies 371 * are needed we fail. 372 */ 373 if (iommu->aiomt_buf_dma_ncookie != 1) { 374 cmn_err(CE_WARN, "%s: %s%d: Cannot handle multiple " 375 "cookies for DMA to AMD IOMMU tables and buffers. " 376 "#cookies=%u", f, driver, instance, 377 iommu->aiomt_buf_dma_ncookie); 378 (void) ddi_dma_unbind_handle(iommu->aiomt_dmahdl); 379 iommu->aiomt_buf_dma_cookie.dmac_laddress = 0; 380 iommu->aiomt_buf_dma_cookie.dmac_size = 0; 381 iommu->aiomt_buf_dma_cookie.dmac_type = 0; 382 iommu->aiomt_buf_dma_ncookie = 0; 383 ddi_dma_mem_free(&iommu->aiomt_dma_mem_hdl); 384 iommu->aiomt_dma_mem_hdl = NULL; 385 iommu->aiomt_dma_bufva = NULL; 386 iommu->aiomt_dma_mem_realsz = 0; 387 ddi_dma_free_handle(&iommu->aiomt_dmahdl); 388 iommu->aiomt_dmahdl = NULL; 389 return (DDI_FAILURE); 390 } 391 392 /* 393 * The address in the cookie must be 4K aligned and >= table size 394 */ 395 ASSERT((iommu->aiomt_buf_dma_cookie.dmac_cookie_addr 396 & AMD_IOMMU_TABLE_ALIGN) == 0); 397 ASSERT(iommu->aiomt_buf_dma_cookie.dmac_size 398 <= iommu->aiomt_dma_mem_realsz); 399 ASSERT(iommu->aiomt_buf_dma_cookie.dmac_size >= dma_bufsz); 400 401 /* 402 * Setup the device table pointers in the iommu struct as 403 * well as the IOMMU device table register 404 */ 405 iommu->aiomt_devtbl = iommu->aiomt_dma_bufva; 406 bzero(iommu->aiomt_devtbl, iommu->aiomt_devtbl_sz); 407 408 /* 409 * Set V=1 and TV = 0, so any inadvertant pass-thrus cause 410 * page faults. Also set SE bit so we aren't swamped with 411 * page fault messages 412 */ 413 for (i = 0; i <= AMD_IOMMU_MAX_DEVICEID; i++) { 414 /*LINTED*/ 415 dentry = (uint64_t *)&iommu->aiomt_devtbl 416 [i * AMD_IOMMU_DEVTBL_ENTRY_SZ]; 417 AMD_IOMMU_REG_SET64(dentry, AMD_IOMMU_DEVTBL_V, 1); 418 AMD_IOMMU_REG_SET64(&(dentry[1]), AMD_IOMMU_DEVTBL_SE, 1); 419 } 420 421 addr = (caddr_t)(uintptr_t)iommu->aiomt_buf_dma_cookie.dmac_cookie_addr; 422 AMD_IOMMU_REG_SET64(REGADDR64(iommu->aiomt_reg_devtbl_va), 423 AMD_IOMMU_DEVTABBASE, ((uint64_t)(uintptr_t)addr) >> 12); 424 sz = (iommu->aiomt_devtbl_sz >> 12) - 1; 425 ASSERT(sz <= ((1 << 9) - 1)); 426 AMD_IOMMU_REG_SET64(REGADDR64(iommu->aiomt_reg_devtbl_va), 427 AMD_IOMMU_DEVTABSIZE, sz); 428 429 /* 430 * Setup the command buffer pointers 431 */ 432 iommu->aiomt_cmdbuf = iommu->aiomt_devtbl + 433 iommu->aiomt_devtbl_sz; 434 bzero(iommu->aiomt_cmdbuf, iommu->aiomt_cmdbuf_sz); 435 addr += iommu->aiomt_devtbl_sz; 436 AMD_IOMMU_REG_SET64(REGADDR64(iommu->aiomt_reg_cmdbuf_va), 437 AMD_IOMMU_COMBASE, ((uint64_t)(uintptr_t)addr) >> 12); 438 439 p2sz = AMD_IOMMU_CMDBUF_SZ; 440 ASSERT(p2sz >= AMD_IOMMU_CMDBUF_MINSZ && 441 p2sz <= AMD_IOMMU_CMDBUF_MAXSZ); 442 AMD_IOMMU_REG_SET64(REGADDR64(iommu->aiomt_reg_cmdbuf_va), 443 AMD_IOMMU_COMLEN, p2sz); 444 /*LINTED*/ 445 iommu->aiomt_cmd_tail = (uint32_t *)iommu->aiomt_cmdbuf; 446 AMD_IOMMU_REG_SET64(REGADDR64(iommu->aiomt_reg_cmdbuf_head_va), 447 AMD_IOMMU_CMDHEADPTR, 0); 448 AMD_IOMMU_REG_SET64(REGADDR64(iommu->aiomt_reg_cmdbuf_tail_va), 449 AMD_IOMMU_CMDTAILPTR, 0); 450 451 /* 452 * Setup the event log pointers 453 */ 454 iommu->aiomt_eventlog = iommu->aiomt_cmdbuf + 455 iommu->aiomt_eventlog_sz; 456 bzero(iommu->aiomt_eventlog, iommu->aiomt_eventlog_sz); 457 addr += iommu->aiomt_cmdbuf_sz; 458 AMD_IOMMU_REG_SET64(REGADDR64(iommu->aiomt_reg_eventlog_va), 459 AMD_IOMMU_EVENTBASE, ((uint64_t)(uintptr_t)addr) >> 12); 460 p2sz = AMD_IOMMU_EVENTLOG_SZ; 461 ASSERT(p2sz >= AMD_IOMMU_EVENTLOG_MINSZ && 462 p2sz <= AMD_IOMMU_EVENTLOG_MAXSZ); 463 AMD_IOMMU_REG_SET64(REGADDR64(iommu->aiomt_reg_eventlog_va), 464 AMD_IOMMU_EVENTLEN, sz); 465 /*LINTED*/ 466 iommu->aiomt_event_head = (uint32_t *)iommu->aiomt_eventlog; 467 AMD_IOMMU_REG_SET64(REGADDR64(iommu->aiomt_reg_eventlog_head_va), 468 AMD_IOMMU_EVENTHEADPTR, 0); 469 AMD_IOMMU_REG_SET64(REGADDR64(iommu->aiomt_reg_eventlog_tail_va), 470 AMD_IOMMU_EVENTTAILPTR, 0); 471 472 /* dma sync so device sees this init */ 473 SYNC_FORDEV(iommu->aiomt_dmahdl); 474 475 if (amd_iommu_debug & AMD_IOMMU_DEBUG_TABLES) { 476 cmn_err(CE_NOTE, "%s: %s%d: successfully setup AMD IOMMU " 477 "tables, idx=%d", f, driver, instance, iommu->aiomt_idx); 478 } 479 480 return (DDI_SUCCESS); 481 } 482 483 static void 484 amd_iommu_teardown_tables_and_buffers(amd_iommu_t *iommu, int type) 485 { 486 dev_info_t *dip = iommu->aiomt_dip; 487 int instance = ddi_get_instance(dip); 488 const char *driver = ddi_driver_name(dip); 489 const char *f = "amd_iommu_teardown_tables_and_buffers"; 490 491 iommu->aiomt_eventlog = NULL; 492 AMD_IOMMU_REG_SET64(REGADDR64(iommu->aiomt_reg_eventlog_va), 493 AMD_IOMMU_EVENTBASE, 0); 494 AMD_IOMMU_REG_SET64(REGADDR64(iommu->aiomt_reg_eventlog_va), 495 AMD_IOMMU_EVENTLEN, 0); 496 AMD_IOMMU_REG_SET64(REGADDR64(iommu->aiomt_reg_eventlog_head_va), 497 AMD_IOMMU_EVENTHEADPTR, 0); 498 AMD_IOMMU_REG_SET64(REGADDR64(iommu->aiomt_reg_eventlog_head_va), 499 AMD_IOMMU_EVENTTAILPTR, 0); 500 501 502 iommu->aiomt_cmdbuf = NULL; 503 AMD_IOMMU_REG_SET64(REGADDR64(iommu->aiomt_reg_cmdbuf_va), 504 AMD_IOMMU_COMBASE, 0); 505 AMD_IOMMU_REG_SET64(REGADDR64(iommu->aiomt_reg_cmdbuf_va), 506 AMD_IOMMU_COMLEN, 0); 507 AMD_IOMMU_REG_SET64(REGADDR64(iommu->aiomt_reg_cmdbuf_head_va), 508 AMD_IOMMU_CMDHEADPTR, 0); 509 AMD_IOMMU_REG_SET64(REGADDR64(iommu->aiomt_reg_cmdbuf_head_va), 510 AMD_IOMMU_CMDTAILPTR, 0); 511 512 513 iommu->aiomt_devtbl = NULL; 514 AMD_IOMMU_REG_SET64(REGADDR64(iommu->aiomt_reg_devtbl_va), 515 AMD_IOMMU_DEVTABBASE, 0); 516 AMD_IOMMU_REG_SET64(REGADDR64(iommu->aiomt_reg_devtbl_va), 517 AMD_IOMMU_DEVTABSIZE, 0); 518 519 if (iommu->aiomt_dmahdl == NULL || type == AMD_IOMMU_QUIESCE) 520 return; 521 522 /* Unbind the handle */ 523 if (ddi_dma_unbind_handle(iommu->aiomt_dmahdl) != DDI_SUCCESS) { 524 cmn_err(CE_WARN, "%s: %s%d: failed to unbind handle: " 525 "%p for IOMMU idx=%d", f, driver, instance, 526 (void *)iommu->aiomt_dmahdl, iommu->aiomt_idx); 527 } 528 iommu->aiomt_buf_dma_cookie.dmac_laddress = 0; 529 iommu->aiomt_buf_dma_cookie.dmac_size = 0; 530 iommu->aiomt_buf_dma_cookie.dmac_type = 0; 531 iommu->aiomt_buf_dma_ncookie = 0; 532 533 /* Free the table memory allocated for DMA */ 534 ddi_dma_mem_free(&iommu->aiomt_dma_mem_hdl); 535 iommu->aiomt_dma_mem_hdl = NULL; 536 iommu->aiomt_dma_bufva = NULL; 537 iommu->aiomt_dma_mem_realsz = 0; 538 539 /* Free the DMA handle */ 540 ddi_dma_free_handle(&iommu->aiomt_dmahdl); 541 iommu->aiomt_dmahdl = NULL; 542 } 543 544 static void 545 amd_iommu_enable_interrupts(amd_iommu_t *iommu) 546 { 547 ASSERT(AMD_IOMMU_REG_GET64(REGADDR64(iommu->aiomt_reg_status_va), 548 AMD_IOMMU_CMDBUF_RUN) == 0); 549 ASSERT(AMD_IOMMU_REG_GET64(REGADDR64(iommu->aiomt_reg_status_va), 550 AMD_IOMMU_EVENT_LOG_RUN) == 0); 551 552 /* Must be set prior to enabling command buffer */ 553 /* Must be set prior to enabling event logging */ 554 AMD_IOMMU_REG_SET64(REGADDR64(iommu->aiomt_reg_ctrl_va), 555 AMD_IOMMU_CMDBUF_ENABLE, 1); 556 /* No interrupts for completion wait - too heavy weight. use polling */ 557 AMD_IOMMU_REG_SET64(REGADDR64(iommu->aiomt_reg_ctrl_va), 558 AMD_IOMMU_COMWAITINT_ENABLE, 0); 559 AMD_IOMMU_REG_SET64(REGADDR64(iommu->aiomt_reg_ctrl_va), 560 AMD_IOMMU_EVENTLOG_ENABLE, 1); 561 AMD_IOMMU_REG_SET64(REGADDR64(iommu->aiomt_reg_ctrl_va), 562 AMD_IOMMU_EVENTINT_ENABLE, 1); 563 } 564 565 static int 566 amd_iommu_setup_exclusion(amd_iommu_t *iommu) 567 { 568 amd_iommu_acpi_ivmd_t *minfop; 569 570 minfop = amd_iommu_lookup_all_ivmd(); 571 572 if (minfop && minfop->acm_ExclRange == 1) { 573 cmn_err(CE_NOTE, "Programming exclusion range"); 574 AMD_IOMMU_REG_SET64(REGADDR64(iommu->aiomt_reg_excl_base_va), 575 AMD_IOMMU_EXCL_BASE_ADDR, 576 minfop->acm_ivmd_phys_start >> 12); 577 AMD_IOMMU_REG_SET64(REGADDR64(iommu->aiomt_reg_excl_base_va), 578 AMD_IOMMU_EXCL_BASE_ALLOW, 1); 579 AMD_IOMMU_REG_SET64(REGADDR64(iommu->aiomt_reg_excl_base_va), 580 AMD_IOMMU_EXCL_BASE_EXEN, 1); 581 AMD_IOMMU_REG_SET64(REGADDR64(iommu->aiomt_reg_excl_lim_va), 582 AMD_IOMMU_EXCL_LIM, (minfop->acm_ivmd_phys_start + 583 minfop->acm_ivmd_phys_len) >> 12); 584 } else { 585 if (amd_iommu_debug) { 586 cmn_err(CE_NOTE, "Skipping exclusion range"); 587 } 588 AMD_IOMMU_REG_SET64(REGADDR64(iommu->aiomt_reg_excl_base_va), 589 AMD_IOMMU_EXCL_BASE_ADDR, 0); 590 AMD_IOMMU_REG_SET64(REGADDR64(iommu->aiomt_reg_excl_base_va), 591 AMD_IOMMU_EXCL_BASE_ALLOW, 1); 592 AMD_IOMMU_REG_SET64(REGADDR64(iommu->aiomt_reg_excl_base_va), 593 AMD_IOMMU_EXCL_BASE_EXEN, 0); 594 AMD_IOMMU_REG_SET64(REGADDR64(iommu->aiomt_reg_excl_lim_va), 595 AMD_IOMMU_EXCL_LIM, 0); 596 } 597 598 return (DDI_SUCCESS); 599 } 600 601 static void 602 amd_iommu_teardown_exclusion(amd_iommu_t *iommu) 603 { 604 (void) amd_iommu_setup_exclusion(iommu); 605 } 606 607 static uint_t 608 amd_iommu_intr_handler(caddr_t arg1, caddr_t arg2) 609 { 610 /*LINTED*/ 611 amd_iommu_t *iommu = (amd_iommu_t *)arg1; 612 dev_info_t *dip = iommu->aiomt_dip; 613 int instance = ddi_get_instance(dip); 614 const char *driver = ddi_driver_name(dip); 615 const char *f = "amd_iommu_intr_handler"; 616 617 ASSERT(arg1); 618 ASSERT(arg2 == NULL); 619 620 if (amd_iommu_debug & AMD_IOMMU_DEBUG_INTR) { 621 cmn_err(CE_NOTE, "%s: %s%d: IOMMU unit idx=%d. In INTR handler", 622 f, driver, instance, iommu->aiomt_idx); 623 } 624 625 if (AMD_IOMMU_REG_GET64(REGADDR64(iommu->aiomt_reg_status_va), 626 AMD_IOMMU_EVENT_LOG_INT) == 1) { 627 if (amd_iommu_debug & AMD_IOMMU_DEBUG_INTR) { 628 cmn_err(CE_NOTE, "%s: %s%d: IOMMU unit idx=%d " 629 "Event Log Interrupt", f, driver, instance, 630 iommu->aiomt_idx); 631 } 632 (void) amd_iommu_read_log(iommu, AMD_IOMMU_LOG_DISPLAY); 633 WAIT_SEC(1); 634 AMD_IOMMU_REG_SET64(REGADDR64(iommu->aiomt_reg_status_va), 635 AMD_IOMMU_EVENT_LOG_INT, 1); 636 return (DDI_INTR_CLAIMED); 637 } 638 639 if (AMD_IOMMU_REG_GET64(REGADDR64(iommu->aiomt_reg_status_va), 640 AMD_IOMMU_EVENT_OVERFLOW_INT) == 1) { 641 cmn_err(CE_NOTE, "!%s: %s%d: IOMMU unit idx=%d " 642 "Event Overflow Interrupt", f, driver, instance, 643 iommu->aiomt_idx); 644 (void) amd_iommu_read_log(iommu, AMD_IOMMU_LOG_DISCARD); 645 AMD_IOMMU_REG_SET64(REGADDR64(iommu->aiomt_reg_status_va), 646 AMD_IOMMU_EVENT_LOG_INT, 1); 647 AMD_IOMMU_REG_SET64(REGADDR64(iommu->aiomt_reg_status_va), 648 AMD_IOMMU_EVENT_OVERFLOW_INT, 1); 649 return (DDI_INTR_CLAIMED); 650 } 651 652 return (DDI_INTR_UNCLAIMED); 653 } 654 655 656 static int 657 amd_iommu_setup_interrupts(amd_iommu_t *iommu) 658 { 659 dev_info_t *dip = iommu->aiomt_dip; 660 int instance = ddi_get_instance(dip); 661 const char *driver = ddi_driver_name(dip); 662 int intrcap0; 663 int intrcapN; 664 int type; 665 int err; 666 int req; 667 int avail; 668 int p2req; 669 int actual; 670 int i; 671 int j; 672 const char *f = "amd_iommu_setup_interrupts"; 673 674 if (ddi_intr_get_supported_types(dip, &type) != DDI_SUCCESS) { 675 cmn_err(CE_WARN, "%s: %s%d: ddi_intr_get_supported_types " 676 "failed: idx=%d", f, driver, instance, iommu->aiomt_idx); 677 return (DDI_FAILURE); 678 } 679 680 if (amd_iommu_debug & AMD_IOMMU_DEBUG_INTR) { 681 cmn_err(CE_NOTE, "%s: %s%d: AMD IOMMU idx=%d. " 682 "Interrupt types supported = 0x%x", f, driver, instance, 683 iommu->aiomt_idx, type); 684 } 685 686 /* 687 * for now we only support MSI 688 */ 689 if ((type & DDI_INTR_TYPE_MSI) == 0) { 690 cmn_err(CE_WARN, "%s: %s%d: AMD IOMMU idx=%d. " 691 "MSI interrupts not supported. Failing init.", 692 f, driver, instance, iommu->aiomt_idx); 693 return (DDI_FAILURE); 694 } 695 696 if (amd_iommu_debug & AMD_IOMMU_DEBUG_INTR) { 697 cmn_err(CE_NOTE, "%s: %s%d: AMD IOMMU idx=%d. MSI supported", 698 f, driver, instance, iommu->aiomt_idx); 699 } 700 701 err = ddi_intr_get_nintrs(dip, DDI_INTR_TYPE_MSI, &req); 702 if (err != DDI_SUCCESS) { 703 cmn_err(CE_WARN, "%s: %s%d: AMD IOMMU idx=%d. " 704 "ddi_intr_get_nintrs failed err = %d", 705 f, driver, instance, iommu->aiomt_idx, err); 706 return (DDI_FAILURE); 707 } 708 709 if (amd_iommu_debug & AMD_IOMMU_DEBUG_INTR) { 710 cmn_err(CE_NOTE, "%s: %s%d: AMD IOMMU idx=%d. " 711 "MSI number of interrupts requested: %d", 712 f, driver, instance, iommu->aiomt_idx, req); 713 } 714 715 if (req == 0) { 716 cmn_err(CE_WARN, "%s: %s%d: AMD IOMMU idx=%d: 0 MSI " 717 "interrupts requested. Failing init", f, 718 driver, instance, iommu->aiomt_idx); 719 return (DDI_FAILURE); 720 } 721 722 err = ddi_intr_get_navail(dip, DDI_INTR_TYPE_MSI, &avail); 723 if (err != DDI_SUCCESS) { 724 cmn_err(CE_WARN, "%s: %s%d: AMD IOMMU idx=%d " 725 "ddi_intr_get_navail failed err = %d", f, 726 driver, instance, iommu->aiomt_idx, err); 727 return (DDI_FAILURE); 728 } 729 730 if (amd_iommu_debug & AMD_IOMMU_DEBUG_INTR) { 731 cmn_err(CE_NOTE, "%s: %s%d: AMD IOMMU idx=%d. " 732 "MSI number of interrupts available: %d", 733 f, driver, instance, iommu->aiomt_idx, avail); 734 } 735 736 if (avail == 0) { 737 cmn_err(CE_WARN, "%s: %s%d: AMD IOMMU idx=%d: 0 MSI " 738 "interrupts available. Failing init", f, 739 driver, instance, iommu->aiomt_idx); 740 return (DDI_FAILURE); 741 } 742 743 if (avail < req) { 744 cmn_err(CE_WARN, "%s: %s%d: AMD IOMMU idx=%d: MSI " 745 "interrupts: requested (%d) > available (%d). " 746 "Failing init", f, driver, instance, iommu->aiomt_idx, 747 req, avail); 748 return (DDI_FAILURE); 749 } 750 751 /* Allocate memory for DDI interrupt handles */ 752 iommu->aiomt_intr_htable_sz = req * sizeof (ddi_intr_handle_t); 753 iommu->aiomt_intr_htable = kmem_zalloc(iommu->aiomt_intr_htable_sz, 754 KM_SLEEP); 755 756 iommu->aiomt_intr_state = AMD_IOMMU_INTR_TABLE; 757 758 /* Convert req to a power of two as required by ddi_intr_alloc */ 759 p2req = 0; 760 while (1<<p2req <= req) 761 p2req++; 762 p2req--; 763 req = 1<<p2req; 764 765 if (amd_iommu_debug & AMD_IOMMU_DEBUG_INTR) { 766 cmn_err(CE_NOTE, "%s: %s%d: AMD IOMMU idx=%d. " 767 "MSI power of 2 number of interrupts: %d,%d", 768 f, driver, instance, iommu->aiomt_idx, p2req, req); 769 } 770 771 err = ddi_intr_alloc(iommu->aiomt_dip, iommu->aiomt_intr_htable, 772 DDI_INTR_TYPE_MSI, 0, req, &actual, DDI_INTR_ALLOC_STRICT); 773 if (err != DDI_SUCCESS) { 774 cmn_err(CE_WARN, "%s: %s%d: AMD IOMMU idx=%d: " 775 "ddi_intr_alloc failed: err = %d", 776 f, driver, instance, iommu->aiomt_idx, err); 777 amd_iommu_teardown_interrupts(iommu); 778 return (DDI_FAILURE); 779 } 780 781 iommu->aiomt_actual_intrs = actual; 782 iommu->aiomt_intr_state = AMD_IOMMU_INTR_ALLOCED; 783 784 if (amd_iommu_debug & AMD_IOMMU_DEBUG_INTR) { 785 cmn_err(CE_NOTE, "%s: %s%d: AMD IOMMU idx=%d. " 786 "number of interrupts actually allocated %d", 787 f, driver, instance, iommu->aiomt_idx, actual); 788 } 789 790 if (iommu->aiomt_actual_intrs < req) { 791 cmn_err(CE_WARN, "%s: %s%d: AMD IOMMU idx=%d: " 792 "ddi_intr_alloc failed: actual (%d) < req (%d)", 793 f, driver, instance, iommu->aiomt_idx, 794 iommu->aiomt_actual_intrs, req); 795 amd_iommu_teardown_interrupts(iommu); 796 return (DDI_FAILURE); 797 } 798 799 for (i = 0; i < iommu->aiomt_actual_intrs; i++) { 800 if (ddi_intr_add_handler(iommu->aiomt_intr_htable[i], 801 amd_iommu_intr_handler, (void *)iommu, NULL) 802 != DDI_SUCCESS) { 803 cmn_err(CE_WARN, "%s: %s%d: AMD IOMMU idx=%d: " 804 "ddi_intr_add_handler failed: intr = %d, err = %d", 805 f, driver, instance, iommu->aiomt_idx, i, err); 806 for (j = 0; j < i; j++) { 807 (void) ddi_intr_remove_handler( 808 iommu->aiomt_intr_htable[j]); 809 } 810 amd_iommu_teardown_interrupts(iommu); 811 return (DDI_FAILURE); 812 } 813 } 814 iommu->aiomt_intr_state = AMD_IOMMU_INTR_HANDLER; 815 816 intrcap0 = intrcapN = -1; 817 if (ddi_intr_get_cap(iommu->aiomt_intr_htable[0], &intrcap0) 818 != DDI_SUCCESS || 819 ddi_intr_get_cap( 820 iommu->aiomt_intr_htable[iommu->aiomt_actual_intrs - 1], &intrcapN) 821 != DDI_SUCCESS || intrcap0 != intrcapN) { 822 cmn_err(CE_WARN, "%s: %s%d: AMD IOMMU idx=%d: " 823 "ddi_intr_get_cap failed or inconsistent cap among " 824 "interrupts: intrcap0 (%d) < intrcapN (%d)", 825 f, driver, instance, iommu->aiomt_idx, intrcap0, intrcapN); 826 amd_iommu_teardown_interrupts(iommu); 827 return (DDI_FAILURE); 828 } 829 iommu->aiomt_intr_cap = intrcap0; 830 831 if (intrcap0 & DDI_INTR_FLAG_BLOCK) { 832 /* Need to call block enable */ 833 if (amd_iommu_debug & AMD_IOMMU_DEBUG_INTR) { 834 cmn_err(CE_NOTE, "%s: %s%d: AMD IOMMU idx=%d: " 835 "Need to call block enable", 836 f, driver, instance, iommu->aiomt_idx); 837 } 838 if (ddi_intr_block_enable(iommu->aiomt_intr_htable, 839 iommu->aiomt_actual_intrs) != DDI_SUCCESS) { 840 cmn_err(CE_WARN, "%s: %s%d: AMD IOMMU idx=%d: " 841 "ddi_intr_block enable failed ", f, driver, 842 instance, iommu->aiomt_idx); 843 (void) ddi_intr_block_disable(iommu->aiomt_intr_htable, 844 iommu->aiomt_actual_intrs); 845 amd_iommu_teardown_interrupts(iommu); 846 return (DDI_FAILURE); 847 } 848 } else { 849 if (amd_iommu_debug & AMD_IOMMU_DEBUG_INTR) { 850 cmn_err(CE_NOTE, "%s: %s%d: AMD IOMMU idx=%d: " 851 "Need to call individual enable", 852 f, driver, instance, iommu->aiomt_idx); 853 } 854 for (i = 0; i < iommu->aiomt_actual_intrs; i++) { 855 if (ddi_intr_enable(iommu->aiomt_intr_htable[i]) 856 != DDI_SUCCESS) { 857 cmn_err(CE_WARN, "%s: %s%d: AMD IOMMU idx=%d: " 858 "ddi_intr_enable failed: intr = %d", f, 859 driver, instance, iommu->aiomt_idx, i); 860 for (j = 0; j < i; j++) { 861 (void) ddi_intr_disable( 862 iommu->aiomt_intr_htable[j]); 863 } 864 amd_iommu_teardown_interrupts(iommu); 865 return (DDI_FAILURE); 866 } 867 } 868 } 869 iommu->aiomt_intr_state = AMD_IOMMU_INTR_ENABLED; 870 871 if (amd_iommu_debug & AMD_IOMMU_DEBUG_INTR) { 872 cmn_err(CE_NOTE, "%s: %s%d: AMD IOMMU idx=%d: " 873 "Interrupts successfully %s enabled. # of interrupts = %d", 874 f, driver, instance, iommu->aiomt_idx, 875 (intrcap0 & DDI_INTR_FLAG_BLOCK) ? "(block)" : 876 "(individually)", iommu->aiomt_actual_intrs); 877 } 878 879 return (DDI_SUCCESS); 880 } 881 882 static void 883 amd_iommu_teardown_interrupts(amd_iommu_t *iommu) 884 { 885 int i; 886 887 if (iommu->aiomt_intr_state & AMD_IOMMU_INTR_ENABLED) { 888 if (iommu->aiomt_intr_cap & DDI_INTR_FLAG_BLOCK) { 889 (void) ddi_intr_block_disable(iommu->aiomt_intr_htable, 890 iommu->aiomt_actual_intrs); 891 } else { 892 for (i = 0; i < iommu->aiomt_actual_intrs; i++) { 893 (void) ddi_intr_disable( 894 iommu->aiomt_intr_htable[i]); 895 } 896 } 897 } 898 899 if (iommu->aiomt_intr_state & AMD_IOMMU_INTR_HANDLER) { 900 for (i = 0; i < iommu->aiomt_actual_intrs; i++) { 901 (void) ddi_intr_remove_handler( 902 iommu->aiomt_intr_htable[i]); 903 } 904 } 905 906 if (iommu->aiomt_intr_state & AMD_IOMMU_INTR_ALLOCED) { 907 for (i = 0; i < iommu->aiomt_actual_intrs; i++) { 908 (void) ddi_intr_free(iommu->aiomt_intr_htable[i]); 909 } 910 } 911 if (iommu->aiomt_intr_state & AMD_IOMMU_INTR_TABLE) { 912 kmem_free(iommu->aiomt_intr_htable, 913 iommu->aiomt_intr_htable_sz); 914 } 915 iommu->aiomt_intr_htable = NULL; 916 iommu->aiomt_intr_htable_sz = 0; 917 iommu->aiomt_intr_state = AMD_IOMMU_INTR_INVALID; 918 } 919 920 static amd_iommu_t * 921 amd_iommu_init(dev_info_t *dip, ddi_acc_handle_t handle, int idx, 922 uint16_t cap_base) 923 { 924 amd_iommu_t *iommu; 925 int instance = ddi_get_instance(dip); 926 const char *driver = ddi_driver_name(dip); 927 uint32_t caphdr; 928 uint32_t low_addr32; 929 uint32_t hi_addr32; 930 uint32_t range; 931 uint32_t misc; 932 uint64_t pgoffset; 933 amd_iommu_acpi_global_t *global; 934 amd_iommu_acpi_ivhd_t *hinfop; 935 const char *f = "amd_iommu_init"; 936 937 global = amd_iommu_lookup_acpi_global(); 938 hinfop = amd_iommu_lookup_any_ivhd(); 939 940 low_addr32 = PCI_CAP_GET32(handle, 0, cap_base, 941 AMD_IOMMU_CAP_ADDR_LOW_OFF); 942 if (!(low_addr32 & AMD_IOMMU_REG_ADDR_LOCKED)) { 943 cmn_err(CE_WARN, "%s: %s%d: capability registers not locked. " 944 "Unable to use IOMMU unit idx=%d - skipping ...", f, driver, 945 instance, idx); 946 return (NULL); 947 } 948 949 iommu = kmem_zalloc(sizeof (amd_iommu_t), KM_SLEEP); 950 mutex_init(&iommu->aiomt_mutex, NULL, MUTEX_DRIVER, NULL); 951 mutex_enter(&iommu->aiomt_mutex); 952 953 mutex_init(&iommu->aiomt_cmdlock, NULL, MUTEX_DRIVER, NULL); 954 mutex_init(&iommu->aiomt_eventlock, NULL, MUTEX_DRIVER, NULL); 955 956 iommu->aiomt_dip = dip; 957 iommu->aiomt_idx = idx; 958 959 /* 960 * Since everything in the capability block is locked and RO at this 961 * point, copy everything into the IOMMU struct 962 */ 963 964 /* Get cap header */ 965 caphdr = PCI_CAP_GET32(handle, 0, cap_base, AMD_IOMMU_CAP_HDR_OFF); 966 iommu->aiomt_cap_hdr = caphdr; 967 iommu->aiomt_npcache = AMD_IOMMU_REG_GET32(&caphdr, 968 AMD_IOMMU_CAP_NPCACHE); 969 iommu->aiomt_httun = AMD_IOMMU_REG_GET32(&caphdr, AMD_IOMMU_CAP_HTTUN); 970 971 if (hinfop) 972 iommu->aiomt_iotlb = hinfop->ach_IotlbSup; 973 else 974 iommu->aiomt_iotlb = 975 AMD_IOMMU_REG_GET32(&caphdr, AMD_IOMMU_CAP_IOTLB); 976 977 iommu->aiomt_captype = AMD_IOMMU_REG_GET32(&caphdr, AMD_IOMMU_CAP_TYPE); 978 iommu->aiomt_capid = AMD_IOMMU_REG_GET32(&caphdr, AMD_IOMMU_CAP_ID); 979 980 /* 981 * Get address of IOMMU control registers 982 */ 983 hi_addr32 = PCI_CAP_GET32(handle, 0, cap_base, 984 AMD_IOMMU_CAP_ADDR_HI_OFF); 985 iommu->aiomt_low_addr32 = low_addr32; 986 iommu->aiomt_hi_addr32 = hi_addr32; 987 low_addr32 &= ~AMD_IOMMU_REG_ADDR_LOCKED; 988 989 if (hinfop) { 990 iommu->aiomt_reg_pa = hinfop->ach_IOMMU_reg_base; 991 ASSERT(hinfop->ach_IOMMU_pci_seg == 0); 992 } else { 993 iommu->aiomt_reg_pa = ((uint64_t)hi_addr32 << 32 | low_addr32); 994 } 995 996 /* 997 * Get cap range reg 998 */ 999 range = PCI_CAP_GET32(handle, 0, cap_base, AMD_IOMMU_CAP_RANGE_OFF); 1000 iommu->aiomt_range = range; 1001 iommu->aiomt_rng_valid = AMD_IOMMU_REG_GET32(&range, 1002 AMD_IOMMU_RNG_VALID); 1003 if (iommu->aiomt_rng_valid) { 1004 iommu->aiomt_rng_bus = AMD_IOMMU_REG_GET32(&range, 1005 AMD_IOMMU_RNG_BUS); 1006 iommu->aiomt_first_devfn = AMD_IOMMU_REG_GET32(&range, 1007 AMD_IOMMU_FIRST_DEVFN); 1008 iommu->aiomt_last_devfn = AMD_IOMMU_REG_GET32(&range, 1009 AMD_IOMMU_LAST_DEVFN); 1010 } else { 1011 iommu->aiomt_rng_bus = 0; 1012 iommu->aiomt_first_devfn = 0; 1013 iommu->aiomt_last_devfn = 0; 1014 } 1015 1016 if (hinfop) 1017 iommu->aiomt_ht_unitid = hinfop->ach_IOMMU_UnitID; 1018 else 1019 iommu->aiomt_ht_unitid = AMD_IOMMU_REG_GET32(&range, 1020 AMD_IOMMU_HT_UNITID); 1021 1022 /* 1023 * Get cap misc reg 1024 */ 1025 misc = PCI_CAP_GET32(handle, 0, cap_base, AMD_IOMMU_CAP_MISC_OFF); 1026 iommu->aiomt_misc = misc; 1027 1028 if (global) { 1029 iommu->aiomt_htatsresv = global->acg_HtAtsResv; 1030 iommu->aiomt_vasize = global->acg_VAsize; 1031 iommu->aiomt_pasize = global->acg_PAsize; 1032 } else { 1033 iommu->aiomt_htatsresv = AMD_IOMMU_REG_GET32(&misc, 1034 AMD_IOMMU_HT_ATSRSV); 1035 iommu->aiomt_vasize = AMD_IOMMU_REG_GET32(&misc, 1036 AMD_IOMMU_VA_SIZE); 1037 iommu->aiomt_pasize = AMD_IOMMU_REG_GET32(&misc, 1038 AMD_IOMMU_PA_SIZE); 1039 } 1040 1041 if (hinfop) { 1042 iommu->aiomt_msinum = hinfop->ach_IOMMU_MSInum; 1043 } else { 1044 iommu->aiomt_msinum = 1045 AMD_IOMMU_REG_GET32(&misc, AMD_IOMMU_MSINUM); 1046 } 1047 1048 /* 1049 * Set up mapping between control registers PA and VA 1050 */ 1051 pgoffset = iommu->aiomt_reg_pa & MMU_PAGEOFFSET; 1052 ASSERT(pgoffset == 0); 1053 iommu->aiomt_reg_pages = mmu_btopr(AMD_IOMMU_REG_SIZE + pgoffset); 1054 iommu->aiomt_reg_size = mmu_ptob(iommu->aiomt_reg_pages); 1055 1056 iommu->aiomt_va = (uintptr_t)device_arena_alloc( 1057 ptob(iommu->aiomt_reg_pages), VM_SLEEP); 1058 if (iommu->aiomt_va == 0) { 1059 cmn_err(CE_WARN, "%s: %s%d: Failed to alloc VA for IOMMU " 1060 "control regs. Skipping IOMMU idx=%d", f, driver, 1061 instance, idx); 1062 mutex_exit(&iommu->aiomt_mutex); 1063 (void) amd_iommu_fini(iommu, AMD_IOMMU_TEARDOWN); 1064 return (NULL); 1065 } 1066 1067 hat_devload(kas.a_hat, (void *)(uintptr_t)iommu->aiomt_va, 1068 iommu->aiomt_reg_size, 1069 mmu_btop(iommu->aiomt_reg_pa), PROT_READ | PROT_WRITE 1070 | HAT_STRICTORDER, HAT_LOAD_LOCK); 1071 1072 iommu->aiomt_reg_va = iommu->aiomt_va + pgoffset; 1073 1074 /* 1075 * Setup the various control register's VA 1076 */ 1077 iommu->aiomt_reg_devtbl_va = iommu->aiomt_reg_va + 1078 AMD_IOMMU_DEVTBL_REG_OFF; 1079 iommu->aiomt_reg_cmdbuf_va = iommu->aiomt_reg_va + 1080 AMD_IOMMU_CMDBUF_REG_OFF; 1081 iommu->aiomt_reg_eventlog_va = iommu->aiomt_reg_va + 1082 AMD_IOMMU_EVENTLOG_REG_OFF; 1083 iommu->aiomt_reg_ctrl_va = iommu->aiomt_reg_va + 1084 AMD_IOMMU_CTRL_REG_OFF; 1085 iommu->aiomt_reg_excl_base_va = iommu->aiomt_reg_va + 1086 AMD_IOMMU_EXCL_BASE_REG_OFF; 1087 iommu->aiomt_reg_excl_lim_va = iommu->aiomt_reg_va + 1088 AMD_IOMMU_EXCL_LIM_REG_OFF; 1089 iommu->aiomt_reg_cmdbuf_head_va = iommu->aiomt_reg_va + 1090 AMD_IOMMU_CMDBUF_HEAD_REG_OFF; 1091 iommu->aiomt_reg_cmdbuf_tail_va = iommu->aiomt_reg_va + 1092 AMD_IOMMU_CMDBUF_TAIL_REG_OFF; 1093 iommu->aiomt_reg_eventlog_head_va = iommu->aiomt_reg_va + 1094 AMD_IOMMU_EVENTLOG_HEAD_REG_OFF; 1095 iommu->aiomt_reg_eventlog_tail_va = iommu->aiomt_reg_va + 1096 AMD_IOMMU_EVENTLOG_TAIL_REG_OFF; 1097 iommu->aiomt_reg_status_va = iommu->aiomt_reg_va + 1098 AMD_IOMMU_STATUS_REG_OFF; 1099 1100 1101 /* 1102 * Setup the DEVICE table, CMD buffer, and LOG buffer in 1103 * memory and setup DMA access to this memory location 1104 */ 1105 if (amd_iommu_setup_tables_and_buffers(iommu) != DDI_SUCCESS) { 1106 mutex_exit(&iommu->aiomt_mutex); 1107 (void) amd_iommu_fini(iommu, AMD_IOMMU_TEARDOWN); 1108 return (NULL); 1109 } 1110 1111 if (amd_iommu_setup_exclusion(iommu) != DDI_SUCCESS) { 1112 mutex_exit(&iommu->aiomt_mutex); 1113 (void) amd_iommu_fini(iommu, AMD_IOMMU_TEARDOWN); 1114 return (NULL); 1115 } 1116 1117 amd_iommu_enable_interrupts(iommu); 1118 1119 if (amd_iommu_setup_interrupts(iommu) != DDI_SUCCESS) { 1120 mutex_exit(&iommu->aiomt_mutex); 1121 (void) amd_iommu_fini(iommu, AMD_IOMMU_TEARDOWN); 1122 return (NULL); 1123 } 1124 1125 /* 1126 * need to setup domain table before gfx bypass 1127 */ 1128 amd_iommu_init_page_tables(iommu); 1129 1130 /* 1131 * Set pass-thru for special devices like IOAPIC and HPET 1132 * 1133 * Also, gfx devices don't use DDI for DMA. No need to register 1134 * before setting up gfx passthru 1135 */ 1136 if (amd_iommu_setup_passthru(iommu) != DDI_SUCCESS) { 1137 mutex_exit(&iommu->aiomt_mutex); 1138 (void) amd_iommu_fini(iommu, AMD_IOMMU_TEARDOWN); 1139 return (NULL); 1140 } 1141 1142 if (amd_iommu_start(iommu) != DDI_SUCCESS) { 1143 mutex_exit(&iommu->aiomt_mutex); 1144 (void) amd_iommu_fini(iommu, AMD_IOMMU_TEARDOWN); 1145 return (NULL); 1146 } 1147 1148 /* xxx register/start race */ 1149 if (amd_iommu_register(iommu) != DDI_SUCCESS) { 1150 mutex_exit(&iommu->aiomt_mutex); 1151 (void) amd_iommu_fini(iommu, AMD_IOMMU_TEARDOWN); 1152 return (NULL); 1153 } 1154 1155 if (amd_iommu_debug) { 1156 cmn_err(CE_NOTE, "%s: %s%d: IOMMU idx=%d inited.", f, driver, 1157 instance, idx); 1158 } 1159 1160 return (iommu); 1161 } 1162 1163 static int 1164 amd_iommu_fini(amd_iommu_t *iommu, int type) 1165 { 1166 int idx = iommu->aiomt_idx; 1167 dev_info_t *dip = iommu->aiomt_dip; 1168 int instance = ddi_get_instance(dip); 1169 const char *driver = ddi_driver_name(dip); 1170 const char *f = "amd_iommu_fini"; 1171 1172 if (type == AMD_IOMMU_TEARDOWN) { 1173 mutex_enter(&iommu->aiomt_mutex); 1174 if (amd_iommu_unregister(iommu) != DDI_SUCCESS) { 1175 cmn_err(CE_NOTE, "%s: %s%d: Fini of IOMMU unit failed. " 1176 "idx = %d", f, driver, instance, idx); 1177 return (DDI_FAILURE); 1178 } 1179 } 1180 1181 amd_iommu_stop(iommu); 1182 1183 if (type == AMD_IOMMU_TEARDOWN) { 1184 amd_iommu_fini_page_tables(iommu); 1185 amd_iommu_teardown_interrupts(iommu); 1186 amd_iommu_teardown_exclusion(iommu); 1187 } 1188 1189 amd_iommu_teardown_tables_and_buffers(iommu, type); 1190 1191 if (type == AMD_IOMMU_QUIESCE) 1192 return (DDI_SUCCESS); 1193 1194 if (iommu->aiomt_va != NULL) { 1195 hat_unload(kas.a_hat, (void *)(uintptr_t)iommu->aiomt_va, 1196 iommu->aiomt_reg_size, HAT_UNLOAD_UNLOCK); 1197 device_arena_free((void *)(uintptr_t)iommu->aiomt_va, 1198 ptob(iommu->aiomt_reg_pages)); 1199 iommu->aiomt_va = NULL; 1200 iommu->aiomt_reg_va = NULL; 1201 } 1202 mutex_destroy(&iommu->aiomt_eventlock); 1203 mutex_destroy(&iommu->aiomt_cmdlock); 1204 mutex_exit(&iommu->aiomt_mutex); 1205 mutex_destroy(&iommu->aiomt_mutex); 1206 kmem_free(iommu, sizeof (amd_iommu_t)); 1207 1208 cmn_err(CE_NOTE, "%s: %s%d: Fini of IOMMU unit complete. idx = %d", 1209 f, driver, instance, idx); 1210 1211 return (DDI_SUCCESS); 1212 } 1213 1214 int 1215 amd_iommu_setup(dev_info_t *dip, amd_iommu_state_t *statep) 1216 { 1217 int instance = ddi_get_instance(dip); 1218 const char *driver = ddi_driver_name(dip); 1219 ddi_acc_handle_t handle; 1220 uint8_t base_class; 1221 uint8_t sub_class; 1222 uint8_t prog_class; 1223 int idx; 1224 uint32_t id; 1225 uint16_t cap_base; 1226 uint32_t caphdr; 1227 uint8_t cap_type; 1228 uint8_t cap_id; 1229 amd_iommu_t *iommu; 1230 const char *f = "amd_iommu_setup"; 1231 1232 ASSERT(instance >= 0); 1233 ASSERT(driver); 1234 1235 /* First setup PCI access to config space */ 1236 1237 if (pci_config_setup(dip, &handle) != DDI_SUCCESS) { 1238 cmn_err(CE_WARN, "%s: PCI config setup failed: %s%d", 1239 f, driver, instance); 1240 return (DDI_FAILURE); 1241 } 1242 1243 /* 1244 * The AMD IOMMU is part of an independent PCI function. There may be 1245 * more than one IOMMU in that PCI function 1246 */ 1247 base_class = pci_config_get8(handle, PCI_CONF_BASCLASS); 1248 sub_class = pci_config_get8(handle, PCI_CONF_SUBCLASS); 1249 prog_class = pci_config_get8(handle, PCI_CONF_PROGCLASS); 1250 1251 if (base_class != PCI_CLASS_PERIPH || sub_class != PCI_PERIPH_IOMMU || 1252 prog_class != AMD_IOMMU_PCI_PROG_IF) { 1253 cmn_err(CE_WARN, "%s: %s%d: invalid PCI class(0x%x)/" 1254 "subclass(0x%x)/programming interface(0x%x)", f, driver, 1255 instance, base_class, sub_class, prog_class); 1256 pci_config_teardown(&handle); 1257 return (DDI_FAILURE); 1258 } 1259 1260 /* 1261 * Find and initialize all IOMMU units in this function 1262 */ 1263 for (idx = 0; ; idx++) { 1264 if (pci_cap_probe(handle, idx, &id, &cap_base) != DDI_SUCCESS) 1265 break; 1266 1267 /* check if cap ID is secure device cap id */ 1268 if (id != PCI_CAP_ID_SECURE_DEV) { 1269 if (amd_iommu_debug) { 1270 cmn_err(CE_NOTE, 1271 "%s: %s%d: skipping IOMMU: idx(0x%x) " 1272 "cap ID (0x%x) != secure dev capid (0x%x)", 1273 f, driver, instance, idx, id, 1274 PCI_CAP_ID_SECURE_DEV); 1275 } 1276 continue; 1277 } 1278 1279 /* check if cap type is IOMMU cap type */ 1280 caphdr = PCI_CAP_GET32(handle, 0, cap_base, 1281 AMD_IOMMU_CAP_HDR_OFF); 1282 cap_type = AMD_IOMMU_REG_GET32(&caphdr, AMD_IOMMU_CAP_TYPE); 1283 cap_id = AMD_IOMMU_REG_GET32(&caphdr, AMD_IOMMU_CAP_ID); 1284 1285 if (cap_type != AMD_IOMMU_CAP) { 1286 cmn_err(CE_WARN, "%s: %s%d: skipping IOMMU: idx(0x%x) " 1287 "cap type (0x%x) != AMD IOMMU CAP (0x%x)", f, 1288 driver, instance, idx, cap_type, AMD_IOMMU_CAP); 1289 continue; 1290 } 1291 ASSERT(cap_id == PCI_CAP_ID_SECURE_DEV); 1292 ASSERT(cap_id == id); 1293 1294 iommu = amd_iommu_init(dip, handle, idx, cap_base); 1295 if (iommu == NULL) { 1296 cmn_err(CE_WARN, "%s: %s%d: skipping IOMMU: idx(0x%x) " 1297 "failed to init IOMMU", f, 1298 driver, instance, idx); 1299 continue; 1300 } 1301 1302 if (statep->aioms_iommu_start == NULL) { 1303 statep->aioms_iommu_start = iommu; 1304 } else { 1305 statep->aioms_iommu_end->aiomt_next = iommu; 1306 } 1307 statep->aioms_iommu_end = iommu; 1308 1309 statep->aioms_nunits++; 1310 } 1311 1312 pci_config_teardown(&handle); 1313 1314 if (amd_iommu_debug) { 1315 cmn_err(CE_NOTE, "%s: %s%d: state=%p: setup %d IOMMU units", 1316 f, driver, instance, (void *)statep, statep->aioms_nunits); 1317 } 1318 1319 return (DDI_SUCCESS); 1320 } 1321 1322 int 1323 amd_iommu_teardown(dev_info_t *dip, amd_iommu_state_t *statep, int type) 1324 { 1325 int instance = ddi_get_instance(dip); 1326 const char *driver = ddi_driver_name(dip); 1327 amd_iommu_t *iommu, *next_iommu; 1328 int teardown; 1329 int error = DDI_SUCCESS; 1330 const char *f = "amd_iommu_teardown"; 1331 1332 teardown = 0; 1333 for (iommu = statep->aioms_iommu_start; iommu; 1334 iommu = next_iommu) { 1335 ASSERT(statep->aioms_nunits > 0); 1336 next_iommu = iommu->aiomt_next; 1337 if (amd_iommu_fini(iommu, type) != DDI_SUCCESS) { 1338 error = DDI_FAILURE; 1339 continue; 1340 } 1341 statep->aioms_nunits--; 1342 teardown++; 1343 } 1344 1345 cmn_err(CE_NOTE, "%s: %s%d: state=%p: toredown %d units. " 1346 "%d units left", f, driver, instance, (void *)statep, 1347 teardown, statep->aioms_nunits); 1348 1349 return (error); 1350 } 1351 1352 /* Interface with IOMMULIB */ 1353 /*ARGSUSED*/ 1354 static int 1355 amd_iommu_probe(iommulib_handle_t handle, dev_info_t *rdip) 1356 { 1357 const char *driver = ddi_driver_name(rdip); 1358 char *s; 1359 amd_iommu_t *iommu = iommulib_iommu_getdata(handle); 1360 1361 if (amd_iommu_disable_list) { 1362 s = strstr(amd_iommu_disable_list, driver); 1363 if (s == NULL) 1364 return (DDI_SUCCESS); 1365 if (s == amd_iommu_disable_list || *(s - 1) == ':') { 1366 s += strlen(driver); 1367 if (*s == '\0' || *s == ':') { 1368 amd_iommu_set_passthru(iommu, rdip); 1369 return (DDI_FAILURE); 1370 } 1371 } 1372 } 1373 1374 return (DDI_SUCCESS); 1375 } 1376 1377 /*ARGSUSED*/ 1378 static int 1379 amd_iommu_allochdl(iommulib_handle_t handle, 1380 dev_info_t *dip, dev_info_t *rdip, ddi_dma_attr_t *attr, 1381 int (*waitfp)(caddr_t), caddr_t arg, ddi_dma_handle_t *dma_handlep) 1382 { 1383 return (iommulib_iommu_dma_allochdl(dip, rdip, attr, waitfp, 1384 arg, dma_handlep)); 1385 } 1386 1387 /*ARGSUSED*/ 1388 static int 1389 amd_iommu_freehdl(iommulib_handle_t handle, 1390 dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t dma_handle) 1391 { 1392 return (iommulib_iommu_dma_freehdl(dip, rdip, dma_handle)); 1393 } 1394 1395 /*ARGSUSED*/ 1396 static int 1397 map_current_window(amd_iommu_t *iommu, dev_info_t *rdip, ddi_dma_attr_t *attrp, 1398 struct ddi_dma_req *dmareq, ddi_dma_cookie_t *cookie_array, uint_t ccount, 1399 int km_flags) 1400 { 1401 const char *driver = ddi_driver_name(iommu->aiomt_dip); 1402 int instance = ddi_get_instance(iommu->aiomt_dip); 1403 int idx = iommu->aiomt_idx; 1404 int i; 1405 uint64_t start_va; 1406 char *path; 1407 int error = DDI_FAILURE; 1408 const char *f = "map_current_window"; 1409 1410 path = kmem_alloc(MAXPATHLEN, km_flags); 1411 if (path == NULL) { 1412 return (DDI_DMA_NORESOURCES); 1413 } 1414 1415 (void) ddi_pathname(rdip, path); 1416 mutex_enter(&amd_iommu_pgtable_lock); 1417 1418 if (amd_iommu_debug == AMD_IOMMU_DEBUG_PAGE_TABLES) { 1419 cmn_err(CE_NOTE, "%s: %s%d: idx=%d Attempting to get cookies " 1420 "from handle for device %s", 1421 f, driver, instance, idx, path); 1422 } 1423 1424 start_va = 0; 1425 for (i = 0; i < ccount; i++) { 1426 if ((error = amd_iommu_map_pa2va(iommu, rdip, attrp, dmareq, 1427 cookie_array[i].dmac_cookie_addr, 1428 cookie_array[i].dmac_size, 1429 AMD_IOMMU_VMEM_MAP, &start_va, km_flags)) != DDI_SUCCESS) { 1430 break; 1431 } 1432 cookie_array[i].dmac_cookie_addr = (uintptr_t)start_va; 1433 cookie_array[i].dmac_type = 0; 1434 } 1435 1436 if (i != ccount) { 1437 cmn_err(CE_WARN, "%s: %s%d: idx=%d Cannot map cookie# %d " 1438 "for device %s", f, driver, instance, idx, i, path); 1439 (void) unmap_current_window(iommu, rdip, cookie_array, 1440 ccount, i, 1); 1441 goto out; 1442 } 1443 1444 if (amd_iommu_debug & AMD_IOMMU_DEBUG_PAGE_TABLES) { 1445 cmn_err(CE_NOTE, "%s: return SUCCESS", f); 1446 } 1447 1448 error = DDI_DMA_MAPPED; 1449 out: 1450 mutex_exit(&amd_iommu_pgtable_lock); 1451 kmem_free(path, MAXPATHLEN); 1452 return (error); 1453 } 1454 1455 /*ARGSUSED*/ 1456 static int 1457 unmap_current_window(amd_iommu_t *iommu, dev_info_t *rdip, 1458 ddi_dma_cookie_t *cookie_array, uint_t ccount, int ncookies, int locked) 1459 { 1460 const char *driver = ddi_driver_name(iommu->aiomt_dip); 1461 int instance = ddi_get_instance(iommu->aiomt_dip); 1462 int idx = iommu->aiomt_idx; 1463 int i; 1464 int error = DDI_FAILURE; 1465 char *path; 1466 int pathfree; 1467 const char *f = "unmap_current_window"; 1468 1469 if (!locked) 1470 mutex_enter(&amd_iommu_pgtable_lock); 1471 1472 path = kmem_alloc(MAXPATHLEN, KM_NOSLEEP); 1473 if (path) { 1474 (void) ddi_pathname(rdip, path); 1475 pathfree = 1; 1476 } else { 1477 path = "<path-mem-alloc-failed>"; 1478 pathfree = 0; 1479 } 1480 1481 if (ncookies == -1) 1482 ncookies = ccount; 1483 1484 for (i = 0; i < ncookies; i++) { 1485 if (amd_iommu_unmap_va(iommu, rdip, 1486 cookie_array[i].dmac_cookie_addr, 1487 cookie_array[i].dmac_size, 1488 AMD_IOMMU_VMEM_MAP) != DDI_SUCCESS) { 1489 break; 1490 } 1491 } 1492 1493 if (amd_iommu_cmd(iommu, AMD_IOMMU_CMD_COMPL_WAIT, NULL, 0, 0) 1494 != DDI_SUCCESS) { 1495 cmn_err(CE_WARN, "%s: AMD IOMMU completion wait failed for: %s", 1496 f, path); 1497 } 1498 1499 if (i != ncookies) { 1500 cmn_err(CE_WARN, "%s: %s%d: idx=%d Cannot unmap cookie# %d " 1501 "for device %s", f, driver, instance, idx, i, path); 1502 error = DDI_FAILURE; 1503 goto out; 1504 } 1505 1506 error = DDI_SUCCESS; 1507 1508 out: 1509 if (pathfree) 1510 kmem_free(path, MAXPATHLEN); 1511 if (!locked) 1512 mutex_exit(&amd_iommu_pgtable_lock); 1513 return (error); 1514 } 1515 1516 /*ARGSUSED*/ 1517 static int 1518 amd_iommu_bindhdl(iommulib_handle_t handle, dev_info_t *dip, 1519 dev_info_t *rdip, ddi_dma_handle_t dma_handle, 1520 struct ddi_dma_req *dmareq, ddi_dma_cookie_t *cookiep, 1521 uint_t *ccountp) 1522 { 1523 int dma_error = DDI_DMA_NOMAPPING; 1524 int error; 1525 char *path; 1526 ddi_dma_cookie_t *cookie_array = NULL; 1527 uint_t ccount = 0; 1528 ddi_dma_impl_t *hp; 1529 ddi_dma_attr_t *attrp; 1530 int km_flags; 1531 amd_iommu_t *iommu = iommulib_iommu_getdata(handle); 1532 int instance = ddi_get_instance(rdip); 1533 const char *driver = ddi_driver_name(rdip); 1534 const char *f = "amd_iommu_bindhdl"; 1535 1536 dma_error = iommulib_iommu_dma_bindhdl(dip, rdip, dma_handle, 1537 dmareq, cookiep, ccountp); 1538 1539 if (dma_error != DDI_DMA_MAPPED && dma_error != DDI_DMA_PARTIAL_MAP) 1540 return (dma_error); 1541 1542 km_flags = iommulib_iommu_dma_get_sleep_flags(dip, dma_handle); 1543 1544 path = kmem_alloc(MAXPATHLEN, km_flags); 1545 if (path) { 1546 (void) ddi_pathname(rdip, path); 1547 } else { 1548 dma_error = DDI_DMA_NORESOURCES; 1549 goto unbind; 1550 } 1551 1552 if (amd_iommu_debug & AMD_IOMMU_DEBUG_BIND) { 1553 cmn_err(CE_NOTE, "%s: %s got cookie (%p), #cookies: %d", 1554 f, path, 1555 (void *)cookiep->dmac_cookie_addr, 1556 *ccountp); 1557 } 1558 1559 cookie_array = NULL; 1560 ccount = 0; 1561 if ((error = iommulib_iommu_dma_get_cookies(dip, dma_handle, 1562 &cookie_array, &ccount)) != DDI_SUCCESS) { 1563 cmn_err(CE_WARN, "%s: %s%d: Cannot get cookies " 1564 "for device %s", f, driver, instance, path); 1565 dma_error = error; 1566 goto unbind; 1567 } 1568 1569 hp = (ddi_dma_impl_t *)dma_handle; 1570 attrp = &hp->dmai_attr; 1571 1572 error = map_current_window(iommu, rdip, attrp, dmareq, 1573 cookie_array, ccount, km_flags); 1574 if (error != DDI_SUCCESS) { 1575 dma_error = error; 1576 goto unbind; 1577 } 1578 1579 if ((error = iommulib_iommu_dma_set_cookies(dip, dma_handle, 1580 cookie_array, ccount)) != DDI_SUCCESS) { 1581 cmn_err(CE_WARN, "%s: %s%d: Cannot set cookies " 1582 "for device %s", f, driver, instance, path); 1583 dma_error = error; 1584 goto unbind; 1585 } 1586 1587 *cookiep = cookie_array[0]; 1588 1589 if (amd_iommu_debug & AMD_IOMMU_DEBUG_BIND) { 1590 cmn_err(CE_NOTE, "%s: %s remapped cookie (%p), #cookies: %d", 1591 f, path, 1592 (void *)(uintptr_t)cookiep->dmac_cookie_addr, 1593 *ccountp); 1594 } 1595 1596 kmem_free(path, MAXPATHLEN); 1597 ASSERT(dma_error == DDI_DMA_MAPPED || dma_error == DDI_DMA_PARTIAL_MAP); 1598 return (dma_error); 1599 unbind: 1600 kmem_free(path, MAXPATHLEN); 1601 (void) iommulib_iommu_dma_unbindhdl(dip, rdip, dma_handle); 1602 return (dma_error); 1603 } 1604 1605 /*ARGSUSED*/ 1606 static int 1607 amd_iommu_unbindhdl(iommulib_handle_t handle, 1608 dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t dma_handle) 1609 { 1610 amd_iommu_t *iommu = iommulib_iommu_getdata(handle); 1611 ddi_dma_cookie_t *cookie_array = NULL; 1612 uint_t ccount = 0; 1613 int error = DDI_FAILURE; 1614 int instance = ddi_get_instance(rdip); 1615 const char *driver = ddi_driver_name(rdip); 1616 const char *f = "amd_iommu_unbindhdl"; 1617 1618 cookie_array = NULL; 1619 ccount = 0; 1620 if (iommulib_iommu_dma_get_cookies(dip, dma_handle, &cookie_array, 1621 &ccount) != DDI_SUCCESS) { 1622 cmn_err(CE_WARN, "%s: %s%d: Cannot get cookies " 1623 "for device %p", f, driver, instance, (void *)rdip); 1624 error = DDI_FAILURE; 1625 goto out; 1626 } 1627 1628 if (iommulib_iommu_dma_clear_cookies(dip, dma_handle) != DDI_SUCCESS) { 1629 cmn_err(CE_WARN, "%s: %s%d: Cannot clear cookies " 1630 "for device %p", f, driver, instance, (void *)rdip); 1631 error = DDI_FAILURE; 1632 goto out; 1633 } 1634 1635 if (iommulib_iommu_dma_unbindhdl(dip, rdip, dma_handle) 1636 != DDI_SUCCESS) { 1637 cmn_err(CE_WARN, "%s: %s%d: failed to unbindhdl for dip=%p", 1638 f, driver, instance, (void *)rdip); 1639 error = DDI_FAILURE; 1640 goto out; 1641 } 1642 1643 if (unmap_current_window(iommu, rdip, cookie_array, ccount, -1, 0) 1644 != DDI_SUCCESS) { 1645 cmn_err(CE_WARN, "%s: %s%d: failed to unmap current window " 1646 "for dip=%p", f, driver, instance, (void *)rdip); 1647 error = DDI_FAILURE; 1648 } else { 1649 error = DDI_SUCCESS; 1650 } 1651 out: 1652 if (cookie_array) 1653 kmem_free(cookie_array, sizeof (ddi_dma_cookie_t) * ccount); 1654 return (error); 1655 } 1656 1657 /*ARGSUSED*/ 1658 static int 1659 amd_iommu_sync(iommulib_handle_t handle, dev_info_t *dip, 1660 dev_info_t *rdip, ddi_dma_handle_t dma_handle, off_t off, 1661 size_t len, uint_t cache_flags) 1662 { 1663 ddi_dma_cookie_t *cookie_array = NULL; 1664 uint_t ccount = 0; 1665 int error; 1666 const char *f = "amd_iommu_sync"; 1667 1668 cookie_array = NULL; 1669 ccount = 0; 1670 if (iommulib_iommu_dma_get_cookies(dip, dma_handle, &cookie_array, 1671 &ccount) != DDI_SUCCESS) { 1672 ASSERT(cookie_array == NULL); 1673 cmn_err(CE_WARN, "%s: Cannot get cookies " 1674 "for device %p", f, (void *)rdip); 1675 error = DDI_FAILURE; 1676 goto out; 1677 } 1678 1679 if (iommulib_iommu_dma_clear_cookies(dip, dma_handle) != DDI_SUCCESS) { 1680 cmn_err(CE_WARN, "%s: Cannot clear cookies " 1681 "for device %p", f, (void *)rdip); 1682 error = DDI_FAILURE; 1683 goto out; 1684 } 1685 1686 error = iommulib_iommu_dma_sync(dip, rdip, dma_handle, off, 1687 len, cache_flags); 1688 1689 if (iommulib_iommu_dma_set_cookies(dip, dma_handle, cookie_array, 1690 ccount) != DDI_SUCCESS) { 1691 cmn_err(CE_WARN, "%s: Cannot set cookies " 1692 "for device %p", f, (void *)rdip); 1693 error = DDI_FAILURE; 1694 } else { 1695 cookie_array = NULL; 1696 ccount = 0; 1697 } 1698 1699 out: 1700 if (cookie_array) 1701 kmem_free(cookie_array, sizeof (ddi_dma_cookie_t) * ccount); 1702 return (error); 1703 } 1704 1705 /*ARGSUSED*/ 1706 static int 1707 amd_iommu_win(iommulib_handle_t handle, dev_info_t *dip, 1708 dev_info_t *rdip, ddi_dma_handle_t dma_handle, uint_t win, 1709 off_t *offp, size_t *lenp, ddi_dma_cookie_t *cookiep, 1710 uint_t *ccountp) 1711 { 1712 int error = DDI_FAILURE; 1713 amd_iommu_t *iommu = iommulib_iommu_getdata(handle); 1714 ddi_dma_cookie_t *cookie_array = NULL; 1715 uint_t ccount = 0; 1716 int km_flags; 1717 ddi_dma_impl_t *hp; 1718 ddi_dma_attr_t *attrp; 1719 struct ddi_dma_req sdmareq = {0}; 1720 int instance = ddi_get_instance(rdip); 1721 const char *driver = ddi_driver_name(rdip); 1722 const char *f = "amd_iommu_win"; 1723 1724 km_flags = iommulib_iommu_dma_get_sleep_flags(dip, dma_handle); 1725 1726 cookie_array = NULL; 1727 ccount = 0; 1728 if (iommulib_iommu_dma_get_cookies(dip, dma_handle, &cookie_array, 1729 &ccount) != DDI_SUCCESS) { 1730 cmn_err(CE_WARN, "%s: %s%d: Cannot get cookies " 1731 "for device %p", f, driver, instance, (void *)rdip); 1732 error = DDI_FAILURE; 1733 goto out; 1734 } 1735 1736 if (iommulib_iommu_dma_clear_cookies(dip, dma_handle) != DDI_SUCCESS) { 1737 cmn_err(CE_WARN, "%s: %s%d: Cannot clear cookies " 1738 "for device %p", f, driver, instance, (void *)rdip); 1739 error = DDI_FAILURE; 1740 goto out; 1741 } 1742 1743 if (iommulib_iommu_dma_win(dip, rdip, dma_handle, win, 1744 offp, lenp, cookiep, ccountp) != DDI_SUCCESS) { 1745 cmn_err(CE_WARN, "%s: %s%d: failed switch windows for dip=%p", 1746 f, driver, instance, (void *)rdip); 1747 error = DDI_FAILURE; 1748 goto out; 1749 } 1750 1751 (void) unmap_current_window(iommu, rdip, cookie_array, ccount, -1, 0); 1752 1753 if (cookie_array) { 1754 kmem_free(cookie_array, sizeof (ddi_dma_cookie_t) * ccount); 1755 cookie_array = NULL; 1756 ccount = 0; 1757 } 1758 1759 cookie_array = NULL; 1760 ccount = 0; 1761 if (iommulib_iommu_dma_get_cookies(dip, dma_handle, &cookie_array, 1762 &ccount) != DDI_SUCCESS) { 1763 cmn_err(CE_WARN, "%s: %s%d: Cannot get cookies " 1764 "for device %p", f, driver, instance, (void *)rdip); 1765 error = DDI_FAILURE; 1766 goto out; 1767 } 1768 1769 hp = (ddi_dma_impl_t *)dma_handle; 1770 attrp = &hp->dmai_attr; 1771 1772 sdmareq.dmar_flags = DDI_DMA_RDWR; 1773 error = map_current_window(iommu, rdip, attrp, &sdmareq, 1774 cookie_array, ccount, km_flags); 1775 1776 if (iommulib_iommu_dma_set_cookies(dip, dma_handle, cookie_array, 1777 ccount) != DDI_SUCCESS) { 1778 cmn_err(CE_WARN, "%s: %s%d: Cannot set cookies " 1779 "for device %p", f, driver, instance, (void *)rdip); 1780 error = DDI_FAILURE; 1781 goto out; 1782 } 1783 1784 *cookiep = cookie_array[0]; 1785 1786 return (error == DDI_SUCCESS ? DDI_SUCCESS : DDI_FAILURE); 1787 out: 1788 if (cookie_array) 1789 kmem_free(cookie_array, sizeof (ddi_dma_cookie_t) * ccount); 1790 1791 return (error); 1792 } 1793 1794 /* Obsoleted DMA routines */ 1795 1796 /*ARGSUSED*/ 1797 static int 1798 amd_iommu_map(iommulib_handle_t handle, dev_info_t *dip, 1799 dev_info_t *rdip, struct ddi_dma_req *dmareq, 1800 ddi_dma_handle_t *dma_handle) 1801 { 1802 ASSERT(0); 1803 return (iommulib_iommu_dma_map(dip, rdip, dmareq, dma_handle)); 1804 } 1805 1806 /*ARGSUSED*/ 1807 static int 1808 amd_iommu_mctl(iommulib_handle_t handle, dev_info_t *dip, 1809 dev_info_t *rdip, ddi_dma_handle_t dma_handle, 1810 enum ddi_dma_ctlops request, off_t *offp, size_t *lenp, 1811 caddr_t *objpp, uint_t cache_flags) 1812 { 1813 ASSERT(0); 1814 return (iommulib_iommu_dma_mctl(dip, rdip, dma_handle, 1815 request, offp, lenp, objpp, cache_flags)); 1816 } 1817 1818 uint64_t 1819 amd_iommu_reg_get64_workaround(uint64_t *regp, uint32_t bits) 1820 { 1821 split_t s; 1822 uint32_t *ptr32 = (uint32_t *)regp; 1823 uint64_t *s64p = &(s.u64); 1824 1825 s.u32[0] = ptr32[0]; 1826 s.u32[1] = ptr32[1]; 1827 1828 return (AMD_IOMMU_REG_GET64_IMPL(s64p, bits)); 1829 } 1830 1831 uint64_t 1832 amd_iommu_reg_set64_workaround(uint64_t *regp, uint32_t bits, uint64_t value) 1833 { 1834 split_t s; 1835 uint32_t *ptr32 = (uint32_t *)regp; 1836 uint64_t *s64p = &(s.u64); 1837 1838 s.u32[0] = ptr32[0]; 1839 s.u32[1] = ptr32[1]; 1840 1841 AMD_IOMMU_REG_SET64_IMPL(s64p, bits, value); 1842 1843 *regp = s.u64; 1844 1845 return (s.u64); 1846 } 1847 1848 void 1849 amd_iommu_read_boot_props(void) 1850 { 1851 char *propval; 1852 1853 /* 1854 * if "amd-iommu = no/false" boot property is set, 1855 * ignore AMD iommu 1856 */ 1857 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, ddi_root_node(), 1858 DDI_PROP_DONTPASS, "amd-iommu", &propval) == DDI_SUCCESS) { 1859 if (strcmp(propval, "no") == 0 || 1860 strcmp(propval, "false") == 0) { 1861 amd_iommu_disable = 1; 1862 } 1863 ddi_prop_free(propval); 1864 } 1865 1866 /* 1867 * Copy the list of drivers for which IOMMU is disabled by user. 1868 */ 1869 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, ddi_root_node(), 1870 DDI_PROP_DONTPASS, "amd-iommu-disable-list", &propval) 1871 == DDI_SUCCESS) { 1872 amd_iommu_disable_list = kmem_alloc(strlen(propval) + 1, 1873 KM_SLEEP); 1874 (void) strcpy(amd_iommu_disable_list, propval); 1875 ddi_prop_free(propval); 1876 } 1877 1878 } 1879 1880 void 1881 amd_iommu_lookup_conf_props(dev_info_t *dip) 1882 { 1883 char *disable; 1884 1885 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, dip, 1886 DDI_PROP_DONTPASS|DDI_PROP_NOTPROM, "amd-iommu", &disable) 1887 == DDI_PROP_SUCCESS) { 1888 if (strcmp(disable, "no") == 0) { 1889 amd_iommu_disable = 1; 1890 } 1891 ddi_prop_free(disable); 1892 } 1893 1894 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, dip, 1895 DDI_PROP_DONTPASS|DDI_PROP_NOTPROM, "amd-iommu-disable-list", 1896 &disable) == DDI_PROP_SUCCESS) { 1897 amd_iommu_disable_list = kmem_alloc(strlen(disable) + 1, 1898 KM_SLEEP); 1899 (void) strcpy(amd_iommu_disable_list, disable); 1900 ddi_prop_free(disable); 1901 } 1902 } 1903