1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 * 21 * 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 /* 26 * PMC 8x6G register definitions 27 */ 28 #ifndef _PMCS_REG_H 29 #define _PMCS_REG_H 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 /* 35 * PCI Constants 36 */ 37 #define PMCS_VENDOR_ID 0x11F8 38 #define PMCS_DEVICE_ID 0x8001 39 40 #define PMCS_PM8001_REV_A 0 41 #define PMCS_PM8001_REV_B 1 42 #define PMCS_PM8001_REV_C 2 43 44 #define PMCS_REGSET_0 1 45 #define PMCS_REGSET_1 2 46 #define PMCS_REGSET_2 3 47 #define PMCS_REGSET_3 4 48 49 50 /* 51 * PCIe BARs - 4 64KB memory regions 52 * 53 * BAR0-1 64KiB 54 * BAR2-3 64KiB 55 * BAR4 64KiB 56 * BAR5 64KiB 57 */ 58 59 /* 60 * The PMC 8x6G registers are defined by BARs in PCIe space. 61 * 62 * Four memory region BARS are used. 63 * 64 * The first is for the Messaging Unit. 65 * 66 * The second 64KiB region contains the PCS/PMA registers and some of the 67 * Top-Level registers. 68 * 69 * The third 64KiB region is a 64KiB window on the rest of the chip registers 70 * which can be shifted by writing a register in the second region. 71 * 72 * The fourth 64KiB region is for the message passing area. 73 */ 74 75 /* 76 * Messaging Unit Register Offsets 77 */ 78 #define PMCS_MSGU_IBDB 0x04 /* Inbound Doorbell */ 79 #define PMCS_MSGU_IBDB_CLEAR 0x20 /* InBound Doorbell Clear */ 80 #define PMCS_MSGU_OBDB 0x3c /* OutBound Doorbell */ 81 #define PMCS_MSGU_OBDB_CLEAR 0x40 /* OutBound Doorbell Clear */ 82 #define PMCS_MSGU_SCRATCH0 0x44 /* Scratchpad 0 */ 83 #define PMCS_MSGU_SCRATCH1 0x48 /* Scratchpad 1 */ 84 #define PMCS_MSGU_SCRATCH2 0x4C /* Scratchpad 2 */ 85 #define PMCS_MSGU_SCRATCH3 0x50 /* Scratchpad 3 */ 86 #define PMCS_MSGU_HOST_SCRATCH0 0x54 /* Host Scratchpad 0 */ 87 #define PMCS_MSGU_HOST_SCRATCH1 0x58 /* Host Scratchpad 1 */ 88 #define PMCS_MSGU_HOST_SCRATCH2 0x5C /* Host Scratchpad 2 */ 89 #define PMCS_MSGU_HOST_SCRATCH3 0x60 /* Host Scratchpad 3 */ 90 #define PMCS_MSGU_HOST_SCRATCH4 0x64 /* Host Scratchpad 4 */ 91 #define PMCS_MSGU_HOST_SCRATCH5 0x68 /* Host Scratchpad 5 */ 92 #define PMCS_MSGU_HOST_SCRATCH6 0x6C /* Host Scratchpad 6 */ 93 #define PMCS_MSGU_HOST_SCRATCH7 0x70 /* Host Scratchpad 7 */ 94 #define PMCS_MSGU_OBDB_MASK 0x74 /* Outbound Doorbell Mask */ 95 96 /* 97 * Inbound Doorbell and Doorbell Clear Definitions 98 * NB: The Doorbell Clear register is only used on RevA/8000 parts. 99 */ 100 #define PMCS_MSGU_IBDB_MPIIU 0x08 /* Initiate Unfreeze */ 101 #define PMCS_MSGU_IBDB_MPIIF 0x04 /* Initiate Freeze */ 102 #define PMCS_MSGU_IBDB_MPICTU 0x02 /* Initiate MPI Termination */ 103 #define PMCS_MSGU_IBDB_MPIINI 0x01 /* Initiate MPI */ 104 105 /* 106 * Outbound Doorbell and Doorbell Clear Register 107 * 108 * The Doorbell Clear register is only used on RevA/8000 parts. 109 * 110 * Each bit of the ODR is mapped 1-to-1 to a MSI or MSI-X vector 111 * table entry. There are 32 MSI and 16 MSI-X entries. The top 112 * 16 bits are mapped to the low 16 bits for MSI-X. For legacy 113 * INT-X, any bit will generate a host interrupt. 114 * 115 * Each bit in the Outbound Doorbell Clear is used to clear the 116 * corresponding bit in the ODR. For INT-X it also then deasserts 117 * any interrupt condition. 118 */ 119 #define PMCS_MSI_INTS 32 120 #define PMCS_MSIX_INTS 16 121 122 /* 123 * Scratchpad 0 Definitions 124 * 125 * When the AAP is ready state (see Scratchpad 1), bits 31:26 is the offset 126 * within PCIe space for another BAR that, when mapped, will point to a region 127 * that conains the MPI Configuration table (the offset of which is in bits 128 * 25:0 of this register) 129 * 130 * When the AAP is in error state, this register contains additional error 131 * information. 132 */ 133 #define PMCS_MSGU_MPI_BAR_SHIFT 26 134 #define PMCS_MSGU_MPI_OFFSET_MASK ((1 << PMCS_MSGU_MPI_BAR_SHIFT) - 1) 135 136 /* 137 * Scratchpad 1 Definitions 138 * 139 * The bottom two bits are the AAP state of the 8x6G. 140 * 141 * When the AAP is in error state, bits 31:10 contain the error indicator. 142 * 143 */ 144 #define PMCS_MSGU_AAP_STATE_MASK 0x03 145 #define PMCS_MSGU_AAP_STATE_POR 0 146 #define PMCS_MSGU_AAP_STATE_SOFT_RESET 1 147 #define PMCS_MSGU_AAP_STATE_ERROR 2 148 #define PMCS_MSGU_AAP_STATE_READY 3 149 #define PMCS_MSGU_AAP_SFR_PROGRESS 0x04 150 #define PMCS_MSGU_AAP_ERROR_MASK 0xfffffc00 151 152 /* 153 * Scratchpad 2 Definitions 154 * 155 * Bits 31:10 contain error information if the IOP is in error state. 156 */ 157 #define PMCS_MSGU_IOP_STATE_MASK 0x03 158 #define PMCS_MSGU_IOP_STATE_POR 0 159 #define PMCS_MSGU_IOP_STATE_SOFT_RESET 1 160 #define PMCS_MSGU_IOP_STATE_ERROR 2 161 #define PMCS_MSGU_IOP_STATE_READY 3 162 163 #define PMCS_MSGU_HOST_SOFT_RESET_READY 0x04 164 #define PMCS_MSGU_CPU_SOFT_RESET_READY 0x08 165 166 /* 167 * Scratchpad 3 Definitions 168 * 169 * Contains additional error information if the IOP is in error state 170 * (see Scratchpad 2) 171 */ 172 173 /* 174 * Host Scratchpad 0 175 * Soft Reset Signature 176 */ 177 #define HST_SFT_RESET_SIG 0x252ACBCD 178 179 /* 180 * Host Scratchpad 1 181 * 182 * This is a bit mask for freeze or unfreeze operations for IQs 0..31 183 */ 184 185 /* 186 * Host Scratchpad 2 187 * 188 * This is a bit mask for freeze or unfreeze operations for IQs 32..63 189 */ 190 191 /* 192 * Outbound Doorbell Mask Register 193 * 194 * Each bit set here masks bits and interrupt assertion for the corresponding 195 * bit (and vector) in the ODR. 196 */ 197 198 /* 199 * GSM Registers 200 */ 201 #define GSM_BASE_MASK 0x00ffff 202 #define NMI_EN_VPE0_IOP 0x60418 203 #define NMI_EN_VPE0_AAP1 0x70418 204 #define RB6_ACCESS 0x6A80C0 205 #define GSM_CFG_AND_RESET 0x700000 206 #define RAM_ECC_DOUBLE_ERROR_INDICATOR 0x700018 207 #define READ_ADR_PARITY_CHK_EN 0x700038 208 #define WRITE_ADR_PARITY_CHK_EN 0x700040 209 #define WRITE_DATA_PARITY_CHK_EN 0x700048 210 #define READ_ADR_PARITY_ERROR_INDICATOR 0x700058 211 #define WRITE_ADR_PARITY_ERROR_INDICATOR 0x700060 212 #define WRITE_DATA_PARITY_ERROR_INDICATOR 0x700068 213 214 /* 215 * GSM Share Memory, IO Status Table and Ring Buffer 216 */ 217 #define GSM_SM_BLKSZ 0x10000 218 #define GSM_SM_BASE 0x400000 219 #define IO_STATUS_TABLE_BASE 0x640000 220 #define RING_BUF_STORAGE_0 0x680000 221 #define RING_BUF_STORAGE_1 0x690000 222 #define RING_BUF_PTR_ACC_BASE 0x6A0000 223 224 #define IO_STATUS_TABLE_BLKNM 0x4 225 #define GSM_SM_BLKNM 0x10 226 #define RING_BUF_PTR_OFF 0x1000 227 #define RING_BUF_PTR_SIZE 0xFF8 228 #define RING_BUF_ACC_OFF 0x8000 229 #define RING_BUF_ACC_SIZE 0xFF8 230 231 /* 232 * GSM Configuration and Reset Bits 233 */ 234 #define MST_XCBI_SW_RSTB (1 << 14) 235 #define COM_SLV_SW_RSTB (1 << 13) 236 #define QSSP_SW_RSTB (1 << 12) 237 #define RAAE_SW_RSTB (1 << 11) 238 #define RB_1_SW_RSTB (1 << 9) 239 #define SM_SW_RSTB (1 << 8) 240 241 #define COHERENCY_GAP_SHIFT 4 242 #define COHERENCY_GAP_MASK 0xf0 243 #define COHERENCY_GAP_DEFAULT (8 << COHERENCY_GAP_SHIFT) 244 245 #define COHERENCY_MODE (1 << 3) 246 #define RB_WSTRB_ERRCHK_EN (1 << 2) 247 #define RAAE_PORT2_EN (1 << 1) 248 #define GSM_WCI_MODE (1 << 0) 249 #define PMCS_SOFT_RESET_BITS \ 250 (COM_SLV_SW_RSTB|QSSP_SW_RSTB|RAAE_SW_RSTB|RB_1_SW_RSTB|SM_SW_RSTB) 251 252 #define RB6_NMI_SIGNATURE 0x00001234 253 254 /* 255 * PMCS PCI Configuration Registers 256 */ 257 #define PMCS_PCI_PMC 0x40 258 #define PMCS_PCI_PMCSR 0x44 259 #define PMCS_PCI_MSI 0x50 260 #define PMCS_PCI_MAL 0x54 261 #define PMCS_PCI_MAU 0x58 262 #define PMCS_PCI_MD 0x5C 263 #define PMCS_PCI_PCIE 0x70 264 #define PMCS_PCI_DEV_CAP 0x74 265 #define PMCS_PCI_DEV_CTRL 0x78 266 #define PMCS_PCI_LINK_CAP 0x7C 267 #define PMCS_PCI_LINK_CTRL 0x80 268 #define PMCS_PCI_MSIX_CAP 0xAC 269 #define PMCS_PCI_TBL_OFFSET 0xB0 270 #define PMCS_PCI_PBA_OFFSET 0xB4 271 #define PMCS_PCI_PCIE_CAP_HD 0x100 272 #define PMCS_PCI_UE_STAT 0x104 273 #define PMCS_PCI_UE_MASK 0x108 274 #define PMCS_PCI_UE_SEV 0x10C 275 #define PMCS_PCI_CE_STAT 0x110 276 #define PMCS_PCI_CE_MASK 0x114 277 #define PMCS_PCI_ADV_ERR_CTRL 0x118 278 #define PMCS_PCI_HD_LOG_DW 0x11C 279 280 /* 281 * Top Level Registers 282 */ 283 /* these registers are in MEMBASE-III */ 284 #define PMCS_SPC_RESET 0x0 285 #define PMCS_SPC_BOOT_STRAP 0x8 286 #define PMCS_SPC_DEVICE_ID 0x20 287 #define PMCS_DEVICE_REVISION 0x24 288 /* these registers are in MEMBASE-II */ 289 #define PMCS_EVENT_INT_ENABLE 0x3040 290 #define PMCS_EVENT_INT_STAT 0x3044 291 #define PMCS_ERROR_INT_ENABLE 0x3048 292 #define PMCS_ERROR_INT_STAT 0x304C 293 #define PMCS_AXI_TRANS 0x3258 294 #define PMCS_OBDB_AUTO_CLR 0x335C 295 #define PMCS_INT_COALESCING_TIMER 0x33C0 296 #define PMCS_INT_COALESCING_CONTROL 0x33C4 297 298 299 /* 300 * Chip Reset Register Bits (PMCS_SPC_RESET) 301 * 302 * NB: all bits are inverted. That is, the normal state is '1'. 303 * When '0' is set, the action is taken. 304 */ 305 #define PMCS_SPC_HARD_RESET 0x00 306 #define PMCS_SPC_HARD_RESET_CLR 0xffffffff 307 308 309 #define SW_DEVICE_RSTB (1 << 31) 310 #define PCIE_PC_SXCBI_ARESETN (1 << 26) 311 #define PMIC_CORE_RSTB (1 << 25) 312 #define PMIC_SXCBI_ARESETN (1 << 24) 313 #define LMS_SXCBI_ARESETN (1 << 23) 314 #define PCS_SXCBI_ARESETN (1 << 22) 315 #define PCIE_SFT_RSTB (1 << 21) 316 #define PCIE_PWR_RSTB (1 << 20) 317 #define PCIE_AL_SXCBI_ARESETN (1 << 19) 318 #define BDMA_SXCBI_ARESETN (1 << 18) 319 #define BDMA_CORE_RSTB (1 << 17) 320 #define DDR2_RSTB (1 << 16) 321 #define GSM_RSTB (1 << 8) 322 #define PCS_RSTB (1 << 7) 323 #define PCS_LM_RSTB (1 << 6) 324 #define PCS_AAP2_SS_RSTB (1 << 5) 325 #define PCS_AAP1_SS_RSTB (1 << 4) 326 #define PCS_IOP_SS_RSTB (1 << 3) 327 #define PCS_SPBC_RSTB (1 << 2) 328 #define RAAE_RSTB (1 << 1) 329 #define OSSP_RSTB (1 << 0) 330 331 332 /* 333 * Timer Enables Register 334 */ 335 #define PMCS_TENABLE_WINDOW_OFFSET 0x30000 336 #define PMCS_TENABLE_BASE 0x0209C 337 #define PMCS_TENABLE_MULTIPLIER 0x04000 338 339 /* 340 * Special register (MEMBASE-III) for Step 5.5 in soft reset sequence to set 341 * GPIO into tri-state mode (temporary workaround for 1.07.xx beta firmware) 342 */ 343 #define PMCS_GPIO_TRISTATE_MODE_ADDR 0x9010C 344 #define PMCS_GPIO_TSMODE_BIT0 (1 << 0) 345 #define PMCS_GPIO_TSMODE_BIT1 (1 << 1) 346 347 348 /* 349 * Register Access Inline Functions 350 */ 351 uint32_t pmcs_rd_msgunit(pmcs_hw_t *, uint32_t); 352 uint32_t pmcs_rd_gsm_reg(pmcs_hw_t *, uint32_t); 353 uint32_t pmcs_rd_topunit(pmcs_hw_t *, uint32_t); 354 uint32_t pmcs_rd_mpi_tbl(pmcs_hw_t *, uint32_t); 355 uint32_t pmcs_rd_gst_tbl(pmcs_hw_t *, uint32_t); 356 uint32_t pmcs_rd_iqc_tbl(pmcs_hw_t *, uint32_t); 357 uint32_t pmcs_rd_oqc_tbl(pmcs_hw_t *, uint32_t); 358 uint32_t pmcs_rd_iqci(pmcs_hw_t *, uint32_t); 359 uint32_t pmcs_rd_iqpi(pmcs_hw_t *, uint32_t); 360 uint32_t pmcs_rd_oqci(pmcs_hw_t *, uint32_t); 361 uint32_t pmcs_rd_oqpi(pmcs_hw_t *, uint32_t); 362 363 void pmcs_wr_msgunit(pmcs_hw_t *, uint32_t, uint32_t); 364 void pmcs_wr_gsm_reg(pmcs_hw_t *, uint32_t, uint32_t); 365 void pmcs_wr_topunit(pmcs_hw_t *, uint32_t, uint32_t); 366 void pmcs_wr_mpi_tbl(pmcs_hw_t *, uint32_t, uint32_t); 367 void pmcs_wr_gst_tbl(pmcs_hw_t *, uint32_t, uint32_t); 368 void pmcs_wr_iqc_tbl(pmcs_hw_t *, uint32_t, uint32_t); 369 void pmcs_wr_oqc_tbl(pmcs_hw_t *, uint32_t, uint32_t); 370 void pmcs_wr_iqci(pmcs_hw_t *, uint32_t, uint32_t); 371 void pmcs_wr_iqpi(pmcs_hw_t *, uint32_t, uint32_t); 372 void pmcs_wr_oqci(pmcs_hw_t *, uint32_t, uint32_t); 373 void pmcs_wr_oqpi(pmcs_hw_t *, uint32_t, uint32_t); 374 375 #ifdef __cplusplus 376 } 377 #endif 378 #endif /* _PMCS_REG_H */ 379