1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 * 21 * 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 #ifndef _PMCS_DEF_H 26 #define _PMCS_DEF_H 27 #ifdef __cplusplus 28 extern "C" { 29 #endif 30 31 typedef enum { 32 NOTHING, /* nothing connected here */ 33 SATA, /* SATA connection */ 34 SAS, /* direct or indirect SAS connection */ 35 EXPANDER, /* connection to an expander */ 36 NEW /* Brand new device (pending state) */ 37 } pmcs_dtype_t; 38 39 /* 40 * This structure defines a PHY device that represents what we 41 * are connected to. 42 * 43 * The eight real physical PHYs that are in the PMC8X6G are represented 44 * as an array of eight of these structures which define what these 45 * real PHYs are connected to. 46 * 47 * Depending upon what is actually connected to each PHY, the 48 * type set will define what we're connected to. If it is 49 * a direct SATA connection, the phy will describe a SATA endpoint 50 * If it is a direct SAS connection, it will describe a SAS 51 * endpoint. 52 * 53 * If it is an EXPANDER, this will describe the edge of an expander. 54 * As we perform discovery on what is in an EXPANDER we define an 55 * additional list of phys that represent what the Expander is connected to. 56 */ 57 #define PMCS_HW_MIN_LINK_RATE SAS_LINK_RATE_1_5GBIT 58 #define PMCS_HW_MAX_LINK_RATE SAS_LINK_RATE_6GBIT 59 60 #define PMCS_INVALID_DEVICE_ID 0xffffffff 61 #define PMCS_PHY_INVALID_PORT_ID 0xf 62 63 #define PMCS_PM_MAX_NAMELEN 16 64 65 struct pmcs_phy { 66 pmcs_phy_t *sibling; /* sibling phy */ 67 pmcs_phy_t *parent; /* parent phy */ 68 pmcs_phy_t *children; /* head of list of children */ 69 pmcs_phy_t *dead_next; /* dead PHY list link */ 70 list_node_t list_node; /* list element */ 71 uint32_t device_id; /* PMC8X6G device handle */ 72 uint32_t 73 ncphy : 8, /* # of contained phys for expander */ 74 hw_event_ack : 24; /* XXX: first level phy event acked */ 75 uint8_t phynum; /* phy number on parent expander */ 76 uint8_t width; /* how many phys wide */ 77 uint8_t ds_recovery_retries; /* # error retry attempts */ 78 uint8_t ds_prev_good_recoveries; /* # successful recoveries */ 79 clock_t prev_recovery; /* previous successful recovery */ 80 clock_t last_good_recovery; /* oldest successful recovery */ 81 /* within PMCS_MAX_DS_RECOVERY_TIME time frame */ 82 pmcs_dtype_t dtype; /* current dtype of the phy */ 83 pmcs_dtype_t pend_dtype; /* new dtype (pending change) */ 84 uint32_t 85 level : 8, /* level in expander tree */ 86 tolerates_sas2 : 1, /* tolerates SAS2 SMP */ 87 spinup_hold : 1, /* spinup hold needs releasing */ 88 atdt : 3, /* attached device type */ 89 portid : 4, /* PMC8X6G port context */ 90 link_rate : 4, /* current supported speeds */ 91 valid_device_id : 1, /* device id is valid */ 92 abort_sent : 1, /* we've sent an abort */ 93 abort_pending : 1, /* we have an abort pending */ 94 need_rl_ext : 1, /* need SATA RL_EXT recocvery */ 95 subsidiary : 1, /* this is part of a wide phy */ 96 configured : 1, /* is configured */ 97 dead : 1, /* dead */ 98 changed : 1, /* this phy is changing */ 99 deregister_wait : 1; /* phy waiting to get deregistered */ 100 clock_t config_stop; /* When config attempts will stop */ 101 hrtime_t abort_all_start; 102 kcondvar_t abort_all_cv; /* Wait for ABORT_ALL completion */ 103 kmutex_t phy_lock; 104 volatile uint32_t ref_count; /* Targets & work on this PHY */ 105 uint8_t sas_address[8]; /* SAS address for this PHY */ 106 struct { 107 uint32_t 108 prog_min_rate :4, 109 hw_min_rate :4, 110 prog_max_rate :4, 111 hw_max_rate :4, 112 reserved :16; 113 } state; 114 char path[32]; /* path name for this phy */ 115 pmcs_hw_t *pwp; /* back ptr to hba struct */ 116 pmcs_iport_t *iport; /* back ptr to the iport handle */ 117 pmcs_xscsi_t *target; /* back ptr to current target */ 118 kstat_t *phy_stats; /* kstats for this phy */ 119 /* 120 * Attached port phy mask and target port phymask. With 16 bytes 121 * we can represent a phymask for anything with up to 64 ports 122 */ 123 uint64_t att_port_pm; /* att port pm for this PHY */ 124 uint64_t att_port_pm_tmp; /* Temp area for wide-ports */ 125 char att_port_pm_str[PMCS_PM_MAX_NAMELEN + 1]; 126 uint64_t tgt_port_pm; /* tgt port pm for this PHY */ 127 uint64_t tgt_port_pm_tmp; /* Temp area for wide-ports */ 128 char tgt_port_pm_str[PMCS_PM_MAX_NAMELEN + 1]; 129 }; 130 131 /* maximum number of ds recovery retries (ds_recovery_retries) */ 132 #define PMCS_MAX_DS_RECOVERY_RETRIES 10 133 134 /* max time allowed for successful recovery */ 135 #define PMCS_MAX_DS_RECOVERY_TIME (60 * 1000000) /* 60 seconds */ 136 137 /* ds recovery on same same phy is not allowed within this interval */ 138 #define PMCS_DS_RECOVERY_INTERVAL (1000000) /* 1 second */ 139 140 141 /* 142 * Inbound and Outbound Queue Related Definitions. 143 * 144 * The PMC8X6G has a programmable number of inbound and outbound circular 145 * queues for use in message passing between the host and the PMC8X6G 146 * (up to 64 queues for the Rev C Chip). This driver does not use all 147 * possible queues. 148 * 149 * Each Queue is given 4K of consistent memory and we set a 64 byte size for 150 * the queue entry size (this gives us 256 queue entries per queue). 151 * 152 * This allocation then continues up a further PMCS_SCRATCH_SIZE bytes 153 * that the driver uses as a temporary scratch area for things like 154 * SMP discovery. 155 * 156 * This control area looks like this: 157 * 158 * Offset What 159 * ------------------------------------------------ 160 * 0 IQ 0 Consumer Index 161 * 4 IQ 1 Consumer Index 162 * 8..255 ... 163 * 252..255 IQ 63 Consumer Index 164 * 256 OQ 0 Producer Index 165 * 260 OQ 1 Producer Index 166 * 264..259 .... 167 * 508..511 OQ 63 Producer Index 168 * 512..512+PMCS_SCRATCH_SIZE-1 Scratch area. 169 */ 170 #define IQCI_BASE_OFFSET 0 171 #define IQ_OFFSET(qnum) (IQCI_BASE_OFFSET + (qnum << 2)) 172 #define OQPI_BASE_OFFSET 256 173 #define OQ_OFFSET(qnum) (OQPI_BASE_OFFSET + (qnum << 2)) 174 175 /* 176 * Work related structures. Each one of these structures is paired 177 * with *any* command that is fed to the PMC8X6G via one of the 178 * Inbound Queues. The work structure has a tag to compare with 179 * the message that comes back out of an Outbound Queue. The 180 * work structure also points to the phy which this command is 181 * tied to. It also has a pointer a callback function (if defined). 182 * See that TAG Architecture below for the various kinds of 183 * dispositions of a work structure. 184 */ 185 186 /* 187 * Work Structure States 188 * 189 * NIL -> READY 190 * READY -> NIL 191 * READY -> ONCHIP 192 * ONCHIP -> INTR 193 * INTR -> READY 194 * INTR -> NIL 195 * INTR -> ABORTED 196 * INTR -> TIMED_OUT 197 * ABORTED -> NIL 198 * TIMED_OUT -> NIL 199 */ 200 typedef enum { 201 PMCS_WORK_STATE_NIL = 0, 202 PMCS_WORK_STATE_READY, 203 PMCS_WORK_STATE_ONCHIP, 204 PMCS_WORK_STATE_INTR, 205 PMCS_WORK_STATE_IOCOMPQ, 206 PMCS_WORK_STATE_ABORTED, 207 PMCS_WORK_STATE_TIMED_OUT 208 } pmcs_work_state_t; 209 210 struct pmcwork { 211 STAILQ_ENTRY(pmcwork) next; 212 kmutex_t lock; 213 kcondvar_t sleep_cv; 214 void *ptr; /* linkage or callback function */ 215 void *arg; /* command specific data */ 216 pmcs_phy_t *phy; /* phy who owns this command */ 217 pmcs_xscsi_t *xp; /* Back pointer to xscsi struct */ 218 volatile uint32_t htag; /* tag for this structure */ 219 uint32_t abt_htag; /* Tag of command to be aborted */ 220 uint32_t 221 timer : 27, 222 onwire : 1, 223 dead : 1, 224 state : 3; 225 hrtime_t start; /* timestamp start */ 226 uint32_t ssp_event; /* ssp event */ 227 pmcs_dtype_t dtype; /* stash, incase phy gets cleared */ 228 229 void *last_ptr; 230 void *last_arg; 231 pmcs_phy_t *last_phy; 232 pmcs_xscsi_t *last_xp; 233 uint32_t last_htag; 234 pmcs_work_state_t last_state; 235 hrtime_t finish; 236 }; 237 238 #define PMCS_REC_EVENT 0xffffffff /* event recovery */ 239 240 /* 241 * This structure defines a PMC-Sierra defined firmware header. 242 */ 243 #pragma pack(4) 244 typedef struct { 245 char vendor_id[8]; 246 uint8_t product_id; 247 uint8_t hwrev; 248 uint8_t destination_partition; 249 uint8_t reserved0; 250 uint8_t fwrev[4]; 251 uint32_t firmware_length; 252 uint32_t crc; 253 uint32_t start_address; 254 uint8_t data[]; 255 } pmcs_fw_hdr_t; 256 #pragma pack() 257 258 /* 259 * Offlevel work as a bit pattern. 260 */ 261 #define PMCS_WORK_DISCOVER 0 262 #define PMCS_WORK_ABORT_HANDLE 3 263 #define PMCS_WORK_SPINUP_RELEASE 4 264 #define PMCS_WORK_SAS_HW_ACK 5 265 #define PMCS_WORK_SATA_RUN 6 266 #define PMCS_WORK_RUN_QUEUES 7 267 #define PMCS_WORK_ADD_DMA_CHUNKS 8 268 #define PMCS_WORK_DS_ERR_RECOVERY 9 269 #define PMCS_WORK_SSP_EVT_RECOVERY 10 270 #define PMCS_WORK_DEREGISTER_DEV 11 271 272 /* 273 * The actual values as they appear in work_flags 274 */ 275 #define PMCS_WORK_FLAG_DISCOVER (1 << 0) 276 #define PMCS_WORK_FLAG_ABORT_HANDLE (1 << 3) 277 #define PMCS_WORK_FLAG_SPINUP_RELEASE (1 << 4) 278 #define PMCS_WORK_FLAG_SAS_HW_ACK (1 << 5) 279 #define PMCS_WORK_FLAG_SATA_RUN (1 << 6) 280 #define PMCS_WORK_FLAG_RUN_QUEUES (1 << 7) 281 #define PMCS_WORK_FLAG_ADD_DMA_CHUNKS (1 << 8) 282 #define PMCS_WORK_FLAG_DS_ERR_RECOVERY (1 << 9) 283 #define PMCS_WORK_FLAG_SSP_EVT_RECOVERY (1 << 10) 284 #define PMCS_WORK_FLAG_DEREGISTER_DEV (1 << 11) 285 286 /* 287 * This structure is used by this function to test MPI (and interrupts) 288 * after MPI has been started to make sure it's working reliably. 289 */ 290 typedef struct { 291 uint32_t signature; 292 uint32_t count; 293 uint32_t *ptr; 294 } echo_test_t; 295 #define ECHO_SIGNATURE 0xbebebeef 296 297 /* 298 * Tag Architecture. The PMC has 32 bit tags for MPI messages. 299 * We use this tag this way. 300 * 301 * bits what 302 * ------------------------ 303 * 31 done bit 304 * 30..28 tag type 305 * 27..12 rolling serial number 306 * 11..0 index into work area to get pmcwork structure 307 * 308 * A tag type of NONE means that nobody is waiting on any results, 309 * so the interrupt code frees the work structure that has this 310 * tag. 311 * 312 * A tag type of CBACK means that the the interrupt handler 313 * takes the tag 'arg' in the work structure to be a callback 314 * function pointer (see pmcs_cb_t). The callee is responsible 315 * for freeing the work structure that has this tag. 316 * 317 * A tag type of WAIT means that the issuer of the work needs 318 * be woken up from interrupt level when the command completes 319 * (or times out). If work structure tag 'arg' is non-null, 320 * up to 2*PMCS_QENTRY_SIZE bits of data from the Outbound Queue 321 * entry may be copied to the area pointed to by 'arg'. This 322 * allows issuers to get directly at the results of the command 323 * they issed. The synchronization point for the issuer and the 324 * interrupt code for command done notification is the setting 325 * of the 'DONE' bit in the tag as stored in the work structure. 326 */ 327 #define PMCS_TAG_TYPE_FREE 0 328 #define PMCS_TAG_TYPE_NONE 1 329 #define PMCS_TAG_TYPE_CBACK 2 330 #define PMCS_TAG_TYPE_WAIT 3 331 #define PMCS_TAG_TYPE_SHIFT 28 332 #define PMCS_TAG_SERNO_SHIFT 12 333 #define PMCS_TAG_INDEX_SHIFT 0 334 #define PMCS_TAG_TYPE_MASK 0x70000000 335 #define PMCS_TAG_DONE 0x80000000 336 #define PMCS_TAG_SERNO_MASK 0x0ffff000 337 #define PMCS_TAG_INDEX_MASK 0x00000fff 338 #define PMCS_TAG_TYPE(x) \ 339 (((x) & PMCS_TAG_TYPE_MASK) >> PMCS_TAG_TYPE_SHIFT) 340 #define PMCS_TAG_SERNO(x) \ 341 (((x) & PMCS_TAG_SERNO_MASK) >> PMCS_TAG_SERNO_SHIFT) 342 #define PMCS_TAG_INDEX(x) \ 343 (((x) & PMCS_TAG_INDEX_MASK) >> PMCS_TAG_INDEX_SHIFT) 344 #define PMCS_TAG_FREE 0 345 #define PMCS_COMMAND_DONE(x) \ 346 (((x)->htag == PMCS_TAG_FREE) || (((x)->htag & PMCS_TAG_DONE) != 0)) 347 #define PMCS_COMMAND_ACTIVE(x) \ 348 ((x)->htag != PMCS_TAG_FREE && (x)->state == PMCS_WORK_STATE_ONCHIP) 349 350 /* 351 * Miscellaneous Definitions 352 */ 353 #define CLEAN_MESSAGE(m, x) { \ 354 int _j = x; \ 355 while (_j < PMCS_MSG_SIZE) { \ 356 m[_j++] = 0; \ 357 } \ 358 } 359 360 #define COPY_MESSAGE(t, f, a) { \ 361 int _j; \ 362 for (_j = 0; _j < a; _j++) { \ 363 t[_j] = f[_j]; \ 364 } \ 365 while (_j < PMCS_MSG_SIZE) { \ 366 t[_j++] = 0; \ 367 } \ 368 } 369 370 #define PMCS_PHY_ADDRESSABLE(pp) \ 371 ((pp)->level == 0 && (pp)->dtype == SATA && \ 372 ((pp)->sas_address[0] >> 4) != 5) 373 374 #define RESTART_DISCOVERY(pwp) \ 375 ASSERT(!mutex_owned(&pwp->config_lock)); \ 376 mutex_enter(&pwp->config_lock); \ 377 pwp->config_changed = B_TRUE; \ 378 mutex_exit(&pwp->config_lock); \ 379 SCHEDULE_WORK(pwp, PMCS_WORK_DISCOVER); 380 381 #define RESTART_DISCOVERY_LOCKED(pwp) \ 382 ASSERT(mutex_owned(&pwp->config_lock)); \ 383 pwp->config_changed = B_TRUE; \ 384 SCHEDULE_WORK(pwp, PMCS_WORK_DISCOVER); 385 386 #define PHY_CHANGED(pwp, p) \ 387 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, p, NULL, "%s changed in " \ 388 "%s line %d", p->path, __func__, __LINE__); \ 389 p->changed = 1 390 391 #define PHY_CHANGED_AT_LOCATION(pwp, p, func, line) \ 392 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, p, NULL, "%s changed in " \ 393 "%s line %d", p->path, func, line); \ 394 p->changed = 1 395 396 #define PHY_TYPE(pptr) \ 397 (((pptr)->dtype == NOTHING)? "NOTHING" : \ 398 (((pptr)->dtype == SATA)? "SATA" : \ 399 (((pptr)->dtype == SAS)? "SAS" : "EXPANDER"))) 400 401 #define IS_ROOT_PHY(pptr) (pptr->parent == NULL) 402 403 #define PMCS_HIPRI(pwp, oq, c) \ 404 (pwp->hipri_queue & (1 << PMCS_IQ_OTHER)) ? \ 405 (PMCS_IOMB_HIPRI | PMCS_IOMB_IN_SAS(oq, c)) : \ 406 (PMCS_IOMB_IN_SAS(oq, c)) 407 408 #define SCHEDULE_WORK(hwp, wrk) \ 409 (void) atomic_set_long_excl(&hwp->work_flags, wrk) 410 411 /* 412 * Check to see if the requested work bit is set. Either way, the bit will 413 * be cleared upon return. 414 */ 415 #define WORK_SCHEDULED(hwp, wrk) \ 416 (atomic_clear_long_excl(&hwp->work_flags, wrk) == 0) 417 418 /* 419 * Check to see if the requested work bit is set. The value will not be 420 * changed in this case. The atomic_xx_nv operations can be quite expensive 421 * so this should not be used in non-DEBUG code. 422 */ 423 #define WORK_IS_SCHEDULED(hwp, wrk) \ 424 ((atomic_and_ulong_nv(&hwp->work_flags, (ulong_t)-1) & (1 << wrk)) != 0) 425 426 #define WAIT_FOR(p, t, r) \ 427 r = 0; \ 428 while (!PMCS_COMMAND_DONE(p)) { \ 429 clock_t tmp = cv_timedwait(&p->sleep_cv, \ 430 &p->lock, ddi_get_lbolt() + \ 431 drv_usectohz(t * 1000)); \ 432 if (!PMCS_COMMAND_DONE(p) && tmp < 0) { \ 433 r = 1; \ 434 break; \ 435 } \ 436 } 437 438 /* 439 * Signal the next I/O completion thread to start running. 440 */ 441 442 #define PMCS_CQ_RUN_LOCKED(hwp) \ 443 if (!STAILQ_EMPTY(&hwp->cq) || hwp->iocomp_cb_head) { \ 444 pmcs_cq_thr_info_t *cqti; \ 445 cqti = &hwp->cq_info.cq_thr_info \ 446 [hwp->cq_info.cq_next_disp_thr]; \ 447 hwp->cq_info.cq_next_disp_thr++; \ 448 if (hwp->cq_info.cq_next_disp_thr == \ 449 hwp->cq_info.cq_threads) { \ 450 hwp->cq_info.cq_next_disp_thr = 0; \ 451 } \ 452 mutex_enter(&cqti->cq_thr_lock); \ 453 cv_signal(&cqti->cq_cv); \ 454 mutex_exit(&cqti->cq_thr_lock); \ 455 } \ 456 457 #define PMCS_CQ_RUN(hwp) \ 458 mutex_enter(&hwp->cq_lock); \ 459 PMCS_CQ_RUN_LOCKED(hwp); \ 460 mutex_exit(&hwp->cq_lock); 461 462 463 /* 464 * Watchdog/SCSA timer definitions 465 */ 466 /* usecs to SCSA watchdog ticks */ 467 #define US2WT(x) (x)/10 468 469 /* 470 * More misc 471 */ 472 #define BYTE0(x) (((x) >> 0) & 0xff) 473 #define BYTE1(x) (((x) >> 8) & 0xff) 474 #define BYTE2(x) (((x) >> 16) & 0xff) 475 #define BYTE3(x) (((x) >> 24) & 0xff) 476 #define BYTE4(x) (((x) >> 32) & 0xff) 477 #define BYTE5(x) (((x) >> 40) & 0xff) 478 #define BYTE6(x) (((x) >> 48) & 0xff) 479 #define BYTE7(x) (((x) >> 56) & 0xff) 480 #define WORD0(x) (((x) >> 0) & 0xffff) 481 #define WORD1(x) (((x) >> 16) & 0xffff) 482 #define WORD2(x) (((x) >> 32) & 0xffff) 483 #define WORD3(x) (((x) >> 48) & 0xffff) 484 #define DWORD0(x) ((uint32_t)(x)) 485 #define DWORD1(x) ((uint32_t)(((uint64_t)x) >> 32)) 486 487 #define SAS_ADDR_FMT "0x%02x%02x%02x%02x%02x%02x%02x%02x" 488 #define SAS_ADDR_PRT(x) x[0], x[1], x[2], x[3], x[4], x[5], x[6], x[7] 489 490 #define PMCS_VALID_LINK_RATE(r) \ 491 ((r == SAS_LINK_RATE_1_5GBIT) || (r == SAS_LINK_RATE_3GBIT) || \ 492 (r == SAS_LINK_RATE_6GBIT)) 493 494 /* 495 * This is here to avoid inclusion of <sys/ctype.h> which is not lint clean. 496 */ 497 #define HEXDIGIT(x) (((x) >= '0' && (x) <= '9') || \ 498 ((x) >= 'a' && (x) <= 'f') || ((x) >= 'A' && (x) <= 'F')) 499 500 501 typedef void (*pmcs_cb_t) (pmcs_hw_t *, pmcwork_t *, uint32_t *); 502 503 /* 504 * Defines and structure used for tracing/logging information 505 */ 506 507 #define PMCS_TBUF_ELEM_SIZE 120 508 509 #ifdef DEBUG 510 #define PMCS_TBUF_NUM_ELEMS_DEF 100000 511 #else 512 #define PMCS_TBUF_NUM_ELEMS_DEF 15000 513 #endif 514 515 #define PMCS_TBUF_UA_MAX_SIZE 32 516 typedef struct { 517 /* Target-specific data */ 518 uint16_t target_num; 519 char target_ua[PMCS_TBUF_UA_MAX_SIZE]; 520 /* PHY-specific data */ 521 uint8_t phy_sas_address[8]; 522 char phy_path[32]; 523 pmcs_dtype_t phy_dtype; 524 /* Log data */ 525 timespec_t timestamp; 526 char buf[PMCS_TBUF_ELEM_SIZE]; 527 } pmcs_tbuf_t; 528 529 /* 530 * Firmware event log header format 531 */ 532 533 typedef struct pmcs_fw_event_hdr_s { 534 uint32_t fw_el_signature; 535 uint32_t fw_el_entry_start_offset; 536 uint32_t fw_el_rsvd1; 537 uint32_t fw_el_buf_size; 538 uint32_t fw_el_rsvd2; 539 uint32_t fw_el_oldest_idx; 540 uint32_t fw_el_latest_idx; 541 uint32_t fw_el_entry_size; 542 } pmcs_fw_event_hdr_t; 543 544 #ifdef __cplusplus 545 } 546 #endif 547 #endif /* _PMCS_DEF_H */ 548