1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved. 24 */ 25 26 /* 27 * Copyright (c) 2000 to 2010, LSI Corporation. 28 * All rights reserved. 29 * 30 * Redistribution and use in source and binary forms of all code within 31 * this file that is exclusively owned by LSI, with or without 32 * modification, is permitted provided that, in addition to the CDDL 1.0 33 * License requirements, the following conditions are met: 34 * 35 * Neither the name of the author nor the names of its contributors may be 36 * used to endorse or promote products derived from this software without 37 * specific prior written permission. 38 * 39 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 40 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 41 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 42 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 43 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 44 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 45 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 46 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 47 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 48 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 49 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 50 * DAMAGE. 51 */ 52 53 #ifndef _SYS_SCSI_ADAPTERS_MPTVAR_H 54 #define _SYS_SCSI_ADAPTERS_MPTVAR_H 55 56 #include <sys/byteorder.h> 57 #include <sys/isa_defs.h> 58 #include <sys/sunmdi.h> 59 #include <sys/mdi_impldefs.h> 60 #include <sys/scsi/adapters/mpt_sas/mptsas_ioctl.h> 61 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_tool.h> 62 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_cnfg.h> 63 64 #ifdef __cplusplus 65 extern "C" { 66 #endif 67 68 /* 69 * Compile options 70 */ 71 #ifdef DEBUG 72 #define MPTSAS_DEBUG /* turn on debugging code */ 73 #endif /* DEBUG */ 74 75 #define MPTSAS_INITIAL_SOFT_SPACE 4 76 77 #define MAX_MPI_PORTS 16 78 79 /* 80 * Note below macro definition and data type definition 81 * are used for phy mask handling, it should be changed 82 * simultaneously. 83 */ 84 #define MPTSAS_MAX_PHYS 16 85 typedef uint16_t mptsas_phymask_t; 86 87 #define MPTSAS_INVALID_DEVHDL 0xffff 88 #define MPTSAS_SATA_GUID "sata-guid" 89 90 /* 91 * MPT HW defines 92 */ 93 #define MPTSAS_MAX_DISKS_IN_CONFIG 14 94 #define MPTSAS_MAX_DISKS_IN_VOL 10 95 #define MPTSAS_MAX_HOTSPARES 2 96 #define MPTSAS_MAX_RAIDVOLS 2 97 #define MPTSAS_MAX_RAIDCONFIGS 5 98 99 /* 100 * 64-bit SAS WWN is displayed as 16 characters as HEX characters, 101 * plus two means the prefix 'w' and end of the string '\0'. 102 */ 103 #define MPTSAS_WWN_STRLEN (16 + 2) 104 #define MPTSAS_MAX_GUID_LEN 64 105 106 /* 107 * DMA routine flags 108 */ 109 #define MPTSAS_DMA_HANDLE_ALLOCD 0x2 110 #define MPTSAS_DMA_MEMORY_ALLOCD 0x4 111 #define MPTSAS_DMA_HANDLE_BOUND 0x8 112 113 /* 114 * If the HBA supports DMA or bus-mastering, you may have your own 115 * scatter-gather list for physically non-contiguous memory in one 116 * I/O operation; if so, there's probably a size for that list. 117 * It must be placed in the ddi_dma_lim_t structure, so that the system 118 * DMA-support routines can use it to break up the I/O request, so we 119 * define it here. 120 */ 121 #if defined(__sparc) 122 #define MPTSAS_MAX_DMA_SEGS 1 123 #define MPTSAS_MAX_CMD_SEGS 1 124 #else 125 #define MPTSAS_MAX_DMA_SEGS 256 126 #define MPTSAS_MAX_CMD_SEGS 257 127 #endif 128 #define MPTSAS_MAX_FRAME_SGES(mpt) \ 129 (((mpt->m_req_frame_size - (sizeof (MPI2_SCSI_IO_REQUEST))) / 8) + 1) 130 131 /* 132 * Caculating how many 64-bit DMA simple elements can be stored in the first 133 * frame. Note that msg_scsi_io_request contains 2 double-words (8 bytes) for 134 * element storage. And 64-bit dma element is 3 double-words (12 bytes) in 135 * size. 136 */ 137 #define MPTSAS_MAX_FRAME_SGES64(mpt) \ 138 ((mpt->m_req_frame_size - \ 139 (sizeof (MPI2_SCSI_IO_REQUEST)) + sizeof (MPI2_SGE_IO_UNION)) / 12) 140 141 /* 142 * Scatter-gather list structure defined by HBA hardware 143 */ 144 typedef struct NcrTableIndirect { /* Table Indirect entries */ 145 uint32_t count; /* 24 bit count */ 146 union { 147 uint32_t address32; /* 32 bit address */ 148 struct { 149 uint32_t Low; 150 uint32_t High; 151 } address64; /* 64 bit address */ 152 } addr; 153 } mptti_t; 154 155 /* 156 * preferred pkt_private length in 64-bit quantities 157 */ 158 #ifdef _LP64 159 #define PKT_PRIV_SIZE 2 160 #define PKT_PRIV_LEN 16 /* in bytes */ 161 #else /* _ILP32 */ 162 #define PKT_PRIV_SIZE 1 163 #define PKT_PRIV_LEN 8 /* in bytes */ 164 #endif 165 166 #define PKT2CMD(pkt) ((struct mptsas_cmd *)((pkt)->pkt_ha_private)) 167 #define CMD2PKT(cmdp) ((struct scsi_pkt *)((cmdp)->cmd_pkt)) 168 #define EXTCMDS_STATUS_SIZE (sizeof (struct scsi_arq_status)) 169 170 /* 171 * get offset of item in structure 172 */ 173 #define MPTSAS_GET_ITEM_OFF(type, member) ((size_t)(&((type *)0)->member)) 174 175 /* 176 * WWID provided by LSI firmware is generated by firmware but the WWID is not 177 * IEEE NAA standard format, OBP has no chance to distinguish format of unit 178 * address. According LSI's confirmation, the top nibble of RAID WWID is 179 * meanless, so the consensus between Solaris and OBP is to replace top nibble 180 * of WWID provided by LSI to "3" always to hint OBP that this is a RAID WWID 181 * format unit address. 182 */ 183 #define MPTSAS_RAID_WWID(wwid) \ 184 ((wwid & 0x0FFFFFFFFFFFFFFF) | 0x3000000000000000) 185 186 typedef struct mptsas_target { 187 uint64_t m_sas_wwn; /* hash key1 */ 188 mptsas_phymask_t m_phymask; /* hash key2 */ 189 /* 190 * m_dr_flag is a flag for DR, make sure the member 191 * take the place of dr_flag of mptsas_hash_data. 192 */ 193 uint8_t m_dr_flag; /* dr_flag */ 194 uint16_t m_devhdl; 195 uint32_t m_deviceinfo; 196 uint8_t m_phynum; 197 uint32_t m_dups; 198 int32_t m_timeout; 199 int32_t m_timebase; 200 int32_t m_t_throttle; 201 int32_t m_t_ncmds; 202 int32_t m_reset_delay; 203 int32_t m_t_nwait; 204 205 uint16_t m_qfull_retry_interval; 206 uint8_t m_qfull_retries; 207 uint16_t m_enclosure; 208 uint16_t m_slot_num; 209 uint32_t m_tgt_unconfigured; 210 211 } mptsas_target_t; 212 213 typedef struct mptsas_smp { 214 uint64_t m_sasaddr; /* hash key1 */ 215 mptsas_phymask_t m_phymask; /* hash key2 */ 216 uint8_t reserved1; 217 uint16_t m_devhdl; 218 uint32_t m_deviceinfo; 219 uint16_t m_pdevhdl; 220 uint32_t m_pdevinfo; 221 } mptsas_smp_t; 222 223 typedef struct mptsas_hash_data { 224 uint64_t key1; 225 mptsas_phymask_t key2; 226 uint8_t dr_flag; 227 uint16_t devhdl; 228 uint32_t device_info; 229 } mptsas_hash_data_t; 230 231 typedef struct mptsas_cache_frames { 232 ddi_dma_handle_t m_dma_hdl; 233 ddi_acc_handle_t m_acc_hdl; 234 caddr_t m_frames_addr; 235 uint32_t m_phys_addr; 236 } mptsas_cache_frames_t; 237 238 typedef struct mptsas_cmd { 239 uint_t cmd_flags; /* flags from scsi_init_pkt */ 240 ddi_dma_handle_t cmd_dmahandle; /* dma handle */ 241 ddi_dma_cookie_t cmd_cookie; 242 uint_t cmd_cookiec; 243 uint_t cmd_winindex; 244 uint_t cmd_nwin; 245 uint_t cmd_cur_cookie; 246 off_t cmd_dma_offset; 247 size_t cmd_dma_len; 248 uint32_t cmd_totaldmacount; 249 250 ddi_dma_handle_t cmd_arqhandle; /* dma arq handle */ 251 ddi_dma_cookie_t cmd_arqcookie; 252 struct buf *cmd_arq_buf; 253 ddi_dma_handle_t cmd_ext_arqhandle; /* dma extern arq handle */ 254 ddi_dma_cookie_t cmd_ext_arqcookie; 255 struct buf *cmd_ext_arq_buf; 256 257 int cmd_pkt_flags; 258 259 /* timer for command in active slot */ 260 int cmd_active_timeout; 261 262 struct scsi_pkt *cmd_pkt; 263 struct scsi_arq_status cmd_scb; 264 uchar_t cmd_cdblen; /* length of cdb */ 265 uchar_t cmd_rqslen; /* len of requested rqsense */ 266 uchar_t cmd_privlen; 267 uint_t cmd_scblen; 268 uint32_t cmd_dmacount; 269 uint64_t cmd_dma_addr; 270 uchar_t cmd_age; 271 ushort_t cmd_qfull_retries; 272 uchar_t cmd_queued; /* true if queued */ 273 struct mptsas_cmd *cmd_linkp; 274 mptti_t *cmd_sg; /* Scatter/Gather structure */ 275 uchar_t cmd_cdb[SCSI_CDB_SIZE]; 276 uint64_t cmd_pkt_private[PKT_PRIV_LEN]; 277 uint32_t cmd_slot; 278 uint32_t ioc_cmd_slot; 279 280 mptsas_cache_frames_t *cmd_extra_frames; 281 282 uint32_t cmd_rfm; 283 mptsas_target_t *cmd_tgt_addr; 284 } mptsas_cmd_t; 285 286 /* 287 * These are the defined cmd_flags for this structure. 288 */ 289 #define CFLAG_CMDDISC 0x000001 /* cmd currently disconnected */ 290 #define CFLAG_WATCH 0x000002 /* watchdog time for this command */ 291 #define CFLAG_FINISHED 0x000004 /* command completed */ 292 #define CFLAG_CHKSEG 0x000008 /* check cmd_data within seg */ 293 #define CFLAG_COMPLETED 0x000010 /* completion routine called */ 294 #define CFLAG_PREPARED 0x000020 /* pkt has been init'ed */ 295 #define CFLAG_IN_TRANSPORT 0x000040 /* in use by host adapter driver */ 296 #define CFLAG_RESTORE_PTRS 0x000080 /* implicit restore ptr on reconnect */ 297 #define CFLAG_ARQ_IN_PROGRESS 0x000100 /* auto request sense in progress */ 298 #define CFLAG_TRANFLAG 0x0001ff /* covers transport part of flags */ 299 #define CFLAG_TM_CMD 0x000200 /* cmd is a task management command */ 300 #define CFLAG_CMDARQ 0x000400 /* cmd is a 'rqsense' command */ 301 #define CFLAG_DMAVALID 0x000800 /* dma mapping valid */ 302 #define CFLAG_DMASEND 0x001000 /* data is going 'out' */ 303 #define CFLAG_CMDIOPB 0x002000 /* this is an 'iopb' packet */ 304 #define CFLAG_CDBEXTERN 0x004000 /* cdb kmem_alloc'd */ 305 #define CFLAG_SCBEXTERN 0x008000 /* scb kmem_alloc'd */ 306 #define CFLAG_FREE 0x010000 /* packet is on free list */ 307 #define CFLAG_PRIVEXTERN 0x020000 /* target private kmem_alloc'd */ 308 #define CFLAG_DMA_PARTIAL 0x040000 /* partial xfer OK */ 309 #define CFLAG_QFULL_STATUS 0x080000 /* pkt got qfull status */ 310 #define CFLAG_TIMEOUT 0x100000 /* passthru/config command timeout */ 311 #define CFLAG_PMM_RECEIVED 0x200000 /* use cmd_pmm* for saving pointers */ 312 #define CFLAG_RETRY 0x400000 /* cmd has been retried */ 313 #define CFLAG_CMDIOC 0x800000 /* cmd is just for for ioc, no io */ 314 #define CFLAG_EXTARQBUFVALID 0x1000000 /* extern arq buf handle is valid */ 315 #define CFLAG_PASSTHRU 0x2000000 /* cmd is a passthrough command */ 316 #define CFLAG_XARQ 0x4000000 /* cmd requests for extra sense */ 317 #define CFLAG_CMDACK 0x8000000 /* cmd for event ack */ 318 #define CFLAG_TXQ 0x10000000 /* cmd queued in the tx_waitq */ 319 #define CFLAG_FW_CMD 0x20000000 /* cmd is a fw up/down command */ 320 #define CFLAG_CONFIG 0x40000000 /* cmd is for config header/page */ 321 #define CFLAG_FW_DIAG 0x80000000 /* cmd is for FW diag buffers */ 322 323 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE 8 324 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK 0xC0 325 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_PERIPHERAL 0x00 326 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_FLAT_SPACE 0x40 327 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT 0x80 328 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_EXTENDED_UNIT 0xC0 329 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_2B 0x00 330 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_4B 0x01 331 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_6B 0x10 332 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_8B 0x20 333 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_SIZE 0x30 334 335 #define MPTSAS_HASH_ARRAY_SIZE 16 336 /* 337 * hash table definition 338 */ 339 340 #define MPTSAS_HASH_FIRST 0xffff 341 #define MPTSAS_HASH_NEXT 0x0000 342 343 typedef struct mptsas_dma_alloc_state 344 { 345 ddi_dma_handle_t handle; 346 caddr_t memp; 347 size_t size; 348 ddi_acc_handle_t accessp; 349 ddi_dma_cookie_t cookie; 350 } mptsas_dma_alloc_state_t; 351 352 /* 353 * passthrough request structure 354 */ 355 typedef struct mptsas_pt_request { 356 uint8_t *request; 357 uint32_t request_size; 358 uint32_t data_size; 359 uint32_t dataout_size; 360 uint32_t direction; 361 ddi_dma_cookie_t data_cookie; 362 ddi_dma_cookie_t dataout_cookie; 363 } mptsas_pt_request_t; 364 365 /* 366 * config page request structure 367 */ 368 typedef struct mptsas_config_request { 369 uint32_t page_address; 370 uint8_t action; 371 uint8_t page_type; 372 uint8_t page_number; 373 uint8_t page_length; 374 uint8_t page_version; 375 uint8_t ext_page_type; 376 uint16_t ext_page_length; 377 } mptsas_config_request_t; 378 379 typedef struct mptsas_fw_diagnostic_buffer { 380 mptsas_dma_alloc_state_t buffer_data; 381 uint8_t extended_type; 382 uint8_t buffer_type; 383 uint8_t force_release; 384 uint32_t product_specific[23]; 385 uint8_t immediate; 386 uint8_t enabled; 387 uint8_t valid_data; 388 uint8_t owned_by_firmware; 389 uint32_t unique_id; 390 } mptsas_fw_diagnostic_buffer_t; 391 392 /* 393 * FW diag request structure 394 */ 395 typedef struct mptsas_diag_request { 396 mptsas_fw_diagnostic_buffer_t *pBuffer; 397 uint8_t function; 398 } mptsas_diag_request_t; 399 400 typedef struct mptsas_hash_node { 401 void *data; 402 struct mptsas_hash_node *next; 403 } mptsas_hash_node_t; 404 405 typedef struct mptsas_hash_table { 406 struct mptsas_hash_node *head[MPTSAS_HASH_ARRAY_SIZE]; 407 /* 408 * last position in traverse 409 */ 410 struct mptsas_hash_node *cur; 411 uint16_t line; 412 413 } mptsas_hash_table_t; 414 415 /* 416 * RAID volume information 417 */ 418 typedef struct mptsas_raidvol { 419 ushort_t m_israid; 420 uint16_t m_raidhandle; 421 uint64_t m_raidwwid; 422 uint8_t m_state; 423 uint32_t m_statusflags; 424 uint32_t m_settings; 425 uint16_t m_devhdl[MPTSAS_MAX_DISKS_IN_VOL]; 426 uint8_t m_disknum[MPTSAS_MAX_DISKS_IN_VOL]; 427 ushort_t m_diskstatus[MPTSAS_MAX_DISKS_IN_VOL]; 428 uint64_t m_raidsize; 429 int m_raidlevel; 430 int m_ndisks; 431 mptsas_target_t *m_raidtgt; 432 } mptsas_raidvol_t; 433 434 /* 435 * RAID configurations 436 */ 437 typedef struct mptsas_raidconfig { 438 mptsas_raidvol_t m_raidvol[MPTSAS_MAX_RAIDVOLS]; 439 uint16_t m_physdisk_devhdl[ 440 MPTSAS_MAX_DISKS_IN_CONFIG]; 441 uint8_t m_native; 442 } m_raidconfig_t; 443 444 /* 445 * Structure to hold active outstanding cmds. Also, keep 446 * timeout on a per target basis. 447 */ 448 typedef struct mptsas_slots { 449 mptsas_hash_table_t m_tgttbl; 450 mptsas_hash_table_t m_smptbl; 451 m_raidconfig_t m_raidconfig[MPTSAS_MAX_RAIDCONFIGS]; 452 uint8_t m_num_raid_configs; 453 uint16_t m_tags; 454 size_t m_size; 455 uint16_t m_n_slots; 456 mptsas_cmd_t *m_slot[1]; 457 } mptsas_slots_t; 458 459 /* 460 * Structure to hold command and packets for event ack 461 * and task management commands. 462 */ 463 typedef struct m_event_struct { 464 struct mptsas_cmd m_event_cmd; 465 struct m_event_struct *m_event_linkp; 466 /* 467 * event member record the failure event and eventcntx 468 * event member would be used in send ack pending process 469 */ 470 uint32_t m_event; 471 uint32_t m_eventcntx; 472 uint_t in_use; 473 struct scsi_pkt m_event_pkt; /* must be last */ 474 /* ... scsi_pkt_size() */ 475 } m_event_struct_t; 476 #define M_EVENT_STRUCT_SIZE (sizeof (m_event_struct_t) - \ 477 sizeof (struct scsi_pkt) + scsi_pkt_size()) 478 479 #define MAX_IOC_COMMANDS 8 480 481 /* 482 * A pool of MAX_IOC_COMMANDS is maintained for event ack commands. 483 * A new event ack command requests mptsas_cmd and scsi_pkt structures 484 * from this pool, and returns it back when done. 485 */ 486 487 typedef struct m_replyh_arg { 488 void *mpt; 489 uint32_t rfm; 490 } m_replyh_arg_t; 491 _NOTE(DATA_READABLE_WITHOUT_LOCK(m_replyh_arg_t::mpt)) 492 _NOTE(DATA_READABLE_WITHOUT_LOCK(m_replyh_arg_t::rfm)) 493 494 /* 495 * Flags for DR handler topology change 496 */ 497 #define MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE 0x0 498 #define MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED 0x1 499 #define MPTSAS_TOPO_FLAG_LUN_ASSOCIATED 0x2 500 #define MPTSAS_TOPO_FLAG_RAID_ASSOCIATED 0x4 501 #define MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED 0x8 502 #define MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE 0x10 503 504 typedef struct mptsas_topo_change_list { 505 void *mpt; 506 uint_t event; 507 union { 508 uint8_t physport; 509 mptsas_phymask_t phymask; 510 } un; 511 uint16_t devhdl; 512 void *object; 513 uint8_t flags; 514 struct mptsas_topo_change_list *next; 515 } mptsas_topo_change_list_t; 516 517 518 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::mpt)) 519 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::event)) 520 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::physport)) 521 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::devhdl)) 522 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::object)) 523 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::flags)) 524 525 /* 526 * Status types when calling mptsas_get_target_device_info 527 */ 528 #define DEV_INFO_SUCCESS 0x0 529 #define DEV_INFO_FAIL_PAGE0 0x1 530 #define DEV_INFO_WRONG_DEVICE_TYPE 0x2 531 #define DEV_INFO_PHYS_DISK 0x3 532 #define DEV_INFO_FAIL_ALLOC 0x4 533 534 /* 535 * mpt hotplug event defines 536 */ 537 #define MPTSAS_DR_EVENT_RECONFIG_TARGET 0x01 538 #define MPTSAS_DR_EVENT_OFFLINE_TARGET 0x02 539 #define MPTSAS_TOPO_FLAG_REMOVE_HANDLE 0x04 540 541 /* 542 * SMP target hotplug events 543 */ 544 #define MPTSAS_DR_EVENT_RECONFIG_SMP 0x10 545 #define MPTSAS_DR_EVENT_OFFLINE_SMP 0x20 546 #define MPTSAS_DR_EVENT_MASK 0x3F 547 548 /* 549 * mpt hotplug status definition for m_dr_flag 550 */ 551 552 /* 553 * MPTSAS_DR_INACTIVE 554 * 555 * The target is in a normal operating state. 556 * No dynamic reconfiguration operation is in progress. 557 */ 558 #define MPTSAS_DR_INACTIVE 0x0 559 /* 560 * MPTSAS_DR_INTRANSITION 561 * 562 * The target is in a transition mode since 563 * hotplug event happens and offline procedure has not 564 * been finished 565 */ 566 #define MPTSAS_DR_INTRANSITION 0x1 567 568 typedef struct mptsas_tgt_private { 569 int t_lun; 570 struct mptsas_target *t_private; 571 } mptsas_tgt_private_t; 572 573 /* 574 * The following defines are used in mptsas_set_init_mode to track the current 575 * state as we progress through reprogramming the HBA from target mode into 576 * initiator mode. 577 */ 578 579 #define IOUC_READ_PAGE0 0x00000100 580 #define IOUC_READ_PAGE1 0x00000200 581 #define IOUC_WRITE_PAGE1 0x00000400 582 #define IOUC_DONE 0x00000800 583 #define DISCOVERY_IN_PROGRESS MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS 584 #define AUTO_PORT_CONFIGURATION MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG 585 586 /* 587 * Last allocated slot is used for TM requests. Since only m_max_requests 588 * frames are allocated, the last SMID will be m_max_requests - 1. 589 */ 590 #define MPTSAS_SLOTS_SIZE(mpt) \ 591 (sizeof (struct mptsas_slots) + (sizeof (struct mptsas_cmd *) * \ 592 mpt->m_max_requests)) 593 #define MPTSAS_TM_SLOT(mpt) (mpt->m_max_requests - 1) 594 595 /* 596 * Macro for phy_flags 597 */ 598 599 typedef struct smhba_info { 600 kmutex_t phy_mutex; 601 uint8_t phy_id; 602 uint64_t sas_addr; 603 char path[8]; 604 uint16_t owner_devhdl; 605 uint16_t attached_devhdl; 606 uint8_t attached_phy_identify; 607 uint32_t attached_phy_info; 608 uint8_t programmed_link_rate; 609 uint8_t hw_link_rate; 610 uint8_t change_count; 611 uint32_t phy_info; 612 uint8_t negotiated_link_rate; 613 uint8_t port_num; 614 kstat_t *phy_stats; 615 uint32_t invalid_dword_count; 616 uint32_t running_disparity_error_count; 617 uint32_t loss_of_dword_sync_count; 618 uint32_t phy_reset_problem_count; 619 void *mpt; 620 } smhba_info_t; 621 622 typedef struct mptsas_phy_info { 623 uint8_t port_num; 624 uint8_t port_flags; 625 uint16_t ctrl_devhdl; 626 uint32_t phy_device_type; 627 uint16_t attached_devhdl; 628 mptsas_phymask_t phy_mask; 629 smhba_info_t smhba_info; 630 } mptsas_phy_info_t; 631 632 633 typedef struct mptsas_doneq_thread_arg { 634 void *mpt; 635 uint64_t t; 636 } mptsas_doneq_thread_arg_t; 637 638 #define MPTSAS_DONEQ_THREAD_ACTIVE 0x1 639 typedef struct mptsas_doneq_thread_list { 640 mptsas_cmd_t *doneq; 641 mptsas_cmd_t **donetail; 642 kthread_t *threadp; 643 kcondvar_t cv; 644 ushort_t reserv1; 645 uint32_t reserv2; 646 kmutex_t mutex; 647 uint32_t flag; 648 uint32_t len; 649 mptsas_doneq_thread_arg_t arg; 650 } mptsas_doneq_thread_list_t; 651 652 typedef struct mptsas { 653 int m_instance; 654 655 struct mptsas *m_next; 656 657 scsi_hba_tran_t *m_tran; 658 smp_hba_tran_t *m_smptran; 659 kmutex_t m_mutex; 660 kcondvar_t m_cv; 661 kcondvar_t m_passthru_cv; 662 kcondvar_t m_fw_cv; 663 kcondvar_t m_config_cv; 664 kcondvar_t m_fw_diag_cv; 665 dev_info_t *m_dip; 666 667 /* 668 * soft state flags 669 */ 670 uint_t m_softstate; 671 672 struct mptsas_slots *m_active; /* outstanding cmds */ 673 674 mptsas_cmd_t *m_waitq; /* cmd queue for active request */ 675 mptsas_cmd_t **m_waitqtail; /* wait queue tail ptr */ 676 677 kmutex_t m_tx_waitq_mutex; 678 mptsas_cmd_t *m_tx_waitq; /* TX cmd queue for active request */ 679 mptsas_cmd_t **m_tx_waitqtail; /* tx_wait queue tail ptr */ 680 int m_tx_draining; /* TX queue draining flag */ 681 682 mptsas_cmd_t *m_doneq; /* queue of completed commands */ 683 mptsas_cmd_t **m_donetail; /* queue tail ptr */ 684 685 /* 686 * variables for helper threads (fan-out interrupts) 687 */ 688 mptsas_doneq_thread_list_t *m_doneq_thread_id; 689 uint32_t m_doneq_thread_n; 690 uint32_t m_doneq_thread_threshold; 691 uint32_t m_doneq_length_threshold; 692 uint32_t m_doneq_len; 693 kcondvar_t m_doneq_thread_cv; 694 kmutex_t m_doneq_mutex; 695 696 int m_ncmds; /* number of outstanding commands */ 697 m_event_struct_t *m_ioc_event_cmdq; /* cmd queue for ioc event */ 698 m_event_struct_t **m_ioc_event_cmdtail; /* ioc cmd queue tail */ 699 700 ddi_acc_handle_t m_datap; /* operating regs data access handle */ 701 702 struct _MPI2_SYSTEM_INTERFACE_REGS *m_reg; 703 704 ushort_t m_devid; /* device id of chip. */ 705 uchar_t m_revid; /* revision of chip. */ 706 uint16_t m_svid; /* subsystem Vendor ID of chip */ 707 uint16_t m_ssid; /* subsystem Device ID of chip */ 708 709 uchar_t m_sync_offset; /* default offset for this chip. */ 710 711 timeout_id_t m_quiesce_timeid; 712 timeout_id_t m_pm_timeid; 713 714 ddi_dma_handle_t m_dma_req_frame_hdl; 715 ddi_acc_handle_t m_acc_req_frame_hdl; 716 ddi_dma_handle_t m_dma_reply_frame_hdl; 717 ddi_acc_handle_t m_acc_reply_frame_hdl; 718 ddi_dma_handle_t m_dma_free_queue_hdl; 719 ddi_acc_handle_t m_acc_free_queue_hdl; 720 ddi_dma_handle_t m_dma_post_queue_hdl; 721 ddi_acc_handle_t m_acc_post_queue_hdl; 722 723 /* 724 * list of reset notification requests 725 */ 726 struct scsi_reset_notify_entry *m_reset_notify_listf; 727 728 /* 729 * qfull handling 730 */ 731 timeout_id_t m_restart_cmd_timeid; 732 733 /* 734 * scsi reset delay per bus 735 */ 736 uint_t m_scsi_reset_delay; 737 738 int m_pm_idle_delay; 739 740 uchar_t m_polled_intr; /* intr was polled. */ 741 uchar_t m_suspended; /* true if driver is suspended */ 742 743 struct kmem_cache *m_kmem_cache; 744 struct kmem_cache *m_cache_frames; 745 746 /* 747 * hba options. 748 */ 749 uint_t m_options; 750 751 int m_in_callback; 752 753 int m_power_level; /* current power level */ 754 755 int m_busy; /* power management busy state */ 756 757 off_t m_pmcsr_offset; /* PMCSR offset */ 758 759 ddi_acc_handle_t m_config_handle; 760 761 ddi_dma_attr_t m_io_dma_attr; /* Used for data I/O */ 762 ddi_dma_attr_t m_msg_dma_attr; /* Used for message frames */ 763 ddi_device_acc_attr_t m_dev_acc_attr; 764 ddi_device_acc_attr_t m_reg_acc_attr; 765 766 /* 767 * request/reply variables 768 */ 769 caddr_t m_req_frame; 770 uint64_t m_req_frame_dma_addr; 771 caddr_t m_reply_frame; 772 uint64_t m_reply_frame_dma_addr; 773 caddr_t m_free_queue; 774 uint64_t m_free_queue_dma_addr; 775 caddr_t m_post_queue; 776 uint64_t m_post_queue_dma_addr; 777 778 m_replyh_arg_t *m_replyh_args; 779 780 uint16_t m_max_requests; 781 uint16_t m_req_frame_size; 782 783 /* 784 * Max frames per request reprted in IOC Facts 785 */ 786 uint8_t m_max_chain_depth; 787 /* 788 * Max frames per request which is used in reality. It's adjusted 789 * according DMA SG length attribute, and shall not exceed the 790 * m_max_chain_depth. 791 */ 792 uint8_t m_max_request_frames; 793 794 uint16_t m_free_queue_depth; 795 uint16_t m_post_queue_depth; 796 uint16_t m_max_replies; 797 uint32_t m_free_index; 798 uint32_t m_post_index; 799 uint8_t m_reply_frame_size; 800 uint32_t m_ioc_capabilities; 801 802 /* 803 * indicates if the firmware was upload by the driver 804 * at boot time 805 */ 806 ushort_t m_fwupload; 807 808 uint16_t m_productid; 809 810 /* 811 * per instance data structures for dma memory resources for 812 * MPI handshake protocol. only one handshake cmd can run at a time. 813 */ 814 ddi_dma_handle_t m_hshk_dma_hdl; 815 816 ddi_acc_handle_t m_hshk_acc_hdl; 817 818 caddr_t m_hshk_memp; 819 820 size_t m_hshk_dma_size; 821 822 /* Firmware version on the card at boot time */ 823 uint32_t m_fwversion; 824 825 /* MSI specific fields */ 826 ddi_intr_handle_t *m_htable; /* For array of interrupts */ 827 int m_intr_type; /* What type of interrupt */ 828 int m_intr_cnt; /* # of intrs count returned */ 829 size_t m_intr_size; /* Size of intr array */ 830 uint_t m_intr_pri; /* Interrupt priority */ 831 int m_intr_cap; /* Interrupt capabilities */ 832 ddi_taskq_t *m_event_taskq; 833 834 /* SAS specific information */ 835 836 union { 837 uint64_t m_base_wwid; /* Base WWID */ 838 struct { 839 #ifdef _BIG_ENDIAN 840 uint32_t m_base_wwid_hi; 841 uint32_t m_base_wwid_lo; 842 #else 843 uint32_t m_base_wwid_lo; 844 uint32_t m_base_wwid_hi; 845 #endif 846 } sasaddr; 847 } un; 848 849 uint8_t m_num_phys; /* # of PHYs */ 850 mptsas_phy_info_t m_phy_info[MPTSAS_MAX_PHYS]; 851 uint8_t m_port_chng; /* initiator port changes */ 852 MPI2_CONFIG_PAGE_MAN_0 m_MANU_page0; /* Manufactor page 0 info */ 853 MPI2_CONFIG_PAGE_MAN_1 m_MANU_page1; /* Manufactor page 1 info */ 854 855 /* FMA Capabilities */ 856 int m_fm_capabilities; 857 ddi_taskq_t *m_dr_taskq; 858 int m_mpxio_enable; 859 uint8_t m_done_traverse_dev; 860 uint8_t m_done_traverse_smp; 861 int m_passthru_in_progress; 862 int m_diag_action_in_progress; 863 uint16_t m_dev_handle; 864 uint16_t m_smp_devhdl; 865 866 /* 867 * Event recording 868 */ 869 uint8_t m_event_index; 870 uint32_t m_event_number; 871 uint32_t m_event_mask[4]; 872 mptsas_event_entry_t m_events[MPTSAS_EVENT_QUEUE_SIZE]; 873 874 /* 875 * FW diag Buffer List 876 */ 877 mptsas_fw_diagnostic_buffer_t 878 m_fw_diag_buffer_list[MPI2_DIAG_BUF_TYPE_COUNT]; 879 880 /* 881 * Event Replay flag (MUR support) 882 */ 883 uint8_t m_event_replay; 884 885 /* 886 * IR Capable flag 887 */ 888 uint8_t m_ir_capable; 889 890 /* 891 * Is HBA processing a diag reset? 892 */ 893 uint8_t m_in_reset; 894 895 /* 896 * per instance cmd data structures for task management cmds 897 */ 898 m_event_struct_t m_event_task_mgmt; /* must be last */ 899 /* ... scsi_pkt_size */ 900 } mptsas_t; 901 #define MPTSAS_SIZE (sizeof (struct mptsas) - \ 902 sizeof (struct scsi_pkt) + scsi_pkt_size()) 903 /* 904 * Only one of below two conditions is satisfied, we 905 * think the target is associated to the iport and 906 * allow call into mptsas_probe_lun(). 907 * 1. physicalsport == physport 908 * 2. (phymask & (1 << physport)) == 0 909 * The condition #2 is because LSI uses lowest PHY 910 * number as the value of physical port when auto port 911 * configuration. 912 */ 913 #define IS_SAME_PORT(physicalport, physport, phymask, dynamicport) \ 914 ((physicalport == physport) || (dynamicport && (phymask & \ 915 (1 << physport)))) 916 917 _NOTE(MUTEX_PROTECTS_DATA(mptsas::m_mutex, mptsas)) 918 _NOTE(SCHEME_PROTECTS_DATA("safe sharing", mptsas::m_next)) 919 _NOTE(SCHEME_PROTECTS_DATA("stable data", mptsas::m_dip mptsas::m_tran)) 920 _NOTE(SCHEME_PROTECTS_DATA("stable data", mptsas::m_kmem_cache)) 921 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_io_dma_attr.dma_attr_sgllen)) 922 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_devid)) 923 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_productid)) 924 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_port_type)) 925 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_mpxio_enable)) 926 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_ntargets)) 927 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_instance)) 928 929 /* 930 * These should eventually migrate into the mpt header files 931 * that may become the /kernel/misc/mpt module... 932 */ 933 #define mptsas_init_std_hdr(hdl, mp, DevHandle, Lun, ChainOffset, Function) \ 934 mptsas_put_msg_DevHandle(hdl, mp, DevHandle); \ 935 mptsas_put_msg_ChainOffset(hdl, mp, ChainOffset); \ 936 mptsas_put_msg_Function(hdl, mp, Function); \ 937 mptsas_put_msg_Lun(hdl, mp, Lun) 938 939 #define mptsas_put_msg_DevHandle(hdl, mp, val) \ 940 ddi_put16(hdl, &(mp)->DevHandle, (val)) 941 #define mptsas_put_msg_ChainOffset(hdl, mp, val) \ 942 ddi_put8(hdl, &(mp)->ChainOffset, (val)) 943 #define mptsas_put_msg_Function(hdl, mp, val) \ 944 ddi_put8(hdl, &(mp)->Function, (val)) 945 #define mptsas_put_msg_Lun(hdl, mp, val) \ 946 ddi_put8(hdl, &(mp)->LUN[1], (val)) 947 948 #define mptsas_get_msg_Function(hdl, mp) \ 949 ddi_get8(hdl, &(mp)->Function) 950 951 #define mptsas_get_msg_MsgFlags(hdl, mp) \ 952 ddi_get8(hdl, &(mp)->MsgFlags) 953 954 #define MPTSAS_ENABLE_DRWE(hdl) \ 955 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 956 MPI2_WRSEQ_FLUSH_KEY_VALUE); \ 957 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 958 MPI2_WRSEQ_1ST_KEY_VALUE); \ 959 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 960 MPI2_WRSEQ_2ND_KEY_VALUE); \ 961 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 962 MPI2_WRSEQ_3RD_KEY_VALUE); \ 963 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 964 MPI2_WRSEQ_4TH_KEY_VALUE); \ 965 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 966 MPI2_WRSEQ_5TH_KEY_VALUE); \ 967 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 968 MPI2_WRSEQ_6TH_KEY_VALUE); 969 970 /* 971 * m_options flags 972 */ 973 #define MPTSAS_OPT_PM 0x01 /* Power Management */ 974 975 /* 976 * m_softstate flags 977 */ 978 #define MPTSAS_SS_DRAINING 0x02 979 #define MPTSAS_SS_QUIESCED 0x04 980 #define MPTSAS_SS_MSG_UNIT_RESET 0x08 981 982 /* 983 * regspec defines. 984 */ 985 #define CONFIG_SPACE 0 /* regset[0] - configuration space */ 986 #define IO_SPACE 1 /* regset[1] - used for i/o mapped device */ 987 #define MEM_SPACE 2 /* regset[2] - used for memory mapped device */ 988 #define BASE_REG2 3 /* regset[3] - used for 875 scripts ram */ 989 990 /* 991 * Handy constants 992 */ 993 #define FALSE 0 994 #define TRUE 1 995 #define UNDEFINED -1 996 #define FAILED -2 997 998 /* 999 * power management. 1000 */ 1001 #define MPTSAS_POWER_ON(mpt) { \ 1002 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset, \ 1003 PCI_PMCSR_D0); \ 1004 delay(drv_usectohz(10000)); \ 1005 (void) pci_restore_config_regs(mpt->m_dip); \ 1006 mptsas_setup_cmd_reg(mpt); \ 1007 } 1008 1009 #define MPTSAS_POWER_OFF(mpt) { \ 1010 (void) pci_save_config_regs(mpt->m_dip); \ 1011 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset, \ 1012 PCI_PMCSR_D3HOT); \ 1013 mpt->m_power_level = PM_LEVEL_D3; \ 1014 } 1015 1016 /* 1017 * inq_dtype: 1018 * Bits 5 through 7 are the Peripheral Device Qualifier 1019 * 001b: device not connected to the LUN 1020 * Bits 0 through 4 are the Peripheral Device Type 1021 * 1fh: Unknown or no device type 1022 * 1023 * Although the inquiry may return success, the following value 1024 * means no valid LUN connected. 1025 */ 1026 #define MPTSAS_VALID_LUN(sd_inq) \ 1027 (((sd_inq->inq_dtype & 0xe0) != 0x20) && \ 1028 ((sd_inq->inq_dtype & 0x1f) != 0x1f)) 1029 1030 /* 1031 * Default is to have 10 retries on receiving QFULL status and 1032 * each retry to be after 100 ms. 1033 */ 1034 #define QFULL_RETRIES 10 1035 #define QFULL_RETRY_INTERVAL 100 1036 1037 /* 1038 * Handy macros 1039 */ 1040 #define Tgt(sp) ((sp)->cmd_pkt->pkt_address.a_target) 1041 #define Lun(sp) ((sp)->cmd_pkt->pkt_address.a_lun) 1042 1043 #define IS_HEX_DIGIT(n) (((n) >= '0' && (n) <= '9') || \ 1044 ((n) >= 'a' && (n) <= 'f') || ((n) >= 'A' && (n) <= 'F')) 1045 1046 /* 1047 * poll time for mptsas_pollret() and mptsas_wait_intr() 1048 */ 1049 #define MPTSAS_POLL_TIME 30000 /* 30 seconds */ 1050 1051 /* 1052 * default time for mptsas_do_passthru 1053 */ 1054 #define MPTSAS_PASS_THRU_TIME_DEFAULT 60 /* 60 seconds */ 1055 1056 /* 1057 * macro to return the effective address of a given per-target field 1058 */ 1059 #define EFF_ADDR(start, offset) ((start) + (offset)) 1060 1061 #define SDEV2ADDR(devp) (&((devp)->sd_address)) 1062 #define SDEV2TRAN(devp) ((devp)->sd_address.a_hba_tran) 1063 #define PKT2TRAN(pkt) ((pkt)->pkt_address.a_hba_tran) 1064 #define ADDR2TRAN(ap) ((ap)->a_hba_tran) 1065 #define DIP2TRAN(dip) (ddi_get_driver_private(dip)) 1066 1067 1068 #define TRAN2MPT(hba) ((mptsas_t *)(hba)->tran_hba_private) 1069 #define DIP2MPT(dip) (TRAN2MPT((scsi_hba_tran_t *)DIP2TRAN(dip))) 1070 #define SDEV2MPT(sd) (TRAN2MPT(SDEV2TRAN(sd))) 1071 #define PKT2MPT(pkt) (TRAN2MPT(PKT2TRAN(pkt))) 1072 1073 #define ADDR2MPT(ap) (TRAN2MPT(ADDR2TRAN(ap))) 1074 1075 #define POLL_TIMEOUT (2 * SCSI_POLL_TIMEOUT * 1000000) 1076 #define SHORT_POLL_TIMEOUT (1000000) /* in usec, about 1 secs */ 1077 #define MPTSAS_QUIESCE_TIMEOUT 1 /* 1 sec */ 1078 #define MPTSAS_PM_IDLE_TIMEOUT 60 /* 60 seconds */ 1079 1080 #define MPTSAS_GET_ISTAT(mpt) (ddi_get32((mpt)->m_datap, \ 1081 &(mpt)->m_reg->HostInterruptStatus)) 1082 1083 #define MPTSAS_SET_SIGP(P) \ 1084 ClrSetBits(mpt->m_devaddr + NREG_ISTAT, 0, NB_ISTAT_SIGP) 1085 1086 #define MPTSAS_RESET_SIGP(P) (void) ddi_get8(mpt->m_datap, \ 1087 (uint8_t *)(mpt->m_devaddr + NREG_CTEST2)) 1088 1089 #define MPTSAS_GET_INTCODE(P) (ddi_get32(mpt->m_datap, \ 1090 (uint32_t *)(mpt->m_devaddr + NREG_DSPS))) 1091 1092 1093 #define MPTSAS_START_CMD(mpt, req_desc_lo, req_desc_hi) \ 1094 ddi_put32(mpt->m_datap, &mpt->m_reg->RequestDescriptorPostLow,\ 1095 req_desc_lo);\ 1096 ddi_put32(mpt->m_datap, &mpt->m_reg->RequestDescriptorPostHigh,\ 1097 req_desc_hi); 1098 1099 #define INTPENDING(mpt) \ 1100 (MPTSAS_GET_ISTAT(mpt) & MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT) 1101 1102 /* 1103 * Mask all interrupts to disable 1104 */ 1105 #define MPTSAS_DISABLE_INTR(mpt) \ 1106 ddi_put32((mpt)->m_datap, &(mpt)->m_reg->HostInterruptMask, \ 1107 (MPI2_HIM_RIM | MPI2_HIM_DIM | MPI2_HIM_RESET_IRQ_MASK)) 1108 1109 /* 1110 * Mask Doorbell and Reset interrupts to enable reply desc int. 1111 */ 1112 #define MPTSAS_ENABLE_INTR(mpt) \ 1113 ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask, \ 1114 (MPI2_HIM_DIM | MPI2_HIM_RESET_IRQ_MASK)) 1115 1116 #define MPTSAS_GET_NEXT_REPLY(mpt, index) \ 1117 &((uint64_t *)(void *)mpt->m_post_queue)[index] 1118 1119 #define MPTSAS_GET_NEXT_FRAME(mpt, SMID) \ 1120 (mpt->m_req_frame + (mpt->m_req_frame_size * SMID)) 1121 1122 #define ClrSetBits32(hdl, reg, clr, set) \ 1123 ddi_put32(hdl, (reg), \ 1124 ((ddi_get32(mpt->m_datap, (reg)) & ~(clr)) | (set))) 1125 1126 #define ClrSetBits(reg, clr, set) \ 1127 ddi_put8(mpt->m_datap, (uint8_t *)(reg), \ 1128 ((ddi_get8(mpt->m_datap, (uint8_t *)(reg)) & ~(clr)) | (set))) 1129 1130 #define MPTSAS_WAITQ_RM(mpt, cmdp) \ 1131 if ((cmdp = mpt->m_waitq) != NULL) { \ 1132 /* If the queue is now empty fix the tail pointer */ \ 1133 if ((mpt->m_waitq = cmdp->cmd_linkp) == NULL) \ 1134 mpt->m_waitqtail = &mpt->m_waitq; \ 1135 cmdp->cmd_linkp = NULL; \ 1136 cmdp->cmd_queued = FALSE; \ 1137 } 1138 1139 #define MPTSAS_TX_WAITQ_RM(mpt, cmdp) \ 1140 if ((cmdp = mpt->m_tx_waitq) != NULL) { \ 1141 /* If the queue is now empty fix the tail pointer */ \ 1142 if ((mpt->m_tx_waitq = cmdp->cmd_linkp) == NULL) \ 1143 mpt->m_tx_waitqtail = &mpt->m_tx_waitq; \ 1144 cmdp->cmd_linkp = NULL; \ 1145 cmdp->cmd_queued = FALSE; \ 1146 } 1147 1148 /* 1149 * defaults for the global properties 1150 */ 1151 #define DEFAULT_SCSI_OPTIONS SCSI_OPTIONS_DR 1152 #define DEFAULT_TAG_AGE_LIMIT 2 1153 #define DEFAULT_WD_TICK 10 1154 1155 /* 1156 * invalid hostid. 1157 */ 1158 #define MPTSAS_INVALID_HOSTID -1 1159 1160 /* 1161 * Get/Set hostid from SCSI port configuration page 1162 */ 1163 #define MPTSAS_GET_HOST_ID(configuration) (configuration & 0xFF) 1164 #define MPTSAS_SET_HOST_ID(hostid) (hostid | ((1 << hostid) << 16)) 1165 1166 /* 1167 * Config space. 1168 */ 1169 #define MPTSAS_LATENCY_TIMER 0x40 1170 1171 /* 1172 * Offset to firmware version 1173 */ 1174 #define MPTSAS_FW_VERSION_OFFSET 9 1175 1176 /* 1177 * Offset and masks to get at the ProductId field 1178 */ 1179 #define MPTSAS_FW_PRODUCTID_OFFSET 8 1180 #define MPTSAS_FW_PRODUCTID_MASK 0xFFFF0000 1181 #define MPTSAS_FW_PRODUCTID_SHIFT 16 1182 1183 /* 1184 * Subsystem ID for HBAs. 1185 */ 1186 #define MPTSAS_HBA_SUBSYSTEM_ID 0x10C0 1187 #define MPTSAS_RHEA_SUBSYSTEM_ID 0x10B0 1188 1189 /* 1190 * reset delay tick 1191 */ 1192 #define MPTSAS_WATCH_RESET_DELAY_TICK 50 /* specified in milli seconds */ 1193 1194 /* 1195 * Ioc reset return values 1196 */ 1197 #define MPTSAS_RESET_FAIL -1 1198 #define MPTSAS_NO_RESET 0 1199 #define MPTSAS_SUCCESS_HARDRESET 1 1200 1201 /* 1202 * throttle support. 1203 */ 1204 #define MAX_THROTTLE 32 1205 #define HOLD_THROTTLE 0 1206 #define DRAIN_THROTTLE -1 1207 #define QFULL_THROTTLE -2 1208 1209 /* 1210 * Passthrough/config request flags 1211 */ 1212 #define MPTSAS_DATA_ALLOCATED 0x0001 1213 #define MPTSAS_DATAOUT_ALLOCATED 0x0002 1214 #define MPTSAS_REQUEST_POOL_CMD 0x0004 1215 #define MPTSAS_ADDRESS_REPLY 0x0008 1216 #define MPTSAS_CMD_TIMEOUT 0x0010 1217 1218 /* 1219 * response code tlr flag 1220 */ 1221 #define MPTSAS_SCSI_RESPONSE_CODE_TLR_OFF 0x02 1222 1223 /* 1224 * System Events 1225 */ 1226 #ifndef DDI_VENDOR_LSI 1227 #define DDI_VENDOR_LSI "LSI" 1228 #endif /* DDI_VENDOR_LSI */ 1229 1230 /* 1231 * Shared functions 1232 */ 1233 int mptsas_save_cmd(struct mptsas *mpt, struct mptsas_cmd *cmd); 1234 void mptsas_remove_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd); 1235 void mptsas_waitq_add(mptsas_t *mpt, mptsas_cmd_t *cmd); 1236 int mptsas_config_space_init(struct mptsas *mpt); 1237 int mptsas_init_chip(mptsas_t *mpt, int first_time); 1238 void mptsas_log(struct mptsas *mpt, int level, char *fmt, ...); 1239 int mptsas_poll(mptsas_t *mpt, mptsas_cmd_t *poll_cmd, int polltime); 1240 int mptsas_do_dma(mptsas_t *mpt, uint32_t size, int var, int (*callback)()); 1241 int mptsas_send_config_request_msg(mptsas_t *mpt, uint8_t action, 1242 uint8_t pagetype, uint32_t pageaddress, uint8_t pagenumber, 1243 uint8_t pageversion, uint8_t pagelength, uint32_t 1244 SGEflagslength, uint32_t SGEaddress32); 1245 int mptsas_send_extended_config_request_msg(mptsas_t *mpt, uint8_t action, 1246 uint8_t extpagetype, uint32_t pageaddress, uint8_t pagenumber, 1247 uint8_t pageversion, uint16_t extpagelength, 1248 uint32_t SGEflagslength, uint32_t SGEaddress32); 1249 int mptsas_update_flash(mptsas_t *mpt, caddr_t ptrbuffer, uint32_t size, 1250 uint8_t type, int mode); 1251 int mptsas_check_flash(mptsas_t *mpt, caddr_t origfile, uint32_t size, 1252 uint8_t type, int mode); 1253 int mptsas_download_firmware(); 1254 int mptsas_can_download_firmware(); 1255 int mptsas_dma_alloc(mptsas_t *mpt, mptsas_dma_alloc_state_t *dma_statep); 1256 void mptsas_dma_free(mptsas_dma_alloc_state_t *dma_statep); 1257 mptsas_phymask_t mptsas_physport_to_phymask(mptsas_t *mpt, uint8_t physport); 1258 void mptsas_fma_check(mptsas_t *mpt, mptsas_cmd_t *cmd); 1259 int mptsas_check_acc_handle(ddi_acc_handle_t handle); 1260 int mptsas_check_dma_handle(ddi_dma_handle_t handle); 1261 void mptsas_fm_ereport(mptsas_t *mpt, char *detail); 1262 1263 /* 1264 * impl functions 1265 */ 1266 int mptsas_ioc_wait_for_response(mptsas_t *mpt); 1267 int mptsas_ioc_wait_for_doorbell(mptsas_t *mpt); 1268 int mptsas_ioc_reset(mptsas_t *mpt); 1269 int mptsas_send_handshake_msg(mptsas_t *mpt, caddr_t memp, int numbytes, 1270 ddi_acc_handle_t accessp); 1271 int mptsas_get_handshake_msg(mptsas_t *mpt, caddr_t memp, int numbytes, 1272 ddi_acc_handle_t accessp); 1273 int mptsas_send_config_request_msg(mptsas_t *mpt, uint8_t action, 1274 uint8_t pagetype, uint32_t pageaddress, uint8_t pagenumber, 1275 uint8_t pageversion, uint8_t pagelength, uint32_t SGEflagslength, 1276 uint32_t SGEaddress32); 1277 int mptsas_send_extended_config_request_msg(mptsas_t *mpt, uint8_t action, 1278 uint8_t extpagetype, uint32_t pageaddress, uint8_t pagenumber, 1279 uint8_t pageversion, uint16_t extpagelength, 1280 uint32_t SGEflagslength, uint32_t SGEaddress32); 1281 1282 int mptsas_request_from_pool(mptsas_t *mpt, mptsas_cmd_t **cmd, 1283 struct scsi_pkt **pkt); 1284 void mptsas_return_to_pool(mptsas_t *mpt, mptsas_cmd_t *cmd); 1285 void mptsas_destroy_ioc_event_cmd(mptsas_t *mpt); 1286 void mptsas_start_config_page_access(mptsas_t *mpt, mptsas_cmd_t *cmd); 1287 int mptsas_access_config_page(mptsas_t *mpt, uint8_t action, uint8_t page_type, 1288 uint8_t page_number, uint32_t page_address, int (*callback) (mptsas_t *, 1289 caddr_t, ddi_acc_handle_t, uint16_t, uint32_t, va_list), ...); 1290 1291 int mptsas_ioc_task_management(mptsas_t *mpt, int task_type, 1292 uint16_t dev_handle, int lun, uint8_t *reply, uint32_t reply_size, 1293 int mode); 1294 int mptsas_send_event_ack(mptsas_t *mpt, uint32_t event, uint32_t eventcntx); 1295 void mptsas_send_pending_event_ack(mptsas_t *mpt); 1296 void mptsas_set_throttle(struct mptsas *mpt, mptsas_target_t *ptgt, int what); 1297 int mptsas_restart_ioc(mptsas_t *mpt); 1298 void mptsas_update_driver_data(struct mptsas *mpt); 1299 uint64_t mptsas_get_sata_guid(mptsas_t *mpt, mptsas_target_t *ptgt, int lun); 1300 1301 /* 1302 * init functions 1303 */ 1304 int mptsas_ioc_get_facts(mptsas_t *mpt); 1305 int mptsas_ioc_get_port_facts(mptsas_t *mpt, int port); 1306 int mptsas_ioc_enable_port(mptsas_t *mpt); 1307 int mptsas_ioc_enable_event_notification(mptsas_t *mpt); 1308 int mptsas_ioc_init(mptsas_t *mpt); 1309 1310 /* 1311 * configuration pages operation 1312 */ 1313 int mptsas_get_sas_device_page0(mptsas_t *mpt, uint32_t page_address, 1314 uint16_t *dev_handle, uint64_t *sas_wwn, uint32_t *dev_info, 1315 uint8_t *physport, uint8_t *phynum, uint16_t *pdevhandle, 1316 uint16_t *slot_num, uint16_t *enclosure); 1317 int mptsas_get_sas_io_unit_page(mptsas_t *mpt); 1318 int mptsas_get_sas_io_unit_page_hndshk(mptsas_t *mpt); 1319 int mptsas_get_sas_expander_page0(mptsas_t *mpt, uint32_t page_address, 1320 mptsas_smp_t *info); 1321 int mptsas_set_ioc_params(mptsas_t *mpt); 1322 int mptsas_get_manufacture_page5(mptsas_t *mpt); 1323 int mptsas_get_sas_port_page0(mptsas_t *mpt, uint32_t page_address, 1324 uint64_t *sas_wwn, uint8_t *portwidth); 1325 int mptsas_get_bios_page3(mptsas_t *mpt, uint32_t *bios_version); 1326 int 1327 mptsas_get_sas_phy_page0(mptsas_t *mpt, uint32_t page_address, 1328 smhba_info_t *info); 1329 int 1330 mptsas_get_sas_phy_page1(mptsas_t *mpt, uint32_t page_address, 1331 smhba_info_t *info); 1332 int 1333 mptsas_get_manufacture_page0(mptsas_t *mpt); 1334 void 1335 mptsas_create_phy_stats(mptsas_t *mpt, char *iport, dev_info_t *dip); 1336 void mptsas_destroy_phy_stats(mptsas_t *mpt); 1337 int mptsas_smhba_phy_init(mptsas_t *mpt); 1338 /* 1339 * RAID functions 1340 */ 1341 int mptsas_get_raid_settings(mptsas_t *mpt, mptsas_raidvol_t *raidvol); 1342 int mptsas_get_raid_info(mptsas_t *mpt); 1343 int mptsas_get_physdisk_settings(mptsas_t *mpt, mptsas_raidvol_t *raidvol, 1344 uint8_t physdisknum); 1345 int mptsas_delete_volume(mptsas_t *mpt, uint16_t volid); 1346 void mptsas_raid_action_system_shutdown(mptsas_t *mpt); 1347 1348 #define MPTSAS_IOCSTATUS(status) (status & MPI2_IOCSTATUS_MASK) 1349 /* 1350 * debugging. 1351 */ 1352 #if defined(MPTSAS_DEBUG) 1353 1354 void mptsas_printf(char *fmt, ...); 1355 1356 #define MPTSAS_DBGPR(m, args) \ 1357 if (mptsas_debug_flags & (m)) \ 1358 mptsas_printf args 1359 #else /* ! defined(MPTSAS_DEBUG) */ 1360 #define MPTSAS_DBGPR(m, args) 1361 #endif /* defined(MPTSAS_DEBUG) */ 1362 1363 #define NDBG0(args) MPTSAS_DBGPR(0x01, args) /* init */ 1364 #define NDBG1(args) MPTSAS_DBGPR(0x02, args) /* normal running */ 1365 #define NDBG2(args) MPTSAS_DBGPR(0x04, args) /* property handling */ 1366 #define NDBG3(args) MPTSAS_DBGPR(0x08, args) /* pkt handling */ 1367 1368 #define NDBG4(args) MPTSAS_DBGPR(0x10, args) /* kmem alloc/free */ 1369 #define NDBG5(args) MPTSAS_DBGPR(0x20, args) /* polled cmds */ 1370 #define NDBG6(args) MPTSAS_DBGPR(0x40, args) /* interrupts */ 1371 #define NDBG7(args) MPTSAS_DBGPR(0x80, args) /* queue handling */ 1372 1373 #define NDBG8(args) MPTSAS_DBGPR(0x0100, args) /* arq */ 1374 #define NDBG9(args) MPTSAS_DBGPR(0x0200, args) /* Tagged Q'ing */ 1375 #define NDBG10(args) MPTSAS_DBGPR(0x0400, args) /* halting chip */ 1376 #define NDBG11(args) MPTSAS_DBGPR(0x0800, args) /* power management */ 1377 1378 #define NDBG12(args) MPTSAS_DBGPR(0x1000, args) /* enumeration */ 1379 #define NDBG13(args) MPTSAS_DBGPR(0x2000, args) /* configuration page */ 1380 #define NDBG14(args) MPTSAS_DBGPR(0x4000, args) /* LED control */ 1381 #define NDBG15(args) MPTSAS_DBGPR(0x8000, args) 1382 1383 #define NDBG16(args) MPTSAS_DBGPR(0x010000, args) 1384 #define NDBG17(args) MPTSAS_DBGPR(0x020000, args) /* scatter/gather */ 1385 #define NDBG18(args) MPTSAS_DBGPR(0x040000, args) 1386 #define NDBG19(args) MPTSAS_DBGPR(0x080000, args) /* handshaking */ 1387 1388 #define NDBG20(args) MPTSAS_DBGPR(0x100000, args) /* events */ 1389 #define NDBG21(args) MPTSAS_DBGPR(0x200000, args) /* dma */ 1390 #define NDBG22(args) MPTSAS_DBGPR(0x400000, args) /* reset */ 1391 #define NDBG23(args) MPTSAS_DBGPR(0x800000, args) /* abort */ 1392 1393 #define NDBG24(args) MPTSAS_DBGPR(0x1000000, args) /* capabilities */ 1394 #define NDBG25(args) MPTSAS_DBGPR(0x2000000, args) /* flushing */ 1395 #define NDBG26(args) MPTSAS_DBGPR(0x4000000, args) 1396 #define NDBG27(args) MPTSAS_DBGPR(0x8000000, args) 1397 1398 #define NDBG28(args) MPTSAS_DBGPR(0x10000000, args) /* hotplug */ 1399 #define NDBG29(args) MPTSAS_DBGPR(0x20000000, args) /* timeouts */ 1400 #define NDBG30(args) MPTSAS_DBGPR(0x40000000, args) /* mptsas_watch */ 1401 #define NDBG31(args) MPTSAS_DBGPR(0x80000000, args) /* negotations */ 1402 1403 /* 1404 * auto request sense 1405 */ 1406 #define RQ_MAKECOM_COMMON(pkt, flag, cmd) \ 1407 (pkt)->pkt_flags = (flag), \ 1408 ((union scsi_cdb *)(pkt)->pkt_cdbp)->scc_cmd = (cmd), \ 1409 ((union scsi_cdb *)(pkt)->pkt_cdbp)->scc_lun = \ 1410 (pkt)->pkt_address.a_lun 1411 1412 #define RQ_MAKECOM_G0(pkt, flag, cmd, addr, cnt) \ 1413 RQ_MAKECOM_COMMON((pkt), (flag), (cmd)), \ 1414 FORMG0ADDR(((union scsi_cdb *)(pkt)->pkt_cdbp), (addr)), \ 1415 FORMG0COUNT(((union scsi_cdb *)(pkt)->pkt_cdbp), (cnt)) 1416 1417 1418 #ifdef __cplusplus 1419 } 1420 #endif 1421 1422 #endif /* _SYS_SCSI_ADAPTERS_MPTVAR_H */ 1423