1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _NV_SATA_H 28 #define _NV_SATA_H 29 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 36 /* 37 * SGPIO Support 38 * Enable SGPIO support only on x86/x64, because it is implemented using 39 * functions that are only available on x86/x64. 40 */ 41 42 #define NV_MAX_PORTS(nvc) nvc->nvc_sata_hba_tran.sata_tran_hba_num_cports 43 44 typedef struct nv_port nv_port_t; 45 46 #ifdef SGPIO_SUPPORT 47 typedef struct nv_sgp_cmn nv_sgp_cmn_t; 48 #endif 49 50 typedef struct nv_ctl { 51 /* 52 * Each of these are specific to the chipset in use. 53 */ 54 uint_t (*nvc_interrupt)(caddr_t arg1, caddr_t arg2); 55 void (*nvc_reg_init)(struct nv_ctl *nvc, 56 ddi_acc_handle_t pci_conf_handle); 57 58 dev_info_t *nvc_dip; /* devinfo pointer of controller */ 59 60 struct nv_port *nvc_port; /* array of pointers to port struct */ 61 62 /* 63 * handle and base address to register space. 64 * 65 * 0: port 0 task file 66 * 1: port 0 status 67 * 2: port 1 task file 68 * 3: port 1 status 69 * 4: bus master for both ports 70 * 5: extended registers for SATA features 71 */ 72 ddi_acc_handle_t nvc_bar_hdl[6]; 73 uchar_t *nvc_bar_addr[6]; 74 75 /* 76 * sata registers in bar 5 which are shared on all devices 77 * on the channel. 78 */ 79 uint32_t *nvc_mcp5x_ctl; 80 uint32_t *nvc_mcp5x_ncq; /* NCQ status control bits */ 81 82 kmutex_t nvc_mutex; /* ctrl level lock */ 83 84 ddi_intr_handle_t *nvc_htable; /* For array of interrupts */ 85 int nvc_intr_type; /* What type of interrupt */ 86 int nvc_intr_cnt; /* # of intrs count returned */ 87 size_t nvc_intr_size; /* Size of intr array to */ 88 uint_t nvc_intr_pri; /* Interrupt priority */ 89 int nvc_intr_cap; /* Interrupt capabilities */ 90 uint8_t *nvc_ck804_int_status; /* interrupt status ck804 */ 91 92 sata_hba_tran_t nvc_sata_hba_tran; /* sata_hba_tran for ctrl */ 93 94 /* 95 * enable/disable interrupts, controller specific 96 */ 97 void (*nvc_set_intr)(nv_port_t *nvp, int flag); 98 int nvc_state; /* state flags of ctrl see below */ 99 uint8_t nvc_revid; /* PCI revid of device */ 100 boolean_t dma_40bit; /* 40bit DMA support */ 101 102 #ifdef SGPIO_SUPPORT 103 int nvc_mcp5x_flag; /* is the controller MCP51/MCP55 */ 104 uint8_t nvc_ctlr_num; /* controller number within the part */ 105 uint32_t nvc_sgp_csr; /* SGPIO CSR i/o address */ 106 volatile nv_sgp_cb_t *nvc_sgp_cbp; /* SGPIO Command Block */ 107 nv_sgp_cmn_t *nvc_sgp_cmn; /* SGPIO shared data */ 108 #endif 109 } nv_ctl_t; 110 111 112 struct nv_port { 113 114 struct nv_ctl *nvp_ctlp; /* back pointer to controller */ 115 116 uint8_t nvp_port_num; /* port number, ie 1 or 2 */ 117 118 uint8_t nvp_type; /* SATA_DTYPE_{NONE,ATADISK,UNKNOWN} */ 119 uint32_t nvp_signature; /* sig acquired from task file regs */ 120 uchar_t *nvp_cmd_addr; /* base addr for cmd regs for port */ 121 uchar_t *nvp_bm_addr; /* base addr for bus master for port */ 122 uchar_t *nvp_ctl_addr; /* base addr for ctrl regs for port */ 123 124 ddi_acc_handle_t nvp_cmd_hdl; 125 uchar_t *nvp_data; /* data register */ 126 uchar_t *nvp_error; /* error register (read) */ 127 uchar_t *nvp_feature; /* features (write) */ 128 uchar_t *nvp_count; /* sector count */ 129 uchar_t *nvp_sect; /* sector number */ 130 uchar_t *nvp_lcyl; /* cylinder low byte */ 131 uchar_t *nvp_hcyl; /* cylinder high byte */ 132 uchar_t *nvp_drvhd; /* drive/head register */ 133 uchar_t *nvp_status; /* status/command register */ 134 uchar_t *nvp_cmd; /* status/command register */ 135 136 ddi_acc_handle_t nvp_ctl_hdl; 137 uchar_t *nvp_altstatus; /* alternate status (read) */ 138 uchar_t *nvp_devctl; /* device control (write) */ 139 140 ddi_acc_handle_t nvp_bm_hdl; 141 uchar_t *nvp_bmisx; 142 uint32_t *nvp_bmidtpx; 143 uchar_t *nvp_bmicx; 144 145 ddi_dma_handle_t *nvp_sg_dma_hdl; /* dma handle to prd table */ 146 caddr_t *nvp_sg_addr; /* virtual addr of prd table */ 147 uint32_t *nvp_sg_paddr; /* physical address of prd table */ 148 ddi_acc_handle_t *nvp_sg_acc_hdl; /* mem acc handle to the prd table */ 149 150 uint32_t *nvp_sstatus; 151 uint32_t *nvp_serror; 152 uint32_t *nvp_sctrl; 153 uint32_t *nvp_sactive; 154 155 kmutex_t nvp_mutex; /* main per port mutex */ 156 kcondvar_t nvp_poll_cv; /* handshake cv between poll & isr */ 157 158 /* 159 * nvp_slot is a pointer to an array of nv_slot 160 */ 161 struct nv_slot *nvp_slot; 162 uint32_t nvp_sactive_cache; /* cache of SACTIVE */ 163 uint8_t nvp_queue_depth; 164 165 /* 166 * NCQ flow control. During NCQ operation, no other commands 167 * allowed. The following are used to enforce this. 168 */ 169 int nvp_ncq_run; 170 int nvp_non_ncq_run; 171 172 timeout_id_t nvp_timeout_id; 173 174 clock_t nvp_reset_time; /* time of last reset */ 175 clock_t nvp_probe_time; /* time when probe began */ 176 clock_t nvp_link_lost_time; /* time link lost was noticed */ 177 178 int nvp_state; /* state of port. flags defined below */ 179 180 uint16_t *nvp_mcp5x_int_status; 181 uint16_t *nvp_mcp5x_int_ctl; 182 183 #ifdef SGPIO_SUPPORT 184 uint8_t nvp_sgp_ioctl_mod; /* LEDs modified by ioctl */ 185 #endif 186 }; 187 188 189 typedef struct nv_device_table { 190 ushort_t vendor_id; /* vendor id */ 191 ushort_t device_id; /* device id */ 192 ushort_t type; /* chipset type, ck804 or mcp51/mcp55 */ 193 } nv_device_table_t; 194 195 196 typedef struct nv_slot { 197 caddr_t nvslot_v_addr; /* I/O buffer address */ 198 size_t nvslot_byte_count; /* # bytes left to read/write */ 199 sata_pkt_t *nvslot_spkt; 200 uint8_t nvslot_rqsense_buff[SATA_ATAPI_RQSENSE_LEN]; 201 clock_t nvslot_stime; 202 int (*nvslot_start)(nv_port_t *nvp, int queue); 203 void (*nvslot_intr)(nv_port_t *nvp, 204 struct nv_slot *nv_slotp); 205 uint32_t nvslot_flags; 206 } nv_slot_t; 207 208 209 #ifdef SGPIO_SUPPORT 210 struct nv_sgp_cmn { 211 uint16_t nvs_magic; /* verification of valid structure */ 212 uint8_t nvs_in_use; /* bit-field of active ctlrs */ 213 uint8_t nvs_connected; /* port connected bit-field flag */ 214 uint8_t nvs_activity; /* port usage bit-field flag */ 215 int nvs_taskq_delay; /* rest time for activity LED taskq */ 216 kmutex_t nvs_slock; /* lock for shared data */ 217 kmutex_t nvs_tlock; /* lock for taskq */ 218 kcondvar_t nvs_cv; /* condition variable for taskq wait */ 219 ddi_taskq_t *nvs_taskq; /* activity LED taskq */ 220 }; 221 #endif 222 223 224 /* 225 * nvslot_flags 226 */ 227 #define NVSLOT_COMPLETE 0x01 228 #define NVSLOT_NCQ 0x02 /* NCQ is active */ 229 #define NVSLOT_RQSENSE 0x04 /* processing request sense */ 230 231 /* 232 * state values for nv_attach 233 */ 234 #define ATTACH_PROGRESS_NONE (1 << 0) 235 #define ATTACH_PROGRESS_STATEP_ALLOC (1 << 1) 236 #define ATTACH_PROGRESS_PCI_HANDLE (1 << 2) 237 #define ATTACH_PROGRESS_BARS (1 << 3) 238 #define ATTACH_PROGRESS_INTR_ADDED (1 << 4) 239 #define ATTACH_PROGRESS_MUTEX_INIT (1 << 5) 240 #define ATTACH_PROGRESS_CTL_SETUP (1 << 6) 241 #define ATTACH_PROGRESS_TRAN_SETUP (1 << 7) 242 #define ATTACH_PROGRESS_COUNT (1 << 8) 243 #define ATTACH_PROGRESS_CONF_HANDLE (1 << 9) 244 #define ATTACH_PROGRESS_SATA_MODULE (1 << 10) 245 246 #ifdef DEBUG 247 248 #define NV_DEBUG 1 249 250 #endif /* DEBUG */ 251 252 253 /* 254 * nv_debug_flags 255 */ 256 #define NVDBG_ALWAYS 0x0001 257 #define NVDBG_INIT 0x0002 258 #define NVDBG_ENTRY 0x0004 259 #define NVDBG_DELIVER 0x0008 260 #define NVDBG_EVENT 0x0010 261 #define NVDBG_SYNC 0x0020 262 #define NVDBG_PKTCOMP 0x0040 263 #define NVDBG_TIMEOUT 0x0080 264 #define NVDBG_INFO 0x0100 265 #define NVDBG_VERBOSE 0x0200 266 #define NVDBG_INTR 0x0400 267 #define NVDBG_ERRS 0x0800 268 #define NVDBG_COOKIES 0x1000 269 #define NVDBG_HOT 0x2000 270 #define NVDBG_PROBE 0x4000 271 #define NVDBG_ATAPI 0x8000 272 273 #ifdef DEBUG 274 #define NVLOG(a) nv_log a 275 #else 276 #define NVLOG(a) 277 #endif 278 279 #define NV_SUCCESS 0 280 #define NV_FAILURE -1 281 282 /* 283 * indicates whether nv_wait functions can sleep or not. 284 */ 285 #define NV_SLEEP 1 286 #define NV_NOSLEEP 2 287 288 /* 289 * port offsets from base address ioaddr1 290 */ 291 #define NV_DATA 0x00 /* data register */ 292 #define NV_ERROR 0x01 /* error register (read) */ 293 #define NV_FEATURE 0x01 /* features (write) */ 294 #define NV_COUNT 0x02 /* sector count */ 295 #define NV_SECT 0x03 /* sector number */ 296 #define NV_LCYL 0x04 /* cylinder low byte */ 297 #define NV_HCYL 0x05 /* cylinder high byte */ 298 #define NV_DRVHD 0x06 /* drive/head register */ 299 #define NV_STATUS 0x07 /* status/command register */ 300 #define NV_CMD 0x07 /* status/command register */ 301 302 /* 303 * port offsets from base address ioaddr2 304 */ 305 #define NV_ALTSTATUS 0x02 /* alternate status (read) */ 306 #define NV_DEVCTL 0x02 /* device control (write) */ 307 308 /* 309 * device control register 310 */ 311 #define ATDC_NIEN 0x02 /* disable interrupts */ 312 #define ATDC_SRST 0x04 /* controller reset */ 313 #define ATDC_D3 0x08 /* mysterious bit */ 314 #define ATDC_HOB 0x80 /* high order byte to read 48-bit values */ 315 316 317 #define MCP5X_CTL 0x400 /* queuing control */ 318 #define MCP5X_INT_STATUS 0x440 /* status bits for interrupt */ 319 #define MCP5X_INT_CTL 0x444 /* enable bits for interrupt */ 320 #define MCP5X_NCQ 0x448 /* NCQ status and ctrl bits */ 321 322 /* 323 * if either of these bits are set, when using NCQ, if no other commands are 324 * active while a new command is started, DMA engine can be programmed ahead 325 * of time to save extra interrupt. Presumably pre-programming is discarded 326 * if a subsequent command ends up finishing first. 327 */ 328 #define MCP_SATA_AE_NCQ_PDEV_FIRST_CMD (1 << 7) 329 #define MCP_SATA_AE_NCQ_SDEV_FIRST_CMD (1 << 23) 330 331 /* 332 * bit definitions to indicate which NCQ command requires 333 * DMA setup. 334 */ 335 #define MCP_SATA_AE_NCQ_PDEV_DMA_SETUP_TAG_SHIFT 2 336 #define MCP_SATA_AE_NCQ_SDEV_DMA_SETUP_TAG_SHIFT 18 337 #define MCP_SATA_AE_NCQ_DMA_SETUP_TAG_MASK 0x1f 338 339 340 /* 341 * Bits for NV_MCP5X_INT_CTL and NV_MCP5X_INT_STATUS 342 */ 343 #define MCP5X_INT_SNOTIFY 0x200 /* snotification set */ 344 #define MCP5X_INT_SERROR 0x100 /* serror set */ 345 #define MCP5X_INT_DMA_SETUP 0x80 /* DMA to be programmed */ 346 #define MCP5X_INT_DH_REGFIS 0x40 /* REGFIS received */ 347 #define MCP5X_INT_SDB_FIS 0x20 /* SDB FIS */ 348 #define MCP5X_INT_TX_BACKOUT 0x10 /* TX backout */ 349 #define MCP5X_INT_REM 0x08 /* device removed */ 350 #define MCP5X_INT_ADD 0x04 /* device added */ 351 #define MCP5X_INT_PM 0x02 /* power changed */ 352 #define MCP5X_INT_COMPLETE 0x01 /* device interrupt */ 353 354 /* 355 * Bits above that are not used for now. 356 */ 357 #define MCP5X_INT_IGNORE (MCP5X_INT_DMA_SETUP|MCP5X_INT_DH_REGFIS|\ 358 MCP5X_INT_SDB_FIS|MCP5X_INT_TX_BACKOUT|MCP5X_INT_PM|\ 359 MCP5X_INT_SNOTIFY|MCP5X_INT_SERROR) 360 361 /* 362 * Bits for MCP_SATA_AE_CTL 363 */ 364 #define MCP_SATA_AE_CTL_PRI_SWNCQ (1 << 1) /* software NCQ chan 0 */ 365 #define MCP_SATA_AE_CTL_SEC_SWNCQ (1 << 2) /* software NCQ chan 1 */ 366 367 #define NV_DELAY_NSEC(wait_ns) \ 368 { \ 369 hrtime_t start, end; \ 370 start = end = gethrtime(); \ 371 while ((end - start) < wait_ns) \ 372 end = gethrtime(); \ 373 } 374 375 /* 376 * signatures in task file registers after device reset 377 */ 378 #define NV_SIG_DISK 0x00000101 379 #define NV_SIG_ATAPI 0xeb140101 380 #define NV_SIG_PM 0x96690101 381 #define NV_SIG_NOTREADY 0x00000000 382 383 /* 384 * These bar5 offsets are common to mcp51/mcp55/ck804 and thus 385 * prefixed with NV. 386 */ 387 #define NV_SSTATUS 0x00 388 #define NV_SERROR 0x04 389 #define NV_SCTRL 0x08 390 #define NV_SACTIVE 0x0c 391 #define NV_SNOTIFICATION 0x10 392 393 #define CH0_SREG_OFFSET 0x0 394 #define CH1_SREG_OFFSET 0x40 395 396 397 /* 398 * The following config space offsets are needed to enable 399 * bar 5 register access in ck804/mcp51/mcp55 400 */ 401 #define NV_SATA_CFG_20 0x50 402 #define NV_BAR5_SPACE_EN 0x04 403 #define NV_40BIT_PRD 0x20 404 405 /* 406 * ck804 interrupt status register 407 */ 408 409 /* 410 * offsets to bar 5 registers 411 */ 412 #define CK804_SATA_INT_STATUS 0x440 413 #define CK804_SATA_INT_EN 0x441 414 415 416 /* 417 * bit fields for int status and int enable 418 * registers 419 */ 420 #define CK804_INT_PDEV_INT 0x01 /* completion interrupt */ 421 #define CK804_INT_PDEV_PM 0x02 /* power change */ 422 #define CK804_INT_PDEV_ADD 0x04 /* hot plug */ 423 #define CK804_INT_PDEV_REM 0x08 /* hot remove */ 424 #define CK804_INT_PDEV_HOT CK804_INT_PDEV_ADD|CK804_INT_PDEV_REM 425 426 #define CK804_INT_SDEV_INT 0x10 /* completion interrupt */ 427 #define CK804_INT_SDEV_PM 0x20 /* power change */ 428 #define CK804_INT_SDEV_ADD 0x40 /* hot plug */ 429 #define CK804_INT_SDEV_REM 0x80 /* hot remove */ 430 #define CK804_INT_SDEV_HOT CK804_INT_SDEV_ADD|CK804_INT_SDEV_REM 431 432 #define CK804_INT_PDEV_ALL CK804_INT_PDEV_INT|CK804_INT_PDEV_HOT|\ 433 CK804_INT_PDEV_PM 434 #define CK804_INT_SDEV_ALL CK804_INT_SDEV_INT|CK804_INT_SDEV_HOT|\ 435 CK804_INT_SDEV_PM 436 437 /* 438 * config space offset 42 439 */ 440 #define NV_SATA_CFG_42 0xac 441 442 /* 443 * bit in CFG_42 which delays hotplug interrupt until 444 * PHY ready 445 */ 446 #define CK804_CFG_DELAY_HOTPLUG_INTR (0x1 << 12) 447 448 449 /* 450 * bar 5 offsets for SATA registers in ck804 451 */ 452 #define CK804_CH1_SSTATUS 0x00 453 #define CK804_CH1_SERROR 0x04 454 #define CK804_CH1_SCTRL 0x08 455 #define CK804_CH1_SACTIVE 0x0c 456 #define CK804_CH1_SNOTIFICATION 0x10 457 458 #define CK804_CH2_SSTATUS 0x40 459 #define CK804_CH2_SERROR 0x44 460 #define CK804_CH2_SCTRL 0x48 461 #define CK804_CH2_SACTIVE 0x4c 462 #define CK804_CH2_SNOTIFICATION 0x50 463 464 465 /* 466 * bar 5 offsets for ADMACTL settings for both ck804/mcp51/mcp/55 467 */ 468 #define NV_ADMACTL_X 0x4C0 469 #define NV_ADMACTL_Y 0x5C0 470 471 /* 472 * Bits for NV_ADMACTL_X and NV_ADMACTL_Y 473 */ 474 #define NV_HIRQ_EN 0x01 /* hot plug/unplug interrupt enable */ 475 #define NV_CH_RST 0x04 /* reset channel */ 476 477 478 /* 479 * bar 5 offset for ADMASTAT regs for ck804 480 */ 481 #define CK804_ADMASTAT_X 0x4C4 482 #define CK804_ADMASTAT_Y 0x5C4 483 484 /* 485 * Bits for CK804_ADMASTAT_X and CK804_ADMASTAT_Y 486 */ 487 #define CK804_HPIRQ 0x4 488 #define MCP05_HUIRQ 0x2 489 490 491 /* 492 * bar 4 offset to bus master command registers 493 */ 494 #define BMICX_REG 0 495 496 /* 497 * bit definitions for BMICX_REG 498 */ 499 #define BMICX_SSBM 0x01 /* Start/Stop Bus Master */ 500 /* 1=Start (Enable) */ 501 /* 0=Start (Disable) */ 502 503 /* 504 * NOTE: "read" and "write" are the actions of the DMA engine 505 * on the PCI bus, not the SATA bus. Therefore for a ATA READ 506 * command, program the DMA engine to "write to memory" mode 507 * (and vice versa). 508 */ 509 #define BMICX_RWCON 0x08 /* Read/Write Control */ 510 #define BMICX_RWCON_WRITE_TO_MEMORY 0x08 /* 1=Write (dev to host) */ 511 #define BMICX_RWCON_READ_FROM_MEMORY 0x00 /* 0=Read (host to dev) */ 512 513 /* 514 * BMICX bits to preserve during updates 515 */ 516 #define BMICX_MASK (~(BMICX_SSBM | BMICX_RWCON)) 517 518 /* 519 * bar 4 offset to bus master status register 520 */ 521 #define BMISX_REG 2 522 523 /* 524 * bit fields for bus master status register 525 */ 526 #define BMISX_BMIDEA 0x01 /* Bus Master IDE Active */ 527 #define BMISX_IDERR 0x02 /* IDE DMA Error */ 528 #define BMISX_IDEINTS 0x04 /* IDE Interrupt Status */ 529 530 /* 531 * bus master status register bits to preserve 532 */ 533 #define BMISX_MASK 0xf8 534 535 /* 536 * bar4 offset to bus master PRD descriptor table 537 */ 538 #define BMIDTPX_REG 4 539 540 541 /* 542 * structure for a single entry in the PRD table 543 * (physical region descriptor table) 544 */ 545 typedef struct prde { 546 uint32_t p_address; /* physical address */ 547 uint32_t p_count; /* byte count, EOT in high order bit */ 548 } prde_t; 549 550 551 #define PRDE_EOT ((uint_t)0x80000000) 552 553 #define NV_DMA_NSEGS 256 /* XXX DEBUG TEST change back to 257 */ 554 555 /* 556 * ck804 and mcp55 both have 2 ports per controller 557 */ 558 #define NV_NUM_CPORTS 2 559 560 /* 561 * Number of slots to allocate in data nv_sata structures to handle 562 * multiple commands at once. This does not reflect the capability of 563 * the drive or the hardware, and in many cases will not match. 564 * 1 or 32 slots are allocated, so in cases where the driver has NCQ 565 * enabled but the drive doesn't support it, or supports fewer than 566 * 32 slots, here may be an over allocation of memory. 567 */ 568 #ifdef NCQ 569 #define NV_QUEUE_SLOTS 32 570 #else 571 #define NV_QUEUE_SLOTS 1 572 #endif 573 574 /* 575 * wait 30 seconds for signature 576 */ 577 #define NV_SIG_TIMEOUT 45 578 579 #define NV_BM_64K_BOUNDARY 0x10000ull 580 581 /* 582 * every 1 second 583 */ 584 #define NV_ONE_SEC 1000000 585 586 587 /* 588 * the amount of time link can be down during 589 * reset without taking action. 590 */ 591 #define NV_LINK_LOST_OK 2 592 593 /* 594 * nv_reset() flags 595 */ 596 #define NV_RESET_SEND_EVENT 0x1 /* send reset event to sata module */ 597 #define NV_RESET_WAIT 0x2 /* OK to block waiting for reset */ 598 599 600 601 #define NV_RESET_ATTEMPTS 3 602 603 /* 604 * nvp_state flags 605 */ 606 #define NV_PORT_INACTIVE 0x001 607 #define NV_PORT_ABORTING 0x002 608 #define NV_PORT_HOTREMOVED 0x004 609 #define NV_PORT_INIT 0x008 610 #define NV_PORT_FAILED 0x010 611 #define NV_PORT_RESET 0x020 612 #define NV_PORT_RESET_PROBE 0x040 613 #define NV_PORT_RESTORE 0x080 614 615 /* 616 * nvc_state flags 617 */ 618 #define NV_CTRL_SUSPEND 0x1 619 620 621 /* 622 * flags for ck804_set_intr/mcp5x_set_intr 623 */ 624 #define NV_INTR_DISABLE 0x1 625 #define NV_INTR_ENABLE 0x2 626 #define NV_INTR_CLEAR_ALL 0x4 627 #define NV_INTR_DISABLE_NON_BLOCKING 0x8 628 629 /* 630 * sizes of strings to allocate 631 */ 632 #define NV_STRING_10 10 633 #define NV_STRING_512 512 634 635 #define NV_BYTES_PER_SEC 512 636 637 #define NV_WAIT_REG_CHECK 10 /* 10 microseconds */ 638 #define NV_ATA_NUM_CMDS 256 /* max num ATA cmds possible, 8 bits */ 639 #define NV_PRINT_INTERVAL 40 /* throttle debug msg from flooding */ 640 #define MCP5X_INT_CLEAR 0xffff /* clear all interrupts */ 641 642 /* 643 * definition labels for the BAR registers 644 */ 645 #define NV_BAR_0 0 /* chan 0 task file regs */ 646 #define NV_BAR_1 1 /* chan 0 status reg */ 647 #define NV_BAR_2 2 /* chan 1 task file regs */ 648 #define NV_BAR_3 3 /* chan 1 status reg */ 649 #define NV_BAR_4 4 /* bus master regs */ 650 #define NV_BAR_5 5 /* extra regs mostly SATA related */ 651 652 /* 653 * transform seconds to microseconds 654 */ 655 #define NV_SEC2USEC(x) x * MICROSEC 656 657 658 /* 659 * ck804 maps in task file regs into bar 5. These are 660 * only used to identify ck804, therefore only this reg is 661 * listed here. 662 */ 663 #define NV_BAR5_TRAN_LEN_CH_X 0x518 664 665 /* 666 * if after this many iterations through the interrupt 667 * processing loop, declare the interrupt wedged and 668 * disable. 669 */ 670 #define NV_MAX_INTR_LOOP 10 671 672 /* 673 * flag values for nv_copy_regs_out 674 */ 675 #define NV_COPY_COMPLETE 0x01 /* normal command completion */ 676 #define NV_COPY_ERROR 0x02 /* error, did not complete ok */ 677 #define NV_COPY_SSREGS 0x04 /* SS port registers */ 678 679 #ifdef SGPIO_SUPPORT 680 #define SGPIO_MAGIC 0x39da /* verifies good sgpio struct */ 681 #define SGPIO_LOOP_WAIT_USECS 62500 /* 1/16 second (in usecs) */ 682 #define SGPIO_TQ_NAME_LEN 32 683 684 /* 685 * The drive number format is ccp (binary). 686 * cc is the controller number (0-based number) 687 * p is the port number (0 or 1) 688 */ 689 #define SGP_DRV_TO_PORT(d) ((d) & 1) 690 #define SGP_DRV_TO_CTLR(d) ((d) >> 1) 691 #define SGP_CTLR_PORT_TO_DRV(c, p) (((c) << 1) | ((p) & 1)) 692 #endif 693 694 #ifdef __cplusplus 695 } 696 #endif 697 698 #endif /* _NV_SATA_H */ 699