1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_NXGE_NXGE_N2_ESR_HW_H 27 #define _SYS_NXGE_NXGE_N2_ESR_HW_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #define ESR_N2_DEV_ADDR 0x1E 36 #define ESR_N2_BASE 0x8000 37 38 /* 39 * Definitions for TI WIZ6C2xxN2x0 Macro Family. 40 */ 41 42 /* Register Blocks base address */ 43 44 #define ESR_N2_PLL_REG_OFFSET 0 45 #define ESR_N2_TEST_REG_OFFSET 0x004 46 #define ESR_N2_TX_REG_OFFSET 0x100 47 #define ESR_N2_TX_0_REG_OFFSET 0x100 48 #define ESR_N2_TX_1_REG_OFFSET 0x104 49 #define ESR_N2_TX_2_REG_OFFSET 0x108 50 #define ESR_N2_TX_3_REG_OFFSET 0x10c 51 #define ESR_N2_TX_4_REG_OFFSET 0x110 52 #define ESR_N2_TX_5_REG_OFFSET 0x114 53 #define ESR_N2_TX_6_REG_OFFSET 0x118 54 #define ESR_N2_TX_7_REG_OFFSET 0x11c 55 #define ESR_N2_RX_REG_OFFSET 0x120 56 #define ESR_N2_RX_0_REG_OFFSET 0x120 57 #define ESR_N2_RX_1_REG_OFFSET 0x124 58 #define ESR_N2_RX_2_REG_OFFSET 0x128 59 #define ESR_N2_RX_3_REG_OFFSET 0x12c 60 #define ESR_N2_RX_4_REG_OFFSET 0x130 61 #define ESR_N2_RX_5_REG_OFFSET 0x134 62 #define ESR_N2_RX_6_REG_OFFSET 0x138 63 #define ESR_N2_RX_7_REG_OFFSET 0x13c 64 #define ESR_N2_P1_REG_OFFSET 0x400 65 66 /* Register address */ 67 68 #define ESR_N2_PLL_CFG_REG ESR_N2_BASE + ESR_N2_PLL_REG_OFFSET 69 #define ESR_N2_PLL_CFG_L_REG ESR_N2_BASE + ESR_N2_PLL_REG_OFFSET 70 #define ESR_N2_PLL_CFG_H_REG ESR_N2_BASE + ESR_N2_PLL_REG_OFFSET + 1 71 #define ESR_N2_PLL_STS_REG ESR_N2_BASE + ESR_N2_PLL_REG_OFFSET + 2 72 #define ESR_N2_PLL_STS_L_REG ESR_N2_BASE + ESR_N2_PLL_REG_OFFSET + 2 73 #define ESR_N2_PLL_STS_H_REG ESR_N2_BASE + ESR_N2_PLL_REG_OFFSET + 3 74 #define ESR_N2_TEST_CFG_REG ESR_N2_BASE + ESR_N2_TEST_REG_OFFSET 75 #define ESR_N2_TEST_CFG_L_REG ESR_N2_BASE + ESR_N2_TEST_REG_OFFSET 76 #define ESR_N2_TEST_CFG_H_REG ESR_N2_BASE + ESR_N2_TEST_REG_OFFSET + 1 77 78 #define ESR_N2_TX_CFG_REG_ADDR(chan) (ESR_N2_BASE + ESR_N2_TX_REG_OFFSET +\ 79 (chan * 4)) 80 #define ESR_N2_TX_CFG_L_REG_ADDR(chan) (ESR_N2_BASE + ESR_N2_TX_REG_OFFSET +\ 81 (chan * 4)) 82 #define ESR_N2_TX_CFG_H_REG_ADDR(chan) (ESR_N2_BASE + ESR_N2_TX_REG_OFFSET +\ 83 (chan * 4) + 1) 84 #define ESR_N2_TX_STS_REG_ADDR(chan) (ESR_N2_BASE + ESR_N2_TX_REG_OFFSET +\ 85 (chan * 4) + 2) 86 #define ESR_N2_TX_STS_L_REG_ADDR(chan) (ESR_N2_BASE + ESR_N2_TX_REG_OFFSET +\ 87 (chan * 4) + 2) 88 #define ESR_N2_TX_STS_H_REG_ADDR(chan) (ESR_N2_BASE + ESR_N2_TX_REG_OFFSET +\ 89 (chan * 4) + 3) 90 #define ESR_N2_RX_CFG_REG_ADDR(chan) (ESR_N2_BASE + ESR_N2_RX_REG_OFFSET +\ 91 (chan * 4)) 92 #define ESR_N2_RX_CFG_L_REG_ADDR(chan) (ESR_N2_BASE + ESR_N2_RX_REG_OFFSET +\ 93 (chan * 4)) 94 #define ESR_N2_RX_CFG_H_REG_ADDR(chan) (ESR_N2_BASE + ESR_N2_RX_REG_OFFSET +\ 95 (chan * 4) + 1) 96 #define ESR_N2_RX_STS_REG_ADDR(chan) (ESR_N2_BASE + ESR_N2_RX_REG_OFFSET +\ 97 (chan * 4) + 2) 98 #define ESR_N2_RX_STS_L_REG_ADDR(chan) (ESR_N2_BASE + ESR_N2_RX_REG_OFFSET +\ 99 (chan * 4) + 2) 100 #define ESR_N2_RX_STS_H_REG_ADDR(chan) (ESR_N2_BASE + ESR_N2_RX_REG_OFFSET +\ 101 (chan * 4) + 3) 102 103 /* PLL Configuration Low 16-bit word */ 104 typedef union _esr_ti_cfgpll_l { 105 uint16_t value; 106 107 struct { 108 #if defined(_BIT_FIELDS_HTOL) 109 uint16_t res2 : 6; 110 uint16_t lb : 2; 111 uint16_t res1 : 3; 112 uint16_t mpy : 4; 113 uint16_t enpll : 1; 114 #elif defined(_BIT_FIELDS_LTOH) 115 uint16_t enpll : 1; 116 uint16_t mpy : 4; 117 uint16_t res1 : 3; 118 uint16_t lb : 2; 119 uint16_t res2 : 6; 120 #endif 121 } bits; 122 } esr_ti_cfgpll_l_t; 123 124 /* PLL Configurations */ 125 #define CFGPLL_LB_FREQ_DEP_BANDWIDTH 0 126 #define CFGPLL_LB_LOW_BANDWIDTH 0x2 127 #define CFGPLL_LB_HIGH_BANDWIDTH 0x3 128 #define CFGPLL_MPY_4X 0 129 #define CFGPLL_MPY_5X 0x1 130 #define CFGPLL_MPY_6X 0x2 131 #define CFGPLL_MPY_8X 0x4 132 #define CFGPLL_MPY_10X 0x5 133 #define CFGPLL_MPY_12X 0x6 134 #define CFGPLL_MPY_12P5X 0x7 135 136 /* Rx Configuration Low 16-bit word */ 137 138 typedef union _esr_ti_cfgrx_l { 139 uint16_t value; 140 141 struct { 142 #if defined(_BIT_FIELDS_HTOL) 143 uint16_t los : 2; 144 uint16_t align : 2; 145 uint16_t res : 1; 146 uint16_t term : 3; 147 uint16_t invpair : 1; 148 uint16_t rate : 2; 149 uint16_t buswidth : 3; 150 uint16_t entest : 1; 151 uint16_t enrx : 1; 152 #elif defined(_BIT_FIELDS_LTOH) 153 uint16_t enrx : 1; 154 uint16_t entest : 1; 155 uint16_t buswidth : 3; 156 uint16_t rate : 2; 157 uint16_t invpair : 1; 158 uint16_t term : 3; 159 uint16_t res : 1; 160 uint16_t align : 2; 161 uint16_t los : 2; 162 #endif 163 } bits; 164 } esr_ti_cfgrx_l_t; 165 166 /* Rx Configuration High 16-bit word */ 167 168 typedef union _esr_ti_cfgrx_h { 169 uint16_t value; 170 171 struct { 172 #if defined(_BIT_FIELDS_HTOL) 173 uint16_t res2 : 6; 174 uint16_t bsinrxn : 1; 175 uint16_t bsinrxp : 1; 176 uint16_t res1 : 1; 177 uint16_t eq : 4; 178 uint16_t cdr : 3; 179 #elif defined(_BIT_FIELDS_LTOH) 180 uint16_t cdr : 3; 181 uint16_t eq : 4; 182 uint16_t res1 : 1; 183 uint16_t bsinrxp : 1; 184 uint16_t bsinrxn : 1; 185 uint16_t res2 : 6; 186 #endif 187 } bits; 188 } esr_ti_cfgrx_h_t; 189 190 /* Receive Configurations */ 191 #define CFGRX_BUSWIDTH_10BIT 0 192 #define CFGRX_BUSWIDTH_8BIT 1 193 #define CFGRX_RATE_FULL 0 194 #define CFGRX_RATE_HALF 1 195 #define CFGRX_RATE_QUAD 2 196 #define CFGRX_TERM_VDDT 0 197 #define CFGRX_TERM_0P8VDDT 1 198 #define CFGRX_TERM_FLOAT 3 199 #define CFGRX_ALIGN_DIS 0 200 #define CFGRX_ALIGN_EN 1 201 #define CFGRX_ALIGN_JOG 2 202 #define CFGRX_LOS_DIS 0 203 #define CFGRX_LOS_HITHRES 1 204 #define CFGRX_LOS_LOTHRES 2 205 #define CFGRX_CDR_1ST_ORDER 0 206 #define CFGRX_CDR_2ND_ORDER_HP 1 207 #define CFGRX_CDR_2ND_ORDER_MP 2 208 #define CFGRX_CDR_2ND_ORDER_LP 3 209 #define CFGRX_CDR_1ST_ORDER_FAST_LOCK 4 210 #define CFGRX_CDR_2ND_ORDER_HP_FAST_LOCK 5 211 #define CFGRX_CDR_2ND_ORDER_MP_FAST_LOCK 6 212 #define CFGRX_CDR_2ND_ORDER_LP_FAST_LOCK 7 213 #define CFGRX_EQ_MAX_LF 0 214 #define CFGRX_EQ_ADAPTIVE_LP_ADAPTIVE_ZF 0x1 215 #define CFGRX_EQ_ADAPTIVE_LF_1084MHZ_ZF 0x8 216 #define CFGRX_EQ_ADAPTIVE_LF_805MHZ_ZF 0x9 217 #define CFGRX_EQ_ADAPTIVE_LP_573MHZ_ZF 0xA 218 #define CFGRX_EQ_ADAPTIVE_LP_402MHZ_ZF 0xB 219 #define CFGRX_EQ_ADAPTIVE_LP_304MHZ_ZF 0xC 220 #define CFGRX_EQ_ADAPTIVE_LP_216MHZ_ZF 0xD 221 #define CFGRX_EQ_ADAPTIVE_LP_156MHZ_ZF 0xE 222 #define CFGRX_EQ_ADAPTIVE_LP_135HZ_ZF 0xF 223 224 /* Rx Status Low 16-bit word */ 225 226 typedef union _esr_ti_stsrx_l { 227 uint16_t value; 228 229 struct { 230 #if defined(_BIT_FIELDS_HTOL) 231 uint16_t res : 10; 232 uint16_t bsrxn : 1; 233 uint16_t bsrxp : 1; 234 uint16_t losdtct : 1; 235 uint16_t oddcg : 1; 236 uint16_t sync : 1; 237 uint16_t testfail : 1; 238 #elif defined(_BIT_FIELDS_LTOH) 239 uint16_t testfail : 1; 240 uint16_t sync : 1; 241 uint16_t oddcg : 1; 242 uint16_t losdtct : 1; 243 uint16_t bsrxp : 1; 244 uint16_t bsrxn : 1; 245 uint16_t res : 10; 246 #endif 247 } bits; 248 } esr_ti_stsrx_l_t; 249 250 /* Tx Configuration Low 16-bit word */ 251 252 typedef union _esr_ti_cfgtx_l { 253 uint16_t value; 254 255 struct { 256 #if defined(_BIT_FIELDS_HTOL) 257 uint16_t de : 4; 258 uint16_t swing : 3; 259 uint16_t cm : 1; 260 uint16_t invpair : 1; 261 uint16_t rate : 2; 262 uint16_t buswwidth : 3; 263 uint16_t entest : 1; 264 uint16_t entx : 1; 265 #elif defined(_BIT_FIELDS_LTOH) 266 uint16_t entx : 1; 267 uint16_t entest : 1; 268 uint16_t buswwidth : 3; 269 uint16_t rate : 2; 270 uint16_t invpair : 1; 271 uint16_t cm : 1; 272 uint16_t swing : 3; 273 uint16_t de : 4; 274 #endif 275 } bits; 276 } esr_ti_cfgtx_l_t; 277 278 /* Tx Configuration High 16-bit word */ 279 280 typedef union _esr_ti_cfgtx_h { 281 uint16_t value; 282 283 struct { 284 #if defined(_BIT_FIELDS_HTOL) 285 uint16_t res : 14; 286 uint16_t bstx : 1; 287 uint16_t enftp : 1; 288 #elif defined(_BIT_FIELDS_LTOH) 289 uint16_t enftp : 1; 290 uint16_t bstx : 1; 291 uint16_t res : 14; 292 #endif 293 } bits; 294 } esr_ti_cfgtx_h_t; 295 296 /* Transmit Configurations */ 297 #define CFGTX_BUSWIDTH_10BIT 0 298 #define CFGTX_BUSWIDTH_8BIT 1 299 #define CFGTX_RATE_FULL 0 300 #define CFGTX_RATE_HALF 1 301 #define CFGTX_RATE_QUAD 2 302 #define CFGTX_SWING_125MV 0 303 #define CFGTX_SWING_250MV 1 304 #define CFGTX_SWING_500MV 2 305 #define CFGTX_SWING_625MV 3 306 #define CFGTX_SWING_750MV 4 307 #define CFGTX_SWING_1000MV 5 308 #define CFGTX_SWING_1250MV 6 309 #define CFGTX_SWING_1375MV 7 310 #define CFGTX_DE_0 0 311 #define CFGTX_DE_4P76 1 312 #define CFGTX_DE_9P52 2 313 #define CFGTX_DE_14P28 3 314 #define CFGTX_DE_19P04 4 315 #define CFGTX_DE_23P8 5 316 #define CFGTX_DE_28P56 6 317 #define CFGTX_DE_33P32 7 318 319 /* Test Configuration */ 320 321 typedef union _esr_ti_testcfg { 322 uint16_t value; 323 324 struct { 325 #if defined(_BIT_FIELDS_HTOL) 326 uint16_t res1 : 1; 327 uint16_t invpat : 1; 328 uint16_t rate : 2; 329 uint16_t res : 1; 330 uint16_t enbspls : 1; 331 uint16_t enbsrx : 1; 332 uint16_t enbstx : 1; 333 uint16_t loopback : 2; 334 uint16_t clkbyp : 2; 335 uint16_t enrxpatt : 1; 336 uint16_t entxpatt : 1; 337 uint16_t testpatt : 2; 338 #elif defined(_BIT_FIELDS_LTOH) 339 uint16_t testpatt : 2; 340 uint16_t entxpatt : 1; 341 uint16_t enrxpatt : 1; 342 uint16_t clkbyp : 2; 343 uint16_t loopback : 2; 344 uint16_t enbstx : 1; 345 uint16_t enbsrx : 1; 346 uint16_t enbspls : 1; 347 uint16_t res : 1; 348 uint16_t rate : 2; 349 uint16_t invpat : 1; 350 uint16_t res1 : 1; 351 #endif 352 } bits; 353 } esr_ti_testcfg_t; 354 355 #define TESTCFG_PAD_LOOPBACK 0x1 356 #define TESTCFG_INNER_CML_DIS_LOOPBACK 0x2 357 #define TESTCFG_INNER_CML_EN_LOOOPBACK 0x3 358 359 #ifdef __cplusplus 360 } 361 #endif 362 363 #endif /* _SYS_NXGE_NXGE_N2_ESR_HW_H */ 364