1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* Copyright 2009 QLogic Corporation */ 23 24 /* 25 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms. 27 */ 28 29 #ifndef _QL_XIOCTL_H 30 #define _QL_XIOCTL_H 31 32 /* 33 * ISP2xxx Solaris Fibre Channel Adapter (FCA) driver header file. 34 * 35 * *********************************************************************** 36 * * ** 37 * * NOTICE ** 38 * * COPYRIGHT (C) 1996-2009 QLOGIC CORPORATION ** 39 * * ALL RIGHTS RESERVED ** 40 * * ** 41 * *********************************************************************** 42 * 43 */ 44 45 #ifdef __cplusplus 46 extern "C" { 47 #endif 48 49 #include <exioct.h> 50 51 /* 0xFFFFFA Mgmt Server */ 52 #define MANAGEMENT_SERVER_LOOP_ID 0xfe 53 #define MANAGEMENT_SERVER_24XX_LOOP_ID 0x7ef 54 55 /* Returned Mailbox registers. */ 56 typedef struct ql_mbx_ret { 57 uint16_t mb[MAX_MBOX_COUNT]; 58 } ql_mbx_ret_t; 59 60 /* 61 * Name type defines for use with ql_scsi_passthru() and 62 * elsewhere when searching for name matches. 63 * NOTE that these defines are used both as flags and values. 64 */ 65 #define QLNT_NODE 0x01 66 #define QLNT_PORT 0x02 67 #define QLNT_BOTH (QLNT_NODE | QLNT_PORT) 68 #define QLNT_PID 0x04 69 #define QLNT_LOOP_ID 0x08 70 #define QLNT_MASK 0x0F 71 72 /* 73 * CT information unit basic preamble. 74 */ 75 typedef struct ql_ct_iu_preamble { 76 uint8_t revision; 77 uint8_t in_id[3]; 78 uint8_t gs_type; 79 uint8_t gs_subtype; 80 uint8_t options; 81 uint8_t reserved; 82 uint16_t command_response_code; 83 uint16_t max_residual_size; 84 uint8_t fragment_id; 85 uint8_t reason_code; 86 uint8_t reason_code_explanation; 87 uint8_t vendor_specific; 88 } ql_ct_iu_preamble_t; 89 90 #define GS_TYPE_DIR_SERVER 0xFC 91 92 /* 93 * Link Status Counts structure 94 * 95 * Counts are BIG ENDIAN 96 */ 97 typedef struct ql_link_stats { 98 uint32_t link_fail_cnt; 99 uint32_t sync_loss_cnt; 100 uint32_t signal_loss_cnt; 101 uint32_t prot_err_cnt; /* Primitive seq protocol errors */ 102 uint32_t inv_xmit_cnt; /* Invalid transmission word count */ 103 uint32_t inv_crc_cnt; /* Invalid CRC count */ 104 } ql_link_stats_t; 105 106 /* 107 * Report LUN definitions. 108 */ 109 typedef struct ql_rpt_hdr { 110 uint32_t len; 111 uint32_t rsrv; 112 } ql_rpt_hdr_t; 113 114 typedef struct ql_rpt_lun { 115 struct { 116 uint8_t b : 6; 117 uint8_t address_method : 2; 118 } msb; 119 uint8_t lsb; 120 uint8_t unused[6]; 121 } ql_rpt_lun_t; 122 123 typedef struct ql_rpt_lun_lst { 124 ql_rpt_hdr_t hdr; 125 ql_rpt_lun_t lst[MAX_LUNS]; 126 } ql_rpt_lun_lst_t; 127 128 #define INQ_DATA_SIZE 8 129 130 /* 131 * Flash definitions. 132 */ 133 typedef struct ql_flash_info { 134 uint32_t type; /* flash type */ 135 uint32_t size; /* length in bytes of flash */ 136 uint32_t sec_mask; /* sector number mask */ 137 uint8_t man_id; /* flash chip manufacturer id */ 138 uint8_t id; /* flash chip id */ 139 uint8_t cap; /* flash chip capacity */ 140 } ql_flash_info_t; 141 142 /* 143 * Flash Description Table 144 */ 145 #define FLASH_DESC_VERSION 1 146 #define FLASH_DESC_VAILD 0x44494C51 /* "QLID" */ 147 typedef struct flash_desc { 148 uint32_t flash_valid; 149 uint16_t flash_version; 150 uint16_t flash_len; 151 uint16_t flash_checksum; 152 uint16_t flash_unused; 153 uint8_t flash_model[16]; 154 uint16_t flash_manuf; 155 uint16_t flash_id; 156 uint8_t flash_flag; 157 uint8_t erase_cmd; 158 uint8_t alt_erase_cmd; 159 uint8_t write_enable_cmd; 160 uint8_t write_enable_bits; 161 uint8_t write_statusreg_cmd; 162 uint8_t unprotect_sector_cmd; 163 uint8_t read_manuf_cmd; 164 uint32_t block_size; 165 uint32_t alt_block_size; 166 uint32_t flash_size; 167 uint32_t write_enable_data; 168 uint8_t readid_address_len; 169 uint8_t write_disable_bits; 170 uint8_t read_device_id_len; 171 uint8_t chip_erase_cmd; 172 uint16_t read_timeout; 173 uint8_t protect_sector_cmd; 174 uint8_t exp_reserved[65]; 175 } flash_desc_t; 176 177 /* flash manufacturer id's */ 178 #define AMD_FLASH 0x01 /* AMD / Spansion */ 179 #define ST_FLASH 0x20 /* ST Electronics */ 180 #define SST_FLASH 0xbf /* SST Electronics */ 181 #define MXIC_FLASH 0xc2 /* Macronix (MXIC) */ 182 #define ATMEL_FLASH 0x1f /* Atmel (AT26DF081A) */ 183 #define WINBOND_FLASH 0xef /* Winbond (W25X16) */ 184 #define INTEL_FLASH 0x89 /* Intel (QB25F016S33B8) */ 185 186 /* flash id defines */ 187 #define AMD_FLASHID_128K 0x6e /* 128k AMD flash chip */ 188 #define AMD_FLASHID_512K 0x4f /* 512k AMD flash chip */ 189 #define AMD_FLASHID_512Kt 0xb9 /* 512k AMD flash chip - top boot blk */ 190 #define AMD_FLASHID_512Kb 0xba /* 512k AMD flash chip - btm boot blk */ 191 #define AMD_FLASHID_1024K 0x38 /* 1 MB AMD flash chip */ 192 #define ST_FLASHID_128K 0x23 /* 128k ST flash chip */ 193 #define ST_FLASHID_512K 0xe3 /* 512k ST flash chip */ 194 #define ST_FLASHID_M25PXX 0x20 /* M25Pxx ST flash chip */ 195 #define SST_FLASHID_128K 0xd5 /* 128k SST flash chip */ 196 #define SST_FLASHID_1024K 0xd8 /* 1 MB SST flash chip */ 197 #define SST_FLASHID_1024K_A 0x80 /* 1 MB SST 25LF080A flash chip */ 198 #define SST_FLASHID_1024K_B 0x8e /* 1 MB SST 25VF080B flash chip */ 199 #define SST_FLASHID_2048K 0x25 /* 2 MB SST 25VF016B flash chip */ 200 #define MXIC_FLASHID_512K 0x4f /* 512k MXIC flash chip */ 201 #define MXIC_FLASHID_1024K 0x38 /* 1 MB MXIC flash chip */ 202 #define MXIC_FLASHID_25LXX 0x20 /* 25Lxx MXIC flash chip */ 203 #define ATMEL_FLASHID_1024K 0x45 /* 1 MB ATMEL flash chip */ 204 #define SPAN_FLASHID_2048K 0x02 /* 2 MB Spansion flash chip */ 205 #define WINBOND_FLASHID 0x30 /* Winbond W25Xxx flash chip */ 206 #define INTEL_FLASHID 0x89 /* Intel QB25F016S33B8 flash chip */ 207 208 /* flash type defines */ 209 #define FLASH128 BIT_0 210 #define FLASH512 BIT_1 211 #define FLASH512S BIT_2 212 #define FLASH1024 BIT_3 213 #define FLASH2048 BIT_4 214 #define FLASH4096 BIT_5 215 #define FLASH8192 BIT_6 216 #define FLASH_PAGE BIT_31 217 #define FLASH_LEGACY (FLASH128 | FLASH512S) 218 219 typedef struct ql_ledstate { 220 uint32_t BeaconState; 221 uint32_t LEDflags; 222 uint32_t flags; 223 } ql_ledstate_t; 224 225 /* 226 * ledstate flags definitions 227 */ 228 #define LED_ACTIVE BIT_0 229 230 /* 231 * ledstate BeaconState definitions 232 */ 233 #define BEACON_OFF 0 234 #define BEACON_ON BIT_0 235 236 /* 237 * ledstate LEDflags definitions 238 */ 239 #define LED_ALL_OFF 0 240 #define LED_RED BIT_0 241 #define LED_GREEN BIT_6 242 #define LED_AMBER BIT_7 243 #define LED_MASK (LED_AMBER | LED_GREEN | LED_RED) 244 245 /* 246 * 24xx ledstate LEDflags definitions 247 */ 248 #define LED_MASK_UPDATE_24 (BIT_20 | BIT_19 | BIT_18) 249 #define LED_YELLOW_24 BIT_2 250 #define LED_GREEN_24 BIT_3 251 #define LED_AMBER_24 BIT_4 252 #define LED_MASK_COLORS_24 (LED_AMBER_24 | LED_GREEN_24 | LED_YELLOW_24) 253 254 typedef struct { 255 uint8_t signature[2]; 256 uint8_t reserved[0x16]; 257 uint8_t dataoffset[2]; 258 uint8_t pad[6]; 259 } pci_header_t; 260 261 typedef struct { 262 uint8_t signature[4]; 263 uint8_t vid[2]; 264 uint8_t did[2]; 265 uint8_t reserved0[2]; 266 uint8_t pcidatalen[2]; 267 uint8_t pcidatarev; 268 uint8_t classcode[3]; 269 uint8_t imagelength[2]; /* In sectors */ 270 uint8_t revisionlevel[2]; 271 uint8_t codetype; 272 uint8_t indicator; 273 uint8_t reserved1[2]; 274 uint8_t pad[8]; 275 } pci_data_t; 276 277 #define PCI_HEADER0 0x55 278 #define PCI_HEADER1 0xAA 279 #define PCI_DATASIG "PCIR" 280 #define PCI_SECTOR_SIZE 0x200 281 #define PCI_CODE_X86PC 0 282 #define PCI_CODE_FCODE 1 283 #define PCI_CODE_HPPA 2 284 #define PCI_CODE_EFI 3 285 #define PCI_CODE_FW 0xfe 286 #define PCI_IND_LAST_IMAGE 0x80 287 #define SBUS_CODE_FCODE 0xf1 288 289 typedef struct ql_fcache { 290 struct ql_fcache *next; 291 uint32_t type; 292 int8_t verstr[FCHBA_OPTION_ROM_VERSION_LEN]; 293 uint32_t buflen; 294 uint8_t *buf; 295 } ql_fcache_t; 296 297 /* fcache types */ 298 #define FTYPE_UNKNOWN 0 299 #define FTYPE_FCODE BIT_0 300 #define FTYPE_BIOS BIT_1 301 #define FTYPE_EFI BIT_2 302 #define FTYPE_FW BIT_3 303 #define FTYPE_HPPA BIT_4 304 305 #define FBUFSIZE 100 306 307 /* 308 * Flash Layout Table definitions. 309 */ 310 typedef struct ql_flash_layout_pointer { 311 uint8_t sig[4]; 312 uint8_t addr[4]; 313 uint8_t version; 314 uint8_t reserved[5]; 315 uint8_t checksum[2]; 316 } ql_flt_ptr_t; 317 318 typedef struct ql_flash_layout_header { 319 uint8_t version[2]; 320 uint8_t len[2]; 321 uint8_t checksum[2]; 322 uint8_t reserved[2]; 323 } ql_flt_hdr_t; 324 325 typedef struct ql_flash_layout_region { 326 uint8_t region; 327 uint8_t reserved; 328 uint8_t attribute; 329 uint8_t reserved_1; 330 uint8_t size[4]; 331 uint8_t beg_addr[4]; 332 uint8_t end_addr[4]; 333 } ql_flt_region_t; 334 335 #define FLASH_FW_REGION 0x01 336 #define FLASH_VPD_0_REGION 0x14 337 #define FLASH_NVRAM_0_REGION 0x15 338 #define FLASH_VPD_1_REGION 0x16 339 #define FLASH_NVRAM_1_REGION 0x17 340 #define FLASH_DESC_TABLE_REGION 0x1A 341 #define FLASH_ERROR_LOG_0_REGION 0x1D 342 #define FLASH_ERROR_LOG_1_REGION 0x1F 343 #define FLASH_GOLDEN_FW_REGION 0x2F 344 345 #define FLASH_LAYOUT_TABLE_SIZE 4096 346 347 /* 348 * Per instance XIOCTL context defintions. 349 */ 350 typedef struct ql_xioctl { 351 /* Driver context */ 352 flash_desc_t fdesc; 353 354 /* Adapter I/O statistics */ 355 uint32_t ControllerErrorCount; 356 uint32_t DeviceErrorCount; 357 uint32_t TotalLipResets; 358 uint32_t TotalInterrupts; 359 360 uint64_t BytesRequested; 361 uint64_t IosRequested; 362 363 /* SNIA stat counters */ 364 int64_t IOInputRequests; 365 int64_t IOOutputRequests; 366 int64_t IOControlRequests; 367 int64_t IOOutputMByteCnt; /* # of mb's */ 368 int64_t IOInputMByteCnt; /* # of mb's */ 369 370 /* SNIA intermediate (less than 1mb) counters */ 371 int64_t IOOutputByteCnt; 372 int64_t IOInputByteCnt; 373 374 /* Adapter LED state */ 375 ql_ledstate_t ledstate; 376 377 /* Async event context */ 378 void *aen_tracking_queue; 379 uint8_t aen_q_head; 380 uint8_t aen_q_tail; 381 382 uint32_t flags; 383 } ql_xioctl_t; 384 385 /* 386 * ql adapter flag defintions. 387 */ 388 #define QL_AEN_TRACKING_ENABLE BIT_0 389 #define QL_MGMT_SERVER_LOGIN BIT_1 390 391 /* 392 * Global Data in ql_xioctl.c source file. 393 */ 394 395 /* 396 * Global Function Prototypes in ql_xioctl.c source file. 397 */ 398 int ql_alloc_xioctl_resource(ql_adapter_state_t *); 399 void ql_free_xioctl_resource(ql_adapter_state_t *); 400 int ql_xioctl(ql_adapter_state_t *, int, intptr_t, int, cred_t *, int *); 401 void ql_enqueue_aen(ql_adapter_state_t *, uint16_t, void *); 402 int ql_setup_fcache(ql_adapter_state_t *); 403 void ql_blink_led(ql_adapter_state_t *); 404 void ql_fcache_rel(ql_fcache_t *); 405 ql_fcache_t *ql_get_fbuf(ql_fcache_t *, uint32_t); 406 int ql_dump_fcode(ql_adapter_state_t *, uint8_t *, uint32_t, uint32_t); 407 int ql_pci_dump(ql_adapter_state_t *, uint32_t *, uint32_t, int); 408 int ql_load_fcode(ql_adapter_state_t *, uint8_t *, uint32_t, uint32_t); 409 410 #ifdef __cplusplus 411 } 412 #endif 413 414 #endif /* _QL_XIOCTL_H */ 415