1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* Copyright 2009 QLogic Corporation */ 23 24 /* 25 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms. 27 */ 28 29 #ifndef _QL_MBX_H 30 #define _QL_MBX_H 31 32 /* 33 * ISP2xxx Solaris Fibre Channel Adapter (FCA) driver header file. 34 * 35 * *********************************************************************** 36 * * ** 37 * * NOTICE ** 38 * * COPYRIGHT (C) 1996-2009 QLOGIC CORPORATION ** 39 * * ALL RIGHTS RESERVED ** 40 * * ** 41 * *********************************************************************** 42 * 43 */ 44 45 #ifdef __cplusplus 46 extern "C" { 47 #endif 48 49 /* 50 * ISP mailbox Self-Test status codes 51 */ 52 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */ 53 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */ 54 #define MBS_BUSY 4 /* Busy. */ 55 56 /* 57 * ISP mailbox command complete status codes 58 */ 59 #define MBS_COMMAND_COMPLETE 0x4000 60 #define MBS_INVALID_COMMAND 0x4001 61 #define MBS_HOST_INTERFACE_ERROR 0x4002 62 #define MBS_TEST_FAILED 0x4003 63 #define MBS_POST_ERROR 0x4004 64 #define MBS_COMMAND_ERROR 0x4005 65 #define MBS_COMMAND_PARAMETER_ERROR 0x4006 66 #define MBS_PORT_ID_USED 0x4007 67 #define MBS_LOOP_ID_USED 0x4008 68 #define MBS_ALL_IDS_IN_USE 0x4009 69 #define MBS_NOT_LOGGED_IN 0x400A 70 #define MBS_LOOP_DOWN 0x400B 71 #define MBS_LOOP_BACK_ERROR 0x400C 72 #define MBS_CHECKSUM_ERROR 0x4010 73 74 /* 75 * Sub-error Codes for Mailbox Command Completion Status Code 4005h 76 */ 77 #define MBSS_NO_LINK 0x0001 78 #define MBSS_IOCB_ALLOC_ERR 0x0002 79 #define MBSS_ECB_ALLOC_ERR 0x0003 80 #define MBSS_CMD_FAILURE 0x0004 81 #define MBSS_NO_FABRIC 0x0005 82 #define MBSS_FIRMWARE_NOT_RDY 0x0007 83 #define MBSS_INITIATOR_DISABLED 0x0008 84 #define MBSS_NOT_LOGGED_IN 0x0009 85 #define MBSS_PARTIAL_DATA_XFER 0x000A 86 #define MBSS_TOPOLOGY_ERR 0x0016 87 #define MBSS_CHIP_RESET_NEEDED 0x0017 88 #define MBSS_MULTIPLE_OPEN_EXCH 0x0018 89 #define MBSS_IOCB_COUNT_ERR 0x0019 90 #define MBSS_CMD_AFTER_FW_INIT_ERR 0x001A 91 #define MBSS_NO_VIRTUAL_PORT_ID 0x001B 92 #define MBSS_INVALID_FCF_INDEX 0x0022 93 #define MBSS_MPI_PROCESSOR_ERR 0x0023 94 #define MBSS_SEMAPHORE_ERR 0x0024 95 #define MBSS_RANGE_ERR 0x0025 96 #define MBSS_TRANSFER_SIZE_TO_LARGE 0x0026 97 #define MBSS_CHECKSUM_ERR 0x0027 98 #define MBSS_CONFIGURATION_ERR 0x0028 99 100 /* 101 * ISP mailbox asynchronous event status codes 102 */ 103 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */ 104 #define MBA_RESET 0x8001 /* Reset Detected. */ 105 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */ 106 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */ 107 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */ 108 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */ 109 #define MBA_MENLO_ALERT 0x800f /* Menlo Alert Notification. */ 110 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */ 111 /* occurred. */ 112 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */ 113 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */ 114 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */ 115 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */ 116 #define MBA_RSCN_UPDATE 0x8015 /* State Change Registration. */ 117 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */ 118 #define MBA_LIP_ERROR 0x8017 /* Loop initialization errors. */ 119 #define MBA_SECURITY_UPDATE 0x801B /* FC-SP security update. */ 120 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */ 121 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */ 122 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */ 123 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */ 124 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */ 125 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */ 126 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */ 127 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */ 128 /* used. */ 129 #define MBA_ERROR_LOGGING_DISABLED 0x8029 /* Error Logging Disabled. */ 130 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */ 131 #define MBA_DCBX_COMPLETED 0x8030 /* DCBX completed. */ 132 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */ 133 #define MBA_FCF_CONFIG_ERROR 0x8031 /* FCF configuration error. */ 134 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */ 135 #define MBA_DCBX_PARAM_CHANGED 0x8032 /* DCBX parameters changed. */ 136 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */ 137 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */ 138 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */ 139 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */ 140 #define MBA_ZIO_UPDATE 0x8040 /* ZIO response queue update. */ 141 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */ 142 #define MBA_PORT_BYPASS_CHANGED 0x8043 /* Crystal+ port#0 bypass transition */ 143 #define MBA_RECEIVE_ERROR 0x8048 /* Receive Error */ 144 #define MBA_LS_RJT_SENT 0x8049 /* LS_RJT response sent */ 145 #define MBA_FW_RESTART_COMP 0x8060 /* Firmware Restart Complete. */ 146 #define MBA_IDC_COMPLETE 0x8100 /* Inter-driver communication */ 147 /* complete. */ 148 #define MBA_IDC_NOTIFICATION 0x8101 /* Inter-driver communication */ 149 /* notification. */ 150 #define MBA_IDC_TIME_EXTENDED 0x8102 /* Inter-driver communication */ 151 /* time extended. */ 152 153 /* Driver defined. */ 154 #define MBA_CMPLT_1_32BIT 0x9000 /* Completion 1 32bit IOSB. */ 155 156 /* 157 * Mailbox 23 event codes 158 */ 159 #define MBX23_MBX_OR_ASYNC_EVENT 0x0 160 #define MBX23_RESPONSE_QUEUE_UPDATE 0x1 161 #define MBX23_SCSI_COMPLETION 0x2 162 163 /* 164 * System Error event (0x8002) defines 165 */ 166 #define SE_MPI_RISC BIT_2 167 #define SE_NIC_1 BIT_1 168 #define SE_NIC_2 BIT_0 169 170 /* 171 * Menlo alert event defines 172 */ 173 #define MLA_PANIC_RECOVERY 0x1 174 #define MLA_LOGIN_OPERATIONAL_FW 0x2 175 #define MLA_LOGIN_DIAGNOSTIC_FW 0x3 176 #define MLA_LOGIN_GOLDEN_FW 0x4 177 #define MLA_REJECT_RESPONSE 0x5 178 179 /* 180 * ISP mailbox commands 181 */ 182 #define MBC_LOAD_RAM 1 /* Load RAM. */ 183 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */ 184 #define MBC_DUMP_RAM 3 /* Dump RAM. */ 185 #define MBC_WRITE_RAM_WORD 4 /* Write RAM word. */ 186 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */ 187 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */ 188 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */ 189 #define MBC_ABOUT_FIRMWARE 8 /* About Firmware. */ 190 #define MBC_DUMP_RISC_RAM 0xa /* Dump RISC RAM command. */ 191 #define MBC_LOAD_RAM_EXTENDED 0xb /* Load RAM extended. */ 192 #define MBC_DUMP_RAM_EXTENDED 0xc /* Dump RAM extended. */ 193 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */ 194 #define MBC_SERDES_TRANSMIT_PARAMETERS 0x10 /* Serdes Xmit Parameters */ 195 #define MBC_2300_EXECUTE_IOCB 0x12 /* ISP2300 Execute IOCB cmd */ 196 #define MBC_GET_IO_STATUS 0x12 /* ISP2422 Get I/O Status */ 197 #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware */ 198 #define MBC_ABORT_COMMAND_IOCB 0x15 /* Abort IOCB command. */ 199 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */ 200 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */ 201 #define MBC_RESET 0x18 /* Target reset. */ 202 #define MBC_XMIT_PARM 0x19 /* Change default xmit parms */ 203 #define MBC_PORT_PARAM 0x1a /* Get/set port speed parms */ 204 #define MBC_GET_ID 0x20 /* Get loop id of ISP2200. */ 205 #define MBC_GET_TIMEOUT_PARAMETERS 0x22 /* Get Timeout Parameters. */ 206 #define MBC_TRACE_CONTROL 0x27 /* Trace control. */ 207 #define MBC_GET_FIRMWARE_OPTIONS 0x28 /* Get firmware options */ 208 #define MBC_READ_SFP 0x31 /* Read SFP. */ 209 #define MBC_SET_FIRMWARE_OPTIONS 0x38 /* set firmware options */ 210 #define MBC_RESET_MENLO 0x3a /* Reset Menlo. */ 211 #define MBC_RESTART_MPI 0x3d /* Restart MPI. */ 212 #define MBC_FLASH_ACCESS 0x3e /* Flash Access Control */ 213 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */ 214 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */ 215 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */ 216 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */ 217 #define MBC_ECHO 0x44 /* ELS ECHO */ 218 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */ 219 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */ 220 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get Port Database + login */ 221 #define MBC_INITIALIZE_MULTI_ID_FW 0x48 /* Initialize multi-id fw */ 222 #define MBC_GET_DCBX_PARAMS 0x51 /* Get DCBX parameters */ 223 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */ 224 #define MBC_EXECUTE_IOCB 0x54 /* 64 Bit Execute IOCB cmd. */ 225 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */ 226 #define MBC_SET_PARAMETERS 0x59 /* Set RNID parameters */ 227 #define MBC_GET_PARAMETERS 0x5a /* Get RNID parameters */ 228 #define MBC_DATA_RATE 0x5d /* Data Rate */ 229 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */ 230 #define MBC_INITIATE_LIP 0x62 /* Initiate LIP */ 231 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */ 232 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */ 233 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */ 234 #define MBC_TARGET_RESET 0x66 /* Target Reset. */ 235 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */ 236 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */ 237 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */ 238 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */ 239 #define MBC_GET_LINK_STATUS 0x6b /* Get Link Status. */ 240 #define MBC_LIP_RESET 0x6c /* LIP reset. */ 241 #define MBC_GET_STATUS_COUNTS 0x6d /* Get Link Statistics and */ 242 /* Private Data Counts */ 243 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */ 244 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */ 245 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */ 246 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */ 247 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */ 248 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */ 249 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list */ 250 #define MBC_INITIALIZE_IP 0x77 /* Initialize IP */ 251 #define MBC_SEND_FARP_REQ_COMMAND 0x78 /* FARP request. */ 252 #define MBC_UNLOAD_IP 0x79 /* Unload IP */ 253 #define MBC_GET_XGMAC_STATS 0x7a /* Get XGMAC Statistics. */ 254 #define MBC_GET_ID_LIST 0x7c /* Get port ID list. */ 255 #define MBC_SEND_LFA_COMMAND 0x7d /* Send Loop Fabric Address */ 256 #define MBC_LUN_RESET 0x7e /* Send Task mgmt LUN reset */ 257 #define MBC_IDC_REQUEST 0x100 /* IDC request */ 258 #define MBC_IDC_ACK 0x101 /* IDC acknowledge */ 259 #define MBC_IDC_TIME_EXTEND 0x102 /* IDC extend time */ 260 #define MBC_PORT_RESET 0x120 /* Port Reset */ 261 #define MBC_SET_PORT_CONFIG 0x122 /* Set port configuration */ 262 #define MBC_GET_PORT_CONFIG 0x123 /* Get port configuration */ 263 264 /* 265 * Mbc 0x100 (IDC request) 266 */ 267 /* Timeout Value */ 268 #define IDC_TIMEOUT_POS 8 269 #define IDC_TIMEOUT_MASK (BIT_11 | BIT_10 | BIT_9 | BIT_8) 270 271 /* Function Destination Selector */ 272 #define IDC_FUNC_DST_MASK (BIT_5 | BIT_4) 273 #define IDC_FUNC_DST_MBX3 0 274 #define IDC_FUNC_DST_SP 0x10 275 276 /* Function Source */ 277 #define IDC_FUNC_SRC_MASK (BIT_3 | BIT_2 | BIT_1 | BIT_0) 278 279 /* Information opcode */ 280 #define IDC_OPC_DRV_START 0x100 281 #define IDC_OPC_FLASH_ACC 0x101 282 #define IDC_OPC_RESTART_MPI 0x102 283 284 /* Function Destination Mask */ 285 #define IDC_FUNC_3 BIT_3 286 #define IDC_FUNC_2 BIT_2 287 #define IDC_FUNC_1 BIT_1 288 #define IDC_FUNC_0 BIT_0 289 #define IDC_FC_FUNC (BIT_3 | BIT_2) 290 #define IDC_NIC_FUNC (BIT_1 | BIT_0) 291 #define IDC_ALL_FUNC (IDC_FC_FUNC | IDC_NIC_FUNC) 292 293 /* Requestor Id Function Type */ 294 #define IDC_RIT_MASK (BIT_6 | BIT_5 | BIT_4) 295 #define IDC_RIT_NIC 0 296 #define IDC_RIT_FC 0x10 297 298 /* Requestor Id Originator */ 299 #define IDC_RIO_MASK (BIT_3 | BIT_2 | BIT_1 | BIT_0) 300 #define IDC_RIO_DRV 0 301 #define IDC_RIO_FW 1 302 #define IDC_RIO_MPI 2 303 #define IDC_RIO_DRV_APP 3 304 #define IDC_RIO_QL_APP 4 305 #define IDC_RIO_QL_MFG 5 306 #define IDC_RIO_OTH_APP 6 307 308 /* Region Code */ 309 #define IDC_RC_POS 8 310 #define IDC_RC_MASK 0xFF00 311 312 /* Region Size in 64k blocks */ 313 #define IDC_RS_POS 0 314 #define IDC_RS_MASK 0xFF 315 316 /* Message Source */ 317 #define IDC_MSG_QLGC BIT_15 318 319 /* Message Subcode */ 320 #define IDC_MS_MASK (BIT_7 | BIT_6 | BIT_5 | BIT_4) 321 #define IDC_MS_NONE 0x00 322 #define IDC_MS_READ 0x10 323 #define IDC_MS_WRITE 0x20 324 #define IDC_MS_ERASE 0x30 325 326 /* Marker */ 327 #define IDC_MM_MASK (BIT_3 | BIT_2 | BIT_1 | BIT_0) 328 #define IDC_MM_NONE 0x0 329 #define IDC_MM_BEG 0x1 330 #define IDC_MM_END 0x2 331 #define IDC_MM_WIP 0x3 332 #define IDC_MM_ABORT 0x4 333 334 /* 335 * Mbc 0x3e (Flash Access Control) 336 */ 337 #define FAC_FORCE_SEMA_LOCK BIT_15 338 #define FAC_APPL_ID BIT_14 339 #define FAC_WRT_PROTECT 0 340 #define FAC_WRT_ENABLE 1 341 #define FAC_ERASE_SECTOR 2 342 #define FAC_SEMA_LOCK 3 343 #define FAC_SEMA_UNLOCK 4 344 #define FAC_GET_SECTOR_SIZE 5 345 #define FAC_ADDR_MASK 0x3fff 346 347 /* 348 * Mbc 20h (Get ID) returns the switch capabilities in mailbox7. 349 * The extra bits were added with 4.00.28 MID firmware. 350 */ 351 #define GID_TOP_NL_PORT 0 352 #define GID_TOP_FL_PORT 1 353 #define GID_TOP_N_PORT 2 354 #define GID_TOP_F_PORT 3 355 #define GID_TOP_N_PORT_NO_TGT 4 356 357 #define GID_FP_IN_ORDER BIT_8 358 #define GID_FP_MAC_ADDR BIT_9 359 #define GID_FP_NPIV_SUPPORT BIT_10 /* implies FDISC support */ 360 #define GID_FP_VF_SUPPORT BIT_12 361 #define GID_FP_SP_SUPPORT BIT_13 362 363 /* 364 * Driver Mailbox command definitions. 365 */ 366 #define MAILBOX_TOV 30 /* Default Timeout value. */ 367 368 /* Mailbox command parameter structure definition. */ 369 typedef struct mbx_cmd { 370 uint32_t out_mb; /* Outgoing from driver */ 371 uint32_t in_mb; /* Incomming from RISC */ 372 uint16_t mb[MAX_MBOX_COUNT]; 373 clock_t timeout; /* Timeout in seconds. */ 374 } mbx_cmd_t; 375 376 /* Returned Mailbox registers. */ 377 typedef struct ql_mbx_data { 378 uint16_t mb[MAX_MBOX_COUNT]; 379 } ql_mbx_data_t; 380 381 /* Mailbox bit definitions for out_mb and in_mb */ 382 #define MBX_29 BIT_29 383 #define MBX_28 BIT_28 384 #define MBX_27 BIT_27 385 #define MBX_26 BIT_26 386 #define MBX_25 BIT_25 387 #define MBX_24 BIT_24 388 #define MBX_23 BIT_23 389 #define MBX_22 BIT_22 390 #define MBX_21 BIT_21 391 #define MBX_20 BIT_20 392 #define MBX_19 BIT_19 393 #define MBX_18 BIT_18 394 #define MBX_17 BIT_17 395 #define MBX_16 BIT_16 396 #define MBX_15 BIT_15 397 #define MBX_14 BIT_14 398 #define MBX_13 BIT_13 399 #define MBX_12 BIT_12 400 #define MBX_11 BIT_11 401 #define MBX_10 BIT_10 402 #define MBX_9 BIT_9 403 #define MBX_8 BIT_8 404 #define MBX_7 BIT_7 405 #define MBX_6 BIT_6 406 #define MBX_5 BIT_5 407 #define MBX_4 BIT_4 408 #define MBX_3 BIT_3 409 #define MBX_2 BIT_2 410 #define MBX_1 BIT_1 411 #define MBX_0 BIT_0 412 413 #define MBX_0_THRU_1 MBX_0|MBX_1 414 #define MBX_0_THRU_2 MBX_0_THRU_1|MBX_2 415 #define MBX_0_THRU_3 MBX_0_THRU_2|MBX_3 416 #define MBX_0_THRU_4 MBX_0_THRU_3|MBX_4 417 #define MBX_0_THRU_5 MBX_0_THRU_4|MBX_5 418 #define MBX_0_THRU_6 MBX_0_THRU_5|MBX_6 419 #define MBX_0_THRU_7 MBX_0_THRU_6|MBX_7 420 #define MBX_0_THRU_8 MBX_0_THRU_7|MBX_8 421 #define MBX_0_THRU_9 MBX_0_THRU_8|MBX_9 422 #define MBX_0_THRU_10 MBX_0_THRU_9|MBX_10 423 424 /* 425 * Firmware state codes from get firmware state mailbox command 426 */ 427 #define FSTATE_CONFIG_WAIT 0 428 #define FSTATE_WAIT_AL_PA 1 429 #define FSTATE_WAIT_LOGIN 2 430 #define FSTATE_READY 3 431 #define FSTATE_LOSS_SYNC 4 432 #define FSTATE_ERROR 5 433 #define FSTATE_NON_PART 7 434 435 /* 436 * Firmware options 1, 2, 3. 437 */ 438 #define FO1_AE_ON_LIPF8 BIT_0 439 #define FO1_AE_ALL_LIP_RESET BIT_1 440 #define FO1_CTIO_RETRY BIT_3 441 #define FO1_DISABLE_LIP_F7_SW BIT_4 442 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5 443 #define FO1_DISABLE_GPIO BIT_6 444 #define FO1_AE_AUTO_BYPASS BIT_9 445 #define FO1_ENABLE_PURE_IOCB BIT_10 446 #define FO1_AE_PLOGI_RJT BIT_11 447 #define FO1_AE_IMMEDIATE_NOTIFY_IOCB BIT_11 448 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12 449 #define FO1_AE_QUEUE_FULL BIT_13 450 #define FO1_POST_NOTIFY_ACK_IOCB_2_ATIO BIT_13 451 #define FO1_POST_NOTIFY_ACK_IOCB BIT_14 452 453 #define FO2_ENABLE_SELECTIVE_CLASS_2 BIT_5 454 #define FO2_REV_LOOPBACK BIT_1 455 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0 456 457 #define FO3_NO_ABORT_IO_ON_LINK_DOWN BIT_14 458 #define FO3_HOLD_STS_FOR_ABTS_RSP BIT_12 459 #define FO3_STARTUP_OPTS_VALID BIT_5 460 #define FO3_SEND_N2N_PRLI BIT_4 461 #define FO3_AE_RND_ERROR BIT_1 462 #define FO3_ENABLE_EMERG_IOCB BIT_0 463 464 #define FO13_LESB_NO_RESET BIT_0 465 466 /* 467 * f/w trace opcodes - mailbox 1(bits 7-0) 468 */ 469 #define FTO_INSERT_TIME_STAMP 1 470 #define FTO_RESERVED_2 2 471 #define FTO_RESERVED_3 3 472 #define FTO_EXT_TRACE_ENABLE 4 473 #define FTO_EXT_TRACE_DISABLE 5 474 #define FTO_FCE_TRACE_ENABLE 8 475 #define FTO_FCE_TRACE_DISABLE 9 476 #define FTO_FCEMAXTRACEBUF 0x840 /* max frame size */ 477 478 /* 479 * fw version 1 attributes defines from firmware version mailbox command 480 */ 481 #define FWATTRIB_EF 0x7 482 #define FWATTRIB_TP 0x17 483 #define FWATTRIB_IP 0x37 484 #define FWATTRIB_TPX 0x117 485 #define FWATTRIB_IPX 0x137 486 #define FWATTRIB_FL 0x217 487 #define FWATTRIB_FPX 0x317 488 489 /* 490 * fw version 2 attributes defines 491 */ 492 #define FWATTRIB2_CLASS2 BIT_0 493 #define FWATTRIB2_IP BIT_1 494 #define FWATTRIB2_MID BIT_2 495 #define FWATTRIB2_SB2 BIT_3 496 #define FWATTRIB2_T10_CRC BIT_4 497 #define FWATTRIB2_VI BIT_5 498 #define FWATTRIB2_MQUE BIT_6 499 #define FWATTRIB2_FCOE BIT_11 500 #define FWATTRIB2_EX_REL BIT_13 501 502 /* 503 * Diagnostic ELS ECHO parameter structure definition. 504 */ 505 typedef struct echo { 506 uint16_t options; 507 uint32_t transfer_count; 508 ddi_dma_cookie_t transfer_data_address; 509 ddi_dma_cookie_t receive_data_address; 510 } echo_t; 511 512 /* 513 * LFA command structure. 514 */ 515 #define LFA_PAYLOAD_SIZE 38 516 typedef struct lfa_cmd { 517 uint8_t resp_buffer_length[2]; /* length in 16bit words. */ 518 uint8_t reserved[2]; 519 uint8_t resp_buffer_address[8]; 520 uint8_t subcommand_length[2]; /* length in 16bit words. */ 521 uint8_t reserved_1[2]; 522 uint8_t addr[4]; 523 uint8_t subcommand[2]; 524 uint8_t payload[LFA_PAYLOAD_SIZE]; 525 } lfa_cmd_t; 526 527 /* Define size of Loop Position Map. */ 528 #define LOOP_POSITION_MAP_SIZE 128 /* bytes */ 529 530 /* 531 * Port Database structure definition 532 * Little endian except where noted. 533 */ 534 #define PORT_DATABASE_SIZE 128 /* bytes */ 535 typedef struct port_database_23 { 536 uint8_t options; 537 uint8_t control; 538 uint8_t master_state; 539 uint8_t slave_state; 540 uint8_t hard_address[3]; 541 uint8_t rsvd; 542 uint32_t port_id; 543 uint8_t node_name[8]; /* Big endian. */ 544 uint8_t port_name[8]; /* Big endian. */ 545 uint16_t execution_throttle; 546 uint16_t execution_count; 547 uint8_t reset_count; 548 uint8_t reserved_2; 549 uint16_t resource_allocation; 550 uint16_t current_allocation; 551 uint16_t queue_head; 552 uint16_t queue_tail; 553 uint16_t transmit_execution_list_next; 554 uint16_t transmit_execution_list_previous; 555 uint16_t common_features; 556 uint16_t total_concurrent_sequences; 557 uint16_t RO_by_information_category; 558 uint8_t recipient; 559 uint8_t initiator; 560 uint16_t receive_data_size; 561 uint16_t concurrent_sequences; 562 uint16_t open_sequences_per_exchange; 563 uint16_t lun_abort_flags; 564 uint16_t lun_stop_flags; 565 uint16_t stop_queue_head; 566 uint16_t stop_queue_tail; 567 uint16_t port_retry_timer; 568 uint16_t next_sequence_id; 569 uint16_t frame_count; 570 uint16_t PRLI_payload_length; 571 uint16_t PRLI_service_parameter_word_0; /* Big endian */ 572 /* Bits 15-0 of word 0 */ 573 uint16_t PRLI_service_parameter_word_3; /* Big endian */ 574 /* Bits 15-0 of word 3 */ 575 uint16_t loop_id; 576 uint16_t extended_lun_info_list_pointer; 577 uint16_t extended_lun_stop_list_pointer; 578 } port_database_23_t; 579 580 typedef struct port_database_24 { 581 uint16_t flags; 582 uint8_t current_login_state; 583 uint8_t last_stable_login_state; 584 uint8_t hard_address[3]; 585 uint8_t rsvd; 586 uint8_t port_id[3]; 587 uint8_t sequence_id; 588 uint16_t port_retry_timer; 589 uint16_t n_port_handle; 590 uint16_t receive_data_size; 591 uint8_t reserved_1[2]; 592 uint16_t PRLI_service_parameter_word_0; /* Big endian */ 593 /* Bits 15-0 of word 0 */ 594 uint16_t PRLI_service_parameter_word_3; /* Big endian */ 595 /* Bits 15-0 of word 3 */ 596 uint8_t port_name[8]; /* Big endian. */ 597 uint8_t node_name[8]; /* Big endian. */ 598 uint8_t reserved_2[24]; 599 } port_database_24_t; 600 601 /* 602 * Port database slave/master/current_login/ast_stable_login states 603 */ 604 #define PD_STATE_DISCOVERY 0 605 #define PD_STATE_WAIT_DISCOVERY_ACK 1 606 #define PD_STATE_PORT_LOGIN 2 607 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3 608 #define PD_STATE_PLOGI_PENDING 3 609 #define PD_STATE_PROCESS_LOGIN 4 610 #define PD_STATE_PLOGI_COMPLETED 4 611 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5 612 #define PD_STATE_PRLI_PENDING 5 613 #define PD_STATE_PORT_LOGGED_IN 6 614 #define PD_STATE_PLOGI_PRLI_COMPLETED 6 615 #define PD_STATE_PORT_UNAVAILABLE 7 616 #define PD_STATE_PROCESS_LOGOUT 8 617 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9 618 #define PD_STATE_PORT_LOGOUT 10 619 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11 620 621 #define PD_PORT_LOGIN(tq) \ 622 (tq->master_state == PD_STATE_PROCESS_LOGIN || \ 623 tq->master_state == PD_STATE_PORT_LOGGED_IN || \ 624 tq->slave_state == PD_STATE_PROCESS_LOGIN || \ 625 tq->slave_state == PD_STATE_PORT_LOGGED_IN) 626 627 /* 628 * ql_login_lport() options 629 */ 630 #define LLF_NONE 0 631 #define LLF_PLOGI BIT_0 /* unconditional PLOGI */ 632 633 /* 634 * ql_login_fport() options 635 */ 636 #define LFF_NONE 0 637 #define LFF_NO_PLOGI BIT_0 638 #define LFF_NO_PRLI BIT_1 639 640 /* 641 * ql_get_port_database() options 642 */ 643 #define PDF_NONE 0 644 #define PDF_PLOGI BIT_0 645 #define PDF_ADISC BIT_1 646 647 /* 648 * ql_get_adapter_id() returned connection types 649 */ 650 #define CNX_LOOP_NO_FABRIC 0 651 #define CNX_FLPORT_IN_LOOP 1 652 #define CNX_NPORT_2_NPORT_P2P 2 653 #define CNX_FLPORT_P2P 3 654 #define CNX_NPORT_2_NPORT_NO_TGT_RSP 4 655 656 /* 657 * Global Data in ql_mbx.c source file. 658 */ 659 660 /* 661 * Global Function Prototypes in ql_mbx.c source file. 662 */ 663 int ql_initialize_ip(ql_adapter_state_t *); 664 int ql_shutdown_ip(ql_adapter_state_t *); 665 int ql_online_selftest(ql_adapter_state_t *); 666 int ql_loop_back(ql_adapter_state_t *, uint16_t, lbp_t *, uint32_t, uint32_t); 667 int ql_echo(ql_adapter_state_t *, uint16_t, echo_t *); 668 int ql_send_change_request(ql_adapter_state_t *, uint16_t); 669 int ql_send_lfa(ql_adapter_state_t *, lfa_cmd_t *); 670 int ql_clear_aca(ql_adapter_state_t *, ql_tgt_t *, uint16_t); 671 int ql_target_reset(ql_adapter_state_t *, ql_tgt_t *, uint16_t); 672 int ql_abort_target(ql_adapter_state_t *, ql_tgt_t *, uint16_t); 673 int ql_lun_reset(ql_adapter_state_t *, ql_tgt_t *, uint16_t); 674 int ql_clear_task_set(ql_adapter_state_t *, ql_tgt_t *, uint16_t); 675 int ql_abort_task_set(ql_adapter_state_t *, ql_tgt_t *, uint16_t); 676 int ql_loop_port_bypass(ql_adapter_state_t *, ql_tgt_t *); 677 int ql_loop_port_enable(ql_adapter_state_t *, ql_tgt_t *); 678 int ql_login_lport(ql_adapter_state_t *, ql_tgt_t *, uint16_t, uint16_t); 679 int ql_login_fport(ql_adapter_state_t *, ql_tgt_t *, uint16_t, uint16_t, 680 ql_mbx_data_t *); 681 int ql_logout_fabric_port(ql_adapter_state_t *, ql_tgt_t *); 682 int ql_log_iocb(ql_adapter_state_t *, ql_tgt_t *, uint16_t, uint16_t, 683 ql_mbx_data_t *); 684 int ql_get_port_database(ql_adapter_state_t *, ql_tgt_t *, uint8_t); 685 int ql_get_loop_position_map(ql_adapter_state_t *, size_t, caddr_t); 686 int ql_set_rnid_params(ql_adapter_state_t *, size_t, caddr_t); 687 int ql_send_rnid_els(ql_adapter_state_t *, uint16_t, uint8_t, size_t, caddr_t); 688 int ql_get_rnid_params(ql_adapter_state_t *, size_t, caddr_t); 689 int ql_get_link_status(ql_adapter_state_t *, uint16_t, size_t, caddr_t, 690 uint8_t); 691 int ql_get_status_counts(ql_adapter_state_t *, uint16_t, size_t, caddr_t, 692 uint8_t); 693 int ql_reset_link_status(ql_adapter_state_t *); 694 int ql_loop_reset(ql_adapter_state_t *); 695 int ql_initiate_lip(ql_adapter_state_t *); 696 int ql_full_login_lip(ql_adapter_state_t *); 697 int ql_lip_reset(ql_adapter_state_t *, uint16_t); 698 int ql_abort_command(ql_adapter_state_t *, ql_srb_t *); 699 int ql_verify_checksum(ql_adapter_state_t *); 700 int ql_get_id_list(ql_adapter_state_t *, caddr_t, uint32_t, ql_mbx_data_t *); 701 int ql_wrt_risc_ram(ql_adapter_state_t *, uint32_t, uint64_t, uint32_t); 702 int ql_rd_risc_ram(ql_adapter_state_t *, uint32_t, uint64_t, uint32_t); 703 int ql_issue_mbx_iocb(ql_adapter_state_t *, caddr_t, uint32_t); 704 int ql_mbx_wrap_test(ql_adapter_state_t *, ql_mbx_data_t *); 705 int ql_execute_fw(ql_adapter_state_t *); 706 int ql_get_firmware_option(ql_adapter_state_t *, ql_mbx_data_t *); 707 int ql_set_firmware_option(ql_adapter_state_t *, ql_mbx_data_t *); 708 int ql_init_firmware(ql_adapter_state_t *); 709 int ql_get_firmware_state(ql_adapter_state_t *, ql_mbx_data_t *); 710 int ql_get_adapter_id(ql_adapter_state_t *, ql_mbx_data_t *); 711 int ql_get_fw_version(ql_adapter_state_t *, ql_mbx_data_t *); 712 int ql_data_rate(ql_adapter_state_t *, ql_mbx_data_t *); 713 int ql_diag_loopback(ql_adapter_state_t *, uint16_t, caddr_t, uint32_t, 714 uint16_t, uint32_t, ql_mbx_data_t *); 715 int ql_diag_echo(ql_adapter_state_t *, uint16_t, caddr_t, uint32_t, uint16_t, 716 ql_mbx_data_t *); 717 int ql_serdes_param(ql_adapter_state_t *, ql_mbx_data_t *); 718 int ql_get_timeout_parameters(ql_adapter_state_t *, uint16_t *); 719 int ql_stop_firmware(ql_adapter_state_t *); 720 int ql_read_sfp(ql_adapter_state_t *, dma_mem_t *, uint16_t, uint16_t); 721 int ql_iidma_rate(ql_adapter_state_t *, uint16_t, uint32_t *, uint32_t); 722 int ql_fw_etrace(ql_adapter_state_t *, dma_mem_t *, uint16_t); 723 int ql_reset_menlo(ql_adapter_state_t *, ql_mbx_data_t *, uint16_t); 724 int ql_restart_mpi(ql_adapter_state_t *); 725 int ql_idc_request(ql_adapter_state_t *, ql_mbx_data_t *); 726 int ql_idc_ack(ql_adapter_state_t *); 727 int ql_idc_time_extend(ql_adapter_state_t *, ql_mbx_data_t *); 728 int ql_port_reset(ql_adapter_state_t *); 729 int ql_set_port_config(ql_adapter_state_t *, ql_mbx_data_t *); 730 int ql_get_port_config(ql_adapter_state_t *, ql_mbx_data_t *); 731 int ql_flash_access(ql_adapter_state_t *, uint16_t, uint32_t, uint32_t, 732 uint32_t *); 733 int ql_get_xgmac_stats(ql_adapter_state_t *, size_t, caddr_t); 734 int ql_get_dcbx_params(ql_adapter_state_t *, uint32_t, caddr_t); 735 /* 736 * Mailbox command table initializer 737 */ 738 #define MBOX_CMD_TABLE() \ 739 { \ 740 {MBC_LOAD_RAM, "MBC_LOAD_RAM"}, \ 741 {MBC_EXECUTE_FIRMWARE, "MBC_EXECUTE_FIRMWARE"}, \ 742 {MBC_DUMP_RAM, "MBC_DUMP_RAM"}, \ 743 {MBC_WRITE_RAM_WORD, "MBC_WRITE_RAM_WORD"}, \ 744 {MBC_READ_RAM_WORD, "MBC_READ_RAM_WORD"}, \ 745 {MBC_MAILBOX_REGISTER_TEST, "MBC_MAILBOX_REGISTER_TEST"}, \ 746 {MBC_VERIFY_CHECKSUM, "MBC_VERIFY_CHECKSUM"}, \ 747 {MBC_ABOUT_FIRMWARE, "MBC_ABOUT_FIRMWARE"}, \ 748 {MBC_DUMP_RISC_RAM, "MBC_DUMP_RISC_RAM"}, \ 749 {MBC_LOAD_RAM_EXTENDED, "MBC_LOAD_RAM_EXTENDED"}, \ 750 {MBC_DUMP_RAM_EXTENDED, "MBC_DUMP_RAM_EXTENDED"}, \ 751 {MBC_READ_RAM_EXTENDED, "MBC_READ_RAM_EXTENDED"}, \ 752 {MBC_SERDES_TRANSMIT_PARAMETERS, "MBC_SERDES_TRANSMIT_PARAMETERS"},\ 753 {MBC_2300_EXECUTE_IOCB, "MBC_2300_EXECUTE_IOCB"}, \ 754 {MBC_GET_IO_STATUS, "MBC_GET_IO_STATUS"}, \ 755 {MBC_STOP_FIRMWARE, "MBC_STOP_FIRMWARE"}, \ 756 {MBC_ABORT_COMMAND_IOCB, "MBC_ABORT_COMMAND_IOCB"}, \ 757 {MBC_ABORT_DEVICE, "MBC_ABORT_DEVICE"}, \ 758 {MBC_ABORT_TARGET, "MBC_ABORT_TARGET"}, \ 759 {MBC_RESET, "MBC_RESET"}, \ 760 {MBC_XMIT_PARM, "MBC_XMIT_PARM"}, \ 761 {MBC_PORT_PARAM, "MBC_PORT_PARAM"}, \ 762 {MBC_GET_ID, "MBC_GET_ID"}, \ 763 {MBC_GET_TIMEOUT_PARAMETERS, "MBC_GET_TIMEOUT_PARAMETERS"}, \ 764 {MBC_TRACE_CONTROL, "MBC_TRACE_CONTROL"}, \ 765 {MBC_GET_FIRMWARE_OPTIONS, "MBC_GET_FIRMWARE_OPTIONS"}, \ 766 {MBC_READ_SFP, "MBC_READ_SFP"}, \ 767 {MBC_SET_FIRMWARE_OPTIONS, "MBC_SET_FIRMWARE_OPTIONS"}, \ 768 {MBC_RESET_MENLO, "MBC_RESET_MENLO"}, \ 769 {MBC_RESTART_MPI, "MBC_RESTART_MPI"}, \ 770 {MBC_FLASH_ACCESS, "MBC_FLASH_ACCESS"}, \ 771 {MBC_LOOP_PORT_BYPASS, "MBC_LOOP_PORT_BYPASS"}, \ 772 {MBC_LOOP_PORT_ENABLE, "MBC_LOOP_PORT_ENABLE"}, \ 773 {MBC_GET_RESOURCE_COUNTS, "MBC_GET_RESOURCE_COUNTS"}, \ 774 {MBC_NON_PARTICIPATE, "MBC_NON_PARTICIPATE"}, \ 775 {MBC_ECHO, "MBC_ECHO"}, \ 776 {MBC_DIAGNOSTIC_LOOP_BACK, "MBC_DIAGNOSTIC_LOOP_BACK"}, \ 777 {MBC_ONLINE_SELF_TEST, "MBC_ONLINE_SELF_TEST"}, \ 778 {MBC_ENHANCED_GET_PORT_DATABASE, "MBC_ENHANCED_GET_PORT_DATABASE"},\ 779 {MBC_INITIALIZE_MULTI_ID_FW, "MBC_INITIALIZE_MULTI_ID_FW"}, \ 780 {MBC_GET_DCBX_PARAMS, "MBC_GET_DCBX_PARAMS"}, \ 781 {MBC_RESET_LINK_STATUS, "MBC_RESET_LINK_STATUS"}, \ 782 {MBC_EXECUTE_IOCB, "MBC_EXECUTE_IOCB"}, \ 783 {MBC_SEND_RNID_ELS, "MBC_SEND_RNID_ELS"}, \ 784 {MBC_SET_PARAMETERS, "MBC_SET_PARAMETERS"}, \ 785 {MBC_GET_PARAMETERS, "MBC_GET_PARAMETERS"}, \ 786 {MBC_DATA_RATE, "MBC_DATA_RATE"}, \ 787 {MBC_INITIALIZE_FIRMWARE, "MBC_INITIALIZE_FIRMWARE"}, \ 788 {MBC_INITIATE_LIP, "MBC_INITIATE_LIP"}, \ 789 {MBC_GET_FC_AL_POSITION_MAP, "MBC_GET_FC_AL_POSITION_MAP"}, \ 790 {MBC_GET_PORT_DATABASE, "MBC_GET_PORT_DATABASE"}, \ 791 {MBC_CLEAR_ACA, "MBC_CLEAR_ACA"}, \ 792 {MBC_TARGET_RESET, "MBC_TARGET_RESET"}, \ 793 {MBC_CLEAR_TASK_SET, "MBC_CLEAR_TASK_SET"}, \ 794 {MBC_ABORT_TASK_SET, "MBC_ABORT_TASK_SET"}, \ 795 {MBC_GET_FIRMWARE_STATE, "MBC_GET_FIRMWARE_STATE"}, \ 796 {MBC_GET_PORT_NAME, "MBC_GET_PORT_NAME"}, \ 797 {MBC_GET_LINK_STATUS, "MBC_GET_LINK_STATUS"}, \ 798 {MBC_LIP_RESET, "MBC_LIP_RESET"}, \ 799 {MBC_GET_STATUS_COUNTS, "MBC_GET_STATUS_COUNTS"}, \ 800 {MBC_SEND_SNS_COMMAND, "MBC_SEND_SNS_COMMAND"}, \ 801 {MBC_LOGIN_FABRIC_PORT, "MBC_LOGIN_FABRIC_PORT"}, \ 802 {MBC_SEND_CHANGE_REQUEST, "MBC_SEND_CHANGE_REQUEST"}, \ 803 {MBC_LOGOUT_FABRIC_PORT, "MBC_LOGOUT_FABRIC_PORT"}, \ 804 {MBC_LIP_FULL_LOGIN, "MBC_LIP_FULL_LOGIN"}, \ 805 {MBC_LOGIN_LOOP_PORT, "MBC_LOGIN_LOOP_PORT"}, \ 806 {MBC_PORT_NODE_NAME_LIST, "MBC_PORT_NODE_NAME_LIST"}, \ 807 {MBC_INITIALIZE_IP, "MBC_INITIALIZE_IP"}, \ 808 {MBC_SEND_FARP_REQ_COMMAND, "MBC_SEND_FARP_REQ_COMMAND"}, \ 809 {MBC_UNLOAD_IP, "MBC_UNLOAD_IP"}, \ 810 {MBC_GET_XGMAC_STATS, "MBC_GET_XGMAC_STATS"}, \ 811 {MBC_GET_ID_LIST, "MBC_GET_ID_LIST"}, \ 812 {MBC_SEND_LFA_COMMAND, "MBC_SEND_LFA_COMMAND"}, \ 813 {MBC_LUN_RESET, "MBC_LUN_RESET"}, \ 814 {MBC_IDC_REQUEST, "MBC_IDC_REQUEST"}, \ 815 {MBC_IDC_ACK, "MBC_IDC_ACK"}, \ 816 {MBC_IDC_TIME_EXTEND, "MBC_IDC_TIME_EXTEND"}, \ 817 {MBC_PORT_RESET, "MBC_PORT_RESET"}, \ 818 {MBC_SET_PORT_CONFIG, "MBC_SET_PORT_CONFIG"}, \ 819 {MBC_GET_PORT_CONFIG, "MBC_GET_PORT_CONFIG"}, \ 820 {NULL, "Unsupported"} \ 821 } 822 823 #ifdef __cplusplus 824 } 825 #endif 826 827 #endif /* _QL_MBX_H */ 828