1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* Copyright 2009 QLogic Corporation */ 23 24 /* 25 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms. 27 */ 28 29 #ifndef _QL_API_H 30 #define _QL_API_H 31 32 /* 33 * ISP2xxx Solaris Fibre Channel Adapter (FCA) driver header file. 34 * 35 * *********************************************************************** 36 * * ** 37 * * NOTICE ** 38 * * COPYRIGHT (C) 1996-2009 QLOGIC CORPORATION ** 39 * * ALL RIGHTS RESERVED ** 40 * * ** 41 * *********************************************************************** 42 * 43 */ 44 45 #ifdef __cplusplus 46 extern "C" { 47 #endif 48 49 /* OS include files. */ 50 #include <sys/scsi/scsi_types.h> 51 #include <sys/byteorder.h> 52 #include <sys/pci.h> 53 #include <sys/utsname.h> 54 #include <sys/file.h> 55 #include <sys/param.h> 56 #include <ql_open.h> 57 58 #include <sys/fibre-channel/fc.h> 59 #include <sys/fibre-channel/impl/fc_fcaif.h> 60 61 #ifndef DDI_INTR_TYPE_FIXED 62 #define DDI_INTR_TYPE_FIXED 0x1 63 #endif 64 #ifndef DDI_INTR_TYPE_MSI 65 #define DDI_INTR_TYPE_MSI 0x2 66 #endif 67 #ifndef DDI_INTR_TYPE_MSIX 68 #define DDI_INTR_TYPE_MSIX 0x4 69 #endif 70 #ifndef DDI_INTR_FLAG_BLOCK 71 #define DDI_INTR_FLAG_BLOCK 0x100 72 #endif 73 #ifndef DDI_INTR_ALLOC_NORMAL 74 #define DDI_INTR_ALLOC_NORMAL 0 75 #endif 76 #ifndef DDI_INTR_ALLOC_STRICT 77 #define DDI_INTR_ALLOC_STRICT 1 78 #endif 79 80 /* 81 * NPIV defines 82 */ 83 #ifndef FC_NPIV_FDISC_FAILED 84 #define FC_NPIV_FDISC_FAILED 0x45 85 #endif 86 #ifndef FC_NPIV_FDISC_WWN_INUSE 87 #define FC_NPIV_FDISC_WWN_INUSE 0x46 88 #endif 89 #ifndef FC_NPIV_NOT_SUPPORTED 90 #define FC_NPIV_NOT_SUPPORTED 0x47 91 #endif 92 #ifndef FC_NPIV_WRONG_TOPOLOGY 93 #define FC_NPIV_WRONG_TOPOLOGY 0x48 94 #endif 95 #ifndef FC_NPIV_NPIV_BOUND 96 #define FC_NPIV_NPIV_BOUND 0x49 97 #endif 98 99 #pragma weak ddi_intr_get_supported_types 100 #pragma weak ddi_intr_get_nintrs 101 #pragma weak ddi_intr_alloc 102 #pragma weak ddi_intr_free 103 #pragma weak ddi_intr_get_pri 104 #pragma weak ddi_intr_add_handler 105 #pragma weak ddi_intr_dup_handler 106 #pragma weak ddi_intr_get_navail 107 #pragma weak ddi_intr_block_disable 108 #pragma weak ddi_intr_block_enable 109 #pragma weak ddi_intr_disable 110 #pragma weak ddi_intr_enable 111 #pragma weak ddi_intr_get_cap 112 #pragma weak ddi_intr_remove_handler 113 extern int ddi_intr_get_supported_types(); 114 extern int ddi_intr_get_nintrs(); 115 extern int ddi_intr_alloc(); 116 extern int ddi_intr_free(); 117 extern int ddi_intr_get_pri(); 118 extern int ddi_intr_add_handler(); 119 extern int ddi_intr_dup_handler(); 120 extern int ddi_intr_get_navail(); 121 extern int ddi_intr_block_disable(); 122 extern int ddi_intr_block_enable(); 123 extern int ddi_intr_disable(); 124 extern int ddi_intr_enable(); 125 extern int ddi_intr_get_cap(); 126 extern int ddi_intr_remove_handler(); 127 128 #ifndef QL_DRV_HARDENING 129 #define ddi_devstate_t int 130 #define DDI_DEVSTATE_UP 0 131 #define ddi_get_devstate(a) DDI_DEVSTATE_UP 132 #define ddi_dev_report_fault(a, b, c, d) 133 #define ddi_check_dma_handle(a) DDI_SUCCESS 134 #define ddi_check_acc_handle(a) DDI_SUCCESS 135 #define QL_CLEAR_DMA_HANDLE(x) 136 #else 137 #define QL_CLEAR_DMA_HANDLE(x) ((ddi_dma_impl_t *)x)->dmai_fault_notify = 0; \ 138 ((ddi_dma_impl_t *)x)->dmai_fault_check = 0; \ 139 ((ddi_dma_impl_t *)x)->dmai_fault = 0 140 #endif 141 142 #ifndef FC_STATE_1GBIT_SPEED 143 #define FC_STATE_1GBIT_SPEED FC_STATE_FULL_SPEED 144 #endif 145 #ifndef FC_STATE_2GBIT_SPEED 146 #define FC_STATE_2GBIT_SPEED FC_STATE_DOUBLE_SPEED 147 #endif 148 #ifndef FC_STATE_4GBIT_SPEED 149 #define FC_STATE_4GBIT_SPEED FC_STATE_DOUBLE_SPEED 150 #endif 151 152 /* 153 * Data bit definitions. 154 */ 155 #define BIT_0 0x1 156 #define BIT_1 0x2 157 #define BIT_2 0x4 158 #define BIT_3 0x8 159 #define BIT_4 0x10 160 #define BIT_5 0x20 161 #define BIT_6 0x40 162 #define BIT_7 0x80 163 #define BIT_8 0x100 164 #define BIT_9 0x200 165 #define BIT_10 0x400 166 #define BIT_11 0x800 167 #define BIT_12 0x1000 168 #define BIT_13 0x2000 169 #define BIT_14 0x4000 170 #define BIT_15 0x8000 171 #define BIT_16 0x10000 172 #define BIT_17 0x20000 173 #define BIT_18 0x40000 174 #define BIT_19 0x80000 175 #define BIT_20 0x100000 176 #define BIT_21 0x200000 177 #define BIT_22 0x400000 178 #define BIT_23 0x800000 179 #define BIT_24 0x1000000 180 #define BIT_25 0x2000000 181 #define BIT_26 0x4000000 182 #define BIT_27 0x8000000 183 #define BIT_28 0x10000000 184 #define BIT_29 0x20000000 185 #define BIT_30 0x40000000 186 #define BIT_31 0x80000000 187 188 /* 189 * Local Macro Definitions. 190 */ 191 #ifndef TRUE 192 #define TRUE B_TRUE 193 #endif 194 195 #ifndef FALSE 196 #define FALSE B_FALSE 197 #endif 198 199 /* 200 * I/O register 201 */ 202 #define RD_REG_BYTE(ha, addr) \ 203 (uint8_t)ddi_get8(ha->dev_handle, (uint8_t *)addr) 204 #define RD_REG_WORD(ha, addr) \ 205 (uint16_t)ddi_get16(ha->dev_handle, (uint16_t *)addr) 206 #define RD_REG_DWORD(ha, addr) \ 207 (uint32_t)ddi_get32(ha->dev_handle, (uint32_t *)addr) 208 209 #define WRT_REG_BYTE(ha, addr, data) \ 210 ddi_put8(ha->dev_handle, (uint8_t *)addr, (uint8_t)data) 211 #define WRT_REG_WORD(ha, addr, data) \ 212 ddi_put16(ha->dev_handle, (uint16_t *)addr, (uint16_t)data) 213 #define WRT_REG_DWORD(ha, addr, data) \ 214 ddi_put32(ha->dev_handle, (uint32_t *)addr, (uint32_t)data) 215 216 #define RD8_IO_REG(ha, regname) \ 217 RD_REG_BYTE(ha, (ha->iobase + ha->reg_off->regname)) 218 #define RD16_IO_REG(ha, regname) \ 219 RD_REG_WORD(ha, (ha->iobase + ha->reg_off->regname)) 220 #define RD32_IO_REG(ha, regname) \ 221 RD_REG_DWORD(ha, (ha->iobase + ha->reg_off->regname)) 222 223 #define WRT8_IO_REG(ha, regname, data) \ 224 WRT_REG_BYTE(ha, (ha->iobase + ha->reg_off->regname), data) 225 #define WRT16_IO_REG(ha, regname, data) \ 226 WRT_REG_WORD(ha, (ha->iobase + ha->reg_off->regname), data) 227 #define WRT32_IO_REG(ha, regname, data) \ 228 WRT_REG_DWORD(ha, (ha->iobase + ha->reg_off->regname), data) 229 230 #define RD_IOREG_BYTE(ha, addr) \ 231 (uint8_t)ddi_get8(ha->iomap_dev_handle, (uint8_t *)addr) 232 #define RD_IOREG_WORD(ha, addr) \ 233 (uint16_t)ddi_get16(ha->iomap_dev_handle, (uint16_t *)addr) 234 #define RD_IOREG_DWORD(ha, addr) \ 235 (uint32_t)ddi_get32(ha->iomap_dev_handle, (uint32_t *)addr) 236 237 #define WRT_IOREG_BYTE(ha, addr, data) \ 238 ddi_put8(ha->iomap_dev_handle, (uint8_t *)addr, (uint8_t)data) 239 #define WRT_IOREG_WORD(ha, addr, data) \ 240 ddi_put16(ha->iomap_dev_handle, (uint16_t *)addr, (uint16_t)data) 241 #define WRT_IOREG_DWORD(ha, addr, data) \ 242 ddi_put32(ha->iomap_dev_handle, (uint32_t *)addr, (uint32_t)data) 243 244 #define RD8_IOMAP_REG(ha, regname) \ 245 RD_IOREG_BYTE(ha, (ha->iomap_iobase + ha->reg_off->regname)) 246 #define RD16_IOMAP_REG(ha, regname) \ 247 RD_IOREG_WORD(ha, (ha->iomap_iobase + ha->reg_off->regname)) 248 #define RD32_IOMAP_REG(ha, regname) \ 249 RD_IOREG_DWORD(ha, (ha->iomap_iobase + ha->reg_off->regname)) 250 251 #define WRT8_IOMAP_REG(ha, regname, data) \ 252 WRT_IOREG_BYTE(ha, (ha->iomap_iobase + ha->reg_off->regname), data) 253 #define WRT16_IOMAP_REG(ha, regname, data) \ 254 WRT_IOREG_WORD(ha, (ha->iomap_iobase + ha->reg_off->regname), data) 255 #define WRT32_IOMAP_REG(ha, regname, data) \ 256 WRT_IOREG_DWORD(ha, (ha->iomap_iobase + ha->reg_off->regname), data) 257 258 /* 259 * FCA definitions 260 */ 261 #define MAX_LUNS 16384 262 #define QL_FCA_BRAND 0x0fca2200 263 264 /* Following to be removed when defined by OS. */ 265 /* ************************************************************************ */ 266 #define LA_ELS_FARP_REQ 0x54 267 #define LA_ELS_FARP_REPLY 0x55 268 #define LA_ELS_LPC 0x71 269 #define LA_ELS_LSTS 0x72 270 271 typedef struct { 272 ls_code_t ls_code; 273 uint8_t rsvd[3]; 274 uint8_t port_control; 275 uint8_t lpb[16]; 276 uint8_t lpe[16]; 277 } ql_lpc_t; 278 279 typedef struct { 280 ls_code_t ls_code; 281 } ql_acc_rjt_t; 282 283 typedef fc_linit_resp_t ql_lpc_resp_t; 284 typedef fc_scr_resp_t ql_rscn_resp_t; 285 286 typedef struct { 287 uint16_t class_valid_svc_opt; 288 uint16_t initiator_ctl; 289 uint16_t recipient_ctl; 290 uint16_t rcv_data_size; 291 uint16_t conc_sequences; 292 uint16_t n_port_end_to_end_credit; 293 uint16_t open_sequences_per_exch; 294 uint16_t unused; 295 } class_svc_param_t; 296 297 typedef struct { 298 uint8_t type; 299 uint8_t rsvd; 300 uint16_t process_assoc_flags; 301 uint32_t originator_process; 302 uint32_t responder_process; 303 uint32_t process_flags; 304 } prli_svc_param_t; 305 /* *********************************************************************** */ 306 307 /* 308 * Fibre Channel device definitions. 309 */ 310 #define MAX_22_FIBRE_DEVICES 256 311 #define MAX_24_FIBRE_DEVICES 2048 312 #define MAX_24_VIRTUAL_PORTS 127 313 #define MAX_25_VIRTUAL_PORTS 254 314 315 #define LAST_LOCAL_LOOP_ID 0x7d 316 #define FL_PORT_LOOP_ID 0x7e /* FFFFFE Fabric F_Port */ 317 #define SWITCH_FABRIC_CONTROLLER_LOOP_ID 0x7f /* FFFFFD Fabric Controller */ 318 #define SIMPLE_NAME_SERVER_LOOP_ID 0x80 /* FFFFFC Directory Server */ 319 #define SNS_FIRST_LOOP_ID 0x81 320 #define SNS_LAST_LOOP_ID 0xfe 321 #define IP_BROADCAST_LOOP_ID 0xff /* FFFFFF Broadcast */ 322 #define BROADCAST_ADDR 0xffffff /* FFFFFF Broadcast */ 323 324 /* 325 * Fibre Channel 24xx device definitions. 326 */ 327 #define LAST_N_PORT_HDL 0x7ef 328 #define SNS_24XX_HDL 0x7FC /* SNS FFFFFCh */ 329 #define SFC_24XX_HDL 0x7FD /* fabric controller FFFFFDh */ 330 #define FL_PORT_24XX_HDL 0x7FE /* F_Port FFFFFEh */ 331 #define BROADCAST_24XX_HDL 0x7FF /* IP broadcast FFFFFFh */ 332 333 /* Loop ID's used as flags, must be higher than any valid Loop ID */ 334 #define PORT_NO_LOOP_ID 0x8000 /* Device does not have loop ID. */ 335 #define PORT_LOST_ID 0x4000 /* Device has been lost. */ 336 337 /* Fibre Channel Topoploy. */ 338 #define QL_N_PORT BIT_0 339 #define QL_NL_PORT BIT_1 340 #define QL_F_PORT BIT_2 341 #define QL_FL_PORT BIT_3 342 #define QL_SNS_CONNECTION BIT_4 343 #define QL_LOOP_CONNECTION (QL_NL_PORT | QL_FL_PORT) 344 #define QL_P2P_CONNECTION (QL_F_PORT | QL_N_PORT) 345 346 /* Timeout timer counts in seconds (must greater than 1 second). */ 347 #define WATCHDOG_TIME 5 /* 0 - 255 */ 348 #define PORT_RETRY_TIME 2 /* 0 - 255 */ 349 #define LOOP_DOWN_TIMER_OFF 0 350 #define LOOP_DOWN_TIMER_START 240 /* 0 - 255 */ 351 #define LOOP_DOWN_TIMER_END 1 352 #define LOOP_DOWN_RESET (LOOP_DOWN_TIMER_START - 45) /* 0 - 255 */ 353 #define R_A_TOV_DEFAULT 20 /* 0 - 65535 */ 354 #define IDLE_CHECK_TIMER 300 /* 0 - 65535 */ 355 #define MAX_DEVICE_LOST_RETRY 16 /* 0 - 255 */ 356 357 /* Maximum outstanding commands in ISP queues (1-4095) */ 358 #define MAX_OUTSTANDING_COMMANDS 0x400 359 #define OSC_INDEX_MASK 0xfff 360 #define OSC_INDEX_SHIFT 12 361 362 /* Maximum unsolicited buffers (1-65535) */ 363 #define QL_UB_LIMIT 256 364 365 /* ISP request, response and receive buffer entry counts */ 366 #define REQUEST_ENTRY_CNT 512 /* Request entries (205-65535) */ 367 #define RESPONSE_ENTRY_CNT 256 /* Response entries (1-65535) */ 368 #define RCVBUF_CONTAINER_CNT 64 /* Rcv buffer containers (8-1024) */ 369 370 /* 371 * ISP request, response, mailbox and receive buffer queue sizes 372 */ 373 #define REQUEST_ENTRY_SIZE 64 374 #define REQUEST_QUEUE_SIZE (REQUEST_ENTRY_SIZE * REQUEST_ENTRY_CNT) 375 376 #define RESPONSE_ENTRY_SIZE 64 377 #define RESPONSE_QUEUE_SIZE (RESPONSE_ENTRY_SIZE * RESPONSE_ENTRY_CNT) 378 379 #define MAILBOX_BUFFER_SIZE 0x4000 380 381 #define RCVBUF_CONTAINER_SIZE 12 382 #define RCVBUF_QUEUE_SIZE (RCVBUF_CONTAINER_SIZE * RCVBUF_CONTAINER_CNT) 383 384 385 /* 386 * ISP DMA buffer definitions 387 */ 388 #define REQUEST_Q_BUFFER_OFFSET 0 389 #define RESPONSE_Q_BUFFER_OFFSET (REQUEST_Q_BUFFER_OFFSET + REQUEST_QUEUE_SIZE) 390 #define RCVBUF_Q_BUFFER_OFFSET (RESPONSE_Q_BUFFER_OFFSET + RESPONSE_QUEUE_SIZE) 391 392 /* 393 * DMA attributes definitions. 394 */ 395 #define QL_DMA_LOW_ADDRESS (uint64_t)0 396 #define QL_DMA_HIGH_64BIT_ADDRESS (uint64_t)0xffffffffffffffff 397 #define QL_DMA_HIGH_32BIT_ADDRESS (uint64_t)0xffffffff 398 #define QL_DMA_XFER_COUNTER (uint64_t)0xffffffff 399 #define QL_DMA_ADDRESS_ALIGNMENT (uint64_t)8 400 #define QL_DMA_ALIGN_8_BYTE_BOUNDARY (uint64_t)BIT_3 401 #define QL_DMA_RING_ADDRESS_ALIGNMENT (uint64_t)64 402 #define QL_DMA_ALIGN_64_BYTE_BOUNDARY (uint64_t)BIT_6 403 #define QL_DMA_BURSTSIZES 0xff 404 #define QL_DMA_MIN_XFER_SIZE 1 405 #define QL_DMA_MAX_XFER_SIZE (uint64_t)0xffffffff 406 #define QL_DMA_SEGMENT_BOUNDARY (uint64_t)0xffffffff 407 408 #ifdef __sparc 409 #define QL_DMA_SG_LIST_LENGTH 1 410 #define QL_FCSM_CMD_SGLLEN 1 411 #define QL_FCSM_RSP_SGLLEN 1 412 #define QL_FCIP_CMD_SGLLEN 1 413 #define QL_FCIP_RSP_SGLLEN 1 414 #define QL_FCP_CMD_SGLLEN 1 415 #define QL_FCP_RSP_SGLLEN 1 416 #else 417 #define QL_DMA_SG_LIST_LENGTH 1024 418 #define QL_FCSM_CMD_SGLLEN 1 419 #define QL_FCSM_RSP_SGLLEN 6 420 /* 421 * QL_FCIP_CMD_SGLLEN needs to be increased as we changed the max fcip packet 422 * size to about 64K. With this, we need to increase the maximum number of 423 * scatter-gather elements allowable from the existing 7. We want it to be more 424 * like 17 (max fragments for an fcip packet that is unaligned). (64K / 4K) + 1 425 * or whatever. Otherwise the DMA breakup routines will give bad results. 426 */ 427 #define QL_FCIP_CMD_SGLLEN 17 428 #define QL_FCIP_RSP_SGLLEN 1 429 #define QL_FCP_CMD_SGLLEN 1 430 #define QL_FCP_RSP_SGLLEN 1 431 #endif 432 433 #ifndef DDI_DMA_RELAXED_ORDERING 434 #define DDI_DMA_RELAXED_ORDERING 0x400 435 #endif 436 437 #define QL_DMA_GRANULARITY 1 438 #define QL_DMA_XFER_FLAGS 0 439 440 typedef union { 441 uint64_t size64; /* 1 X 64 bit number */ 442 uint32_t size32[2]; /* 2 x 32 bit number */ 443 uint16_t size16[4]; /* 4 x 16 bit number */ 444 uint8_t size8[8]; /* 8 x 8 bit number */ 445 } conv_num_t; 446 447 /* 448 * Device register offsets. 449 */ 450 #define MAX_MBOX_COUNT 32 451 typedef struct { 452 uint8_t flash_address; /* Flash BIOS address */ 453 uint8_t flash_data; /* Flash BIOS data */ 454 uint8_t ctrl_status; /* Control/Status */ 455 uint8_t ictrl; /* Interrupt control */ 456 uint8_t istatus; /* Interrupt status */ 457 uint8_t semaphore; /* Semaphore */ 458 uint8_t nvram; /* NVRAM register. */ 459 uint8_t req_in; /* for 2200 MBX 4 Write */ 460 uint8_t req_out; /* for 2200 MBX 4 read */ 461 uint8_t resp_in; /* for 2200 MBX 5 Read */ 462 uint8_t resp_out; /* for 2200 MBX 5 Write */ 463 uint8_t intr_info_lo; 464 uint8_t intr_info_hi; 465 uint8_t mbox_cnt; /* Number of mailboxes */ 466 uint8_t mailbox[MAX_MBOX_COUNT]; /* Mailbox registers */ 467 uint8_t fpm_diag_config; 468 uint8_t pcr; /* Processor Control Register. */ 469 uint8_t mctr; /* Memory Configuration and Timing. */ 470 uint8_t fb_cmd; 471 uint8_t hccr; /* Host command & control register. */ 472 uint8_t gpiod; /* GPIO Data register. */ 473 uint8_t gpioe; /* GPIO Enable register. */ 474 uint8_t host_to_host_sema; /* 2312 resource lock register */ 475 uint8_t pri_req_in; /* 2400 */ 476 uint8_t pri_req_out; /* 2400 */ 477 uint8_t atio_req_in; /* 2400 */ 478 uint8_t atio_req_out; /* 2400 */ 479 uint8_t io_base_addr; /* 2400 */ 480 } reg_off_t; 481 482 /* 483 * Mbox-8 read maximum debounce count. 484 * Reading Mbox-8 could be debouncing, before getting stable value. 485 * This is the recommended driver fix from Qlogic along with firmware fix. 486 * During testing, maximum count did not cross 3. 487 */ 488 #define QL_MAX_DEBOUNCE 10 489 490 /* 491 * Control Status register definitions 492 */ 493 #define ISP_FUNC_NUM_MASK (BIT_15 | BIT_14) 494 #define ISP_FLASH_64K_BANK BIT_3 /* Flash BIOS 64K Bank Select */ 495 #define ISP_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */ 496 #define ISP_RESET BIT_0 /* ISP soft reset */ 497 498 /* 499 * Control Status 24xx register definitions 500 */ 501 #define FLASH_NVRAM_ACCESS_ERROR BIT_18 502 #define DMA_ACTIVE BIT_17 503 #define DMA_SHUTDOWN BIT_16 504 #define FUNCTION_NUMBER BIT_15 505 506 #define MWB_4096_BYTES (BIT_5 | BIT_4) 507 #define MWB_2048_BYTES BIT_5 508 #define MWB_1024_BYTES BIT_4 509 #define MWB_512_BYTES 0 510 511 /* 512 * Interrupt Control register definitions 513 */ 514 #define ISP_EN_INT BIT_15 /* ISP enable interrupts. */ 515 #define ISP_EN_RISC BIT_3 /* ISP enable RISC interrupts. */ 516 517 /* 518 * Interrupt Status register definitions 519 */ 520 #define RISC_INT BIT_3 /* RISC interrupt */ 521 522 /* 523 * NVRAM register definitions. 524 */ 525 #define NV_DESELECT 0 526 #define NV_CLOCK BIT_0 527 #define NV_SELECT BIT_1 528 #define NV_DATA_OUT BIT_2 529 #define NV_DATA_IN BIT_3 530 #define NV_PR_ENABLE BIT_13 /* protection register enable */ 531 #define NV_WR_ENABLE BIT_14 /* write enable */ 532 #define NV_BUSY BIT_15 533 534 /* 535 * Flash/NVRAM 24xx definitions 536 */ 537 #define FLASH_DATA_FLAG BIT_31 538 #define FLASH_CONF_ADDR 0x7FFD0000 539 #define FLASH_DATA_ADDR 0x7FF00000 540 #define FLASH_ADDR_MASK 0x7FFF0000 541 542 #define NVRAM_CONF_ADDR 0x7FFF0000 543 #define NVRAM_DATA_ADDR 0x7FFE0000 544 545 #define NVRAM_24XX_FUNC0_ADDR (NVRAM_DATA_ADDR + 0x80) 546 #define NVRAM_24XX_FUNC1_ADDR (NVRAM_DATA_ADDR + 0x180) 547 #define VPD_24XX_FUNC0_ADDR NVRAM_DATA_ADDR 548 #define VPD_24XX_FUNC1_ADDR (NVRAM_DATA_ADDR + 0x100) 549 550 #define NVRAM_25XX_FUNC0_ADDR FLASH_DATA_ADDR + 0x48080 551 #define NVRAM_25XX_FUNC1_ADDR FLASH_DATA_ADDR + 0x48180 552 #define VPD_25XX_FUNC0_ADDR FLASH_DATA_ADDR + 0x48000 553 #define VPD_25XX_FUNC1_ADDR FLASH_DATA_ADDR + 0x48100 554 555 #define FLASH_2400_ERRLOG_START_ADDR_0 0 /* 0x1f000 */ 556 #define FLASH_2400_ERRLOG_START_ADDR_1 0 /* 0x1f200 */ 557 #define FLASH_2500_ERRLOG_START_ADDR_0 0x54000 558 #define FLASH_2500_ERRLOG_START_ADDR_1 0x54400 559 #define FLASH_ERRLOG_SIZE 0x200 560 #define FLASH_ERRLOG_ENTRY_SIZE 4 561 #define FLASH_2500_DESCRIPTOR_TABLE 0x50000 562 563 /* 564 * Flash Error Log Event Codes. 565 */ 566 #define FLASH_ERRLOG_AEN_8002 0x8002 567 #define FLASH_ERRLOG_AEN_8003 0x8003 568 #define FLASH_ERRLOG_AEN_8004 0x8004 569 #define FLASH_ERRLOG_RESET_ERR 0xF00B 570 #define FLASH_ERRLOG_ISP_ERR 0xF020 571 #define FLASH_ERRLOG_PARITY_ERR 0xF022 572 #define FLASH_ERRLOG_NVRAM_CHKSUM_ERR 0xF023 573 #define FLASH_ERRLOG_FLASH_FW_ERR 0xF024 574 575 #define VPD_TAG_END 0x78 576 #define VPD_TAG_CHKSUM "RV" 577 #define VPD_TAG_SN "SN" 578 #define VPD_TAG_PN "PN" 579 #define VPD_TAG_PRODID "\x82" 580 #define VPD_TAG_LRT 0x90 581 #define VPD_TAG_LRTC 0x91 582 583 #define FLASH_24XX_FIRMWARE_ADDR 0x80000 584 /* 585 * RISC to Host Status register definitions. 586 */ 587 #define RH_RISC_INT BIT_15 /* RISC to Host Intrpt Req */ 588 #define RH_RISC_PAUSED BIT_8 /* RISC Paused bit. */ 589 590 /* 591 * RISC to Host Status register status field definitions. 592 */ 593 #define ROM_MBX_SUCCESS 0x01 594 #define ROM_MBX_ERR 0x02 595 #define MBX_SUCCESS 0x10 596 #define MBX_ERR 0x11 597 #define ASYNC_EVENT 0x12 598 #define RESP_UPDATE 0x13 599 #define REQ_UPDATE 0x14 600 #define SCSI_FAST_POST_16 0x15 601 #define SCSI_FAST_POST_32 0x16 602 #define CTIO_FAST_POST 0x17 603 #define IP_FAST_POST_XMT 0x18 604 #define IP_FAST_POST_RCV 0x19 605 #define IP_FAST_POST_BRD 0x1a 606 #define IP_FAST_POST_RCV_ALN 0x1b 607 #define ATIO_UPDATE 0x1c 608 #define ATIO_RESP_UPDATE 0x1d 609 610 /* 611 * HCCR commands. 612 */ 613 #define HC_RESET_RISC 0x1000 /* Reset RISC */ 614 #define HC_PAUSE_RISC 0x2000 /* Pause RISC */ 615 #define HC_RELEASE_RISC 0x3000 /* Release RISC from reset. */ 616 #define HC_DISABLE_PARITY_PAUSE 0x4001 /* qla2200/2300 - disable parity err */ 617 /* RISC pause. */ 618 #define HC_SET_HOST_INT 0x5000 /* Set host interrupt */ 619 #define HC_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */ 620 #define HC_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */ 621 #define HC_HOST_INT BIT_7 /* Host interrupt bit */ 622 #define HC_RISC_PAUSE BIT_5 /* Pause mode bit */ 623 624 /* 625 * HCCR commands for 24xx and 25xx. 626 */ 627 #define HC24_RESET_RISC 0x10000000 /* Reset RISC */ 628 #define HC24_CLEAR_RISC_RESET 0x20000000 /* Release RISC from reset. */ 629 #define HC24_PAUSE_RISC 0x30000000 /* Pause RISC */ 630 #define HC24_RELEASE_PAUSE 0x40000000 /* Release RISC from pause */ 631 #define HC24_SET_HOST_INT 0x50000000 /* Set host interrupt */ 632 #define HC24_CLR_HOST_INT 0x60000000 /* Clear HOST interrupt */ 633 #define HC24_CLR_RISC_INT 0xA0000000 /* Clear RISC interrupt */ 634 #define HC24_HOST_INT BIT_6 /* Host to RISC intrpt bit */ 635 #define HC24_RISC_RESET BIT_5 /* RISC Reset mode bit. */ 636 637 /* 638 * ISP Initialization Control Blocks. 639 * Little endian except where noted. 640 */ 641 #define ICB_VERSION 1 642 typedef struct ql_init_cb { 643 uint8_t version; 644 uint8_t reserved; 645 646 /* 647 * LSB BIT 0 = enable_hard_loop_id 648 * LSB BIT 1 = enable_fairness 649 * LSB BIT 2 = enable_full_duplex 650 * LSB BIT 3 = enable_fast_posting 651 * LSB BIT 4 = enable_target_mode 652 * LSB BIT 5 = disable_initiator_mode 653 * LSB BIT 6 = enable_adisc 654 * LSB BIT 7 = enable_target_inquiry_data 655 * 656 * MSB BIT 0 = enable_port_update_ae 657 * MSB BIT 1 = disable_initial_lip 658 * MSB BIT 2 = enable_decending_soft_assign 659 * MSB BIT 3 = previous_assigned_addressing 660 * MSB BIT 4 = enable_stop_q_on_full 661 * MSB BIT 5 = enable_full_login_on_lip 662 * MSB BIT 6 = enable_node_name 663 * MSB BIT 7 = extended_control_block 664 */ 665 uint8_t firmware_options[2]; 666 667 uint8_t max_frame_length[2]; 668 uint8_t max_iocb_allocation[2]; 669 uint8_t execution_throttle[2]; 670 uint8_t login_retry_count; 671 uint8_t retry_delay; /* unused */ 672 uint8_t port_name[8]; /* Big endian. */ 673 uint8_t hard_address[2]; /* option bit 0 */ 674 uint8_t inquiry; /* option bit 7 */ 675 uint8_t login_timeout; 676 uint8_t node_name[8]; /* Big endian */ 677 uint8_t request_q_outpointer[2]; 678 uint8_t response_q_inpointer[2]; 679 uint8_t request_q_length[2]; 680 uint8_t response_q_length[2]; 681 uint8_t request_q_address[8]; 682 uint8_t response_q_address[8]; 683 uint8_t lun_enables[2]; 684 uint8_t command_resouce_count; 685 uint8_t immediate_notify_resouce_count; 686 uint8_t timeout[2]; 687 uint8_t reserved_2[2]; 688 689 /* 690 * LSB BIT 0 = Timer operation mode bit 0 691 * LSB BIT 1 = Timer operation mode bit 1 692 * LSB BIT 2 = Timer operation mode bit 2 693 * LSB BIT 3 = Timer operation mode bit 3 694 * LSB BIT 4 = P2P Connection option bit 0 695 * LSB BIT 5 = P2P Connection option bit 1 696 * LSB BIT 6 = P2P Connection option bit 2 697 * LSB BIT 7 = Enable Non part on LIHA failure 698 * 699 * MSB BIT 0 = Enable class 2 700 * MSB BIT 1 = Enable ACK0 701 * MSB BIT 2 = 702 * MSB BIT 3 = 703 * MSB BIT 4 = FC Tape Enable 704 * MSB BIT 5 = Enable FC Confirm 705 * MSB BIT 6 = Enable CRN 706 * MSB BIT 7 = 707 */ 708 uint8_t add_fw_opt[2]; 709 710 uint8_t response_accumulation_timer; 711 uint8_t interrupt_delay_timer; 712 713 /* 714 * LSB BIT 0 = Enable Read xfr_rdy 715 * LSB BIT 1 = Soft ID only 716 * LSB BIT 2 = 717 * LSB BIT 3 = 718 * LSB BIT 4 = FCP RSP Payload [0] 719 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 720 * LSB BIT 6 = 721 * LSB BIT 7 = 722 * 723 * MSB BIT 0 = Sbus enable - 2300 724 * MSB BIT 1 = 725 * MSB BIT 2 = 726 * MSB BIT 3 = 727 * MSB BIT 4 = 728 * MSB BIT 5 = enable 50 ohm termination 729 * MSB BIT 6 = Data Rate (2300 only) 730 * MSB BIT 7 = Data Rate (2300 only) 731 */ 732 uint8_t special_options[2]; 733 734 uint8_t reserved_3[26]; 735 } ql_init_cb_t; 736 /* 737 * Virtual port definition. 738 */ 739 740 typedef struct ql_vp_cfg { 741 uint8_t reserved[2]; 742 uint8_t options; 743 uint8_t hard_prev_addr; 744 uint8_t port_name[8]; 745 uint8_t node_name[8]; 746 } ql_vp_cfg_t; 747 748 /* 749 * VP options. 750 */ 751 #define VPO_TARGET_MODE_DISABLED BIT_5 752 #define VPO_INITIATOR_MODE_ENABLED BIT_4 753 #define VPO_ENABLED BIT_3 754 #define VPO_ID_NOT_ACQUIRED BIT_2 755 #define VPO_PREVIOUSLY_ASSIGNED_ID BIT_1 756 #define VPO_HARD_ASSIGNED_ID BIT_0 757 758 #define ICB_24XX_VERSION 1 759 typedef struct ql_init_24xx_cb { 760 uint8_t version[2]; 761 uint8_t reserved_1[2]; 762 uint8_t max_frame_length[2]; 763 uint8_t execution_throttle[2]; 764 uint8_t exchange_count[2]; 765 uint8_t hard_address[2]; 766 uint8_t port_name[8]; /* Big endian. */ 767 uint8_t node_name[8]; /* Big endian. */ 768 769 uint8_t response_q_inpointer[2]; 770 uint8_t request_q_outpointer[2]; 771 772 uint8_t login_retry_count[2]; 773 774 uint8_t prio_request_q_outpointer[2]; 775 776 uint8_t response_q_length[2]; 777 uint8_t request_q_length[2]; 778 779 uint8_t link_down_on_nos[2]; 780 781 uint8_t prio_request_q_length[2]; 782 uint8_t request_q_address[8]; 783 uint8_t response_q_address[8]; 784 uint8_t prio_request_q_address[8]; 785 uint8_t reserved_2[8]; 786 uint8_t atio_q_inpointer[2]; 787 uint8_t atio_q_length[2]; 788 uint8_t atio_q_address[8]; 789 790 uint8_t interrupt_delay_timer[2]; /* 100us per */ 791 uint8_t login_timeout[2]; 792 /* 793 * BIT 0 = Hard Assigned Loop ID 794 * BIT 1 = Enable Fairness 795 * BIT 2 = Enable Full-Duplex 796 * BIT 3 = Reserved 797 * BIT 4 = Target Mode Enable 798 * BIT 5 = Initiator Mode Disable 799 * BIT 6 = Reserved 800 * BIT 7 = Reserved 801 * 802 * BIT 8 = Reserved 803 * BIT 9 = Disable Initial LIP 804 * BIT 10 = Descending Loop ID Search 805 * BIT 11 = Previous Assigned Loop ID 806 * BIT 12 = Reserved 807 * BIT 13 = Full Login after LIP 808 * BIT 14 = Node Name Option 809 * BIT 15-31 = Reserved 810 */ 811 uint8_t firmware_options_1[4]; 812 813 /* 814 * BIT 0 = Operation Mode bit 0 815 * BIT 1 = Operation Mode bit 1 816 * BIT 2 = Operation Mode bit 2 817 * BIT 3 = Operation Mode bit 3 818 * BIT 4 = Connection Options bit 0 819 * BIT 5 = Connection Options bit 1 820 * BIT 6 = Connection Options bit 2 821 * BIT 7 = Enable Non part on LIHA failure 822 * 823 * BIT 8 = Enable Class 2 824 * BIT 9 = Enable ACK0 825 * BIT 10 = Reserved 826 * BIT 11 = Enable FC-SP Security 827 * BIT 12 = FC Tape Enable 828 * BIT 13-31 = Reserved 829 */ 830 uint8_t firmware_options_2[4]; 831 832 /* 833 * BIT 0 = Reserved 834 * BIT 1 = Soft ID only 835 * BIT 2 = Reserved 836 * BIT 3 = Reserved 837 * BIT 4 = FCP RSP Payload bit 0 838 * BIT 5 = FCP RSP Payload bit 1 839 * BIT 6 = Enable Rec Out-of-Order data frame handling 840 * BIT 7 = Disable Automatic PLOGI on Local Loop 841 * 842 * BIT 8 = Reserved 843 * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative 844 * offset handling 845 * BIT 10 = Reserved 846 * BIT 11 = Reserved 847 * BIT 12 = Reserved 848 * BIT 13 = Data Rate bit 0 849 * BIT 14 = Data Rate bit 1 850 * BIT 15 = Data Rate bit 2 851 * BIT 16 = 75-ohm Termination Select 852 * BIT 17-31 = Reserved 853 */ 854 uint8_t firmware_options_3[4]; 855 856 uint8_t reserved_3[24]; 857 858 /* 859 * Multi-ID firmware. 860 */ 861 uint8_t vp_count[2]; 862 863 /* 864 * BIT 1 = Allows mode 2 connection option 865 */ 866 uint8_t global_vp_option[2]; 867 868 ql_vp_cfg_t vpc[MAX_25_VIRTUAL_PORTS+1]; 869 } ql_init_24xx_cb_t; 870 871 typedef union ql_comb_init_cb { 872 ql_init_cb_t cb; 873 ql_init_24xx_cb_t cb24; 874 } ql_comb_init_cb_t; 875 876 /* 877 * ISP IP Initialization Control Block. 878 * Little endian except where noted. 879 */ 880 #define IP_ICB_VERSION 1 881 typedef struct ql_ip_init_cb { 882 uint8_t version; 883 uint8_t reserved; 884 885 /* 886 * LSB BIT 0 = receive_buffer_address_length 887 * LSB BIT 1 = fast post broadcast received 888 * LSB BIT 2 = allow out of receive buffers AE 889 */ 890 uint8_t ip_firmware_options[2]; 891 uint8_t ip_header_size[2]; 892 uint8_t mtu_size[2]; /* max value is 65280 */ 893 uint8_t buf_size[2]; 894 uint8_t reserved_1[8]; 895 uint8_t queue_size[2]; /* 8-1024 */ 896 uint8_t low_water_mark[2]; 897 uint8_t queue_address[8]; 898 uint8_t queue_inpointer[2]; 899 uint8_t fast_post_reg_count[2]; /* 0-14 */ 900 uint8_t cc[2]; 901 uint8_t reserved_2[28]; 902 } ql_ip_init_cb_t; 903 904 #define IP_ICB_24XX_VERSION 1 905 typedef struct ql_ip_init_24xx_cb { 906 uint8_t version; 907 uint8_t reserved; 908 /* 909 * LSB BIT 2 = allow out of receive buffers AE 910 */ 911 uint8_t ip_firmware_options[2]; 912 uint8_t ip_header_size[2]; 913 uint8_t mtu_size[2]; 914 uint8_t buf_size[2]; 915 uint8_t reserved_1[10]; 916 uint8_t low_water_mark[2]; 917 uint8_t reserved_3[12]; 918 uint8_t cc[2]; 919 uint8_t reserved_2[28]; 920 } ql_ip_init_24xx_cb_t; 921 922 typedef union ql_comb_ip_init_cb { 923 ql_ip_init_cb_t cb; 924 ql_ip_init_24xx_cb_t cb24; 925 } ql_comb_ip_init_cb_t; 926 927 /* 928 * f/w module table 929 */ 930 struct fw_table { 931 uint16_t fw_class; 932 int8_t *fw_version; 933 }; 934 935 /* 936 * aif function table 937 */ 938 typedef struct ql_ifunc { 939 uint_t (*ifunc)(); 940 } ql_ifunc_t; 941 942 #define QL_MSIX_AIF 0x0 943 #define QL_MSIX_RSPQ 0x1 944 #define QL_MSIX_MAXAIF QL_MSIX_RSPQ + 1 945 946 /* 947 * DMA memory type. 948 */ 949 typedef enum mem_alloc_type { 950 UNKNOWN_MEMORY, 951 TASK_MEMORY, 952 LITTLE_ENDIAN_DMA, 953 BIG_ENDIAN_DMA, 954 KERNEL_MEM, 955 NO_SWAP_DMA, 956 STRUCT_BUF_MEMORY 957 } mem_alloc_type_t; 958 959 /* 960 * DMA memory alignment type. 961 */ 962 typedef enum men_align_type { 963 QL_DMA_DATA_ALIGN, 964 QL_DMA_RING_ALIGN, 965 } mem_alignment_t; 966 967 /* 968 * DMA memory object. 969 */ 970 typedef struct dma_mem { 971 uint64_t alignment; 972 void *bp; 973 ddi_dma_cookie_t *cookies; 974 ddi_acc_handle_t acc_handle; 975 ddi_dma_handle_t dma_handle; 976 ddi_dma_cookie_t cookie; 977 uint32_t cookie_count; 978 uint32_t size; 979 uint32_t memflags; 980 mem_alloc_type_t type; 981 uint32_t flags; /* Solaris DMA flags. */ 982 } dma_mem_t; 983 984 /* 985 * dma_mem_t memflags defines 986 */ 987 #define MFLG_32BIT_ONLY BIT_0 988 989 /* 990 * 24 bit port ID type definition. 991 */ 992 typedef union { 993 struct { 994 uint8_t d_id[3]; 995 uint8_t rsvd_1; 996 }r; 997 998 uint32_t b24 : 24; 999 1000 #if defined(_BIT_FIELDS_LTOH) 1001 struct { 1002 uint8_t al_pa; 1003 uint8_t area; 1004 uint8_t domain; 1005 uint8_t rsvd_1; 1006 }b; 1007 #elif defined(_BIT_FIELDS_HTOL) 1008 struct { 1009 uint8_t domain; 1010 uint8_t area; 1011 uint8_t al_pa; 1012 uint8_t rsvd_1; 1013 }b; 1014 #else 1015 #error One of _BIT_FIELDS_LTOH or _BIT_FIELDS_HTOL must be defined 1016 #endif 1017 } port_id_t; 1018 1019 /* 1020 * Link list definitions. 1021 */ 1022 typedef struct ql_link { 1023 struct ql_link *prev; 1024 struct ql_link *next; 1025 void *base_address; 1026 struct ql_head *head; /* the queue this link is on */ 1027 } ql_link_t; 1028 1029 typedef struct ql_head { 1030 ql_link_t *first; 1031 ql_link_t *last; 1032 } ql_head_t; 1033 1034 /* 1035 * This is the driver target command structure 1036 */ 1037 typedef struct tgt_cmd { 1038 /* Command link. */ 1039 ql_link_t cmd; 1040 1041 uint8_t type; 1042 uint8_t initiator_id_l; 1043 uint8_t initiator_id_h; 1044 uint16_t rx_id; 1045 1046 uint16_t status; 1047 uint8_t task_flags_l; 1048 uint8_t task_flags_h; 1049 uint8_t execution_codes; 1050 } tgt_cmd_t; 1051 1052 /* Target cmd states */ 1053 #define TGT_CMD_RECEIVED 0x00 1054 #define TGT_CMD_SENT_UP 0x01 1055 #define TGT_CMD_IN_FW 0x02 1056 1057 /* 1058 * This is the per-command structure 1059 */ 1060 typedef struct ql_srb { 1061 /* Command link. */ 1062 ql_link_t cmd; 1063 1064 /* Watchdog link and timer. */ 1065 ql_link_t wdg; 1066 time_t wdg_q_time; 1067 time_t init_wdg_q_time; 1068 uint16_t isp_timeout; 1069 1070 /* FCA and FC Transport data. */ 1071 fc_packet_t *pkt; 1072 struct ql_adapter_state *ha; 1073 uint32_t magic_number; 1074 1075 /* unsolicited buffer context. */ 1076 dma_mem_t ub_buffer; 1077 uint32_t ub_type; 1078 uint32_t ub_size; 1079 1080 /* FCP command. */ 1081 fcp_cmd_t *fcp; 1082 1083 /* Request sense. */ 1084 uint32_t request_sense_length; 1085 caddr_t request_sense_ptr; 1086 1087 /* Device queue pointer. */ 1088 struct ql_lun *lun_queue; 1089 1090 /* Target command pointer. */ 1091 tgt_cmd_t *tgt_cmd; 1092 1093 /* Command state/status flags. */ 1094 volatile uint32_t flags; 1095 1096 /* Command IOCB context. */ 1097 void (*iocb)(struct ql_adapter_state *, 1098 struct ql_srb *, void *); 1099 uint32_t handle; 1100 uint16_t req_cnt; 1101 uint8_t retry_count; 1102 } ql_srb_t; 1103 1104 #define SRB_ISP_STARTED BIT_0 /* Command sent to ISP. */ 1105 #define SRB_ISP_COMPLETED BIT_1 /* ISP finished with command. */ 1106 #define SRB_RETRY BIT_2 /* Driver retrying command. */ 1107 #define SRB_POLL BIT_3 /* Poll for completion. */ 1108 #define SRB_WATCHDOG_ENABLED BIT_4 /* Command on watchdog list. */ 1109 #define SRB_ABORT BIT_5 /* SRB to be aborted. */ 1110 #define SRB_UB_IN_FCA BIT_6 /* FCA holds unsolicited buffer */ 1111 #define SRB_UB_IN_ISP BIT_7 /* ISP holds unsolicited buffer */ 1112 #define SRB_UB_CALLBACK BIT_8 /* Unsolicited callback needed. */ 1113 #define SRB_UB_RSCN BIT_9 /* Unsolicited RSCN callback. */ 1114 #define SRB_UB_FCP BIT_10 /* Unsolicited RSCN callback. */ 1115 #define SRB_FCP_CMD_PKT BIT_11 /* FCP command type packet. */ 1116 #define SRB_FCP_DATA_PKT BIT_12 /* FCP data type packet. */ 1117 #define SRB_FCP_RSP_PKT BIT_13 /* FCP response type packet. */ 1118 #define SRB_IP_PKT BIT_14 /* IP type packet. */ 1119 #define SRB_GENERIC_SERVICES_PKT BIT_15 /* Generic services type packet */ 1120 #define SRB_COMMAND_TIMEOUT BIT_16 /* Command timed out. */ 1121 #define SRB_ABORTING BIT_17 /* SRB aborting. */ 1122 #define SRB_IN_DEVICE_QUEUE BIT_18 /* In Device Queue */ 1123 #define SRB_IN_TOKEN_ARRAY BIT_19 /* In Token Array */ 1124 #define SRB_UB_FREE_REQUESTED BIT_20 /* UB Free requested */ 1125 #define SRB_UB_ACQUIRED BIT_21 /* UB selected for upcall */ 1126 #define SRB_MS_PKT BIT_22 /* Management Service pkt */ 1127 1128 /* 1129 * This byte will be used to define flags for the LUN on the target. 1130 * Presently, we have untagged-command as one flag. Others can be 1131 * added later, if needed. 1132 */ 1133 typedef struct tgt_lun_flags { 1134 uint8_t 1135 untagged_pending:1, 1136 unused_bits:7; 1137 } tgt_lun_flags_t; 1138 1139 #define QL_IS_UNTAGGED_PENDING(q, lun_num) \ 1140 ((q->lun_flags[lun_num].untagged_pending == TRUE) ? 1 : 0) 1141 #define QL_SET_UNTAGGED_PENDING(q, lun_num) \ 1142 (q->lun_flags[lun_num].untagged_pending = TRUE) 1143 #define QL_CLEAR_UNTAGGED_PENDING(q, lun_num) \ 1144 (q->lun_flags[lun_num].untagged_pending = FALSE) 1145 1146 /* 1147 * Fibre Channel LUN Queue structure 1148 */ 1149 typedef struct ql_lun { 1150 /* Head command link. */ 1151 ql_head_t cmd; 1152 1153 struct ql_target *target_queue; 1154 1155 uint32_t flags; 1156 1157 /* LUN execution throttle. */ 1158 uint16_t lun_outcnt; 1159 1160 uint16_t lun_no; 1161 1162 ql_link_t link; 1163 } ql_lun_t; 1164 1165 /* 1166 * LUN Queue flags 1167 */ 1168 #define LQF_UNTAGGED_PENDING BIT_0 1169 1170 /* 1171 * Fibre Channel Device Queue structure 1172 */ 1173 typedef struct ql_target { 1174 /* Device queue lock. */ 1175 kmutex_t mutex; 1176 1177 /* Head target command link. */ 1178 ql_head_t tgt_cmd; 1179 1180 volatile uint32_t flags; 1181 port_id_t d_id; 1182 uint16_t loop_id; 1183 volatile uint16_t outcnt; /* # of cmds running in ISP */ 1184 uint32_t iidma_rate; 1185 1186 1187 /* Device link. */ 1188 ql_link_t device; 1189 1190 /* Head watchdog link. */ 1191 ql_head_t wdg; 1192 1193 /* Unsolicited buffer IP data. */ 1194 uint32_t ub_frame_ro; 1195 uint16_t ub_sequence_length; 1196 uint16_t ub_loop_id; 1197 uint8_t ub_total_seg_cnt; 1198 uint8_t ub_seq_cnt; 1199 uint8_t ub_seq_id; 1200 1201 /* Port down retry counter. */ 1202 uint16_t port_down_retry_count; 1203 uint16_t qfull_retry_count; 1204 1205 /* logout sent state */ 1206 uint8_t logout_sent; 1207 1208 /* Data from Port database matches machine type. */ 1209 uint8_t master_state; 1210 uint8_t slave_state; 1211 port_id_t hard_addr; 1212 uint8_t port_name[8]; 1213 uint8_t node_name[8]; 1214 uint16_t cmn_features; 1215 uint16_t conc_sequences; 1216 uint16_t relative_offset; 1217 uint16_t class3_recipient_ctl; 1218 uint16_t class3_rcv_data_size; 1219 uint16_t class3_conc_sequences; 1220 uint16_t class3_open_sequences_per_exch; 1221 uint16_t prli_payload_length; 1222 uint16_t prli_svc_param_word_0; 1223 uint16_t prli_svc_param_word_3; 1224 1225 /* LUN context. */ 1226 ql_head_t lun_queues; 1227 ql_lun_t *last_lun_queue; 1228 } ql_tgt_t; 1229 1230 /* 1231 * Target Queue flags 1232 */ 1233 #define TQF_TAPE_DEVICE BIT_0 1234 #define TQF_QUEUE_SUSPENDED BIT_1 /* Queue suspended. */ 1235 #define TQF_FABRIC_DEVICE BIT_2 1236 #define TQF_INITIATOR_DEVICE BIT_3 1237 #define TQF_RSCN_RCVD BIT_4 1238 #define TQF_NEED_AUTHENTICATION BIT_5 1239 #define TQF_PLOGI_PROGRS BIT_6 1240 #define TQF_IIDMA_NEEDED BIT_7 1241 1242 /* 1243 * iiDMA 1244 */ 1245 #define IIDMA_RATE_INIT 0xffffffff /* init state */ 1246 #define IIDMA_RATE_NDEF 0xfffffffe /* not defined in conf file */ 1247 #define IIDMA_RATE_1GB 0x0 1248 #define IIDMA_RATE_2GB 0x1 1249 #define IIDMA_RATE_4GB 0x3 1250 #define IIDMA_RATE_8GB 0x4 1251 #define IIDMA_RATE_MAX IIDMA_RATE_8GB 1252 1253 /* 1254 * Kernel statistic structure definitions. 1255 */ 1256 typedef struct ql_device_stat { 1257 int logouts_recvd; 1258 int task_mgmt_failures; 1259 int data_ro_mismatches; 1260 int dl_len_mismatches; 1261 } ql_device_stat_t; 1262 1263 typedef struct ql_adapter_24xx_stat { 1264 int version; /* version of this struct */ 1265 int lip_count; /* lips forced */ 1266 int ncmds; /* outstanding commands */ 1267 ql_adapter_revlvl_t revlvl; /* adapter revision levels */ 1268 ql_device_stat_t d_stats[MAX_24_FIBRE_DEVICES]; /* per device stats */ 1269 } ql_adapter_stat_t; 1270 1271 /* 1272 * Firmware code segment. 1273 */ 1274 #define MAX_RISC_CODE_SEGMENTS 3 1275 typedef struct fw_code { 1276 caddr_t code; 1277 uint32_t addr; 1278 uint32_t length; 1279 } ql_fw_code_t; 1280 1281 /* diagnostic els ECHO defines */ 1282 #define QL_ECHO_CMD 0x10000000 /* echo opcode */ 1283 #define QL_ECHO_CMD_LENGTH 220 /* command length */ 1284 1285 /* DUMP state flags. */ 1286 #define QL_DUMPING BIT_0 1287 #define QL_DUMP_VALID BIT_1 1288 #define QL_DUMP_UPLOADED BIT_2 1289 1290 /* f/w trace sizes */ 1291 #define FWEXTSIZE (0x4000 * 4) /* bytes - 16kb multiples */ 1292 #define FWFCESIZE (0x4000 * 4) /* bytes - 16kb multiples */ 1293 1294 typedef struct el_trace_desc { 1295 kmutex_t mutex; 1296 uint16_t next; 1297 uint32_t trace_buffer_size; 1298 char *trace_buffer; 1299 } el_trace_desc_t; 1300 1301 1302 /* 1303 * ql attach progress indication 1304 */ 1305 #define QL_SOFT_STATE_ALLOCED BIT_0 1306 #define QL_REGS_MAPPED BIT_1 1307 #define QL_HBA_BUFFER_SETUP BIT_2 1308 #define QL_MUTEX_CV_INITED BIT_3 1309 #define QL_INTR_ADDED BIT_4 1310 #define QL_CONFIG_SPACE_SETUP BIT_5 1311 #define QL_TASK_DAEMON_STARTED BIT_6 1312 #define QL_KSTAT_CREATED BIT_7 1313 #define QL_MINOR_NODE_CREATED BIT_8 1314 #define QL_FCA_TRAN_ALLOCED BIT_9 1315 #define QL_FCA_ATTACH_DONE BIT_10 1316 #define QL_IOMAP_IOBASE_MAPPED BIT_11 1317 1318 /* Device queue head list size (based on AL_PA address). */ 1319 #define DEVICE_HEAD_LIST_SIZE 0x81 1320 1321 /* 1322 * Adapter state structure. 1323 */ 1324 typedef struct ql_adapter_state { 1325 ql_link_t hba; 1326 1327 kmutex_t mutex; 1328 volatile uint32_t flags; /* State flags. */ 1329 uint32_t state; 1330 port_id_t d_id; 1331 uint16_t loop_id; 1332 uint8_t topology; 1333 uint16_t sfp_stat; 1334 1335 uint16_t idle_timer; 1336 uint8_t loop_down_abort_time; 1337 uint8_t port_retry_timer; 1338 uint8_t loop_down_timer; 1339 uint8_t watchdog_timer; 1340 uint16_t r_a_tov; /* 2 * R_A_TOV + 5 */ 1341 1342 /* Task Daemon context. */ 1343 callb_cpr_t cprinfo; 1344 kmutex_t task_daemon_mutex; 1345 kcondvar_t cv_dr_suspended; 1346 kcondvar_t cv_task_daemon; 1347 volatile uint32_t task_daemon_flags; 1348 ql_head_t callback_queue; 1349 1350 /* Interrupt context. */ 1351 kmutex_t intr_mutex; 1352 uint8_t *iobase; 1353 uint8_t rev_id; 1354 uint16_t device_id; 1355 uint16_t subsys_id; 1356 uint16_t subven_id; 1357 uint16_t ven_id; 1358 uint16_t fw_class; 1359 ql_srb_t *status_srb; 1360 volatile uint8_t intr_claimed; 1361 1362 /* 1363 * ISP request queue, response queue, mailbox buffer and 1364 * IP receive queue buffer. 1365 */ 1366 dma_mem_t hba_buf; 1367 1368 /* ISP request queue context. */ 1369 kmutex_t req_ring_mutex; 1370 struct cmd_entry *request_ring_bp; 1371 struct cmd_entry *request_ring_ptr; 1372 uint64_t request_dvma; 1373 uint16_t req_ring_index; 1374 uint16_t req_q_cnt; /* # of available entries. */ 1375 ql_head_t pending_cmds; 1376 ql_srb_t **outstanding_cmds; 1377 uint16_t osc_index; 1378 1379 /* ISP response queue context. */ 1380 struct sts_entry *response_ring_bp; 1381 struct sts_entry *response_ring_ptr; 1382 uint64_t response_dvma; 1383 uint16_t rsp_ring_index; 1384 uint16_t isp_rsp_index; 1385 1386 /* Mailbox context. */ 1387 kmutex_t mbx_mutex; 1388 caddr_t mbx_bp; 1389 struct mbx_cmd *mcp; 1390 kcondvar_t cv_mbx_wait; 1391 kcondvar_t cv_mbx_intr; 1392 volatile uint8_t mailbox_flags; 1393 1394 /* ISP receive buffer queue context. */ 1395 ql_tgt_t *rcv_dev_q; 1396 struct rcvbuf *rcvbuf_ring_bp; 1397 struct rcvbuf *rcvbuf_ring_ptr; 1398 uint64_t rcvbuf_dvma; 1399 uint16_t rcvbuf_ring_index; 1400 1401 /* Unsolicited buffer data. */ 1402 uint16_t ub_outcnt; 1403 uint8_t ub_seq_id; 1404 uint8_t ub_command_count; 1405 uint8_t ub_notify_count; 1406 uint32_t ub_allocated; 1407 kmutex_t ub_mutex; 1408 kcondvar_t cv_ub; 1409 fc_unsol_buf_t **ub_array; 1410 1411 /* Head of device queue list. */ 1412 ql_head_t *dev; 1413 1414 /* Kernel statistics. */ 1415 kstat_t *k_stats; 1416 ql_adapter_stat_t *adapter_stats; 1417 1418 /* Solaris adapter configuration data */ 1419 ddi_acc_handle_t dev_handle; 1420 ddi_acc_handle_t pci_handle; /* config space */ 1421 ddi_acc_handle_t iomap_dev_handle; 1422 caddr_t iomap_iobase; 1423 dev_info_t *dip; 1424 ddi_iblock_cookie_t iblock_cookie; 1425 fc_fca_tran_t *tran; 1426 uint32_t instance; 1427 int8_t *devpath; 1428 uint32_t fru_hba_index; 1429 uint32_t fru_port_index; 1430 uint8_t adapInfo[18]; 1431 1432 /* Adapter context */ 1433 la_els_logi_t loginparams; 1434 fc_fca_bind_info_t bind_info; 1435 ddi_modhandle_t fw_module; 1436 uint16_t fw_major_version; 1437 uint16_t fw_minor_version; 1438 uint16_t fw_subminor_version; 1439 uint16_t fw_attributes; 1440 uint32_t fw_ext_memory_size; 1441 uint32_t parity_pause_errors; 1442 uint16_t parity_hccr_err; 1443 uint32_t parity_stat_err; 1444 reg_off_t *reg_off; 1445 caddr_t risc_code; 1446 uint32_t risc_code_size; 1447 ql_fw_code_t risc_fw[MAX_RISC_CODE_SEGMENTS]; 1448 uint32_t risc_dump_size; 1449 void (*fcp_cmd)(struct ql_adapter_state *, 1450 ql_srb_t *, void *); 1451 void (*ip_cmd)(struct ql_adapter_state *, 1452 ql_srb_t *, void *); 1453 void (*ms_cmd)(struct ql_adapter_state *, 1454 ql_srb_t *, void *); 1455 void (*ctio_cmd)(struct ql_adapter_state *, 1456 ql_srb_t *, void *); 1457 uint8_t cmd_segs; 1458 uint8_t cmd_cont_segs; 1459 1460 /* Target mode context. */ 1461 tgt_cmd_t *ql_nack; 1462 kmutex_t ql_nack_mtx; 1463 1464 /* NVRAM configuration data */ 1465 uint32_t cfg_flags; 1466 ql_comb_init_cb_t init_ctrl_blk; 1467 ql_comb_ip_init_cb_t ip_init_ctrl_blk; 1468 uint16_t nvram_version; 1469 uint16_t adapter_features; 1470 uint32_t fw_transfer_size; 1471 uint16_t execution_throttle; 1472 uint16_t port_down_retry_count; 1473 uint8_t port_down_retry_delay; 1474 uint8_t qfull_retry_count; 1475 uint8_t qfull_retry_delay; 1476 uint16_t serdes_param[4]; 1477 uint8_t loop_reset_delay; 1478 1479 /* Power management context. */ 1480 kmutex_t pm_mutex; 1481 uint32_t busy; 1482 uint8_t power_level; 1483 uint8_t pm_capable; 1484 uint8_t config_saved; 1485 uint8_t lip_on_panic; 1486 port_id_t port_hard_address; 1487 1488 /* sbus card data */ 1489 caddr_t sbus_fpga_iobase; 1490 ddi_acc_handle_t sbus_fpga_dev_handle; 1491 ddi_acc_handle_t sbus_config_handle; 1492 caddr_t sbus_config_base; 1493 1494 /* XIOCTL context pointer. */ 1495 struct ql_xioctl *xioctl; 1496 1497 kmutex_t cache_mutex; 1498 struct ql_fcache *fcache; 1499 int8_t *vcache; 1500 1501 /* AIF (Advanced Interrupt Framework) support */ 1502 ddi_intr_handle_t *htable; 1503 uint32_t hsize; 1504 int32_t intr_cnt; 1505 uint32_t intr_pri; 1506 int32_t intr_cap; 1507 uint32_t iflags; 1508 1509 /* PCI maximum read request override */ 1510 uint16_t pci_max_read_req; 1511 1512 /* port manage mutex */ 1513 kmutex_t portmutex; 1514 uint16_t maximum_luns_per_target; 1515 1516 /* f/w dump mutex */ 1517 uint32_t ql_dump_size; 1518 uint32_t ql_dump_state; 1519 void *ql_dump_ptr; 1520 kmutex_t dump_mutex; 1521 1522 uint8_t fwwait; 1523 1524 dma_mem_t fwexttracebuf; /* extended trace */ 1525 dma_mem_t fwfcetracebuf; /* event trace */ 1526 uint32_t fwfcetraceopt; 1527 uint32_t flash_errlog_start; /* 32bit word addr */ 1528 uint32_t flash_errlog_ptr; /* 32bit word addr */ 1529 1530 /* Virtual port context. */ 1531 fca_port_attrs_t *pi_attrs; 1532 struct ql_adapter_state *pha; 1533 struct ql_adapter_state *vp_next; 1534 uint8_t vp_index; 1535 1536 uint16_t free_loop_id; 1537 1538 el_trace_desc_t *el_trace_desc; 1539 } ql_adapter_state_t; 1540 1541 /* 1542 * adapter state flags 1543 */ 1544 #define FCA_BOUND BIT_0 1545 #define QL_OPENED BIT_1 1546 #define ONLINE BIT_2 1547 #define INTERRUPTS_ENABLED BIT_3 1548 #define ABORT_CMDS_LOOP_DOWN_TMO BIT_4 1549 #define POINT_TO_POINT BIT_5 1550 #define IP_ENABLED BIT_6 1551 #define IP_INITIALIZED BIT_7 1552 #define TARGET_MODE_INITIALIZED BIT_8 1553 #define ADAPTER_SUSPENDED BIT_9 1554 #define ADAPTER_TIMER_BUSY BIT_10 1555 #define PARITY_ERROR BIT_11 1556 #define FLASH_ERRLOG_MARKER BIT_12 1557 #define VP_ENABLED BIT_13 1558 #define FDISC_ENABLED BIT_14 1559 #define MENLO_LOGIN_OPERATIONAL BIT_15 1560 1561 /* 1562 * task daemon flags 1563 */ 1564 #define TASK_DAEMON_STOP_FLG BIT_0 1565 #define TASK_DAEMON_SLEEPING_FLG BIT_1 1566 #define TASK_DAEMON_ALIVE_FLG BIT_2 1567 #define TASK_DAEMON_IDLE_CHK_FLG BIT_3 1568 #define SUSPENDED_WAKEUP_FLG BIT_4 1569 #define FC_STATE_CHANGE BIT_5 1570 #define NEED_UNSOLICITED_BUFFERS BIT_6 1571 #define RESET_MARKER_NEEDED BIT_7 1572 #define RESET_ACTIVE BIT_8 1573 #define ISP_ABORT_NEEDED BIT_9 1574 #define ABORT_ISP_ACTIVE BIT_10 1575 #define LOOP_RESYNC_NEEDED BIT_11 1576 #define LOOP_RESYNC_ACTIVE BIT_12 1577 #define LOOP_DOWN BIT_13 1578 #define DRIVER_STALL BIT_14 1579 #define COMMAND_WAIT_NEEDED BIT_15 1580 #define COMMAND_WAIT_ACTIVE BIT_16 1581 #define STATE_ONLINE BIT_17 1582 #define ABORT_QUEUES_NEEDED BIT_18 1583 #define TASK_DAEMON_STALLED_FLG BIT_19 1584 #define TASK_THREAD_CALLED BIT_20 1585 #define FIRMWARE_UP BIT_21 1586 #define LIP_RESET_PENDING BIT_22 1587 #define FIRMWARE_LOADED BIT_23 1588 #define RSCN_UPDATE_NEEDED BIT_24 1589 #define HANDLE_PORT_BYPASS_CHANGE BIT_25 1590 #define PORT_RETRY_NEEDED BIT_26 1591 #define TASK_DAEMON_POWERING_DOWN BIT_27 1592 #define TD_IIDMA_NEEDED BIT_28 1593 #define SEND_PLOGI BIT_29 1594 1595 /* 1596 * Mailbox flags 1597 */ 1598 #define MBX_WANT_FLG BIT_0 1599 #define MBX_BUSY_FLG BIT_1 1600 #define MBX_INTERRUPT BIT_2 1601 #define MBX_ABORT BIT_3 1602 1603 /* 1604 * Configuration flags 1605 */ 1606 #define CFG_ENABLE_HARD_ADDRESS BIT_0 1607 #define CFG_ENABLE_64BIT_ADDRESSING BIT_1 1608 #define CFG_ENABLE_LIP_RESET BIT_2 1609 #define CFG_ENABLE_FULL_LIP_LOGIN BIT_3 1610 #define CFG_ENABLE_TARGET_RESET BIT_4 1611 #define CFG_ENABLE_LINK_DOWN_REPORTING BIT_5 1612 #define CFG_ENABLE_TARGET_MODE BIT_6 1613 #define CFG_ENABLE_FCP_2_SUPPORT BIT_7 1614 #define CFG_MULTI_CHIP_ADAPTER BIT_8 1615 #define CFG_SBUS_CARD BIT_9 1616 #define CFG_CTRL_2300 BIT_10 1617 #define CFG_CTRL_6322 BIT_11 1618 #define CFG_CTRL_2200 BIT_12 1619 #define CFG_CTRL_2422 BIT_13 1620 #define CFG_CTRL_25XX BIT_14 1621 #define CFG_ENABLE_EXTENDED_LOGGING BIT_15 1622 #define CFG_DISABLE_RISC_CODE_LOAD BIT_16 1623 #define CFG_SET_CACHE_LINE_SIZE_1 BIT_17 1624 #define CFG_TARGET_MODE_ENABLE BIT_18 1625 #define CFG_EXT_FW_INTERFACE BIT_19 1626 #define CFG_LOAD_FLASH_FW BIT_20 1627 #define CFG_DUMP_MAILBOX_TIMEOUT BIT_21 1628 #define CFG_DUMP_ISP_SYSTEM_ERROR BIT_22 1629 #define CFG_DUMP_DRIVER_COMMAND_TIMEOUT BIT_23 1630 #define CFG_DUMP_LOOP_OFFLINE_TIMEOUT BIT_24 1631 #define CFG_ENABLE_FWEXTTRACE BIT_25 1632 #define CFG_ENABLE_FWFCETRACE BIT_26 1633 #define CFG_FW_MISMATCH BIT_27 1634 #define CFG_CTRL_MENLO BIT_28 1635 #define CFG_DISABLE_EXTENDED_LOGGING_TRACE BIT_29 1636 1637 #define CFG_CTRL_2425 (CFG_CTRL_2422 | CFG_CTRL_25XX) 1638 #define CFG_IST(ha, cfgflags) (ha->cfg_flags & cfgflags) 1639 1640 /* 1641 * Interrupt configuration flags 1642 */ 1643 #define IFLG_INTR_LEGACY BIT_0 1644 #define IFLG_INTR_FIXED BIT_1 1645 #define IFLG_INTR_MSI BIT_2 1646 #define IFLG_INTR_MSIX BIT_3 1647 1648 #define IFLG_INTR_AIF (IFLG_INTR_MSI | IFLG_INTR_FIXED | IFLG_INTR_MSIX) 1649 1650 /* 1651 * Macros to help code, maintain, etc. 1652 */ 1653 #define LSB(x) (uint8_t)(x) 1654 #define MSB(x) (uint8_t)((uint16_t)(x) >> 8) 1655 #define MSW(x) (uint16_t)((uint32_t)(x) >> 16) 1656 #define LSW(x) (uint16_t)(x) 1657 #define LSD(x) (uint32_t)(x) 1658 #define MSD(x) (uint32_t)((uint64_t)(x) >> 32) 1659 1660 #define SHORT_TO_LONG(lsw, msw) (uint32_t)((uint16_t)msw << 16 | (uint16_t)lsw) 1661 #define CHAR_TO_SHORT(lsb, msb) (uint16_t)((uint8_t)msb << 8 | (uint8_t)lsb) 1662 #define CHAR_TO_LONG(lsb, b1, b2, msb) \ 1663 (uint32_t)(SHORT_TO_LONG(CHAR_TO_SHORT(lsb, b1), \ 1664 CHAR_TO_SHORT(b2, msb))) 1665 1666 /* Little endian machine correction defines. */ 1667 #ifdef _LITTLE_ENDIAN 1668 #define LITTLE_ENDIAN_16(x) 1669 #define LITTLE_ENDIAN_24(x) 1670 #define LITTLE_ENDIAN_32(x) 1671 #define LITTLE_ENDIAN_64(x) 1672 #define LITTLE_ENDIAN(bp, bytes) 1673 #define BIG_ENDIAN_16(x) ql_chg_endian((uint8_t *)x, 2) 1674 #define BIG_ENDIAN_24(x) ql_chg_endian((uint8_t *)x, 3) 1675 #define BIG_ENDIAN_32(x) ql_chg_endian((uint8_t *)x, 4) 1676 #define BIG_ENDIAN_64(x) ql_chg_endian((uint8_t *)x, 8) 1677 #define BIG_ENDIAN(bp, bytes) ql_chg_endian((uint8_t *)bp, bytes) 1678 #endif /* _LITTLE_ENDIAN */ 1679 1680 /* Big endian machine correction defines. */ 1681 #ifdef _BIG_ENDIAN 1682 #define LITTLE_ENDIAN_16(x) ql_chg_endian((uint8_t *)x, 2) 1683 #define LITTLE_ENDIAN_24(x) ql_chg_endian((uint8_t *)x, 3) 1684 #define LITTLE_ENDIAN_32(x) ql_chg_endian((uint8_t *)x, 4) 1685 #define LITTLE_ENDIAN_64(x) ql_chg_endian((uint8_t *)x, 8) 1686 #define LITTLE_ENDIAN(bp, bytes) ql_chg_endian((uint8_t *)bp, bytes) 1687 #define BIG_ENDIAN_16(x) 1688 #define BIG_ENDIAN_24(x) 1689 #define BIG_ENDIAN_32(x) 1690 #define BIG_ENDIAN_64(x) 1691 #define BIG_ENDIAN(bp, bytes) 1692 #endif /* _BIG_ENDIAN */ 1693 1694 #define LOCAL_LOOP_ID(x) (x <= LAST_LOCAL_LOOP_ID) 1695 1696 #define FABRIC_LOOP_ID(x) (x == FL_PORT_LOOP_ID || \ 1697 x == SIMPLE_NAME_SERVER_LOOP_ID) 1698 1699 #define SNS_LOOP_ID(x) (x >= SNS_FIRST_LOOP_ID && \ 1700 x <= SNS_LAST_LOOP_ID) 1701 1702 #define BROADCAST_LOOP_ID(x) (x == IP_BROADCAST_LOOP_ID) 1703 1704 #define VALID_LOOP_ID(x) (LOCAL_LOOP_ID(x) || SNS_LOOP_ID(x) || \ 1705 FABRIC_LOOP_ID(x) || BROADCAST_LOOP_ID(x)) 1706 1707 #define VALID_N_PORT_HDL(x) (x <= LAST_N_PORT_HDL || \ 1708 (x >= SNS_24XX_HDL && x <= BROADCAST_24XX_HDL)) 1709 1710 #define VALID_DEVICE_ID(ha, x) \ 1711 (ha->cfg_flags & (CFG_CTRL_2422 | CFG_CTRL_25XX) ? \ 1712 VALID_N_PORT_HDL(x) : VALID_LOOP_ID(x)) 1713 1714 #define VALID_TARGET_ID(ha, x) \ 1715 (ha->cfg_flags & (CFG_CTRL_2422 | CFG_CTRL_25XX) ? \ 1716 (x <= LAST_N_PORT_HDL) : (LOCAL_LOOP_ID(x) || SNS_LOOP_ID(x))) 1717 1718 #define RESERVED_LOOP_ID(ha, x) \ 1719 (ha->cfg_flags & (CFG_CTRL_2422 | CFG_CTRL_25XX) ? \ 1720 (x > LAST_N_PORT_HDL && x <= FL_PORT_24XX_HDL) : \ 1721 (x >= FL_PORT_LOOP_ID && x <= SIMPLE_NAME_SERVER_LOOP_ID)) 1722 1723 #define QL_LOOP_TRANSITION (RESET_MARKER_NEEDED | RESET_ACTIVE | \ 1724 ISP_ABORT_NEEDED | ABORT_ISP_ACTIVE | \ 1725 LOOP_RESYNC_NEEDED | LOOP_RESYNC_ACTIVE | \ 1726 COMMAND_WAIT_NEEDED | COMMAND_WAIT_ACTIVE) 1727 1728 #define QL_SUSPENDED (QL_LOOP_TRANSITION | LOOP_DOWN | DRIVER_STALL) 1729 1730 #define LOOP_RECONFIGURE(ha) (ha->task_daemon_flags & (QL_LOOP_TRANSITION | \ 1731 DRIVER_STALL)) 1732 1733 #define DRIVER_SUSPENDED(ha) (ha->task_daemon_flags & QL_SUSPENDED) 1734 1735 #define LOOP_NOT_READY(ha) (ha->task_daemon_flags & (QL_LOOP_TRANSITION | \ 1736 LOOP_DOWN)) 1737 1738 #define LOOP_READY(ha) (LOOP_NOT_READY(ha) == 0) 1739 1740 #define QL_TASK_PENDING(ha) ( \ 1741 ha->task_daemon_flags & (QL_LOOP_TRANSITION | ABORT_QUEUES_NEEDED | \ 1742 PORT_RETRY_NEEDED) || ha->callback_queue.first != NULL) 1743 1744 #define QL_DAEMON_NOT_ACTIVE(ha) ( \ 1745 !(ha->task_daemon_flags & TASK_DAEMON_ALIVE_FLG) || \ 1746 ha->task_daemon_flags & (TASK_DAEMON_SLEEPING_FLG | \ 1747 TASK_DAEMON_STOP_FLG)) 1748 1749 #define QL_DAEMON_SUSPENDED(ha) (\ 1750 (((ha)->cprinfo.cc_events & CALLB_CPR_START) ||\ 1751 ((ha)->flags & ADAPTER_SUSPENDED))) 1752 1753 /* 1754 * Locking Macro Definitions 1755 */ 1756 #define GLOBAL_STATE_LOCK() mutex_enter(&ql_global_mutex) 1757 #define GLOBAL_STATE_UNLOCK() mutex_exit(&ql_global_mutex) 1758 1759 #define TRY_DEVICE_QUEUE_LOCK(q) mutex_tryenter(&q->mutex) 1760 #define DEVICE_QUEUE_LOCK(q) mutex_enter(&q->mutex) 1761 #define DEVICE_QUEUE_UNLOCK(q) mutex_exit(&q->mutex) 1762 1763 #define MBX_REGISTER_LOCK(ha) mutex_enter(&ha->pha->mbx_mutex) 1764 #define MBX_REGISTER_UNLOCK(ha) mutex_exit(&ha->pha->mbx_mutex) 1765 1766 #define INTR_LOCK(ha) mutex_enter(&ha->pha->intr_mutex) 1767 #define INTR_UNLOCK(ha) mutex_exit(&ha->pha->intr_mutex) 1768 1769 #define TASK_DAEMON_LOCK(ha) mutex_enter(&ha->pha->task_daemon_mutex) 1770 #define TASK_DAEMON_UNLOCK(ha) mutex_exit(&ha->pha->task_daemon_mutex) 1771 1772 #define REQUEST_RING_LOCK(ha) mutex_enter(&ha->pha->req_ring_mutex) 1773 #define REQUEST_RING_UNLOCK(ha) mutex_exit(&ha->pha->req_ring_mutex) 1774 1775 #define CACHE_LOCK(ha) mutex_enter(&ha->pha->cache_mutex); 1776 #define CACHE_UNLOCK(ha) mutex_exit(&ha->pha->cache_mutex); 1777 1778 #define PORTMANAGE_LOCK(ha) mutex_enter(&ha->pha->portmutex); 1779 #define PORTMANAGE_UNLOCK(ha) mutex_exit(&ha->pha->portmutex); 1780 1781 #define ADAPTER_STATE_LOCK(ha) mutex_enter(&ha->pha->mutex) 1782 #define ADAPTER_STATE_UNLOCK(ha) mutex_exit(&ha->pha->mutex) 1783 1784 #define QL_DUMP_LOCK(ha) mutex_enter(&ha->pha->dump_mutex) 1785 #define QL_DUMP_UNLOCK(ha) mutex_exit(&ha->pha->dump_mutex) 1786 1787 #define QL_PM_LOCK(ha) mutex_enter(&ha->pha->pm_mutex) 1788 #define QL_PM_UNLOCK(ha) mutex_exit(&ha->pha->pm_mutex) 1789 1790 #define QL_UB_LOCK(ha) mutex_enter(&ha->pha->ub_mutex) 1791 #define QL_UB_UNLOCK(ha) mutex_exit(&ha->pha->ub_mutex) 1792 1793 #define GLOBAL_HW_LOCK() mutex_enter(&ql_global_hw_mutex) 1794 #define GLOBAL_HW_UNLOCK() mutex_exit(&ql_global_hw_mutex) 1795 1796 /* 1797 * PCI power management control/status register location 1798 */ 1799 #define QL_PM_CS_REG 0x48 1800 1801 /* 1802 * ql component 1803 */ 1804 #define QL_POWER_COMPONENT 0 1805 1806 typedef struct ql_config_space { 1807 uint16_t chs_command; 1808 uint8_t chs_cache_line_size; 1809 uint8_t chs_latency_timer; 1810 uint8_t chs_header_type; 1811 uint8_t chs_sec_latency_timer; 1812 uint8_t chs_bridge_control; 1813 uint32_t chs_base0; 1814 uint32_t chs_base1; 1815 uint32_t chs_base2; 1816 uint32_t chs_base3; 1817 uint32_t chs_base4; 1818 uint32_t chs_base5; 1819 } ql_config_space_t; 1820 1821 #ifdef USE_DDI_INTERFACES 1822 1823 #define QL_SAVE_CONFIG_REGS(dip) pci_save_config_regs(dip) 1824 #define QL_RESTORE_CONFIG_REGS(dip) pci_restore_config_regs(dip) 1825 1826 #else /* USE_DDI_INTERFACES */ 1827 1828 #define QL_SAVE_CONFIG_REGS(dip) ql_save_config_regs(dip) 1829 #define QL_RESTORE_CONFIG_REGS(dip) ql_restore_config_regs(dip) 1830 1831 #endif /* USE_DDI_INTERFACES */ 1832 1833 #define QL_IS_SET(x, y) (((x) & (y)) == (y)) 1834 1835 /* 1836 * QL local function return status codes 1837 */ 1838 #define QL_SUCCESS 0x4000 1839 #define QL_INVALID_COMMAND 0x4001 1840 #define QL_INTERFACE_ERROR 0x4002 1841 #define QL_TEST_FAILED 0x4003 1842 #define QL_COMMAND_ERROR 0x4005 1843 #define QL_PARAMETER_ERROR 0x4006 1844 #define QL_PORT_ID_USED 0x4007 1845 #define QL_LOOP_ID_USED 0x4008 1846 #define QL_ALL_IDS_IN_USE 0x4009 1847 #define QL_NOT_LOGGED_IN 0x400A 1848 #define QL_LOOP_DOWN 0x400B 1849 #define QL_LOOP_BACK_ERROR 0x400C 1850 #define QL_CHECKSUM_ERROR 0x4010 1851 1852 #define QL_FUNCTION_TIMEOUT 0x100 1853 #define QL_FUNCTION_PARAMETER_ERROR 0x101 1854 #define QL_FUNCTION_FAILED 0x102 1855 #define QL_MEMORY_ALLOC_FAILED 0x103 1856 #define QL_FABRIC_NOT_INITIALIZED 0x104 1857 #define QL_LOCK_TIMEOUT 0x105 1858 #define QL_ABORTED 0x106 1859 #define QL_FUNCTION_SUSPENDED 0x107 1860 #define QL_END_OF_DATA 0x108 1861 #define QL_IP_UNSUPPORTED 0x109 1862 #define QL_PM_ERROR 0x10a 1863 #define QL_DATA_EXISTS 0x10b 1864 #define QL_NOT_SUPPORTED 0x10c 1865 #define QL_MEMORY_FULL 0x10d 1866 #define QL_FW_NOT_SUPPORTED 0x10e 1867 #define QL_FWMODLOAD_FAILED 0x10f 1868 #define QL_FWSYM_NOT_FOUND 0x110 1869 #define QL_LOGIN_NOT_SUPPORTED 0x111 1870 1871 /* 1872 * SBus card FPGA register offsets. 1873 */ 1874 #define FPGA_CONF 0x100 1875 #define FPGA_EEPROM_LOADDR 0x102 1876 #define FPGA_EEPROM_HIADDR 0x104 1877 #define FPGA_EEPROM_DATA 0x106 1878 #define FPGA_REVISION 0x108 1879 1880 #define SBUS_FLASH_WRITE_ENABLE 0x0080 1881 #define QL_SBUS_FCODE_SIZE 0x30000 1882 #define QL_FCODE_OFFSET 0 1883 #define QL_FPGA_SIZE 0x40000 1884 #define QL_FPGA_OFFSET 0x40000 1885 1886 #define READ_PORT_ID(addr) ((uint32_t)((((uint32_t)((addr)[0])) << 16) | \ 1887 (((uint32_t)((addr)[1])) << 8) | \ 1888 (((uint32_t)((addr)[2]))))) 1889 #define READ_PORT_NAME(addr) ((u_longlong_t)((((uint64_t)((addr)[0])) << 56) | \ 1890 (((uint64_t)((addr)[1])) << 48) | \ 1891 (((uint64_t)((addr)[2])) << 40) | \ 1892 (((uint64_t)((addr)[3])) << 32) | \ 1893 (((uint64_t)((addr)[4])) << 24) | \ 1894 (((uint64_t)((addr)[5])) << 16) | \ 1895 (((uint64_t)((addr)[6])) << 8) | \ 1896 (((uint64_t)((addr)[7]))))) 1897 /* 1898 * Structure used to associate cmds with strings which describe them. 1899 */ 1900 typedef struct cmd_table_entry { 1901 uint16_t cmd; 1902 char *string; 1903 } cmd_table_t; 1904 1905 /* 1906 * ELS command table initializer 1907 */ 1908 #define ELS_CMD_TABLE() \ 1909 { \ 1910 {LA_ELS_RJT, "LA_ELS_RJT"}, \ 1911 {LA_ELS_ACC, "LA_ELS_ACC"}, \ 1912 {LA_ELS_PLOGI, "LA_ELS_PLOGI"}, \ 1913 {LA_ELS_PDISC, "LA_ELS_PDISC"}, \ 1914 {LA_ELS_FLOGI, "LA_ELS_FLOGI"}, \ 1915 {LA_ELS_FDISC, "LA_ELS_FDISC"}, \ 1916 {LA_ELS_LOGO, "LA_ELS_LOGO"}, \ 1917 {LA_ELS_PRLI, "LA_ELS_PRLI"}, \ 1918 {LA_ELS_PRLO, "LA_ELS_PRLO"}, \ 1919 {LA_ELS_ADISC, "LA_ELS_ADISC"}, \ 1920 {LA_ELS_LINIT, "LA_ELS_LINIT"}, \ 1921 {LA_ELS_LPC, "LA_ELS_LPC"}, \ 1922 {LA_ELS_LSTS, "LA_ELS_LSTS"}, \ 1923 {LA_ELS_SCR, "LA_ELS_SCR"}, \ 1924 {LA_ELS_RSCN, "LA_ELS_RSCN"}, \ 1925 {LA_ELS_FARP_REQ, "LA_ELS_FARP_REQ"}, \ 1926 {LA_ELS_FARP_REPLY, "LA_ELS_FARP_REPLY"}, \ 1927 {LA_ELS_RLS, "LA_ELS_RLS"}, \ 1928 {LA_ELS_RNID, "LA_ELS_RNID"}, \ 1929 {NULL, NULL} \ 1930 } 1931 1932 /* 1933 * ELS Passthru IOCB data segment descriptor. 1934 */ 1935 typedef struct data_seg_desc { 1936 uint32_t addr[2]; 1937 uint32_t length; 1938 } data_seg_desc_t; 1939 1940 /* 1941 * ELS descriptor used to abstract the hosts fibre channel packet 1942 * from the ISP ELS code. 1943 */ 1944 typedef struct els_desc { 1945 uint8_t els; /* the ELS command code */ 1946 ddi_acc_handle_t els_handle; 1947 uint16_t n_port_handle; 1948 port_id_t d_id; 1949 port_id_t s_id; 1950 uint16_t control_flags; 1951 uint32_t cmd_byte_count; 1952 uint32_t rsp_byte_count; 1953 data_seg_desc_t tx_dsd; /* FC frame payload */ 1954 data_seg_desc_t rx_dsd; /* ELS resp payload buffer */ 1955 } els_descriptor_t; 1956 1957 typedef struct prli_svc_pram_resp_page { 1958 uint8_t type_code; 1959 uint8_t type_code_ext; 1960 uint16_t prli_resp_flags; 1961 uint32_t orig_process_associator; 1962 uint32_t resp_process_associator; 1963 uint32_t common_parameters; 1964 } prli_svc_pram_resp_page_t; 1965 1966 /* 1967 * PRLI accept Service Parameter Page Word 3 1968 */ 1969 #define PRLI_W3_WRITE_FCP_XFR_RDY_DISABLED BIT_0 1970 #define PRLI_W3_READ_FCP_XFR_RDY_DISABLED BIT_1 1971 #define PRLI_W3_OBSOLETE_BIT_2 BIT_2 1972 #define PRLI_W3_OBSOLETE_BIT_3 BIT_3 1973 #define PRLI_W3_TARGET_FUNCTION BIT_4 1974 #define PRLI_W3_INITIATOR_FUNCTION BIT_5 1975 #define PRLI_W3_DATA_OVERLAY_ALLOWED BIT_6 1976 #define PRLI_W3_CONFIRMED_COMP_ALLOWED BIT_7 1977 #define PRLI_W3_RETRY BIT_8 1978 #define PRLI_W3_TASK_RETRY_ID_REQUESTED BIT_9 1979 1980 typedef struct prli_acc_resp { 1981 uint8_t ls_code; 1982 uint8_t page_length; 1983 uint16_t payload_length; 1984 struct prli_svc_pram_resp_page svc_params; 1985 } prli_acc_resp_t; 1986 1987 #define EL_TRACE_BUF_SIZE 8192 1988 1989 /* 1990 * Global Data in ql_api.c source file. 1991 */ 1992 extern void *ql_state; /* for soft state routine */ 1993 extern uint32_t ql_os_release_level; 1994 extern ql_head_t ql_hba; 1995 extern kmutex_t ql_global_mutex; 1996 extern kmutex_t ql_global_hw_mutex; 1997 extern kmutex_t ql_global_el_mutex; 1998 extern uint8_t ql_ip_fast_post_count; 1999 extern uint32_t ql_ip_buffer_count; 2000 extern uint32_t ql_ip_low_water; 2001 extern uint8_t ql_alpa_to_index[]; 2002 extern uint32_t ql_gfru_hba_index; 2003 2004 /* 2005 * Global Function Prototypes in ql_api.c source file. 2006 */ 2007 void ql_chg_endian(uint8_t *, size_t); 2008 void ql_populate_hba_fru_details(ql_adapter_state_t *, fc_fca_port_info_t *); 2009 void ql_setup_fruinfo(ql_adapter_state_t *); 2010 uint16_t ql_pci_config_get16(ql_adapter_state_t *, off_t); 2011 uint32_t ql_pci_config_get32(ql_adapter_state_t *, off_t); 2012 void ql_pci_config_put8(ql_adapter_state_t *, off_t, uint8_t); 2013 void ql_pci_config_put16(ql_adapter_state_t *, off_t, uint16_t); 2014 void ql_delay(ql_adapter_state_t *, clock_t); 2015 void ql_awaken_task_daemon(ql_adapter_state_t *, ql_srb_t *, uint32_t, 2016 uint32_t); 2017 int ql_abort_device(ql_adapter_state_t *, ql_tgt_t *, int); 2018 int ql_binary_fw_dump(ql_adapter_state_t *, int); 2019 void ql_done(ql_link_t *); 2020 int ql_24xx_flash_id(ql_adapter_state_t *); 2021 int ql_24xx_load_flash(ql_adapter_state_t *, uint8_t *, uint32_t, uint32_t); 2022 int ql_poll_flash(ql_adapter_state_t *, uint32_t, uint8_t); 2023 void ql_flash_disable(ql_adapter_state_t *); 2024 void ql_flash_enable(ql_adapter_state_t *); 2025 int ql_erase_flash(ql_adapter_state_t *, int); 2026 void ql_write_flash_byte(ql_adapter_state_t *, uint32_t, uint8_t); 2027 uint8_t ql_read_flash_byte(ql_adapter_state_t *, uint32_t); 2028 int ql_24xx_read_flash(ql_adapter_state_t *, uint32_t, uint32_t *); 2029 int ql_24xx_write_flash(ql_adapter_state_t *, uint32_t, uint32_t); 2030 fc_unsol_buf_t *ql_get_unsolicited_buffer(ql_adapter_state_t *, uint32_t); 2031 size_t ql_ascii_fw_dump(ql_adapter_state_t *, caddr_t); 2032 void ql_add_link_b(ql_head_t *, ql_link_t *); 2033 void ql_add_link_t(ql_head_t *, ql_link_t *); 2034 void ql_remove_link(ql_head_t *, ql_link_t *); 2035 void ql_next(ql_adapter_state_t *, ql_lun_t *); 2036 void ql_send_logo(ql_adapter_state_t *, ql_tgt_t *, ql_head_t *); 2037 void ql_cthdr_endian(ddi_acc_handle_t, caddr_t, boolean_t); 2038 ql_tgt_t *ql_d_id_to_queue(ql_adapter_state_t *, port_id_t); 2039 ql_tgt_t *ql_loop_id_to_queue(ql_adapter_state_t *, uint16_t); 2040 void ql_cmd_wait(ql_adapter_state_t *); 2041 void ql_loop_online(ql_adapter_state_t *); 2042 ql_tgt_t *ql_dev_init(ql_adapter_state_t *, port_id_t, uint16_t); 2043 int ql_ub_frame_hdr(ql_adapter_state_t *, ql_tgt_t *, uint16_t, ql_head_t *); 2044 void ql_rcv_rscn_els(ql_adapter_state_t *, uint16_t *, ql_head_t *); 2045 int ql_stall_driver(ql_adapter_state_t *, uint32_t); 2046 void ql_restart_driver(ql_adapter_state_t *); 2047 int ql_load_flash(ql_adapter_state_t *, uint8_t *, uint32_t); 2048 int ql_get_dma_mem(ql_adapter_state_t *, dma_mem_t *, uint32_t, 2049 mem_alloc_type_t, mem_alignment_t); 2050 int ql_alloc_phys(ql_adapter_state_t *, dma_mem_t *, int); 2051 void ql_free_phys(ql_adapter_state_t *, dma_mem_t *); 2052 void ql_24xx_protect_flash(ql_adapter_state_t *); 2053 void ql_free_dma_resource(ql_adapter_state_t *, dma_mem_t *); 2054 uint8_t ql_pci_config_get8(ql_adapter_state_t *, off_t); 2055 void ql_pci_config_put32(ql_adapter_state_t *, off_t, uint32_t); 2056 void ql_24xx_unprotect_flash(ql_adapter_state_t *); 2057 char *els_cmd_text(int); 2058 char *mbx_cmd_text(int); 2059 char *cmd_text(cmd_table_t *, int); 2060 uint32_t ql_fwmodule_resolve(ql_adapter_state_t *); 2061 void ql_port_state(ql_adapter_state_t *, uint32_t, uint32_t); 2062 2063 #ifdef __cplusplus 2064 } 2065 #endif 2066 2067 #endif /* _QL_API_H */ 2068