1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2010 Emulex. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _EMLXS_MBOX_H 28 #define _EMLXS_MBOX_H 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 /* SLI 2/3 Mailbox defines */ 35 36 #define MBOX_SIZE 256 37 #define MBOX_EXTENSION_OFFSET MBOX_SIZE 38 39 #ifdef MBOX_EXT_SUPPORT 40 #define MBOX_EXTENSION_SIZE 1024 41 #else 42 #define MBOX_EXTENSION_SIZE 0 43 #endif /* MBOX_EXT_SUPPORT */ 44 45 46 47 /* ==== Mailbox Commands ==== */ 48 #define MBX_SHUTDOWN 0x00 /* terminate testing */ 49 #define MBX_LOAD_SM 0x01 50 #define MBX_READ_NV 0x02 51 #define MBX_WRITE_NV 0x03 52 #define MBX_RUN_BIU_DIAG 0x04 53 #define MBX_INIT_LINK 0x05 54 #define MBX_DOWN_LINK 0x06 55 #define MBX_CONFIG_LINK 0x07 56 #define MBX_PART_SLIM 0x08 57 #define MBX_CONFIG_RING 0x09 58 #define MBX_RESET_RING 0x0A 59 #define MBX_READ_CONFIG 0x0B 60 #define MBX_READ_RCONFIG 0x0C 61 #define MBX_READ_SPARM 0x0D 62 #define MBX_READ_STATUS 0x0E 63 #define MBX_READ_RPI 0x0F 64 #define MBX_READ_XRI 0x10 65 #define MBX_READ_REV 0x11 66 #define MBX_READ_LNK_STAT 0x12 67 #define MBX_REG_LOGIN 0x13 68 #define MBX_UNREG_LOGIN 0x14 /* SLI2/3 */ 69 #define MBX_UNREG_RPI 0x14 /* SLI4 */ 70 #define MBX_READ_LA 0x15 71 #define MBX_CLEAR_LA 0x16 72 #define MBX_DUMP_MEMORY 0x17 73 #define MBX_DUMP_CONTEXT 0x18 74 #define MBX_RUN_DIAGS 0x19 75 #define MBX_RESTART 0x1A 76 #define MBX_UPDATE_CFG 0x1B 77 #define MBX_DOWN_LOAD 0x1C 78 #define MBX_DEL_LD_ENTRY 0x1D 79 #define MBX_RUN_PROGRAM 0x1E 80 #define MBX_SET_MASK 0x20 81 #define MBX_SET_VARIABLE 0x21 82 #define MBX_UNREG_D_ID 0x23 83 #define MBX_KILL_BOARD 0x24 84 #define MBX_CONFIG_FARP 0x25 85 #define MBX_BEACON 0x2A 86 #define MBX_READ_VPI 0x2B 87 #define MBX_CONFIG_MSIX 0x30 88 #define MBX_HEARTBEAT 0x31 89 #define MBX_WRITE_VPARMS 0x32 90 #define MBX_ASYNC_EVENT 0x33 91 92 #define MBX_READ_EVENT_LOG_STATUS 0x37 93 #define MBX_READ_EVENT_LOG 0x38 94 #define MBX_WRITE_EVENT_LOG 0x39 95 #define MBX_NV_LOG 0x3A 96 #define MBX_PORT_CAPABILITIES 0x3B 97 #define MBX_IOV_CONTROL 0x3C 98 #define MBX_IOV_MBX 0x3D 99 100 101 #define MBX_CONFIG_HBQ 0x7C /* SLI3 */ 102 #define MBX_LOAD_AREA 0x81 103 #define MBX_RUN_BIU_DIAG64 0x84 104 #define MBX_GET_DEBUG 0x86 105 #define MBX_CONFIG_PORT 0x88 106 #define MBX_READ_SPARM64 0x8D 107 #define MBX_READ_RPI64 0x8F 108 #define MBX_CONFIG_MSI 0x90 109 #define MBX_REG_LOGIN64 0x93 /* SLI2/3 */ 110 #define MBX_REG_RPI 0x93 /* SLI4 */ 111 #define MBX_READ_LA64 0x95 112 #define MBX_REG_VPI 0x96 /* NPIV */ 113 #define MBX_UNREG_VPI 0x97 /* NPIV */ 114 #define MBX_FLASH_WR_ULA 0x98 115 #define MBX_SET_DEBUG 0x99 116 #define MBX_SLI_CONFIG 0x9B 117 #define MBX_LOAD_EXP_ROM 0x9C 118 #define MBX_REQUEST_FEATURES 0x9D 119 #define MBX_RESUME_RPI 0x9E 120 #define MBX_REG_VFI 0x9F 121 #define MBX_REG_FCFI 0xA0 122 #define MBX_UNREG_VFI 0xA1 123 #define MBX_UNREG_FCFI 0xA2 124 #define MBX_INIT_VFI 0xA3 125 #define MBX_INIT_VPI 0xA4 126 #define MBX_ACCESS_VDATA 0xA5 127 #define MBX_MAX_CMDS 0xA6 128 129 130 /* 131 * Define Status 132 */ 133 #define MBX_SUCCESS 0x0 134 #define MBX_FAILURE 0x1 135 #define MBXERR_NUM_IOCBS 0x2 136 #define MBXERR_IOCBS_EXCEEDED 0x3 137 #define MBXERR_BAD_RING_NUMBER 0x4 138 #define MBXERR_MASK_ENTRIES_RANGE 0x5 139 #define MBXERR_MASKS_EXCEEDED 0x6 140 #define MBXERR_BAD_PROFILE 0x7 141 #define MBXERR_BAD_DEF_CLASS 0x8 142 #define MBXERR_BAD_MAX_RESPONDER 0x9 143 #define MBXERR_BAD_MAX_ORIGINATOR 0xA 144 #define MBXERR_RPI_REGISTERED 0xB 145 #define MBXERR_RPI_FULL 0xC 146 #define MBXERR_NO_RESOURCES 0xD 147 #define MBXERR_BAD_RCV_LENGTH 0xE 148 #define MBXERR_DMA_ERROR 0xF 149 #define MBXERR_NOT_SUPPORTED 0x10 150 #define MBXERR_UNSUPPORTED_FEATURE 0x11 151 #define MBXERR_UNKNOWN_COMMAND 0x12 152 153 /* Driver special codes */ 154 #define MBX_DRIVER_RESERVED 0xF9 /* Set to lowest drv status */ 155 #define MBX_NONEMBED_ERROR 0xF9 156 #define MBX_OVERTEMP_ERROR 0xFA 157 #define MBX_HARDWARE_ERROR 0xFB 158 #define MBX_DRVR_ERROR 0xFC 159 #define MBX_BUSY 0xFD 160 #define MBX_TIMEOUT 0xFE 161 #define MBX_NOT_FINISHED 0xFF 162 163 /* 164 * flags for EMLXS_SLI_ISSUE_MBOX_CMD() 165 */ 166 #define MBX_POLL 0x01 /* poll mailbox till command done, */ 167 /* then return */ 168 #define MBX_SLEEP 0x02 /* sleep till mailbox intr cmpl */ 169 /* wakes thread up */ 170 #define MBX_WAIT 0x03 /* wait for comand done, then return */ 171 #define MBX_NOWAIT 0x04 /* issue command then return immediately */ 172 #define MBX_BOOTSTRAP 0x80 /* issue a command on the bootstrap mbox */ 173 174 175 176 /* 177 * Begin Structure Definitions for Mailbox Commands 178 */ 179 180 typedef struct revcompat 181 { 182 #ifdef EMLXS_BIG_ENDIAN 183 uint32_t ldflag:1; /* Set in SRAM descriptor */ 184 uint32_t ldcount:7; /* For use by program load */ 185 uint32_t kernel:4; /* Kernel ID */ 186 uint32_t kver:4; /* Kernel compatibility version */ 187 uint32_t SMver:4; /* Sequence Manager version */ 188 /* 0 if none */ 189 uint32_t ENDECver:4; /* ENDEC+ version, 0 if none */ 190 uint32_t BIUtype:4; /* PCI = 0 */ 191 uint32_t BIUver:4; /* BIU version, 0 if none */ 192 #endif 193 #ifdef EMLXS_LITTLE_ENDIAN 194 uint32_t BIUver:4; /* BIU version, 0 if none */ 195 uint32_t BIUtype:4; /* PCI = 0 */ 196 uint32_t ENDECver:4; /* ENDEC+ version, 0 if none */ 197 uint32_t SMver:4; /* Sequence Manager version */ 198 /* 0 if none */ 199 uint32_t kver:4; /* Kernel compatibility version */ 200 uint32_t kernel:4; /* Kernel ID */ 201 uint32_t ldcount:7; /* For use by program load */ 202 uint32_t ldflag:1; /* Set in SRAM descriptor */ 203 #endif 204 } REVCOMPAT; 205 206 typedef struct id_word 207 { 208 #ifdef EMLXS_BIG_ENDIAN 209 uint8_t Type; 210 uint8_t Id; 211 uint8_t Ver; 212 uint8_t Rev; 213 #endif 214 #ifdef EMLXS_LITTLE_ENDIAN 215 uint8_t Rev; 216 uint8_t Ver; 217 uint8_t Id; 218 uint8_t Type; 219 #endif 220 union 221 { 222 REVCOMPAT cp; 223 uint32_t revcomp; 224 } un; 225 } PROG_ID; 226 227 typedef struct 228 { 229 #ifdef EMLXS_BIG_ENDIAN 230 uint8_t tval; 231 uint8_t tmask; 232 uint8_t rval; 233 uint8_t rmask; 234 #endif 235 #ifdef EMLXS_LITTLE_ENDIAN 236 uint8_t rmask; 237 uint8_t rval; 238 uint8_t tmask; 239 uint8_t tval; 240 #endif 241 } RR_REG; 242 243 244 /* Structure used for a HBQ entry */ 245 typedef struct 246 { 247 ULP_BDE64 bde; 248 union UN_TAG 249 { 250 uint32_t w; 251 struct 252 { 253 #ifdef EMLXS_BIG_ENDIAN 254 uint32_t HBQ_tag:4; 255 uint32_t HBQE_tag:28; 256 #endif 257 #ifdef EMLXS_LITTLE_ENDIAN 258 uint32_t HBQE_tag:28; 259 uint32_t HBQ_tag:4; 260 #endif 261 } ext; 262 } unt; 263 } HBQE_t; 264 265 typedef struct 266 { 267 #ifdef EMLXS_BIG_ENDIAN 268 uint8_t tmatch; 269 uint8_t tmask; 270 uint8_t rctlmatch; 271 uint8_t rctlmask; 272 #endif 273 #ifdef EMLXS_LITTLE_ENDIAN 274 uint8_t rctlmask; 275 uint8_t rctlmatch; 276 uint8_t tmask; 277 uint8_t tmatch; 278 #endif 279 } HBQ_MASK; 280 281 #define EMLXS_MAX_HBQ_BUFFERS 4096 282 283 typedef struct 284 { 285 uint32_t HBQ_num_mask; /* number of mask entries in */ 286 /* port array */ 287 uint32_t HBQ_recvNotify; /* Rcv buffer notification */ 288 uint32_t HBQ_numEntries; /* # of entries in HBQ */ 289 uint32_t HBQ_headerLen; /* 0 if not profile 4 or 5 */ 290 uint32_t HBQ_logEntry; /* Set to 1 if this HBQ used */ 291 /* for LogEntry */ 292 uint32_t HBQ_profile; /* Selection profile 0=all, */ 293 /* 7=logentry */ 294 uint32_t HBQ_ringMask; /* Binds HBQ to a ring e.g. */ 295 /* Ring0=b0001, ring2=b0100 */ 296 uint32_t HBQ_id; /* index of this hbq in ring */ 297 /* of HBQs[] */ 298 uint32_t HBQ_PutIdx_next; /* Index to next HBQ slot to */ 299 /* use */ 300 uint32_t HBQ_PutIdx; /* HBQ slot to use */ 301 uint32_t HBQ_GetIdx; /* Local copy of Get index */ 302 /* from Port */ 303 uint16_t HBQ_PostBufCnt; /* Current number of entries */ 304 /* in list */ 305 MATCHMAP *HBQ_PostBufs[EMLXS_MAX_HBQ_BUFFERS]; 306 MATCHMAP HBQ_host_buf; /* HBQ host buffer for HBQEs */ 307 HBQ_MASK HBQ_Masks[6]; 308 309 union 310 { 311 uint32_t allprofiles[12]; 312 313 struct 314 { 315 #ifdef EMLXS_BIG_ENDIAN 316 uint32_t seqlenoff:16; 317 uint32_t maxlen:16; 318 #endif 319 #ifdef EMLXS_LITTLE_ENDIAN 320 uint32_t maxlen:16; 321 uint32_t seqlenoff:16; 322 #endif 323 #ifdef EMLXS_BIG_ENDIAN 324 uint32_t rsvd1:28; 325 uint32_t seqlenbcnt:4; 326 #endif 327 #ifdef EMLXS_LITTLE_ENDIAN 328 uint32_t seqlenbcnt:4; 329 uint32_t rsvd1:28; 330 #endif 331 uint32_t rsvd[10]; 332 } profile2; 333 334 struct 335 { 336 #ifdef EMLXS_BIG_ENDIAN 337 uint32_t seqlenoff:16; 338 uint32_t maxlen:16; 339 #endif 340 #ifdef EMLXS_LITTLE_ENDIAN 341 uint32_t maxlen:16; 342 uint32_t seqlenoff:16; 343 #endif 344 #ifdef EMLXS_BIG_ENDIAN 345 uint32_t cmdcodeoff:28; 346 uint32_t rsvd1:12; 347 uint32_t seqlenbcnt:4; 348 #endif 349 #ifdef EMLXS_LITTLE_ENDIAN 350 uint32_t seqlenbcnt:4; 351 uint32_t rsvd1:12; 352 uint32_t cmdcodeoff:28; 353 #endif 354 uint32_t cmdmatch[8]; 355 356 uint32_t rsvd[2]; 357 } profile3; 358 359 struct 360 { 361 #ifdef EMLXS_BIG_ENDIAN 362 uint32_t seqlenoff:16; 363 uint32_t maxlen:16; 364 #endif 365 #ifdef EMLXS_LITTLE_ENDIAN 366 uint32_t maxlen:16; 367 uint32_t seqlenoff:16; 368 #endif 369 #ifdef EMLXS_BIG_ENDIAN 370 uint32_t cmdcodeoff:28; 371 uint32_t rsvd1:12; 372 uint32_t seqlenbcnt:4; 373 #endif 374 #ifdef EMLXS_LITTLE_ENDIAN 375 uint32_t seqlenbcnt:4; 376 uint32_t rsvd1:12; 377 uint32_t cmdcodeoff:28; 378 #endif 379 uint32_t cmdmatch[8]; 380 381 uint32_t rsvd[2]; 382 } profile5; 383 } profiles; 384 } HBQ_INIT_t; 385 386 387 388 /* Structure for MB Command LOAD_SM and DOWN_LOAD */ 389 390 391 typedef struct 392 { 393 #ifdef EMLXS_BIG_ENDIAN 394 uint32_t rsvd2:24; 395 uint32_t keep:1; 396 uint32_t acknowledgment:1; 397 uint32_t version:1; 398 uint32_t erase_or_prog:1; 399 uint32_t update_flash:1; 400 uint32_t update_ram:1; 401 uint32_t method:1; 402 uint32_t load_cmplt:1; 403 #endif 404 #ifdef EMLXS_LITTLE_ENDIAN 405 uint32_t load_cmplt:1; 406 uint32_t method:1; 407 uint32_t update_ram:1; 408 uint32_t update_flash:1; 409 uint32_t erase_or_prog:1; 410 uint32_t version:1; 411 uint32_t acknowledgment:1; 412 uint32_t keep:1; 413 uint32_t rsvd2:24; 414 #endif 415 416 #define DL_FROM_BDE 0 /* method */ 417 #define DL_FROM_SLIM 1 418 419 #define PROGRAM_FLASH 0 /* erase_or_prog */ 420 #define ERASE_FLASH 1 421 422 uint32_t dl_to_adr; 423 uint32_t dl_len; 424 union 425 { 426 uint32_t dl_from_slim_offset; 427 ULP_BDE dl_from_bde; 428 ULP_BDE64 dl_from_bde64; 429 PROG_ID prog_id; 430 } un; 431 } LOAD_SM_VAR; 432 433 434 /* Structure for MB Command READ_NVPARM (02) */ 435 /* Good for SLI2/3 and SLI4 */ 436 437 typedef struct 438 { 439 uint32_t rsvd1[3]; /* Read as all one's */ 440 uint32_t rsvd2; /* Read as all zero's */ 441 uint32_t portname[2]; /* N_PORT name */ 442 uint32_t nodename[2]; /* NODE name */ 443 #ifdef EMLXS_BIG_ENDIAN 444 uint32_t pref_DID:24; 445 uint32_t hardAL_PA:8; 446 #endif 447 #ifdef EMLXS_LITTLE_ENDIAN 448 uint32_t hardAL_PA:8; 449 uint32_t pref_DID:24; 450 #endif 451 uint32_t rsvd3[21]; /* Read as all one's */ 452 } READ_NV_VAR; 453 454 455 /* Structure for MB Command WRITE_NVPARMS (03) */ 456 /* Good for SLI2/3 and SLI4 */ 457 458 typedef struct 459 { 460 uint32_t rsvd1[3]; /* Must be all one's */ 461 uint32_t rsvd2; /* Must be all zero's */ 462 uint32_t portname[2]; /* N_PORT name */ 463 uint32_t nodename[2]; /* NODE name */ 464 #ifdef EMLXS_BIG_ENDIAN 465 uint32_t pref_DID:24; 466 uint32_t hardAL_PA:8; 467 #endif 468 #ifdef EMLXS_LITTLE_ENDIAN 469 uint32_t hardAL_PA:8; 470 uint32_t pref_DID:24; 471 #endif 472 uint32_t rsvd3[21]; /* Must be all one's */ 473 } WRITE_NV_VAR; 474 475 476 /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */ 477 /* Good for SLI2/3 and SLI4 */ 478 479 typedef struct 480 { 481 uint32_t rsvd1; 482 union 483 { 484 struct 485 { 486 ULP_BDE64 xmit_bde64; 487 ULP_BDE64 rcv_bde64; 488 } s2; 489 } un; 490 } BIU_DIAG_VAR; 491 492 493 /* Structure for MB Command INIT_LINK (05) */ 494 /* Good for SLI2/3 and SLI4 */ 495 496 typedef struct 497 { 498 #ifdef EMLXS_BIG_ENDIAN 499 uint32_t rsvd1:24; 500 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective */ 501 /* Reset to */ 502 #endif 503 #ifdef EMLXS_LITTLE_ENDIAN 504 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective */ 505 /* Reset to */ 506 uint32_t rsvd1:24; 507 #endif 508 509 #ifdef EMLXS_BIG_ENDIAN 510 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */ 511 uint8_t rsvd2; 512 uint16_t link_flags; 513 #endif 514 #ifdef EMLXS_LITTLE_ENDIAN 515 uint16_t link_flags; 516 uint8_t rsvd2; 517 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */ 518 #endif 519 #define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) */ 520 /* ENDEC loopback */ 521 #define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */ 522 #define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */ 523 #define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */ 524 #define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */ 525 #define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */ 526 527 #define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */ 528 #define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */ 529 #define FLAGS_PREABORT_RETURN 0x4000 /* Bit 14 */ 530 531 uint32_t link_speed; /* NEW_FEATURE */ 532 #define LINK_SPEED_AUTO 0 /* Auto selection */ 533 #define LINK_SPEED_1G 1 /* 1 Gigabaud */ 534 #define LINK_SPEED_2G 2 /* 2 Gigabaud */ 535 } INIT_LINK_VAR; 536 537 538 /* Structure for MB Command DOWN_LINK (06) */ 539 /* Good for SLI2/3 and SLI4 */ 540 541 typedef struct 542 { 543 uint32_t rsvd1; 544 } DOWN_LINK_VAR; 545 546 547 /* Structure for MB Command CONFIG_LINK (07) */ 548 549 typedef struct 550 { 551 #ifdef EMLXS_BIG_ENDIAN 552 uint32_t cr:1; 553 uint32_t ci:1; 554 uint32_t cr_delay:6; 555 uint32_t cr_count:8; 556 uint32_t rsvd1:8; 557 uint32_t MaxBBC:8; 558 #endif 559 #ifdef EMLXS_LITTLE_ENDIAN 560 uint32_t MaxBBC:8; 561 uint32_t rsvd1:8; 562 uint32_t cr_count:8; 563 uint32_t cr_delay:6; 564 uint32_t ci:1; 565 uint32_t cr:1; 566 #endif 567 uint32_t myId; 568 uint32_t rsvd2; 569 uint32_t edtov; 570 uint32_t arbtov; 571 uint32_t ratov; 572 uint32_t rttov; 573 uint32_t altov; 574 uint32_t crtov; 575 uint32_t citov; 576 #ifdef EMLXS_BIG_ENDIAN 577 uint32_t rrq_enable:1; 578 uint32_t rrq_immed:1; 579 uint32_t rsvd4:29; 580 uint32_t ack0_enable:1; 581 #endif 582 #ifdef EMLXS_LITTLE_ENDIAN 583 uint32_t ack0_enable:1; 584 uint32_t rsvd4:29; 585 uint32_t rrq_immed:1; 586 uint32_t rrq_enable:1; 587 #endif 588 } CONFIG_LINK; 589 590 591 /* Structure for MB Command PART_SLIM (08) */ 592 593 typedef struct 594 { 595 #ifdef EMLXS_BIG_ENDIAN 596 uint32_t unused1:24; 597 uint32_t numRing:8; 598 #endif 599 #ifdef EMLXS_LITTLE_ENDIAN 600 uint32_t numRing:8; 601 uint32_t unused1:24; 602 #endif 603 emlxs_ring_def_t ringdef[4]; 604 uint32_t hbainit; 605 } PART_SLIM_VAR; 606 607 608 /* Structure for MB Command CONFIG_RING (09) */ 609 610 typedef struct 611 { 612 #ifdef EMLXS_BIG_ENDIAN 613 uint32_t unused2:6; 614 uint32_t recvSeq:1; 615 uint32_t recvNotify:1; 616 uint32_t numMask:8; 617 uint32_t profile:8; 618 uint32_t unused1:4; 619 uint32_t ring:4; 620 #endif 621 #ifdef EMLXS_LITTLE_ENDIAN 622 uint32_t ring:4; 623 uint32_t unused1:4; 624 uint32_t profile:8; 625 uint32_t numMask:8; 626 uint32_t recvNotify:1; 627 uint32_t recvSeq:1; 628 uint32_t unused2:6; 629 #endif 630 #ifdef EMLXS_BIG_ENDIAN 631 uint16_t maxRespXchg; 632 uint16_t maxOrigXchg; 633 #endif 634 #ifdef EMLXS_LITTLE_ENDIAN 635 uint16_t maxOrigXchg; 636 uint16_t maxRespXchg; 637 #endif 638 RR_REG rrRegs[6]; 639 } CONFIG_RING_VAR; 640 641 642 /* Structure for MB Command RESET_RING (10) */ 643 644 typedef struct 645 { 646 uint32_t ring_no; 647 } RESET_RING_VAR; 648 649 650 /* Structure for MB Command READ_CONFIG (11) */ 651 /* Good for SLI2/3 only */ 652 653 typedef struct 654 { 655 #ifdef EMLXS_BIG_ENDIAN 656 uint32_t cr:1; 657 uint32_t ci:1; 658 uint32_t cr_delay:6; 659 uint32_t cr_count:8; 660 uint32_t InitBBC:8; 661 uint32_t MaxBBC:8; 662 #endif 663 #ifdef EMLXS_LITTLE_ENDIAN 664 uint32_t MaxBBC:8; 665 uint32_t InitBBC:8; 666 uint32_t cr_count:8; 667 uint32_t cr_delay:6; 668 uint32_t ci:1; 669 uint32_t cr:1; 670 #endif 671 #ifdef EMLXS_BIG_ENDIAN 672 uint32_t topology:8; 673 uint32_t myDid:24; 674 #endif 675 #ifdef EMLXS_LITTLE_ENDIAN 676 uint32_t myDid:24; 677 uint32_t topology:8; 678 #endif 679 /* Defines for topology (defined previously) */ 680 #ifdef EMLXS_BIG_ENDIAN 681 uint32_t AR:1; 682 uint32_t IR:1; 683 uint32_t rsvd1:29; 684 uint32_t ack0:1; 685 #endif 686 #ifdef EMLXS_LITTLE_ENDIAN 687 uint32_t ack0:1; 688 uint32_t rsvd1:29; 689 uint32_t IR:1; 690 uint32_t AR:1; 691 #endif 692 uint32_t edtov; 693 uint32_t arbtov; 694 uint32_t ratov; 695 uint32_t rttov; 696 uint32_t altov; 697 uint32_t lmt; 698 699 #define LMT_1GB_CAPABLE 0x0004 700 #define LMT_2GB_CAPABLE 0x0008 701 #define LMT_4GB_CAPABLE 0x0040 702 #define LMT_8GB_CAPABLE 0x0080 703 #define LMT_10GB_CAPABLE 0x0100 704 /* E2E supported on adapters >= 8GB */ 705 #define LMT_E2E_CAPABLE (LMT_8GB_CAPABLE|LMT_10GB_CAPABLE) 706 707 uint32_t rsvd2; 708 uint32_t rsvd3; 709 uint32_t max_xri; 710 uint32_t max_iocb; 711 uint32_t max_rpi; 712 uint32_t avail_xri; 713 uint32_t avail_iocb; 714 uint32_t avail_rpi; 715 uint32_t max_vpi; 716 uint32_t max_alpa; 717 uint32_t rsvd4; 718 uint32_t avail_vpi; 719 720 } READ_CONFIG_VAR; 721 722 723 /* Structure for MB Command READ_CONFIG(0x11) */ 724 /* Good for SLI4 only */ 725 726 typedef struct 727 { 728 uint32_t rsvd1; /* Word 1 */ 729 #ifdef EMLXS_BIG_ENDIAN 730 uint32_t topology:8; 731 uint32_t rsvd2:24; /* Word 2 */ 732 #endif 733 #ifdef EMLXS_LITTLE_ENDIAN 734 uint32_t rsvd2:24; /* Word 2 */ 735 uint32_t topology:8; 736 #endif 737 uint32_t rsvd3; /* Word 3 */ 738 uint32_t edtov; /* Word 4 */ 739 uint32_t rsvd4; /* Word 5 */ 740 uint32_t ratov; /* Word 6 */ 741 uint32_t rsvd5; /* Word 7 */ 742 uint32_t rsvd6; /* Word 8 */ 743 uint32_t lmt; /* Word 9 */ 744 uint32_t rsvd8; /* Word 10 */ 745 uint32_t rsvd9; /* Word 11 */ 746 747 #ifdef EMLXS_BIG_ENDIAN 748 uint16_t XRICount; /* Word 12 */ 749 uint16_t XRIBase; /* Word 12 */ 750 751 uint16_t RPICount; /* Word 13 */ 752 uint16_t RPIBase; /* Word 13 */ 753 754 uint16_t VPICount; /* Word 14 */ 755 uint16_t VPIBase; /* Word 14 */ 756 757 uint16_t VFICount; /* Word 15 */ 758 uint16_t VFIBase; /* Word 15 */ 759 760 uint16_t FCFICount; /* Word 16 */ 761 uint16_t rsvd10; /* Word 16 */ 762 763 uint16_t EQCount; /* Word 17 */ 764 uint16_t RQCount; /* Word 17 */ 765 766 uint16_t CQCount; /* Word 18 */ 767 uint16_t WQCount; /* Word 18 */ 768 #endif 769 #ifdef EMLXS_LITTLE_ENDIAN 770 uint16_t XRIBase; /* Word 12 */ 771 uint16_t XRICount; /* Word 12 */ 772 773 uint16_t RPIBase; /* Word 13 */ 774 uint16_t RPICount; /* Word 13 */ 775 776 uint16_t VPIBase; /* Word 14 */ 777 uint16_t VPICount; /* Word 14 */ 778 779 uint16_t VFIBase; /* Word 15 */ 780 uint16_t VFICount; /* Word 15 */ 781 782 uint16_t rsvd10; /* Word 16 */ 783 uint16_t FCFICount; /* Word 16 */ 784 785 uint16_t EQCount; /* Word 17 */ 786 uint16_t RQCount; /* Word 17 */ 787 788 uint16_t CQCount; /* Word 18 */ 789 uint16_t WQCount; /* Word 18 */ 790 #endif 791 792 } READ_CONFIG4_VAR; 793 794 /* Structure for MB Command READ_RCONFIG (12) */ 795 796 typedef struct 797 { 798 #ifdef EMLXS_BIG_ENDIAN 799 uint32_t rsvd2:7; 800 uint32_t recvNotify:1; 801 uint32_t numMask:8; 802 uint32_t profile:8; 803 uint32_t rsvd1:4; 804 uint32_t ring:4; 805 #endif 806 #ifdef EMLXS_LITTLE_ENDIAN 807 uint32_t ring:4; 808 uint32_t rsvd1:4; 809 uint32_t profile:8; 810 uint32_t numMask:8; 811 uint32_t recvNotify:1; 812 uint32_t rsvd2:7; 813 #endif 814 #ifdef EMLXS_BIG_ENDIAN 815 uint16_t maxResp; 816 uint16_t maxOrig; 817 #endif 818 #ifdef EMLXS_LITTLE_ENDIAN 819 uint16_t maxOrig; 820 uint16_t maxResp; 821 #endif 822 RR_REG rrRegs[6]; 823 #ifdef EMLXS_BIG_ENDIAN 824 uint16_t cmdRingOffset; 825 uint16_t cmdEntryCnt; 826 uint16_t rspRingOffset; 827 uint16_t rspEntryCnt; 828 uint16_t nextCmdOffset; 829 uint16_t rsvd3; 830 uint16_t nextRspOffset; 831 uint16_t rsvd4; 832 #endif 833 #ifdef EMLXS_LITTLE_ENDIAN 834 uint16_t cmdEntryCnt; 835 uint16_t cmdRingOffset; 836 uint16_t rspEntryCnt; 837 uint16_t rspRingOffset; 838 uint16_t rsvd3; 839 uint16_t nextCmdOffset; 840 uint16_t rsvd4; 841 uint16_t nextRspOffset; 842 #endif 843 } READ_RCONF_VAR; 844 845 846 /* Structure for MB Command READ_SPARM (13) */ 847 /* Structure for MB Command READ_SPARM64 (0x8D) */ 848 /* Good for SLI2/3 and SLI4 */ 849 850 typedef struct 851 { 852 uint32_t rsvd1; 853 uint32_t rsvd2; 854 union 855 { 856 ULP_BDE sp; /* This BDE points to SERV_PARM */ 857 /* structure */ 858 ULP_BDE64 sp64; 859 } un; 860 uint32_t rsvd3; 861 862 #ifdef EMLXS_BIG_ENDIAN 863 uint16_t portNameCnt; 864 uint16_t portNameOffset; 865 866 uint16_t fabricNameCnt; 867 uint16_t fabricNameOffset; 868 869 uint16_t lportNameCnt; 870 uint16_t lportNameOffset; 871 872 uint16_t lfabricNameCnt; 873 uint16_t lfabricNameOffset; 874 875 #endif 876 #ifdef EMLXS_LITTLE_ENDIAN 877 uint16_t portNameOffset; 878 uint16_t portNameCnt; 879 880 uint16_t fabricNameOffset; 881 uint16_t fabricNameCnt; 882 883 uint16_t lportNameOffset; 884 uint16_t lportNameCnt; 885 886 uint16_t lfabricNameOffset; 887 uint16_t lfabricNameCnt; 888 889 #endif 890 891 } READ_SPARM_VAR; 892 893 894 /* Structure for MB Command READ_STATUS (14) */ 895 /* Good for SLI2/3 and SLI4 */ 896 897 typedef struct 898 { 899 #ifdef EMLXS_BIG_ENDIAN 900 uint32_t rsvd1:31; 901 uint32_t clrCounters:1; 902 903 uint16_t activeXriCnt; 904 uint16_t activeRpiCnt; 905 #endif 906 #ifdef EMLXS_LITTLE_ENDIAN 907 uint32_t clrCounters:1; 908 uint32_t rsvd1:31; 909 910 uint16_t activeRpiCnt; 911 uint16_t activeXriCnt; 912 #endif 913 uint32_t xmitByteCnt; 914 uint32_t rcvByteCnt; 915 uint32_t xmitFrameCnt; 916 uint32_t rcvFrameCnt; 917 uint32_t xmitSeqCnt; 918 uint32_t rcvSeqCnt; 919 uint32_t totalOrigExchanges; 920 uint32_t totalRespExchanges; 921 uint32_t rcvPbsyCnt; 922 uint32_t rcvFbsyCnt; 923 } READ_STATUS_VAR; 924 925 926 /* Structure for MB Command READ_RPI (15) */ 927 /* Structure for MB Command READ_RPI64 (0x8F) */ 928 929 typedef struct 930 { 931 #ifdef EMLXS_BIG_ENDIAN 932 uint16_t nextRpi; 933 uint16_t reqRpi; 934 uint32_t rsvd2:8; 935 uint32_t DID:24; 936 #endif 937 #ifdef EMLXS_LITTLE_ENDIAN 938 uint16_t reqRpi; 939 uint16_t nextRpi; 940 uint32_t DID:24; 941 uint32_t rsvd2:8; 942 #endif 943 union 944 { 945 ULP_BDE sp; 946 ULP_BDE64 sp64; 947 } un; 948 } READ_RPI_VAR; 949 950 951 /* Structure for MB Command READ_XRI (16) */ 952 953 typedef struct 954 { 955 #ifdef EMLXS_BIG_ENDIAN 956 uint16_t nextXri; 957 uint16_t reqXri; 958 uint16_t rsvd1; 959 uint16_t rpi; 960 uint32_t rsvd2:8; 961 uint32_t DID:24; 962 uint32_t rsvd3:8; 963 uint32_t SID:24; 964 uint32_t rsvd4; 965 uint8_t seqId; 966 uint8_t rsvd5; 967 uint16_t seqCount; 968 uint16_t oxId; 969 uint16_t rxId; 970 uint32_t rsvd6:30; 971 uint32_t si:1; 972 uint32_t exchOrig:1; 973 #endif 974 #ifdef EMLXS_LITTLE_ENDIAN 975 uint16_t reqXri; 976 uint16_t nextXri; 977 uint16_t rpi; 978 uint16_t rsvd1; 979 uint32_t DID:24; 980 uint32_t rsvd2:8; 981 uint32_t SID:24; 982 uint32_t rsvd3:8; 983 uint32_t rsvd4; 984 uint16_t seqCount; 985 uint8_t rsvd5; 986 uint8_t seqId; 987 uint16_t rxId; 988 uint16_t oxId; 989 uint32_t exchOrig:1; 990 uint32_t si:1; 991 uint32_t rsvd6:30; 992 #endif 993 } READ_XRI_VAR; 994 995 996 /* Structure for MB Command READ_REV (17) */ 997 /* Good for SLI2/3 only */ 998 999 typedef struct 1000 { 1001 #ifdef EMLXS_BIG_ENDIAN 1002 uint32_t cv:1; 1003 uint32_t rr:1; 1004 uint32_t co:1; 1005 uint32_t rp:1; 1006 uint32_t cv3:1; 1007 uint32_t rf3:1; 1008 uint32_t rsvd1:10; 1009 uint32_t offset:14; 1010 uint32_t rv:2; 1011 #endif 1012 #ifdef EMLXS_LITTLE_ENDIAN 1013 uint32_t rv:2; 1014 uint32_t offset:14; 1015 uint32_t rsvd1:10; 1016 uint32_t rf3:1; 1017 uint32_t cv3:1; 1018 uint32_t rp:1; 1019 uint32_t co:1; 1020 uint32_t rr:1; 1021 uint32_t cv:1; 1022 #endif 1023 uint32_t biuRev; 1024 uint32_t smRev; 1025 union 1026 { 1027 uint32_t smFwRev; 1028 struct 1029 { 1030 #ifdef EMLXS_BIG_ENDIAN 1031 uint8_t ProgType; 1032 uint8_t ProgId; 1033 uint16_t ProgVer:4; 1034 uint16_t ProgRev:4; 1035 uint16_t ProgFixLvl:2; 1036 uint16_t ProgDistType:2; 1037 uint16_t DistCnt:4; 1038 #endif 1039 #ifdef EMLXS_LITTLE_ENDIAN 1040 uint16_t DistCnt:4; 1041 uint16_t ProgDistType:2; 1042 uint16_t ProgFixLvl:2; 1043 uint16_t ProgRev:4; 1044 uint16_t ProgVer:4; 1045 uint8_t ProgId; 1046 uint8_t ProgType; 1047 #endif 1048 } b; 1049 } un; 1050 uint32_t endecRev; 1051 #ifdef EMLXS_BIG_ENDIAN 1052 uint8_t feaLevelHigh; 1053 uint8_t feaLevelLow; 1054 uint8_t fcphHigh; 1055 uint8_t fcphLow; 1056 #endif 1057 #ifdef EMLXS_LITTLE_ENDIAN 1058 uint8_t fcphLow; 1059 uint8_t fcphHigh; 1060 uint8_t feaLevelLow; 1061 uint8_t feaLevelHigh; 1062 #endif 1063 uint32_t postKernRev; 1064 uint32_t opFwRev; 1065 uint8_t opFwName[16]; 1066 1067 uint32_t sliFwRev1; 1068 uint8_t sliFwName1[16]; 1069 uint32_t sliFwRev2; 1070 uint8_t sliFwName2[16]; 1071 } READ_REV_VAR; 1072 1073 /* Structure for MB Command READ_REV (17) */ 1074 /* Good for SLI4 only */ 1075 1076 typedef struct 1077 { 1078 #ifdef EMLXS_BIG_ENDIAN 1079 uint32_t Rsvd3:2; 1080 uint32_t VPD:1; 1081 uint32_t rsvd2:6; 1082 uint32_t dcbxMode:2; 1083 uint32_t FCoE:1; 1084 uint32_t sliLevel:4; 1085 uint32_t rsvd1:16; 1086 #endif 1087 #ifdef EMLXS_LITTLE_ENDIAN 1088 uint32_t rsvd1:16; 1089 uint32_t sliLevel:4; 1090 uint32_t FCoE:1; 1091 uint32_t dcbxMode:2; 1092 uint32_t rsvd2:6; 1093 uint32_t VPD:1; 1094 uint32_t Rsvd3:2; 1095 #endif 1096 1097 uint32_t HwRev1; 1098 uint32_t HwRev2; 1099 uint32_t Rsvd4; 1100 uint32_t HwRev3; 1101 1102 #ifdef EMLXS_BIG_ENDIAN 1103 uint8_t feaLevelHigh; 1104 uint8_t feaLevelLow; 1105 uint8_t fcphHigh; 1106 uint8_t fcphLow; 1107 #endif 1108 #ifdef EMLXS_LITTLE_ENDIAN 1109 uint8_t fcphLow; 1110 uint8_t fcphHigh; 1111 uint8_t feaLevelLow; 1112 uint8_t feaLevelHigh; 1113 #endif 1114 1115 uint32_t Redboot; 1116 1117 uint32_t ARMFwId; 1118 uint8_t ARMFwName[16]; 1119 1120 uint32_t ULPFwId; 1121 uint8_t ULPFwName[16]; 1122 1123 uint32_t Rsvd6[30]; 1124 1125 ULP_BDE64 VPDBde; 1126 1127 uint32_t ReturnedVPDLength; 1128 1129 } READ_REV4_VAR; 1130 1131 #define EMLXS_DCBX_MODE_CIN 0 /* Mapped to nonFIP mode */ 1132 #define EMLXS_DCBX_MODE_CEE 1 /* Mapped to FIP mode */ 1133 1134 /* Structure for MB Command READ_LINK_STAT (18) */ 1135 /* Good for SLI2/3 and SLI4 */ 1136 1137 typedef struct 1138 { 1139 uint32_t rsvd1; 1140 uint32_t linkFailureCnt; 1141 uint32_t lossSyncCnt; 1142 1143 uint32_t lossSignalCnt; 1144 uint32_t primSeqErrCnt; 1145 uint32_t invalidXmitWord; 1146 uint32_t crcCnt; 1147 uint32_t primSeqTimeout; 1148 uint32_t elasticOverrun; 1149 uint32_t arbTimeout; 1150 1151 uint32_t rxBufCredit; 1152 uint32_t rxBufCreditCur; 1153 1154 uint32_t txBufCredit; 1155 uint32_t txBufCreditCur; 1156 1157 uint32_t EOFaCnt; 1158 uint32_t EOFdtiCnt; 1159 uint32_t EOFniCnt; 1160 uint32_t SOFfCnt; 1161 uint32_t DropAERCnt; 1162 uint32_t DropRcv; 1163 } READ_LNK_VAR; 1164 1165 1166 /* Structure for MB Command REG_LOGIN (19) */ 1167 /* Structure for MB Command REG_LOGIN64 (0x93) */ 1168 /* Structure for MB Command REG_RPI (0x93) */ 1169 /* Good for SLI2/3 and SLI4 */ 1170 1171 typedef struct 1172 { 1173 #ifdef EMLXS_BIG_ENDIAN 1174 uint16_t rsvd1; 1175 uint16_t rpi; 1176 uint32_t CI:1; 1177 uint32_t rsvd2:7; 1178 uint32_t did:24; 1179 #endif 1180 #ifdef EMLXS_LITTLE_ENDIAN 1181 uint16_t rpi; 1182 uint16_t rsvd1; 1183 uint32_t did:24; 1184 uint32_t rsvd2:7; 1185 uint32_t CI:1; 1186 #endif 1187 union 1188 { 1189 ULP_BDE sp; 1190 ULP_BDE64 sp64; 1191 } un; 1192 1193 #ifdef EMLXS_BIG_ENDIAN 1194 uint16_t rsvd6; 1195 uint16_t vpi; 1196 #endif 1197 #ifdef EMLXS_LITTLE_ENDIAN 1198 uint16_t vpi; 1199 uint16_t rsvd6; 1200 #endif 1201 } REG_LOGIN_VAR; 1202 1203 /* Word 30 contents for REG_LOGIN */ 1204 typedef union 1205 { 1206 struct 1207 { 1208 #ifdef EMLXS_BIG_ENDIAN 1209 uint16_t rsvd1:12; 1210 uint16_t class:4; 1211 uint16_t xri; 1212 #endif 1213 #ifdef EMLXS_LITTLE_ENDIAN 1214 uint16_t xri; 1215 uint16_t class:4; 1216 uint16_t rsvd1:12; 1217 #endif 1218 } f; 1219 uint32_t word; 1220 } REG_WD30; 1221 1222 1223 /* Structure for MB Command UNREG_LOGIN (0x14) - SLI2/3 */ 1224 /* Structure for MB Command UNREG_RPI (0x14) - SLI4 */ 1225 1226 typedef struct 1227 { 1228 #ifdef EMLXS_BIG_ENDIAN 1229 uint16_t ll:2; /* SLI4 only */ 1230 uint16_t rsvd1:14; 1231 uint16_t rpi; 1232 #endif 1233 #ifdef EMLXS_LITTLE_ENDIAN 1234 uint16_t rpi; 1235 uint16_t rsvd1:14; 1236 uint16_t ll:2; /* SLI4 only */ 1237 #endif 1238 1239 uint32_t rsvd2; 1240 uint32_t rsvd3; 1241 uint32_t rsvd4; 1242 uint32_t rsvd5; 1243 #ifdef EMLXS_BIG_ENDIAN 1244 uint16_t rsvd6; 1245 uint16_t vpi; 1246 #endif 1247 #ifdef EMLXS_LITTLE_ENDIAN 1248 uint16_t vpi; 1249 uint16_t rsvd6; 1250 #endif 1251 } UNREG_LOGIN_VAR; 1252 1253 /* Structure for MB Command REG_FCFI (0xA0) */ 1254 /* Good for SLI4 only */ 1255 1256 typedef struct 1257 { 1258 #ifdef EMLXS_BIG_ENDIAN 1259 uint16_t FCFI; 1260 uint16_t InfoIndex; 1261 1262 uint16_t RQId0; 1263 uint16_t RQId1; 1264 uint16_t RQId2; 1265 uint16_t RQId3; 1266 1267 uint8_t Id0_type; 1268 uint8_t Id0_type_mask; 1269 uint8_t Id0_rctl; 1270 uint8_t Id0_rctl_mask; 1271 1272 uint8_t Id1_type; 1273 uint8_t Id1_type_mask; 1274 uint8_t Id1_rctl; 1275 uint8_t Id1_rctl_mask; 1276 1277 uint8_t Id2_type; 1278 uint8_t Id2_type_mask; 1279 uint8_t Id2_rctl; 1280 uint8_t Id2_rctl_mask; 1281 1282 uint8_t Id3_type; 1283 uint8_t Id3_type_mask; 1284 uint8_t Id3_rctl; 1285 uint8_t Id3_rctl_mask; 1286 1287 uint32_t Rsvd1: 17; 1288 uint32_t mam: 2; 1289 uint32_t vv: 1; 1290 uint32_t vlanTag: 12; 1291 #endif 1292 #ifdef EMLXS_LITTLE_ENDIAN 1293 uint16_t InfoIndex; 1294 uint16_t FCFI; 1295 1296 uint16_t RQId1; 1297 uint16_t RQId0; 1298 uint16_t RQId3; 1299 uint16_t RQId2; 1300 1301 uint8_t Id0_rctl_mask; 1302 uint8_t Id0_rctl; 1303 uint8_t Id0_type_mask; 1304 uint8_t Id0_type; 1305 1306 uint8_t Id1_rctl_mask; 1307 uint8_t Id1_rctl; 1308 uint8_t Id1_type_mask; 1309 uint8_t Id1_type; 1310 1311 uint8_t Id2_rctl_mask; 1312 uint8_t Id2_rctl; 1313 uint8_t Id2_type_mask; 1314 uint8_t Id2_type; 1315 1316 uint8_t Id3_rctl_mask; 1317 uint8_t Id3_rctl; 1318 uint8_t Id3_type_mask; 1319 uint8_t Id3_type; 1320 1321 uint32_t vlanTag: 12; 1322 uint32_t vv: 1; 1323 uint32_t mam: 2; 1324 uint32_t Rsvd1: 17; 1325 #endif 1326 1327 } REG_FCFI_VAR; 1328 1329 /* Defines for mam */ 1330 #define EMLXS_REG_FCFI_MAM_SPMA 1 /* Server Provided MAC Address */ 1331 #define EMLXS_REG_FCFI_MAM_FPMA 2 /* Fabric Provided MAC Address */ 1332 1333 /* Structure for MB Command UNREG_FCFI (0xA2) */ 1334 /* Good for SLI4 only */ 1335 1336 typedef struct 1337 { 1338 uint32_t Rsvd1; 1339 #ifdef EMLXS_BIG_ENDIAN 1340 uint16_t Rsvd2; 1341 uint16_t FCFI; 1342 #endif 1343 #ifdef EMLXS_LITTLE_ENDIAN 1344 uint16_t FCFI; 1345 uint16_t Rsvd2; 1346 #endif 1347 } UNREG_FCFI_VAR; 1348 1349 /* Structure for MB Command RESUME_RPI (0x9E) */ 1350 /* Good for SLI4 only */ 1351 1352 typedef struct 1353 { 1354 #ifdef EMLXS_BIG_ENDIAN 1355 uint16_t Rsvd1; 1356 uint16_t RPI; 1357 1358 uint32_t EventTag; 1359 uint32_t rsvd2[3]; 1360 1361 uint16_t VFI; 1362 uint16_t VPI; 1363 #endif 1364 #ifdef EMLXS_LITTLE_ENDIAN 1365 uint16_t RPI; 1366 uint16_t Rsvd1; 1367 1368 uint32_t EventTag; 1369 uint32_t rsvd2[3]; 1370 1371 uint16_t VPI; 1372 uint16_t VFI; 1373 #endif 1374 1375 } RESUME_RPI_VAR; 1376 1377 1378 /* Structure for MB Command UNREG_D_ID (0x23) */ 1379 1380 typedef struct 1381 { 1382 uint32_t did; 1383 1384 uint32_t rsvd2; 1385 uint32_t rsvd3; 1386 uint32_t rsvd4; 1387 uint32_t rsvd5; 1388 #ifdef EMLXS_BIG_ENDIAN 1389 uint16_t rsvd6; 1390 uint16_t vpi; 1391 #endif 1392 #ifdef EMLXS_LITTLE_ENDIAN 1393 uint16_t vpi; 1394 uint16_t rsvd6; 1395 #endif 1396 } UNREG_D_ID_VAR; 1397 1398 1399 /* Structure for MB Command READ_LA (21) */ 1400 /* Structure for MB Command READ_LA64 (0x95) */ 1401 1402 typedef struct 1403 { 1404 uint32_t eventTag; /* Event tag */ 1405 #ifdef EMLXS_BIG_ENDIAN 1406 uint32_t rsvd2:19; 1407 uint32_t fa:1; 1408 uint32_t mm:1; 1409 uint32_t tc:1; 1410 uint32_t pb:1; 1411 uint32_t il:1; 1412 uint32_t attType:8; 1413 #endif 1414 #ifdef EMLXS_LITTLE_ENDIAN 1415 uint32_t attType:8; 1416 uint32_t il:1; 1417 uint32_t pb:1; 1418 uint32_t tc:1; 1419 uint32_t mm:1; 1420 uint32_t fa:1; 1421 uint32_t rsvd2:19; 1422 #endif 1423 #define AT_RESERVED 0x00 /* Reserved - attType */ 1424 #define AT_LINK_UP 0x01 /* Link is up */ 1425 #define AT_LINK_DOWN 0x02 /* Link is down */ 1426 #ifdef EMLXS_BIG_ENDIAN 1427 uint8_t granted_AL_PA; 1428 uint8_t lipAlPs; 1429 uint8_t lipType; 1430 uint8_t topology; 1431 #endif 1432 #ifdef EMLXS_LITTLE_ENDIAN 1433 uint8_t topology; 1434 uint8_t lipType; 1435 uint8_t lipAlPs; 1436 uint8_t granted_AL_PA; 1437 #endif 1438 1439 /* lipType */ 1440 #define LT_PORT_INIT 0x00 /* An L_PORT initing (F7, AL_PS) - lipType */ 1441 #define LT_PORT_ERR 0x01 /* Err @L_PORT rcv'er (F8, AL_PS) */ 1442 #define LT_RESET_APORT 0x02 /* Lip Reset of some other port */ 1443 #define LT_RESET_MYPORT 0x03 /* Lip Reset of my port */ 1444 1445 /* topology */ 1446 #define TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */ 1447 #define TOPOLOGY_LOOP 0x02 /* Topology is FC-AL (private) */ 1448 1449 union 1450 { 1451 ULP_BDE lilpBde; /* This BDE points to a */ 1452 /* 128 byte buffer to store */ 1453 /* the LILP AL_PA position */ 1454 /* map into */ 1455 ULP_BDE64 lilpBde64; 1456 } un; 1457 #ifdef EMLXS_BIG_ENDIAN 1458 uint32_t Dlu:1; 1459 uint32_t Dtf:1; 1460 uint32_t Drsvd2:14; 1461 uint32_t DlnkSpeed:8; 1462 uint32_t DnlPort:4; 1463 uint32_t Dtx:2; 1464 uint32_t Drx:2; 1465 #endif 1466 #ifdef EMLXS_LITTLE_ENDIAN 1467 uint32_t Drx:2; 1468 uint32_t Dtx:2; 1469 uint32_t DnlPort:4; 1470 uint32_t DlnkSpeed:8; 1471 uint32_t Drsvd2:14; 1472 uint32_t Dtf:1; 1473 uint32_t Dlu:1; 1474 #endif 1475 #ifdef EMLXS_BIG_ENDIAN 1476 uint32_t Ulu:1; 1477 uint32_t Utf:1; 1478 uint32_t Ursvd2:14; 1479 uint32_t UlnkSpeed:8; 1480 uint32_t UnlPort:4; 1481 uint32_t Utx:2; 1482 uint32_t Urx:2; 1483 #endif 1484 #ifdef EMLXS_LITTLE_ENDIAN 1485 uint32_t Urx:2; 1486 uint32_t Utx:2; 1487 uint32_t UnlPort:4; 1488 uint32_t UlnkSpeed:8; 1489 uint32_t Ursvd2:14; 1490 uint32_t Utf:1; 1491 uint32_t Ulu:1; 1492 #endif 1493 1494 #define LA_1GHZ_LINK 0x04 /* lnkSpeed */ 1495 #define LA_2GHZ_LINK 0x08 /* lnkSpeed */ 1496 #define LA_4GHZ_LINK 0x10 /* lnkSpeed */ 1497 #define LA_8GHZ_LINK 0x20 /* lnkSpeed */ 1498 #define LA_10GHZ_LINK 0x40 /* lnkSpeed */ 1499 } READ_LA_VAR; 1500 1501 1502 /* Structure for MB Command CLEAR_LA (22) */ 1503 1504 typedef struct 1505 { 1506 uint32_t eventTag; /* Event tag */ 1507 uint32_t rsvd1; 1508 } CLEAR_LA_VAR; 1509 1510 /* Structure for MB Command DUMP */ 1511 /* Good for SLI2/3 only */ 1512 1513 typedef struct 1514 { 1515 #ifdef EMLXS_BIG_ENDIAN 1516 uint32_t rsvd:25; 1517 uint32_t ra:1; 1518 uint32_t co:1; 1519 uint32_t cv:1; 1520 uint32_t type:4; 1521 1522 uint32_t entry_index:16; 1523 uint32_t region_id:16; 1524 #endif 1525 #ifdef EMLXS_LITTLE_ENDIAN 1526 uint32_t type:4; 1527 uint32_t cv:1; 1528 uint32_t co:1; 1529 uint32_t ra:1; 1530 uint32_t rsvd:25; 1531 1532 uint32_t region_id:16; 1533 uint32_t entry_index:16; 1534 #endif 1535 uint32_t base_adr; 1536 uint32_t word_cnt; 1537 uint32_t resp_offset; 1538 } DUMP_VAR; 1539 1540 /* Structure for MB Command DUMP */ 1541 /* Good for SLI4 only */ 1542 1543 typedef struct 1544 { 1545 #ifdef EMLXS_BIG_ENDIAN 1546 uint32_t ppi:4; 1547 uint32_t phy_index:4; 1548 uint32_t rsvd:20; 1549 uint32_t type:4; 1550 1551 uint32_t entry_index:16; 1552 uint32_t region_id:16; 1553 #endif 1554 #ifdef EMLXS_LITTLE_ENDIAN 1555 uint32_t type:4; 1556 uint32_t rsvd:20; 1557 uint32_t phy_index:4; 1558 uint32_t ppi:4; 1559 1560 uint32_t region_id:16; 1561 uint32_t entry_index:16; 1562 #endif 1563 uint32_t available_cnt; 1564 uint32_t addrLow; 1565 uint32_t addrHigh; 1566 uint32_t rsp_cnt; 1567 } DUMP4_VAR; 1568 1569 /* 1570 * Dump type 1571 */ 1572 #define DMP_MEM_REG 0x1 1573 #define DMP_NV_PARAMS 0x2 1574 1575 /* 1576 * Dump region ID 1577 */ 1578 #define NODE_CFG_A_REGION_ID 0 1579 #define NODE_CFG_B_REGION_ID 1 1580 #define NODE_CFG_C_REGION_ID 2 1581 #define NODE_CFG_D_REGION_ID 3 1582 #define WAKE_UP_PARMS_REGION_ID 4 1583 #define DEF_PCI_CFG_REGION_ID 5 1584 #define PCI_CFG_1_REGION_ID 6 1585 #define PCI_CFG_2_REGION_ID 7 1586 #define RSVD1_REGION_ID 8 1587 #define RSVD2_REGION_ID 9 1588 #define RSVD3_REGION_ID 10 1589 #define RSVD4_REGION_ID 11 1590 #define RSVD5_REGION_ID 12 1591 #define RSVD6_REGION_ID 13 1592 #define RSVD7_REGION_ID 14 1593 #define DIAG_TRACE_REGION_ID 15 1594 #define WWN_REGION_ID 16 1595 1596 #define DMP_VPD_REGION 14 1597 #define DMP_VPD_SIZE 1024 1598 #define DMP_VPD_DUMP_WCOUNT 24 1599 1600 #define DMP_FCOE_REGION 23 1601 #define DMP_FCOE_DUMP_WCOUNT 256 1602 1603 1604 /* Structure for MB Command UPDATE_CFG */ 1605 /* Good for SLI2/3 and SLI4 */ 1606 1607 typedef struct 1608 { 1609 #ifdef EMLXS_BIG_ENDIAN 1610 uint32_t rsvd2:16; 1611 uint32_t proc_type:8; 1612 uint32_t rsvd1:1; 1613 uint32_t Abit:1; 1614 uint32_t Obit:1; 1615 uint32_t Vbit:1; 1616 uint32_t req_type:4; 1617 #define INIT_REGION 1 1618 #define UPDATE_DATA 2 1619 #define CLEAN_UP_CFG 3 1620 uint32_t entry_len:16; 1621 uint32_t region_id:16; 1622 #endif 1623 1624 #ifdef EMLXS_LITTLE_ENDIAN 1625 uint32_t req_type:4; 1626 #define INIT_REGION 1 1627 #define UPDATE_DATA 2 1628 #define CLEAN_UP_CFG 3 1629 uint32_t Vbit:1; 1630 uint32_t Obit:1; 1631 uint32_t Abit:1; 1632 uint32_t rsvd1:1; 1633 uint32_t proc_type:8; 1634 uint32_t rsvd2:16; 1635 1636 uint32_t region_id:16; 1637 uint32_t entry_len:16; 1638 #endif 1639 1640 uint32_t rsp_info; 1641 uint32_t byte_len; 1642 uint32_t cfg_data; 1643 } UPDATE_CFG_VAR; 1644 1645 /* Structure for MB Command DEL_LD_ENTRY (29) */ 1646 1647 typedef struct 1648 { 1649 #ifdef EMLXS_LITTLE_ENDIAN 1650 uint32_t list_req:2; 1651 uint32_t list_rsp:2; 1652 uint32_t rsvd:28; 1653 #else 1654 uint32_t rsvd:28; 1655 uint32_t list_rsp:2; 1656 uint32_t list_req:2; 1657 #endif 1658 1659 #define FLASH_LOAD_LIST 1 1660 #define RAM_LOAD_LIST 2 1661 #define BOTH_LISTS 3 1662 1663 PROG_ID prog_id; 1664 } DEL_LD_ENTRY_VAR; 1665 1666 /* Structure for MB Command LOAD_AREA (81) */ 1667 typedef struct 1668 { 1669 #ifdef EMLXS_LITTLE_ENDIAN 1670 uint32_t load_cmplt:1; 1671 uint32_t method:1; 1672 uint32_t rsvd1:1; 1673 uint32_t update_flash:1; 1674 uint32_t erase_or_prog:1; 1675 uint32_t version:1; 1676 uint32_t rsvd2:2; 1677 uint32_t progress:8; 1678 uint32_t step:8; 1679 uint32_t area_id:8; 1680 #else 1681 uint32_t area_id:8; 1682 uint32_t step:8; 1683 uint32_t progress:8; 1684 uint32_t rsvd2:2; 1685 uint32_t version:1; 1686 uint32_t erase_or_prog:1; 1687 uint32_t update_flash:1; 1688 uint32_t rsvd1:1; 1689 uint32_t method:1; 1690 uint32_t load_cmplt:1; 1691 #endif 1692 uint32_t dl_to_adr; 1693 uint32_t dl_len; 1694 union 1695 { 1696 uint32_t dl_from_slim_offset; 1697 ULP_BDE dl_from_bde; 1698 ULP_BDE64 dl_from_bde64; 1699 PROG_ID prog_id; 1700 } un; 1701 } LOAD_AREA_VAR; 1702 1703 /* Structure for MB Command LOAD_EXP_ROM (9C) */ 1704 typedef struct 1705 { 1706 #ifdef EMLXS_LITTLE_ENDIAN 1707 uint32_t rsvd1:8; 1708 uint32_t progress:8; 1709 uint32_t step:8; 1710 uint32_t rsvd2:8; 1711 #else 1712 uint32_t rsvd2:8; 1713 uint32_t step:8; 1714 uint32_t progress:8; 1715 uint32_t rsvd1:8; 1716 #endif 1717 uint32_t dl_to_adr; 1718 uint32_t rsvd3; 1719 union 1720 { 1721 uint32_t word[2]; 1722 PROG_ID prog_id; 1723 } un; 1724 } LOAD_EXP_ROM_VAR; 1725 1726 1727 /* Structure for MB Command CONFIG_HBQ (7C) */ 1728 1729 typedef struct 1730 { 1731 #ifdef EMLXS_BIG_ENDIAN 1732 uint32_t rsvd1:7; 1733 uint32_t recvNotify:1; /* Receive Notification */ 1734 uint32_t numMask:8; /* # Mask Entries */ 1735 uint32_t profile:8; /* Selection Profile */ 1736 uint32_t rsvd2:8; 1737 #endif 1738 #ifdef EMLXS_LITTLE_ENDIAN 1739 uint32_t rsvd2:8; 1740 uint32_t profile:8; /* Selection Profile */ 1741 uint32_t numMask:8; /* # Mask Entries */ 1742 uint32_t recvNotify:1; /* Receive Notification */ 1743 uint32_t rsvd1:7; 1744 #endif 1745 1746 #ifdef EMLXS_BIG_ENDIAN 1747 uint32_t hbqId:16; 1748 uint32_t rsvd3:12; 1749 uint32_t ringMask:4; 1750 #endif 1751 #ifdef EMLXS_LITTLE_ENDIAN 1752 uint32_t ringMask:4; 1753 uint32_t rsvd3:12; 1754 uint32_t hbqId:16; 1755 #endif 1756 1757 #ifdef EMLXS_BIG_ENDIAN 1758 uint32_t numEntries:16; 1759 uint32_t rsvd4:8; 1760 uint32_t headerLen:8; 1761 #endif 1762 #ifdef EMLXS_LITTLE_ENDIAN 1763 uint32_t headerLen:8; 1764 uint32_t rsvd4:8; 1765 uint32_t numEntries:16; 1766 #endif 1767 1768 uint32_t hbqaddrLow; 1769 uint32_t hbqaddrHigh; 1770 1771 #ifdef EMLXS_BIG_ENDIAN 1772 uint32_t rsvd5:31; 1773 uint32_t logEntry:1; 1774 #endif 1775 #ifdef EMLXS_LITTLE_ENDIAN 1776 uint32_t logEntry:1; 1777 uint32_t rsvd5:31; 1778 #endif 1779 1780 uint32_t rsvd6; /* w7 */ 1781 uint32_t rsvd7; /* w8 */ 1782 uint32_t rsvd8; /* w9 */ 1783 1784 HBQ_MASK hbqMasks[6]; 1785 1786 union 1787 { 1788 uint32_t allprofiles[12]; 1789 1790 struct 1791 { 1792 #ifdef EMLXS_BIG_ENDIAN 1793 uint32_t seqlenoff:16; 1794 uint32_t maxlen:16; 1795 #endif 1796 #ifdef EMLXS_LITTLE_ENDIAN 1797 uint32_t maxlen:16; 1798 uint32_t seqlenoff:16; 1799 #endif 1800 #ifdef EMLXS_BIG_ENDIAN 1801 uint32_t rsvd1:28; 1802 uint32_t seqlenbcnt:4; 1803 #endif 1804 #ifdef EMLXS_LITTLE_ENDIAN 1805 uint32_t seqlenbcnt:4; 1806 uint32_t rsvd1:28; 1807 #endif 1808 uint32_t rsvd[10]; 1809 } profile2; 1810 1811 struct 1812 { 1813 #ifdef EMLXS_BIG_ENDIAN 1814 uint32_t seqlenoff:16; 1815 uint32_t maxlen:16; 1816 #endif 1817 #ifdef EMLXS_LITTLE_ENDIAN 1818 uint32_t maxlen:16; 1819 uint32_t seqlenoff:16; 1820 #endif 1821 #ifdef EMLXS_BIG_ENDIAN 1822 uint32_t cmdcodeoff:28; 1823 uint32_t rsvd1:12; 1824 uint32_t seqlenbcnt:4; 1825 #endif 1826 #ifdef EMLXS_LITTLE_ENDIAN 1827 uint32_t seqlenbcnt:4; 1828 uint32_t rsvd1:12; 1829 uint32_t cmdcodeoff:28; 1830 #endif 1831 uint32_t cmdmatch[8]; 1832 1833 uint32_t rsvd[2]; 1834 } profile3; 1835 1836 struct 1837 { 1838 #ifdef EMLXS_BIG_ENDIAN 1839 uint32_t seqlenoff:16; 1840 uint32_t maxlen:16; 1841 #endif 1842 #ifdef EMLXS_LITTLE_ENDIAN 1843 uint32_t maxlen:16; 1844 uint32_t seqlenoff:16; 1845 #endif 1846 #ifdef EMLXS_BIG_ENDIAN 1847 uint32_t cmdcodeoff:28; 1848 uint32_t rsvd1:12; 1849 uint32_t seqlenbcnt:4; 1850 #endif 1851 #ifdef EMLXS_LITTLE_ENDIAN 1852 uint32_t seqlenbcnt:4; 1853 uint32_t rsvd1:12; 1854 uint32_t cmdcodeoff:28; 1855 #endif 1856 uint32_t cmdmatch[8]; 1857 1858 uint32_t rsvd[2]; 1859 } profile5; 1860 } profiles; 1861 } CONFIG_HBQ_VAR; 1862 1863 1864 /* Structure for MB Command REG_VPI(0x96) */ 1865 /* Good for SLI2/3 and SLI4 */ 1866 1867 typedef struct 1868 { 1869 #ifdef EMLXS_BIG_ENDIAN 1870 uint32_t rsvd1; 1871 uint32_t rsvd2:7; 1872 uint32_t upd:1; 1873 uint32_t sid:24; 1874 uint32_t portname[2]; /* N_PORT name */ 1875 uint32_t rsvd5; 1876 uint16_t vfi; 1877 uint16_t vpi; 1878 #endif 1879 #ifdef EMLXS_LITTLE_ENDIAN 1880 uint32_t rsvd1; 1881 uint32_t sid:24; 1882 uint32_t upd:1; 1883 uint32_t rsvd2:7; 1884 uint32_t portname[2]; /* N_PORT name */ 1885 uint32_t rsvd5; 1886 uint16_t vpi; 1887 uint16_t vfi; 1888 #endif 1889 } REG_VPI_VAR; 1890 1891 /* Structure for MB Command INIT_VPI(0xA3) */ 1892 /* Good for SLI4 only */ 1893 1894 typedef struct 1895 { 1896 #ifdef EMLXS_BIG_ENDIAN 1897 uint16_t vfi; 1898 uint16_t vpi; 1899 #endif 1900 #ifdef EMLXS_LITTLE_ENDIAN 1901 uint16_t vpi; 1902 uint16_t vfi; 1903 #endif 1904 } INIT_VPI_VAR; 1905 1906 /* Structure for MB Command UNREG_VPI (0x97) */ 1907 /* Good for SLI2/3 */ 1908 1909 typedef struct 1910 { 1911 uint32_t rsvd1; 1912 uint32_t rsvd2; 1913 uint32_t rsvd3; 1914 uint32_t rsvd4; 1915 uint32_t rsvd5; 1916 #ifdef EMLXS_BIG_ENDIAN 1917 uint16_t rsvd6; 1918 uint16_t vpi; 1919 #endif 1920 #ifdef EMLXS_LITTLE_ENDIAN 1921 uint16_t vpi; 1922 uint16_t rsvd6; 1923 #endif 1924 } UNREG_VPI_VAR; 1925 1926 /* Structure for MB Command UNREG_VPI (0x97) */ 1927 /* Good for SLI4 */ 1928 1929 typedef struct 1930 { 1931 uint32_t rsvd1; 1932 #ifdef EMLXS_BIG_ENDIAN 1933 uint8_t ii:2; 1934 uint16_t rsvd2:14; 1935 uint16_t index; 1936 #endif 1937 #ifdef EMLXS_LITTLE_ENDIAN 1938 uint16_t index; 1939 uint16_t rsvd2:14; 1940 uint8_t ii:2; 1941 #endif 1942 } UNREG_VPI_VAR4; 1943 1944 /* Structure for MB Command REG_VFI(0x9F) */ 1945 /* Good for SLI4 only */ 1946 1947 typedef struct 1948 { 1949 #ifdef EMLXS_BIG_ENDIAN 1950 uint32_t rsvd1:3; 1951 uint32_t vp:1; 1952 uint32_t rsvd2:12; 1953 uint16_t vfi; 1954 1955 uint16_t vpi; 1956 uint16_t fcfi; 1957 1958 uint32_t portname[2]; /* N_PORT name */ 1959 1960 ULP_BDE64 bde; 1961 1962 /* CHANGE with next firmware drop */ 1963 uint32_t edtov; 1964 uint32_t ratov; 1965 1966 uint32_t rsvd5:8; 1967 uint32_t sid:24; 1968 #endif 1969 #ifdef EMLXS_LITTLE_ENDIAN 1970 uint16_t vfi; 1971 uint32_t rsvd2:12; 1972 uint32_t vp:1; 1973 uint32_t rsvd1:3; 1974 1975 uint16_t fcfi; 1976 uint16_t vpi; 1977 1978 uint32_t portname[2]; /* N_PORT name */ 1979 1980 ULP_BDE64 bde; 1981 1982 /* CHANGE with next firmware drop */ 1983 uint32_t edtov; 1984 uint32_t ratov; 1985 1986 uint32_t sid:24; 1987 uint32_t rsvd5:8; 1988 #endif 1989 } REG_VFI_VAR; 1990 1991 /* Structure for MB Command INIT_VFI(0xA4) */ 1992 /* Good for SLI4 only */ 1993 1994 typedef struct 1995 { 1996 #ifdef EMLXS_BIG_ENDIAN 1997 uint32_t vr:1; 1998 uint32_t vt:1; 1999 uint32_t vf:1; 2000 uint32_t rsvd1:13; 2001 uint32_t vfi:16; 2002 2003 uint16_t rsvd2; 2004 uint16_t fcfi; 2005 2006 uint32_t rsvd3:16; 2007 uint32_t pri:3; 2008 uint32_t vf_id:12; 2009 uint32_t rsvd4:1; 2010 2011 uint32_t hop_count:8; 2012 uint32_t rsvd5:24; 2013 #endif 2014 #ifdef EMLXS_LITTLE_ENDIAN 2015 uint32_t vfi:16; 2016 uint32_t rsvd1:13; 2017 uint32_t vf:1; 2018 uint32_t vt:1; 2019 uint32_t vr:1; 2020 2021 uint16_t fcfi; 2022 uint16_t rsvd2; 2023 2024 uint32_t rsvd4:1; 2025 uint32_t vf_id:12; 2026 uint32_t pri:3; 2027 uint32_t rsvd3:16; 2028 2029 uint32_t rsvd5:24; 2030 uint32_t hop_count:8; 2031 #endif 2032 } INIT_VFI_VAR; 2033 2034 /* Structure for MB Command UNREG_VFI (0xA1) */ 2035 /* Good for SLI4 only */ 2036 2037 typedef struct 2038 { 2039 #ifdef EMLXS_BIG_ENDIAN 2040 uint32_t rsvd1:3; 2041 uint32_t vp:1; 2042 uint32_t rsvd2:28; 2043 2044 uint16_t vpi; 2045 uint16_t vfi; 2046 #endif 2047 #ifdef EMLXS_LITTLE_ENDIAN 2048 uint32_t rsvd2:28; 2049 uint32_t vp:1; 2050 uint32_t rsvd1:3; 2051 2052 uint16_t vfi; 2053 uint16_t vpi; 2054 #endif 2055 } UNREG_VFI_VAR; 2056 2057 2058 2059 typedef struct 2060 { 2061 #ifdef EMLXS_BIG_ENDIAN 2062 uint32_t read_log:1; 2063 uint32_t clear_log:1; 2064 uint32_t mbox_rsp:1; 2065 uint32_t resv:28; 2066 #endif 2067 #ifdef EMLXS_LITTLE_ENDIAN 2068 uint32_t resv:28; 2069 uint32_t mbox_rsp:1; 2070 uint32_t clear_log:1; 2071 uint32_t read_log:1; 2072 #endif 2073 2074 uint32_t offset; 2075 2076 union 2077 { 2078 ULP_BDE sp; 2079 ULP_BDE64 sp64; 2080 } un; 2081 } READ_EVT_LOG_VAR; 2082 2083 typedef struct 2084 { 2085 2086 #ifdef EMLXS_BIG_ENDIAN 2087 uint16_t split_log_next; 2088 uint16_t log_next; 2089 2090 uint32_t size; 2091 2092 uint32_t format:8; 2093 uint32_t resv2:22; 2094 uint32_t log_level:1; 2095 uint32_t split_log:1; 2096 #endif 2097 #ifdef EMLXS_LITTLE_ENDIAN 2098 uint16_t log_next; 2099 uint16_t split_log_next; 2100 2101 uint32_t size; 2102 2103 uint32_t split_log:1; 2104 uint32_t log_level:1; 2105 uint32_t resv2:22; 2106 uint32_t format:8; 2107 #endif 2108 2109 uint32_t offset; 2110 } LOG_STATUS_VAR; 2111 2112 2113 /* Structure for MB Command CONFIG_PORT (0x88) */ 2114 typedef struct 2115 { 2116 #ifdef EMLXS_BIG_ENDIAN 2117 uint32_t cBE:1; 2118 uint32_t cET:1; 2119 uint32_t cHpcb:1; 2120 uint32_t rMA:1; 2121 uint32_t sli_mode:4; 2122 uint32_t pcbLen:24; /* bit 23:0 of memory based port */ 2123 /* config block */ 2124 #endif 2125 #ifdef EMLXS_LITTLE_ENDIAN 2126 uint32_t pcbLen:24; /* bit 23:0 of memory based port */ 2127 /* config block */ 2128 uint32_t sli_mode:4; 2129 uint32_t rMA:1; 2130 uint32_t cHpcb:1; 2131 uint32_t cET:1; 2132 uint32_t cBE:1; 2133 #endif 2134 2135 uint32_t pcbLow; /* bit 31:0 of memory based port */ 2136 /* config block */ 2137 uint32_t pcbHigh; /* bit 63:32 of memory based port */ 2138 /* config block */ 2139 uint32_t hbainit[5]; 2140 2141 #ifdef EMLXS_BIG_ENDIAN 2142 uint32_t hps:1; /* Host pointers in SLIM */ 2143 uint32_t rsvd:31; 2144 #endif 2145 #ifdef EMLXS_LITTLE_ENDIAN 2146 uint32_t rsvd:31; 2147 uint32_t hps:1; /* Host pointers in SLIM */ 2148 #endif 2149 2150 #ifdef EMLXS_BIG_ENDIAN 2151 uint32_t rsvd1:24; 2152 uint32_t cmv:1; /* Configure Max VPIs */ 2153 uint32_t ccrp:1; /* Config Command Ring Polling */ 2154 uint32_t csah:1; /* Configure Synchronous Abort */ 2155 /* Handling */ 2156 uint32_t chbs:1; /* Cofigure Host Backing store */ 2157 uint32_t cinb:1; /* Enable Interrupt Notification */ 2158 /* Block */ 2159 uint32_t cerbm:1; /* Configure Enhanced Receive */ 2160 /* Buffer Management */ 2161 uint32_t cmx:1; /* Configure Max XRIs */ 2162 uint32_t cmr:1; /* Configure Max RPIs */ 2163 #endif 2164 #ifdef EMLXS_LITTLE_ENDIAN 2165 uint32_t cmr:1; /* Configure Max RPIs */ 2166 uint32_t cmx:1; /* Configure Max XRIs */ 2167 uint32_t cerbm:1; /* Configure Enhanced Receive */ 2168 /* Buffer Management */ 2169 uint32_t cinb:1; /* Enable Interrupt Notification */ 2170 /* Block */ 2171 uint32_t chbs:1; /* Cofigure Host Backing store */ 2172 uint32_t csah:1; /* Configure Synchronous Abort */ 2173 /* Handling */ 2174 uint32_t ccrp:1; /* Config Command Ring Polling */ 2175 uint32_t cmv:1; /* Configure Max VPIs */ 2176 uint32_t rsvd1:24; 2177 #endif 2178 #ifdef EMLXS_BIG_ENDIAN 2179 uint32_t rsvd2:24; 2180 uint32_t gmv:1; /* Grant Max VPIs */ 2181 uint32_t gcrp:1; /* Grant Command Ring Polling */ 2182 uint32_t gsah:1; /* Grant Synchronous Abort Handling */ 2183 uint32_t ghbs:1; /* Grant Host Backing Store */ 2184 uint32_t ginb:1; /* Grant Interrupt Notification Block */ 2185 uint32_t gerbm:1; /* Grant ERBM Request */ 2186 uint32_t gmx:1; /* Grant Max XRIs */ 2187 uint32_t gmr:1; /* Grant Max RPIs */ 2188 #endif 2189 #ifdef EMLXS_LITTLE_ENDIAN 2190 uint32_t gmr:1; /* Grant Max RPIs */ 2191 uint32_t gmx:1; /* Grant Max XRIs */ 2192 uint32_t gerbm:1; /* Grant ERBM Request */ 2193 uint32_t ginb:1; /* Grant Interrupt Notification Block */ 2194 uint32_t ghbs:1; /* Grant Host Backing Store */ 2195 uint32_t gsah:1; /* Grant Synchronous Abort Handling */ 2196 uint32_t gcrp:1; /* Grant Command Ring Polling */ 2197 uint32_t gmv:1; /* Grant Max VPIs */ 2198 uint32_t rsvd2:24; 2199 #endif 2200 2201 #ifdef EMLXS_BIG_ENDIAN 2202 uint32_t max_rpi:16; /* Max RPIs Port should configure */ 2203 uint32_t max_xri:16; /* Max XRIs Port should configure */ 2204 #endif 2205 #ifdef EMLXS_LITTLE_ENDIAN 2206 uint32_t max_xri:16; /* Max XRIs Port should configure */ 2207 uint32_t max_rpi:16; /* Max RPIs Port should configure */ 2208 #endif 2209 2210 #ifdef EMLXS_BIG_ENDIAN 2211 uint32_t max_hbq:16; /* Max HBQs Host expect to configure */ 2212 uint32_t rsvd3:16; /* Max HBQs Host expect to configure */ 2213 #endif 2214 #ifdef EMLXS_LITTLE_ENDIAN 2215 uint32_t rsvd3:16; /* Max HBQs Host expect to configure */ 2216 uint32_t max_hbq:16; /* Max HBQs Host expect to configure */ 2217 #endif 2218 2219 uint32_t rsvd4; /* Reserved */ 2220 2221 #ifdef EMLXS_BIG_ENDIAN 2222 uint32_t rsvd5:16; /* Reserved */ 2223 uint32_t vpi_max:16; /* Max number of virt N-Ports */ 2224 #endif 2225 #ifdef EMLXS_LITTLE_ENDIAN 2226 uint32_t vpi_max:16; /* Max number of virt N-Ports */ 2227 uint32_t rsvd5:16; /* Reserved */ 2228 #endif 2229 } CONFIG_PORT_VAR; 2230 2231 /* Structure for MB Command REQUEST_FEATURES (0x9D) */ 2232 /* Good for SLI4 only */ 2233 2234 typedef struct 2235 { 2236 #ifdef EMLXS_BIG_ENDIAN 2237 uint32_t rsvd1:31; 2238 uint32_t QueryMode:1; 2239 #endif 2240 #ifdef EMLXS_LITTLE_ENDIAN 2241 uint32_t QueryMode:1; 2242 uint32_t rsvd1:31; 2243 #endif 2244 2245 uint32_t featuresRequested; 2246 uint32_t featuresEnabled; 2247 2248 } REQUEST_FEATURES_VAR; 2249 2250 #define SLI4_FEATURE_INHIBIT_AUTO_ABTS 0x0001 2251 #define SLI4_FEATURE_NPIV 0x0002 2252 #define SLI4_FEATURE_DIF 0x0004 2253 #define SLI4_FEATURE_VIRTUAL_FABRICS 0x0008 2254 #define SLI4_FEATURE_FCP_INITIATOR 0x0010 2255 #define SLI4_FEATURE_FCP_TARGET 0x0020 2256 #define SLI4_FEATURE_FCP_COMBO 0x0040 2257 #define SLI4_FEATURE_INHIBIT_FIP 0x0080 2258 2259 2260 /* SLI-2 Port Control Block */ 2261 2262 /* SLIM POINTER */ 2263 #define SLIMOFF 0x30 /* WORD */ 2264 2265 typedef struct _SLI2_RDSC 2266 { 2267 uint32_t cmdEntries; 2268 uint32_t cmdAddrLow; 2269 uint32_t cmdAddrHigh; 2270 2271 uint32_t rspEntries; 2272 uint32_t rspAddrLow; 2273 uint32_t rspAddrHigh; 2274 } SLI2_RDSC; 2275 2276 typedef struct _PCB 2277 { 2278 #ifdef EMLXS_BIG_ENDIAN 2279 uint32_t type:8; 2280 #define TYPE_NATIVE_SLI2 0x01; 2281 uint32_t feature:8; 2282 #define FEATURE_INITIAL_SLI2 0x01; 2283 uint32_t rsvd:12; 2284 uint32_t maxRing:4; 2285 #endif 2286 #ifdef EMLXS_LITTLE_ENDIAN 2287 uint32_t maxRing:4; 2288 uint32_t rsvd:12; 2289 uint32_t feature:8; 2290 #define FEATURE_INITIAL_SLI2 0x01; 2291 uint32_t type:8; 2292 #define TYPE_NATIVE_SLI2 0x01; 2293 #endif 2294 2295 uint32_t mailBoxSize; 2296 uint32_t mbAddrLow; 2297 uint32_t mbAddrHigh; 2298 2299 uint32_t hgpAddrLow; 2300 uint32_t hgpAddrHigh; 2301 2302 uint32_t pgpAddrLow; 2303 uint32_t pgpAddrHigh; 2304 SLI2_RDSC rdsc[MAX_RINGS_AVAILABLE]; 2305 } PCB; 2306 2307 /* NEW_FEATURE */ 2308 typedef struct 2309 { 2310 #ifdef EMLXS_BIG_ENDIAN 2311 uint32_t rsvd0:27; 2312 uint32_t discardFarp:1; 2313 uint32_t IPEnable:1; 2314 uint32_t nodeName:1; 2315 uint32_t portName:1; 2316 uint32_t filterEnable:1; 2317 #endif 2318 #ifdef EMLXS_LITTLE_ENDIAN 2319 uint32_t filterEnable:1; 2320 uint32_t portName:1; 2321 uint32_t nodeName:1; 2322 uint32_t IPEnable:1; 2323 uint32_t discardFarp:1; 2324 uint32_t rsvd:27; 2325 #endif 2326 NAME_TYPE portname; 2327 NAME_TYPE nodename; 2328 uint32_t rsvd1; 2329 uint32_t rsvd2; 2330 uint32_t rsvd3; 2331 uint32_t IPAddress; 2332 } CONFIG_FARP_VAR; 2333 2334 2335 /* NEW_FEATURE */ 2336 typedef struct 2337 { 2338 #ifdef EMLXS_BIG_ENDIAN 2339 uint32_t defaultMessageNumber:16; 2340 uint32_t rsvd1:3; 2341 uint32_t nid:5; 2342 uint32_t rsvd2:5; 2343 uint32_t defaultPresent:1; 2344 uint32_t addAssociations:1; 2345 uint32_t reportAssociations:1; 2346 #endif 2347 #ifdef EMLXS_LITTLE_ENDIAN 2348 uint32_t reportAssociations:1; 2349 uint32_t addAssociations:1; 2350 uint32_t defaultPresent:1; 2351 uint32_t rsvd2:5; 2352 uint32_t nid:5; 2353 uint32_t rsvd1:3; 2354 uint32_t defaultMessageNumber:16; 2355 #endif 2356 uint32_t attConditions; 2357 uint8_t attentionId[16]; 2358 uint16_t messageNumberByHA[32]; 2359 uint16_t messageNumberByID[16]; 2360 uint32_t rsvd3; 2361 } CONFIG_MSI_VAR; 2362 2363 2364 /* NEW_FEATURE */ 2365 typedef struct 2366 { 2367 #ifdef EMLXS_BIG_ENDIAN 2368 uint32_t defaultMessageNumber:8; 2369 uint32_t rsvd1:11; 2370 uint32_t nid:5; 2371 uint32_t rsvd2:5; 2372 uint32_t defaultPresent:1; 2373 uint32_t addAssociations:1; 2374 uint32_t reportAssociations:1; 2375 #endif 2376 #ifdef EMLXS_LITTLE_ENDIAN 2377 uint32_t reportAssociations:1; 2378 uint32_t addAssociations:1; 2379 uint32_t defaultPresent:1; 2380 uint32_t rsvd2:5; 2381 uint32_t nid:5; 2382 uint32_t rsvd1:11; 2383 uint32_t defaultMessageNumber:8; 2384 #endif 2385 uint32_t attConditions1; 2386 uint32_t attConditions2; 2387 uint8_t attentionId[16]; 2388 uint8_t messageNumberByHA[64]; 2389 uint8_t messageNumberByID[16]; 2390 uint32_t autoClearByHA1; 2391 uint32_t autoClearByHA2; 2392 uint32_t autoClearByID; 2393 uint32_t resv3; 2394 } CONFIG_MSIX_VAR; 2395 2396 2397 /* Union of all Mailbox Command types */ 2398 2399 typedef union 2400 { 2401 uint32_t varWords[31]; 2402 LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */ 2403 READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */ 2404 WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */ 2405 BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */ 2406 INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */ 2407 DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */ 2408 CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */ 2409 PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */ 2410 CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */ 2411 RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */ 2412 READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */ 2413 READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */ 2414 READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */ 2415 READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */ 2416 READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */ 2417 READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */ 2418 READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */ 2419 READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */ 2420 REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */ 2421 UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */ 2422 READ_LA_VAR varReadLA; /* cmd = 21 (READ_LA(64)) */ 2423 CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */ 2424 DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */ 2425 UPDATE_CFG_VAR varUpdateCfg; /* cmd = 0x1b Warm Start */ 2426 /* UPDATE_CFG cmd */ 2427 DEL_LD_ENTRY_VAR varDelLdEntry; /* cmd = 0x1d (DEL_LD_ENTRY) */ 2428 UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */ 2429 CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP) */ 2430 CONFIG_MSI_VAR varCfgMSI; /* cmd = 0x90 (CONFIG_MSI) */ 2431 CONFIG_MSIX_VAR varCfgMSIX; /* cmd = 0x30 (CONFIG_MSIX) */ 2432 CONFIG_HBQ_VAR varCfgHbq; /* cmd = 0x7C (CONFIG_HBQ) */ 2433 LOAD_AREA_VAR varLdArea; /* cmd = 0x81 (LOAD_AREA) */ 2434 CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */ 2435 LOAD_EXP_ROM_VAR varLdExpRom; /* cmd = 0x9C (LOAD_XP_ROM) */ 2436 REG_VPI_VAR varRegVpi; /* cmd = 0x96 (REG_VPI) */ 2437 UNREG_VPI_VAR varUnregVpi; /* cmd = 0x97 (UNREG_VPI) */ 2438 READ_EVT_LOG_VAR varRdEvtLog; /* cmd = 0x38 (READ_EVT_LOG) */ 2439 LOG_STATUS_VAR varLogStat; /* cmd = 0x37 */ 2440 2441 } MAILVARIANTS; 2442 2443 #define MAILBOX_CMD_BSIZE 128 2444 #define MAILBOX_CMD_WSIZE 32 2445 2446 /* 2447 * SLI-2 specific structures 2448 */ 2449 2450 typedef struct _SLI1_DESC 2451 { 2452 emlxs_rings_t mbxCring[4]; 2453 uint32_t mbxUnused[24]; 2454 } SLI1_DESC; /* 128 bytes */ 2455 2456 typedef struct 2457 { 2458 uint32_t cmdPutInx; 2459 uint32_t rspGetInx; 2460 } HGP; 2461 2462 typedef struct 2463 { 2464 uint32_t cmdGetInx; 2465 uint32_t rspPutInx; 2466 } PGP; 2467 2468 typedef struct _SLI2_DESC 2469 { 2470 HGP host[4]; 2471 PGP port[4]; 2472 uint32_t HBQ_PortGetIdx[16]; 2473 } SLI2_DESC; /* 128 bytes */ 2474 2475 typedef union 2476 { 2477 SLI1_DESC s1; /* 32 words, 128 bytes */ 2478 SLI2_DESC s2; /* 32 words, 128 bytes */ 2479 } SLI_VAR; 2480 2481 typedef volatile struct 2482 { 2483 #ifdef EMLXS_BIG_ENDIAN 2484 uint16_t mbxStatus; 2485 uint8_t mbxCommand; 2486 uint8_t mbxReserved:6; 2487 uint8_t mbxHc:1; 2488 uint8_t mbxOwner:1; /* Low order bit first word */ 2489 #endif 2490 #ifdef EMLXS_LITTLE_ENDIAN 2491 uint8_t mbxOwner:1; /* Low order bit first word */ 2492 uint8_t mbxHc:1; 2493 uint8_t mbxReserved:6; 2494 uint8_t mbxCommand; 2495 uint16_t mbxStatus; 2496 #endif 2497 MAILVARIANTS un; /* 124 bytes */ 2498 SLI_VAR us; /* 128 bytes */ 2499 } MAILBOX; /* 256 bytes */ 2500 2501 2502 2503 /* SLI4 IOCTL Mailbox */ 2504 /* ALL SLI4 specific mbox commands have a standard request /response header */ 2505 /* Word 0 is just like SLI 3 */ 2506 2507 typedef struct mbox_req_hdr 2508 { 2509 #ifdef EMLXS_BIG_ENDIAN 2510 uint32_t domain:8; /* word 6 */ 2511 uint32_t port:8; 2512 uint32_t subsystem:8; 2513 uint32_t opcode:8; 2514 #endif 2515 #ifdef EMLXS_LITTLE_ENDIAN 2516 uint32_t opcode:8; 2517 uint32_t subsystem:8; 2518 uint32_t port:8; 2519 uint32_t domain:8; /* word 6 */ 2520 #endif 2521 uint32_t timeout; /* word 7 */ 2522 uint32_t req_length; /* word 8 */ 2523 uint32_t reserved1; /* word 9 */ 2524 } mbox_req_hdr_t; 2525 2526 typedef struct mbox_rsp_hdr 2527 { 2528 #ifdef EMLXS_BIG_ENDIAN 2529 uint32_t domain:8; /* word 6 */ 2530 uint32_t reserved1:8; 2531 uint32_t subsystem:8; 2532 uint32_t opcode:8; 2533 2534 uint32_t reserved2:16; /* word 7 */ 2535 uint32_t extra_status:8; 2536 uint32_t status:8; 2537 #endif 2538 #ifdef EMLXS_LITTLE_ENDIAN 2539 uint32_t opcode:8; 2540 uint32_t subsystem:8; 2541 uint32_t reserved1:8; 2542 uint32_t domain:8; /* word 6 */ 2543 2544 uint32_t status:8; 2545 uint32_t extra_status:8; 2546 uint32_t reserved2:16; /* word 7 */ 2547 #endif 2548 uint32_t rsp_length; /* word 8 */ 2549 uint32_t allocated_length; /* word 9 */ 2550 } mbox_rsp_hdr_t; 2551 2552 #define MBX_RSP_STATUS_SUCCESS 0x00 2553 #define MBX_RSP_STATUS_FAILED 0x01 2554 #define MBX_RSP_STATUS_ILLEGAL_REQ 0x02 2555 #define MBX_RSP_STATUS_ILLEGAL_FIELD 0x03 2556 #define MBX_RSP_STATUS_FCF_IN_USE 0x3A 2557 #define MBX_RSP_STATUS_NO_FCF 0x43 2558 2559 typedef struct be_req_hdr 2560 { 2561 #ifdef EMLXS_BIG_ENDIAN 2562 uint32_t special:8; /* word 1 */ 2563 uint32_t reserved2:16; /* word 1 */ 2564 uint32_t sge_cnt:5; /* word 1 */ 2565 uint32_t reserved1:2; /* word 1 */ 2566 uint32_t embedded:1; /* word 1 */ 2567 #endif 2568 #ifdef EMLXS_LITTLE_ENDIAN 2569 uint32_t embedded:1; /* word 1 */ 2570 uint32_t reserved1:2; /* word 1 */ 2571 uint32_t sge_cnt:5; /* word 1 */ 2572 uint32_t reserved2:16; /* word 1 */ 2573 uint32_t special:8; /* word 1 */ 2574 #endif 2575 uint32_t payload_length; /* word 2 */ 2576 uint32_t tag_low; /* word 3 */ 2577 uint32_t tag_hi; /* word 4 */ 2578 uint32_t reserved3; /* word 5 */ 2579 union 2580 { 2581 mbox_req_hdr_t hdr_req; 2582 mbox_rsp_hdr_t hdr_rsp; 2583 } un_hdr; 2584 } be_req_hdr_t; 2585 2586 #define EMLXS_MAX_NONEMBED_SIZE (1024 * 64) 2587 2588 /* SLI_CONFIG Mailbox commands */ 2589 2590 #define IOCTL_SUBSYSTEM_COMMON 0x01 2591 #define IOCTL_SUBSYSTEM_FCOE 0x0C 2592 #define IOCTL_SUBSYSTEM_DCBX 0x10 2593 2594 #define COMMON_OPCODE_READ_FLASHROM 0x06 2595 #define COMMON_OPCODE_WRITE_FLASHROM 0x07 2596 #define COMMON_OPCODE_CQ_CREATE 0x0C 2597 #define COMMON_OPCODE_EQ_CREATE 0x0D 2598 #define COMMON_OPCODE_MQ_CREATE 0x15 2599 #define COMMON_OPCODE_GET_CNTL_ATTRIB 0x20 2600 #define COMMON_OPCODE_NOP 0x21 2601 #define COMMON_OPCODE_QUERY_FIRMWARE_CONFIG 0x3A 2602 #define COMMON_OPCODE_RESET 0x3D 2603 #define COMMON_OPCODE_MANAGE_FAT 0x44 2604 #define COMMON_OPCODE_MCC_CREATE_EXT 0x5A 2605 2606 #define FCOE_OPCODE_WQ_CREATE 0x01 2607 #define FCOE_OPCODE_CFG_POST_SGL_PAGES 0x03 2608 #define FCOE_OPCODE_RQ_CREATE 0x05 2609 #define FCOE_OPCODE_READ_FCF_TABLE 0x08 2610 #define FCOE_OPCODE_ADD_FCF_TABLE 0x09 2611 #define FCOE_OPCODE_DELETE_FCF_TABLE 0x0A 2612 #define FCOE_OPCODE_POST_HDR_TEMPLATES 0x0B 2613 #define FCOE_OPCODE_REDISCOVER_FCF_TABLE 0x10 2614 2615 #define DCBX_OPCODE_GET_DCBX_MODE 0x04 2616 #define DCBX_OPCODE_SET_DCBX_MODE 0x05 2617 2618 typedef struct 2619 { 2620 struct 2621 { 2622 uint32_t opcode; 2623 #define MGMT_FLASHROM_OPCODE_FLASH 1 2624 #define MGMT_FLASHROM_OPCODE_SAVE 2 2625 #define MGMT_FLASHROM_OPCODE_CLEAR 3 2626 #define MGMT_FLASHROM_OPCODE_REPORT 4 2627 #define MGMT_FLASHROM_OPCODE_INFO 5 2628 #define MGMT_FLASHROM_OPCODE_CRC 6 2629 2630 uint32_t optype; 2631 #define MGMT_FLASHROM_OPTYPE_ISCSI_FIRMWARE 0 2632 #define MGMT_FLASHROM_OPTYPE_REDBOOT 1 2633 #define MGMT_FLASHROM_OPTYPE_ISCSI_BIOS 2 2634 #define MGMT_FLASHROM_OPTYPE_PXE_BIOS 3 2635 #define MGMT_FLASHROM_OPTYPE_CTRLS 4 2636 #define MGMT_FLASHROM_OPTYPE_CFG_IPSEC 5 2637 #define MGMT_FLASHROM_OPTYPE_CFG_INI 6 2638 #define MGMT_FLASHROM_OPTYPE_ROM_OFFSET 7 2639 #define MGMT_FLASHROM_OPTYPE_FCOE_BIOS 8 2640 #define MGMT_FLASHROM_OPTYPE_ISCSI_BACKUP 9 2641 #define MGMT_FLASHROM_OPTYPE_FCOE_FIRMWARE 10 2642 #define MGMT_FLASHROM_OPTYPE_FCOE_BACKUP 11 2643 #define MGMT_FLASHROM_OPTYPE_CTRLP 12 2644 #define MGMT_FLASHROM_OPTYPE_NCSI_FIRMWARE 13 2645 #define MGMT_FLASHROM_OPTYPE_NCSI_8051 14 2646 2647 uint32_t data_buffer_size; /* Align to 4KB */ 2648 uint32_t offset; 2649 uint32_t data_buffer; /* image starts here */ 2650 2651 } params; 2652 2653 } IOCTL_COMMON_FLASHROM; 2654 2655 2656 typedef struct 2657 { 2658 union 2659 { 2660 struct 2661 { 2662 uint32_t fat_operation; 2663 #define RETRIEVE_FAT 0 2664 #define QUERY_FAT 1 2665 #define CLEAR_FAT 2 2666 2667 uint32_t read_log_offset; 2668 uint32_t read_log_length; 2669 uint32_t data_buffer_size; 2670 uint32_t data_buffer; 2671 } request; 2672 2673 struct 2674 { 2675 uint32_t log_size; 2676 uint32_t read_log_length; 2677 uint32_t rsvd0; 2678 uint32_t rsvd1; 2679 uint32_t data_buffer; 2680 } response; 2681 2682 } params; 2683 2684 } IOCTL_COMMON_MANAGE_FAT; 2685 2686 2687 /* IOCTL_COMMON_QUERY_FIRMWARE_CONFIG */ 2688 typedef struct _BE_FW_CFG 2689 { 2690 uint32_t BEConfigNumber; 2691 uint32_t ASICRevision; 2692 uint32_t PhysicalPort; 2693 uint32_t FunctionMode; 2694 uint32_t ULPMode; 2695 2696 } BE_FW_CFG; 2697 2698 typedef struct _IOCTL_COMMON_QUERY_FIRMWARE_CONFIG 2699 { 2700 union 2701 { 2702 struct 2703 { 2704 uint32_t rsvd0; 2705 } request; 2706 2707 BE_FW_CFG response; 2708 2709 } params; 2710 2711 } IOCTL_COMMON_QUERY_FIRMWARE_CONFIG; 2712 2713 2714 2715 /* IOCTL_FCOE_READ_FCF_TABLE */ 2716 typedef struct 2717 { 2718 uint32_t max_recv_size; 2719 uint32_t fka_adv_period; 2720 uint32_t fip_priority; 2721 2722 #ifdef EMLXS_BIG_ENDIAN 2723 uint8_t fcf_mac_address_hi[4]; 2724 2725 uint8_t mac_address_provider; 2726 uint8_t fcf_available; 2727 uint8_t fcf_mac_address_low[2]; 2728 2729 uint8_t fabric_name_identifier[8]; 2730 2731 uint8_t fcf_valid; 2732 uint8_t fc_map[3]; 2733 2734 uint16_t fcf_state; 2735 uint16_t fcf_index; 2736 #endif 2737 #ifdef EMLXS_LITTLE_ENDIAN 2738 uint8_t fcf_mac_address_hi[4]; 2739 2740 uint8_t fcf_mac_address_low[2]; 2741 uint8_t fcf_available; 2742 uint8_t mac_address_provider; 2743 2744 uint8_t fabric_name_identifier[8]; 2745 2746 uint8_t fc_map[3]; 2747 uint8_t fcf_valid; 2748 2749 uint16_t fcf_index; 2750 uint16_t fcf_state; 2751 #endif 2752 2753 uint8_t vlan_bitmap[512]; 2754 uint8_t switch_name_identifier[8]; 2755 2756 } FCF_RECORD_t; 2757 2758 #define EMLXS_FCOE_MAX_RCV_SZ 0x800 2759 2760 /* defines for mac_address_provider */ 2761 #define EMLXS_MAM_BOTH 0 /* Both SPMA and FPMA */ 2762 #define EMLXS_MAM_FPMA 1 /* Fabric Provided MAC Address */ 2763 #define EMLXS_MAM_SPMA 2 /* Server Provided MAC Address */ 2764 2765 typedef struct 2766 { 2767 union 2768 { 2769 struct 2770 { 2771 #ifdef EMLXS_BIG_ENDIAN 2772 uint16_t rsvd0; 2773 uint16_t fcf_index; 2774 #endif 2775 #ifdef EMLXS_LITTLE_ENDIAN 2776 uint16_t fcf_index; 2777 uint16_t rsvd0; 2778 #endif 2779 2780 } request; 2781 2782 struct 2783 { 2784 uint32_t event_tag; 2785 #ifdef EMLXS_BIG_ENDIAN 2786 uint16_t rsvd0; 2787 uint16_t next_valid_fcf_index; 2788 #endif 2789 #ifdef EMLXS_LITTLE_ENDIAN 2790 uint16_t next_valid_fcf_index; 2791 uint16_t rsvd0; 2792 #endif 2793 FCF_RECORD_t fcf_entry[1]; 2794 2795 } response; 2796 2797 } params; 2798 2799 } IOCTL_FCOE_READ_FCF_TABLE; 2800 2801 2802 /* IOCTL_FCOE_ADD_FCF_TABLE */ 2803 typedef struct 2804 { 2805 union 2806 { 2807 struct 2808 { 2809 #ifdef EMLXS_BIG_ENDIAN 2810 uint16_t rsvd0; 2811 uint16_t fcf_index; 2812 #endif 2813 #ifdef EMLXS_LITTLE_ENDIAN 2814 uint16_t fcf_index; 2815 uint16_t rsvd0; 2816 #endif 2817 FCF_RECORD_t fcf_entry; 2818 2819 } request; 2820 } params; 2821 2822 } IOCTL_FCOE_ADD_FCF_TABLE; 2823 2824 2825 /* IOCTL_FCOE_DELETE_FCF_TABLE */ 2826 typedef struct 2827 { 2828 union 2829 { 2830 struct 2831 { 2832 #ifdef EMLXS_BIG_ENDIAN 2833 uint16_t fcf_indexes[1]; 2834 uint16_t fcf_count; 2835 #endif 2836 #ifdef EMLXS_LITTLE_ENDIAN 2837 uint16_t fcf_count; 2838 uint16_t fcf_indexes[1]; 2839 #endif 2840 2841 } request; 2842 } params; 2843 2844 } IOCTL_FCOE_DELETE_FCF_TABLE; 2845 2846 2847 /* IOCTL_FCOE_REDISCOVER_FCF_TABLE */ 2848 typedef struct 2849 { 2850 union 2851 { 2852 struct 2853 { 2854 #ifdef EMLXS_BIG_ENDIAN 2855 uint16_t rsvd0; 2856 uint16_t fcf_count; 2857 #endif 2858 #ifdef EMLXS_LITTLE_ENDIAN 2859 uint16_t fcf_count; 2860 uint16_t rsvd0; 2861 #endif 2862 uint32_t rsvd1; 2863 uint16_t fcf_index[1]; 2864 2865 } request; 2866 } params; 2867 2868 } IOCTL_FCOE_REDISCOVER_FCF_TABLE; 2869 2870 2871 #define FCOE_FCF_MAC0 0x0E 2872 #define FCOE_FCF_MAC1 0xFC 2873 #define FCOE_FCF_MAC2 0x00 2874 #define FCOE_FCF_MAC3 0xFF 2875 #define FCOE_FCF_MAC4 0xFF 2876 #define FCOE_FCF_MAC5 0xFE 2877 2878 #define FCOE_FCF_MAP0 0x0E 2879 #define FCOE_FCF_MAP1 0xFC 2880 #define FCOE_FCF_MAP2 0x00 2881 2882 #define MGMT_STATUS_FCF_IN_USE 0x3a 2883 2884 /* IOCTL_COMMON_NOP */ 2885 typedef struct _IOCTL_COMMON_NOP 2886 { 2887 union 2888 { 2889 struct 2890 { 2891 uint64_t context; 2892 } request; 2893 2894 struct 2895 { 2896 uint64_t context; 2897 } response; 2898 2899 } params; 2900 2901 } IOCTL_COMMON_NOP; 2902 2903 2904 /* Context for EQ create */ 2905 typedef struct _EQ_CONTEXT 2906 { 2907 #ifdef EMLXS_BIG_ENDIAN 2908 uint32_t Size:1; 2909 uint32_t Rsvd2:1; 2910 uint32_t Valid:1; 2911 uint32_t EPIndex:13; 2912 uint32_t Rsvd1:3; 2913 uint32_t ConsumerIndex:13; 2914 2915 uint32_t Armed:1; 2916 uint32_t Stalled:1; 2917 uint32_t SolEvent:1; 2918 uint32_t Count:3; 2919 uint32_t ProtectionDomain:10; 2920 uint32_t Rsvd3:3; 2921 uint32_t ProduderIndex:13; 2922 2923 uint32_t Rsvd7:4; 2924 uint32_t NoDelay:1; 2925 uint32_t Phase:2; 2926 uint32_t Rsvd6:2; 2927 uint32_t DelayMult:10; 2928 uint32_t Rsvd5:1; 2929 uint32_t Func:8; 2930 uint32_t Rsvd4:4; 2931 #endif 2932 #ifdef EMLXS_LITTLE_ENDIAN 2933 uint32_t ConsumerIndex:13; 2934 uint32_t Rsvd1:3; 2935 uint32_t EPIndex:13; 2936 uint32_t Valid:1; 2937 uint32_t Rsvd2:1; 2938 uint32_t Size:1; 2939 2940 uint32_t ProduderIndex:13; 2941 uint32_t Rsvd3:3; 2942 uint32_t ProtectionDomain:10; 2943 uint32_t Count:3; 2944 uint32_t SolEvent:1; 2945 uint32_t Stalled:1; 2946 uint32_t Armed:1; 2947 2948 uint32_t Rsvd4:4; 2949 uint32_t Func:8; 2950 uint32_t Rsvd5:1; 2951 uint32_t DelayMult:10; 2952 uint32_t Rsvd6:2; 2953 uint32_t Phase:2; 2954 uint32_t NoDelay:1; 2955 uint32_t Rsvd7:4; 2956 #endif 2957 2958 uint32_t Rsvd8; 2959 2960 }EQ_CONTEXT; 2961 2962 /* define for Count field */ 2963 #define EQ_ELEMENT_COUNT_1024 2 2964 #define EQ_ELEMENT_COUNT_2048 3 2965 #define EQ_ELEMENT_COUNT_4096 4 2966 2967 /* define for Size field */ 2968 #define EQ_ELEMENT_SIZE_4 0 2969 2970 /* define for DelayMullt - used for interrupt coalescing */ 2971 #define EQ_DELAY_MULT 64 2972 2973 /* Context for CQ create */ 2974 typedef struct _CQ_CONTEXT 2975 { 2976 #ifdef EMLXS_BIG_ENDIAN 2977 uint32_t Eventable:1; 2978 uint32_t SolEvent:1; 2979 uint32_t Valid:1; 2980 uint32_t Count:2; 2981 uint32_t Rsvd2:1; 2982 uint32_t EPIndex:11; 2983 uint32_t NoDelay:1; 2984 uint32_t CoalesceWM:2; 2985 uint32_t Rsvd1:1; 2986 uint32_t ConsumerIndex:11; 2987 2988 uint32_t Armed:1; 2989 uint32_t Stalled:1; 2990 uint32_t EQId:8; 2991 uint32_t ProtectionDomain:10; 2992 uint32_t Rsvd3:1; 2993 uint32_t ProduderIndex:11; 2994 2995 uint32_t Rsvd5:20; 2996 uint32_t Func:8; 2997 uint32_t Rsvd4:4; 2998 #endif 2999 #ifdef EMLXS_LITTLE_ENDIAN 3000 uint32_t ConsumerIndex:11; 3001 uint32_t Rsvd1:1; 3002 uint32_t CoalesceWM:2; 3003 uint32_t NoDelay:1; 3004 uint32_t EPIndex:11; 3005 uint32_t Rsvd2:1; 3006 uint32_t Count:2; 3007 uint32_t Valid:1; 3008 uint32_t SolEvent:1; 3009 uint32_t Eventable:1; 3010 3011 uint32_t ProduderIndex:11; 3012 uint32_t Rsvd3:1; 3013 uint32_t ProtectionDomain:10; 3014 uint32_t EQId:8; 3015 uint32_t Stalled:1; 3016 uint32_t Armed:1; 3017 3018 uint32_t Rsvd4:4; 3019 uint32_t Func:8; 3020 uint32_t Rsvd5:20; 3021 #endif 3022 3023 uint32_t Rsvd6; 3024 3025 } CQ_CONTEXT; 3026 3027 /* define for Count field */ 3028 #define CQ_ELEMENT_COUNT_256 0 3029 #define CQ_ELEMENT_COUNT_512 1 3030 #define CQ_ELEMENT_COUNT_1024 2 3031 3032 /* Context for MQ create */ 3033 typedef struct _MQ_CONTEXT 3034 { 3035 #ifdef EMLXS_BIG_ENDIAN 3036 uint32_t CQId:10; 3037 uint32_t Rsvd2:2; 3038 uint32_t Size:4; 3039 uint32_t Rsvd1:2; 3040 uint32_t ConsumerIndex:14; 3041 3042 uint32_t Valid:1; 3043 uint32_t ProtectionDomain:9; 3044 uint32_t FunctionNumber:8; 3045 uint32_t ProduderIndex:14; 3046 #endif 3047 #ifdef EMLXS_LITTLE_ENDIAN 3048 uint32_t ConsumerIndex:14; 3049 uint32_t Rsvd1:2; 3050 uint32_t Size:4; 3051 uint32_t Rsvd2:2; 3052 uint32_t CQId:10; 3053 3054 uint32_t ProduderIndex:14; 3055 uint32_t FunctionNumber:8; 3056 uint32_t ProtectionDomain:9; 3057 uint32_t Valid:1; 3058 #endif 3059 3060 uint32_t Rsvd3; 3061 uint32_t Rsvd4; 3062 3063 } MQ_CONTEXT; 3064 3065 /* define for Size field */ 3066 #define MQ_ELEMENT_COUNT_16 0x05 3067 3068 /* Context for RQ create */ 3069 typedef struct _RQ_CONTEXT 3070 { 3071 #ifdef EMLXS_BIG_ENDIAN 3072 uint32_t Rsvd2:8; 3073 uint32_t RQState:4; 3074 uint32_t RQSize:4; 3075 uint32_t Rsvd1:16; 3076 3077 uint32_t Rsvd3; 3078 3079 uint32_t Rsvd4:6; 3080 uint32_t CQIdRecv:10; 3081 uint32_t BufferSize:16; 3082 #endif 3083 #ifdef EMLXS_LITTLE_ENDIAN 3084 uint32_t Rsvd1:16; 3085 uint32_t RQSize:4; 3086 uint32_t RQState:4; 3087 uint32_t Rsvd2:8; 3088 3089 uint32_t Rsvd3; 3090 3091 uint32_t BufferSize:16; 3092 uint32_t CQIdRecv:10; 3093 uint32_t Rsvd4:6; 3094 #endif 3095 3096 uint32_t Rsvd5; 3097 3098 } RQ_CONTEXT; 3099 3100 3101 /* IOCTL_COMMON_EQ_CREATE */ 3102 typedef struct 3103 { 3104 union 3105 { 3106 struct 3107 { 3108 #ifdef EMLXS_BIG_ENDIAN 3109 uint16_t Rsvd1; 3110 uint16_t NumPages; 3111 #endif 3112 #ifdef EMLXS_LITTLE_ENDIAN 3113 uint16_t NumPages; 3114 uint16_t Rsvd1; 3115 #endif 3116 EQ_CONTEXT EQContext; 3117 BE_PHYS_ADDR Pages[8]; 3118 } request; 3119 3120 struct 3121 { 3122 #ifdef EMLXS_BIG_ENDIAN 3123 uint16_t Rsvd1; 3124 uint16_t EQId; 3125 #endif 3126 #ifdef EMLXS_LITTLE_ENDIAN 3127 uint16_t EQId; 3128 uint16_t Rsvd1; 3129 #endif 3130 } response; 3131 } params; 3132 3133 } IOCTL_COMMON_EQ_CREATE; 3134 3135 3136 /* IOCTL_COMMON_CQ_CREATE */ 3137 typedef struct 3138 { 3139 union 3140 { 3141 struct 3142 { 3143 #ifdef EMLXS_BIG_ENDIAN 3144 uint16_t Rsvd1; 3145 uint16_t NumPages; 3146 #endif 3147 #ifdef EMLXS_LITTLE_ENDIAN 3148 uint16_t NumPages; 3149 uint16_t Rsvd1; 3150 #endif 3151 CQ_CONTEXT CQContext; 3152 BE_PHYS_ADDR Pages[4]; 3153 } request; 3154 3155 struct 3156 { 3157 #ifdef EMLXS_BIG_ENDIAN 3158 uint16_t Rsvd1; 3159 uint16_t CQId; 3160 #endif 3161 #ifdef EMLXS_LITTLE_ENDIAN 3162 uint16_t CQId; 3163 uint16_t Rsvd1; 3164 #endif 3165 } response; 3166 } params; 3167 3168 } IOCTL_COMMON_CQ_CREATE; 3169 3170 3171 /* IOCTL_COMMON_MQ_CREATE */ 3172 typedef struct 3173 { 3174 union 3175 { 3176 struct 3177 { 3178 #ifdef EMLXS_BIG_ENDIAN 3179 uint16_t Rsvd1; 3180 uint16_t NumPages; 3181 #endif 3182 #ifdef EMLXS_LITTLE_ENDIAN 3183 uint16_t NumPages; 3184 uint16_t Rsvd1; 3185 #endif 3186 MQ_CONTEXT MQContext; 3187 BE_PHYS_ADDR Pages[8]; 3188 } request; 3189 3190 struct 3191 { 3192 #ifdef EMLXS_BIG_ENDIAN 3193 uint16_t Rsvd1; 3194 uint16_t MQId; 3195 #endif 3196 #ifdef EMLXS_LITTLE_ENDIAN 3197 uint16_t MQId; 3198 uint16_t Rsvd1; 3199 #endif 3200 } response; 3201 } params; 3202 3203 } IOCTL_COMMON_MQ_CREATE; 3204 3205 3206 /* IOCTL_COMMON_MCC_CREATE_EXT */ 3207 typedef struct 3208 { 3209 union 3210 { 3211 struct 3212 { 3213 #ifdef EMLXS_BIG_ENDIAN 3214 uint16_t rsvd0; 3215 uint16_t num_pages; 3216 #endif 3217 #ifdef EMLXS_LITTLE_ENDIAN 3218 uint16_t num_pages; 3219 uint16_t rsvd0; 3220 #endif 3221 uint32_t async_event_bitmap; 3222 3223 #define ASYNC_LINK_EVENT 0x2 3224 #define ASYNC_FCF_EVENT 0x4 3225 #define ASYNC_GROUP5_EVENT 0x20 3226 3227 MQ_CONTEXT context; 3228 BE_PHYS_ADDR pages[8]; 3229 } request; 3230 3231 struct 3232 { 3233 #ifdef EMLXS_BIG_ENDIAN 3234 uint16_t rsvd0; 3235 uint16_t id; 3236 #endif 3237 #ifdef EMLXS_LITTLE_ENDIAN 3238 uint16_t id; 3239 uint16_t rsvd0; 3240 #endif 3241 } response; 3242 3243 } params; 3244 3245 } IOCTL_COMMON_MCC_CREATE_EXT; 3246 3247 3248 /* IOCTL_FCOE_RQ_CREATE */ 3249 typedef struct 3250 { 3251 union 3252 { 3253 struct 3254 { 3255 #ifdef EMLXS_BIG_ENDIAN 3256 uint8_t rsvd0; 3257 uint8_t ulpNum; 3258 uint16_t NumPages; 3259 #endif 3260 #ifdef EMLXS_LITTLE_ENDIAN 3261 uint16_t NumPages; 3262 uint8_t ulpNum; 3263 uint8_t rsvd0; 3264 #endif 3265 RQ_CONTEXT RQContext; 3266 BE_PHYS_ADDR Pages[8]; 3267 } request; 3268 3269 struct 3270 { 3271 #ifdef EMLXS_BIG_ENDIAN 3272 uint16_t Rsvd1; 3273 uint16_t RQId; 3274 #endif 3275 #ifdef EMLXS_LITTLE_ENDIAN 3276 uint16_t RQId; 3277 uint16_t Rsvd1; 3278 #endif 3279 } response; 3280 3281 } params; 3282 3283 } IOCTL_FCOE_RQ_CREATE; 3284 3285 3286 /* IOCTL_FCOE_WQ_CREATE */ 3287 typedef struct 3288 { 3289 union 3290 { 3291 struct 3292 { 3293 #ifdef EMLXS_BIG_ENDIAN 3294 uint16_t CQId; 3295 uint16_t NumPages; 3296 #endif 3297 #ifdef EMLXS_LITTLE_ENDIAN 3298 uint16_t NumPages; 3299 uint16_t CQId; 3300 #endif 3301 BE_PHYS_ADDR Pages[4]; 3302 } request; 3303 3304 struct 3305 { 3306 #ifdef EMLXS_BIG_ENDIAN 3307 uint16_t Rsvd0; 3308 uint16_t WQId; 3309 #endif 3310 #ifdef EMLXS_LITTLE_ENDIAN 3311 uint16_t WQId; 3312 uint16_t Rsvd0; 3313 #endif 3314 } response; 3315 3316 } params; 3317 3318 } IOCTL_FCOE_WQ_CREATE; 3319 3320 3321 /* IOCTL_FCOE_CFG_POST_SGL_PAGES */ 3322 typedef struct _FCOE_SGL_PAGES 3323 { 3324 BE_PHYS_ADDR sgl_page0; /* 1st page per XRI */ 3325 BE_PHYS_ADDR sgl_page1; /* 2nd page per XRI */ 3326 3327 } FCOE_SGL_PAGES; 3328 3329 typedef struct 3330 { 3331 union 3332 { 3333 struct 3334 { 3335 #ifdef EMLXS_BIG_ENDIAN 3336 uint16_t xri_count; 3337 uint16_t xri_start; 3338 #endif 3339 #ifdef EMLXS_LITTLE_ENDIAN 3340 uint16_t xri_start; 3341 uint16_t xri_count; 3342 #endif 3343 FCOE_SGL_PAGES pages[1]; 3344 } request; 3345 3346 struct 3347 { 3348 uint32_t rsvd0; 3349 } response; 3350 3351 } params; 3352 3353 uint32_t rsvd0[2]; 3354 3355 } IOCTL_FCOE_CFG_POST_SGL_PAGES; 3356 3357 3358 /* IOCTL_FCOE_POST_HDR_TEMPLATES */ 3359 typedef struct _IOCTL_FCOE_POST_HDR_TEMPLATES 3360 { 3361 union 3362 { 3363 struct 3364 { 3365 #ifdef EMLXS_BIG_ENDIAN 3366 uint16_t num_pages; 3367 uint16_t starting_rpi_index; 3368 #endif 3369 #ifdef EMLXS_LITTLE_ENDIAN 3370 uint16_t starting_rpi_index; 3371 uint16_t num_pages; 3372 #endif 3373 BE_PHYS_ADDR pages[32]; 3374 3375 }request; 3376 3377 }params; 3378 3379 } IOCTL_FCOE_POST_HDR_TEMPLATES; 3380 3381 3382 3383 #define EMLXS_IOCTL_DCBX_MODE_CEE 0 /* Mapped to FIP mode */ 3384 #define EMLXS_IOCTL_DCBX_MODE_CIN 1 /* Mapped to nonFIP mode */ 3385 3386 /* IOCTL_DCBX_GET_DCBX_MODE */ 3387 typedef struct _IOCTL_DCBX_GET_DCBX_MODE 3388 { 3389 union 3390 { 3391 struct 3392 { 3393 #ifdef EMLXS_BIG_ENDIAN 3394 uint8_t rsvd0[3]; 3395 uint8_t port_num; 3396 #endif 3397 #ifdef EMLXS_LITTLE_ENDIAN 3398 uint8_t port_num; 3399 uint8_t rsvd0[3]; 3400 #endif 3401 } request; 3402 3403 struct 3404 { 3405 #ifdef EMLXS_BIG_ENDIAN 3406 uint8_t rsvd1[3]; 3407 uint8_t dcbx_mode; 3408 #endif 3409 #ifdef EMLXS_LITTLE_ENDIAN 3410 uint8_t dcbx_mode; 3411 uint8_t rsvd1[3]; 3412 #endif 3413 } response; 3414 3415 } params; 3416 3417 } IOCTL_DCBX_GET_DCBX_MODE; 3418 3419 3420 /* IOCTL_DCBX_SET_DCBX_MODE */ 3421 typedef struct _IOCTL_DCBX_SET_DCBX_MODE 3422 { 3423 union 3424 { 3425 struct 3426 { 3427 #ifdef EMLXS_BIG_ENDIAN 3428 uint8_t rsvd0[2]; 3429 uint8_t dcbx_mode; 3430 uint8_t port_num; 3431 #endif 3432 #ifdef EMLXS_LITTLE_ENDIAN 3433 uint8_t port_num; 3434 uint8_t dcbx_mode; 3435 uint8_t rsvd0[2]; 3436 #endif 3437 } request; 3438 3439 struct 3440 { 3441 uint32_t rsvd1; 3442 } response; 3443 3444 } params; 3445 3446 } IOCTL_DCBX_SET_DCBX_MODE; 3447 3448 3449 /* IOCTL_COMMON_GET_CNTL_ATTRIB */ 3450 typedef struct 3451 { 3452 char flashrom_version_string[32]; 3453 char manufacturer_name[32]; 3454 char rsvd0[28]; 3455 uint32_t default_extended_timeout; 3456 char controller_model_number[32]; 3457 char controller_description[64]; 3458 char controller_serial_number[32]; 3459 char ip_version_string[32]; 3460 char firmware_version_string[32]; 3461 char bios_version_string[32]; 3462 char redboot_version_string[32]; 3463 char driver_version_string[32]; 3464 char fw_on_flash_version_string[32]; 3465 uint32_t functionalities_supported; 3466 uint16_t max_cdblength; 3467 uint8_t asic_revision; 3468 uint8_t generational_guid[16]; 3469 uint8_t hba_port_count; 3470 uint16_t default_link_down_timeout; 3471 uint8_t iscsi_ver_min_max; 3472 uint8_t multifunction_device; 3473 uint8_t cache_valid; 3474 uint8_t hba_status; 3475 uint8_t max_domains_supported; 3476 uint8_t phy_port; 3477 uint32_t firmware_post_status; 3478 uint32_t hba_mtu[2]; 3479 3480 } MGMT_HBA_ATTRIB; 3481 3482 typedef struct 3483 { 3484 MGMT_HBA_ATTRIB hba_attribs; 3485 uint16_t pci_vendor_id; 3486 uint16_t pci_device_id; 3487 uint16_t pci_sub_vendor_id; 3488 uint16_t pci_sub_system_id; 3489 uint8_t pci_bus_number; 3490 uint8_t pci_device_number; 3491 uint8_t pci_function_number; 3492 uint8_t interface_type; 3493 uint64_t unique_identifier; 3494 3495 } MGMT_CONTROLLER_ATTRIB; 3496 3497 typedef struct 3498 { 3499 union 3500 { 3501 struct 3502 { 3503 uint32_t rsvd0; 3504 } request; 3505 3506 struct 3507 { 3508 MGMT_CONTROLLER_ATTRIB cntl_attributes_info; 3509 } response; 3510 3511 } params; 3512 3513 } IOCTL_COMMON_GET_CNTL_ATTRIB; 3514 3515 3516 typedef union 3517 { 3518 IOCTL_COMMON_NOP NOPVar; 3519 IOCTL_FCOE_WQ_CREATE WQCreateVar; 3520 IOCTL_COMMON_EQ_CREATE EQCreateVar; 3521 IOCTL_COMMON_CQ_CREATE CQCreateVar; 3522 IOCTL_COMMON_MQ_CREATE MQCreateVar; 3523 IOCTL_COMMON_MCC_CREATE_EXT MCCCreateExtVar; 3524 IOCTL_FCOE_CFG_POST_SGL_PAGES PostSGLVar; 3525 IOCTL_COMMON_GET_CNTL_ATTRIB GetCntlAttributesVar; 3526 IOCTL_FCOE_READ_FCF_TABLE ReadFCFTableVar; 3527 IOCTL_FCOE_ADD_FCF_TABLE AddFCFTableVar; 3528 IOCTL_FCOE_REDISCOVER_FCF_TABLE RediscoverFCFTableVar; 3529 IOCTL_COMMON_FLASHROM FlashRomVar; 3530 IOCTL_COMMON_MANAGE_FAT FATVar; 3531 IOCTL_DCBX_GET_DCBX_MODE GetDCBX; 3532 IOCTL_DCBX_SET_DCBX_MODE SetDCBX; 3533 3534 } IOCTL_VARIANTS; 3535 3536 /* Structure for MB Command SLI_CONFIG(0x9b) */ 3537 /* Good for SLI4 only */ 3538 3539 typedef struct 3540 { 3541 be_req_hdr_t be; 3542 BE_PHYS_ADDR payload; 3543 } SLI_CONFIG_VAR; 3544 3545 #define IOCTL_HEADER_SZ (4 * sizeof (uint32_t)) 3546 3547 3548 typedef union 3549 { 3550 uint32_t varWords[63]; 3551 READ_NV_VAR varRDnvp; /* cmd = x02 (READ_NVPARMS) */ 3552 INIT_LINK_VAR varInitLnk; /* cmd = x05 (INIT_LINK) */ 3553 CONFIG_LINK varCfgLnk; /* cmd = x07 (CONFIG_LINK) */ 3554 READ_REV4_VAR varRdRev4; /* cmd = x11 (READ_REV) */ 3555 READ_LNK_VAR varRdLnk; /* cmd = x12 (READ_LNK_STAT) */ 3556 DUMP4_VAR varDmp4; /* cmd = x17 (DUMP) */ 3557 READ_SPARM_VAR varRdSparm; /* cmd = x8D (READ_SPARM64) */ 3558 REG_FCFI_VAR varRegFCFI; /* cmd = xA0 (REG_FCFI) */ 3559 UNREG_FCFI_VAR varUnRegFCFI; /* cmd = xA2 (UNREG_FCFI) */ 3560 READ_LA_VAR varReadLA; /* cmd = x95 (READ_LA64) */ 3561 READ_CONFIG4_VAR varRdConfig4; /* cmd = x0B (READ_CONFIG) */ 3562 RESUME_RPI_VAR varResumeRPI; /* cmd = x9E (RESUME_RPI) */ 3563 REG_LOGIN_VAR varRegLogin; /* cmd = x93 (REG_RPI) */ 3564 UNREG_LOGIN_VAR varUnregLogin; /* cmd = x14 (UNREG_RPI) */ 3565 REG_VPI_VAR varRegVPI4; /* cmd = x96 (REG_VPI) */ 3566 UNREG_VPI_VAR4 varUnRegVPI4; /* cmd = x97 (UNREG_VPI) */ 3567 REG_VFI_VAR varRegVFI4; /* cmd = x9F (REG_VFI) */ 3568 UNREG_VFI_VAR varUnRegVFI4; /* cmd = xA1 (UNREG_VFI) */ 3569 REQUEST_FEATURES_VAR varReqFeatures; /* cmd = x9D (REQ_FEATURES) */ 3570 SLI_CONFIG_VAR varSLIConfig; /* cmd = x9B (SLI_CONFIG) */ 3571 INIT_VPI_VAR varInitVPI4; /* cmd = xA3 (INIT_VPI) */ 3572 INIT_VFI_VAR varInitVFI4; /* cmd = xA4 (INIT_VFI) */ 3573 3574 } MAILVARIANTS4; /* Used for SLI-4 */ 3575 3576 #define MAILBOX_CMD_SLI4_BSIZE 256 3577 #define MAILBOX_CMD_SLI4_WSIZE 64 3578 3579 #define MAILBOX_CMD_MAX_BSIZE 256 3580 #define MAILBOX_CMD_MAX_WSIZE 64 3581 3582 3583 typedef volatile struct 3584 { 3585 #ifdef EMLXS_BIG_ENDIAN 3586 uint16_t mbxStatus; 3587 uint8_t mbxCommand; 3588 uint8_t mbxReserved:6; 3589 uint8_t mbxHc:1; 3590 uint8_t mbxOwner:1; /* Low order bit first word */ 3591 #endif 3592 #ifdef EMLXS_LITTLE_ENDIAN 3593 uint8_t mbxOwner:1; /* Low order bit first word */ 3594 uint8_t mbxHc:1; 3595 uint8_t mbxReserved:6; 3596 uint8_t mbxCommand; 3597 uint16_t mbxStatus; 3598 #endif 3599 MAILVARIANTS4 un; /* 124 bytes */ 3600 } MAILBOX4; /* Used for SLI-4 */ 3601 3602 /* 3603 * End Structure Definitions for Mailbox Commands 3604 */ 3605 3606 3607 typedef struct emlxs_mbq 3608 { 3609 volatile uint32_t mbox[MAILBOX_CMD_MAX_WSIZE]; 3610 struct emlxs_mbq *next; 3611 3612 /* Defferred handling pointers */ 3613 void *nonembed; /* ptr to data buffer */ 3614 /* structure */ 3615 void *bp; /* ptr to data buffer */ 3616 /* structure */ 3617 void *sbp; /* ptr to emlxs_buf_t */ 3618 /* structure */ 3619 void *ubp; /* ptr to fc_unsol_buf_t */ 3620 /* structure */ 3621 void *iocbq; /* ptr to IOCBQ structure */ 3622 void *context; /* ptr to mbox context data */ 3623 void *port; /* Sending port */ 3624 uint32_t flag; 3625 3626 #define MBQ_POOL_ALLOCATED 0x00000001 3627 #define MBQ_PASSTHRU 0x00000002 3628 #define MBQ_EMBEDDED 0x00000004 3629 #define MBQ_BOOTSTRAP 0x00000008 3630 #define MBQ_COMPLETED 0x00010000 /* Used for MBX_SLEEP */ 3631 #define MBQ_INIT_MASK 0x0000ffff 3632 3633 #ifdef MBOX_EXT_SUPPORT 3634 uint8_t *extbuf; /* ptr to mailbox ext buffer */ 3635 uint32_t extsize; /* size of mailbox ext buffer */ 3636 #endif /* MBOX_EXT_SUPPORT */ 3637 uint32_t (*mbox_cmpl)(); 3638 } emlxs_mbq_t; 3639 typedef emlxs_mbq_t MAILBOXQ; 3640 3641 3642 /* We currently do not support IOCBs in SLI1 mode */ 3643 typedef struct 3644 { 3645 MAILBOX mbx; 3646 #ifdef MBOX_EXT_SUPPORT 3647 uint8_t mbxExt[MBOX_EXTENSION_SIZE]; 3648 #endif /* MBOX_EXT_SUPPORT */ 3649 uint8_t pad[(SLI_SLIM1_SIZE - 3650 (sizeof (MAILBOX) + MBOX_EXTENSION_SIZE))]; 3651 } SLIM1; 3652 3653 3654 typedef struct 3655 { 3656 MAILBOX mbx; 3657 #ifdef MBOX_EXT_SUPPORT 3658 uint8_t mbxExt[MBOX_EXTENSION_SIZE]; 3659 #endif /* MBOX_EXT_SUPPORT */ 3660 PCB pcb; 3661 uint8_t IOCBs[SLI_IOCB_MAX_SIZE]; 3662 } SLIM2; 3663 3664 3665 /* def for new 2MB Flash (Pegasus ...) */ 3666 #define MBX_LOAD_AREA 0x81 3667 #define MBX_LOAD_EXP_ROM 0x9C 3668 3669 #define FILE_TYPE_AWC 0xE1A01001 3670 #define FILE_TYPE_DWC 0xE1A02002 3671 #define FILE_TYPE_BWC 0xE1A03003 3672 3673 #define AREA_ID_MASK 0xFFFFFF0F 3674 #define AREA_ID_AWC 0x00000001 3675 #define AREA_ID_DWC 0x00000002 3676 #define AREA_ID_BWC 0x00000003 3677 3678 #define CMD_START_ERASE 1 3679 #define CMD_CONTINUE_ERASE 2 3680 #define CMD_DOWNLOAD 3 3681 #define CMD_END_DOWNLOAD 4 3682 3683 #define RSP_ERASE_STARTED 1 3684 #define RSP_ERASE_COMPLETE 2 3685 #define RSP_DOWNLOAD_MORE 3 3686 #define RSP_DOWNLOAD_DONE 4 3687 3688 #define EROM_CMD_FIND_IMAGE 8 3689 #define EROM_CMD_CONTINUE_ERASE 9 3690 #define EROM_CMD_COPY 10 3691 3692 #define EROM_RSP_ERASE_STARTED 8 3693 #define EROM_RSP_ERASE_COMPLETE 9 3694 #define EROM_RSP_COPY_MORE 10 3695 #define EROM_RSP_COPY_DONE 11 3696 3697 #define ALLext 1 3698 #define DWCext 2 3699 #define BWCext 3 3700 3701 #define NO_ALL 0 3702 #define ALL_WITHOUT_BWC 1 3703 #define ALL_WITH_BWC 2 3704 3705 #define KERNEL_START_ADDRESS 0x000000 3706 #define DOWNLOAD_START_ADDRESS 0x040000 3707 #define EXP_ROM_START_ADDRESS 0x180000 3708 #define SCRATCH_START_ADDRESS 0x1C0000 3709 #define CONFIG_START_ADDRESS 0x1E0000 3710 3711 3712 typedef struct SliAifHdr 3713 { 3714 uint32_t CompressBr; 3715 uint32_t RelocBr; 3716 uint32_t ZinitBr; 3717 uint32_t EntryBr; 3718 uint32_t Area_ID; 3719 uint32_t RoSize; 3720 uint32_t RwSize; 3721 uint32_t DbgSize; 3722 uint32_t ZinitSize; 3723 uint32_t DbgType; 3724 uint32_t ImageBase; 3725 uint32_t Area_Size; 3726 uint32_t AddressMode; 3727 uint32_t DataBase; 3728 uint32_t AVersion; 3729 uint32_t Spare2; 3730 uint32_t DebugSwi; 3731 uint32_t ZinitCode[15]; 3732 } AIF_HDR, *PAIF_HDR; 3733 3734 typedef struct ImageHdr 3735 { 3736 uint32_t BlockSize; 3737 PROG_ID Id; 3738 uint32_t Flags; 3739 uint32_t EntryAdr; 3740 uint32_t InitAdr; 3741 uint32_t ExitAdr; 3742 uint32_t ImageBase; 3743 uint32_t ImageSize; 3744 uint32_t ZinitSize; 3745 uint32_t RelocSize; 3746 uint32_t HdrCks; 3747 } IMAGE_HDR, *PIMAGE_HDR; 3748 3749 3750 3751 typedef struct 3752 { 3753 PROG_ID prog_id; 3754 #ifdef EMLXS_BIG_ENDIAN 3755 uint32_t pci_cfg_rsvd:27; 3756 uint32_t use_hdw_def:1; 3757 uint32_t pci_cfg_sel:3; 3758 uint32_t pci_cfg_lookup_sel:1; 3759 #endif 3760 #ifdef EMLXS_LITTLE_ENDIAN 3761 uint32_t pci_cfg_lookup_sel:1; 3762 uint32_t pci_cfg_sel:3; 3763 uint32_t use_hdw_def:1; 3764 uint32_t pci_cfg_rsvd:27; 3765 #endif 3766 union 3767 { 3768 PROG_ID boot_bios_id; 3769 uint32_t boot_bios_wd[2]; 3770 } u0; 3771 PROG_ID sli1_prog_id; 3772 PROG_ID sli2_prog_id; 3773 PROG_ID sli3_prog_id; 3774 PROG_ID sli4_prog_id; 3775 union 3776 { 3777 PROG_ID EROM_prog_id; 3778 uint32_t EROM_prog_wd[2]; 3779 } u1; 3780 } WAKE_UP_PARMS, *PWAKE_UP_PARMS; 3781 3782 3783 #define PROG_DESCR_STR_LEN 24 3784 #define MAX_LOAD_ENTRY 32 3785 3786 typedef struct 3787 { 3788 uint32_t next; 3789 uint32_t prev; 3790 uint32_t start_adr; 3791 uint32_t len; 3792 union 3793 { 3794 PROG_ID id; 3795 uint32_t wd[2]; 3796 } un; 3797 uint8_t prog_descr[PROG_DESCR_STR_LEN]; 3798 } LOAD_ENTRY; 3799 3800 typedef struct 3801 { 3802 uint32_t head; 3803 uint32_t tail; 3804 uint32_t entry_cnt; 3805 LOAD_ENTRY load_entry[MAX_LOAD_ENTRY]; 3806 } LOAD_LIST; 3807 3808 #ifdef __cplusplus 3809 } 3810 #endif 3811 3812 #endif /* _EMLXS_MBOX_H */ 3813