1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Emulex. All rights reserved. 24 * Use is subject to License terms. 25 */ 26 27 28 #ifndef _EMLXS_DFC_H 29 #define _EMLXS_DFC_H 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #include <sys/fibre-channel/fcio.h> 36 #include <emlxs_fcio.h> 37 38 39 #ifndef DFC_SUPPORT 40 #define DFC_REV 0 41 #else 42 #define DFC_REV 1 43 44 #ifdef DHCHAP_SUPPORT 45 #undef DFC_REV 46 #define DFC_REV 2 47 #endif /* DHCHAP_SUPPORT */ 48 49 #ifdef NPIV_SUPPORT 50 #undef DFC_REV 51 #define DFC_REV 3 52 #endif /* NPIV_SUPPORT */ 53 #endif /* DFC_SUPPORT */ 54 55 56 typedef struct dfc 57 { 58 uint32_t cmd; 59 uint32_t flag; 60 61 void *buf1; 62 uint32_t buf1_size; 63 uint32_t data1; 64 65 void *buf2; 66 uint32_t buf2_size; 67 uint32_t data2; 68 69 void *buf3; 70 uint32_t buf3_size; 71 uint32_t data3; 72 73 void *buf4; 74 uint32_t buf4_size; 75 uint32_t data4; 76 } dfc_t; 77 78 79 /* 80 * 32 bit varient of dfc_t to be used only in the driver and NOT applications 81 */ 82 typedef struct dfc32 83 { 84 uint32_t cmd; 85 uint32_t flag; 86 87 uint32_t buf1; 88 uint32_t buf1_size; 89 uint32_t data1; 90 91 uint32_t buf2; 92 uint32_t buf2_size; 93 uint32_t data2; 94 95 uint32_t buf3; 96 uint32_t buf3_size; 97 uint32_t data3; 98 99 uint32_t buf4; 100 uint32_t buf4_size; 101 uint32_t data4; 102 103 } dfc32_t; 104 105 106 #ifdef SAN_DIAG_SUPPORT 107 typedef struct sd_bucket_info 108 { 109 uint16_t type; 110 uint16_t search_type; 111 uint32_t base; 112 uint32_t step; 113 uint16_t state; 114 uint64_t values[SD_IO_LATENCY_MAX_BUCKETS]; 115 } sd_bucket_info_t; 116 #endif 117 118 /* Valid dfc.dfc_cmd codes (DFC_REV=1) */ 119 #define EMLXS_GET_HBAINFO 1 120 #define EMLXS_GET_IOINFO 2 121 #define EMLXS_GET_LINKINFO 3 122 #define EMLXS_GET_NODEINFO 4 123 #define EMLXS_GET_EVENTINFO 5 124 #define EMLXS_GET_REV 6 125 #define EMLXS_GET_DUMPREGION 7 126 #define EMLXS_GET_HBASTATS 8 127 #define EMLXS_GET_DRVSTATS 9 128 129 /* FCIO_SUPPORT */ 130 #define EMLXS_FCIO_CMD 10 131 132 #define EMLXS_GET_CFG 15 133 #define EMLXS_SET_CFG 16 134 #define EMLXS_GET_EVENT 17 135 #define EMLXS_SET_EVENT 18 136 137 #define EMLXS_SEND_MBOX 20 138 #define EMLXS_SEND_ELS 21 139 #define EMLXS_SEND_CT 22 140 #define EMLXS_SEND_CT_RSP 23 141 #define EMLXS_SEND_MENLO 24 142 #define EMLXS_SEND_SCSI 25 143 144 #define EMLXS_SET_DIAG 30 145 #define EMLXS_LOOPBACK_MODE 31 146 #define EMLXS_LOOPBACK_TEST 32 147 148 #define EMLXS_READ_PCI 40 149 #define EMLXS_WRITE_PCI 41 150 #define EMLXS_WRITE_FLASH 42 151 #define EMLXS_READ_FLASH 43 152 #define EMLXS_READ_MEM 44 153 #define EMLXS_WRITE_MEM 45 154 #define EMLXS_WRITE_CTLREG 46 155 #define EMLXS_READ_CTLREG 47 156 157 158 /* NPIV_SUPPORT */ 159 #define EMLXS_CREATE_VPORT 50 160 #define EMLXS_DESTROY_VPORT 51 161 #define EMLXS_GET_VPORTINFO 52 162 #define EMLXS_NPIV_RESOURCE 53 163 #define EMLXS_NPIV_TEST 54 164 165 /* DHCHAP_SUPPORT */ 166 #define EMLXS_INIT_AUTH 60 167 #define EMLXS_GET_AUTH_CFG 61 168 #define EMLXS_SET_AUTH_CFG 62 169 #define EMLXS_GET_AUTH_PASSWORD 63 170 #define EMLXS_SET_AUTH_PASSWORD 64 171 #define EMLXS_GET_AUTH_STATUS 65 172 #define EMLXS_GET_AUTH_CFG_TABLE 66 173 #define EMLXS_GET_AUTH_KEY_TABLE 67 174 175 /* SFCT_SUPPORT */ 176 #define EMLXS_GET_FCTSTAT 70 177 178 /* SAN DIAG SUPPORT */ 179 #define EMLXS_SD_SET_BUCKET 100 180 #define EMLXS_SD_START_DATA_COLLECTION 101 181 #define EMLXS_SD_STOP_DATA_COLLECTION 102 182 #define EMLXS_SD_RESET_DATA_COLLECTION 103 183 #define EMLXS_SD_GET_DATA 104 184 #define EMLXS_SD_DESTROY_BUCKET 105 185 #define EMLXS_SD_GET_BUCKET 106 186 #define EMLXS_SD_SET_EVENT 107 187 #define EMLXS_SD_GET_EVENT 108 188 189 /* EMLXS_SET_AUTH_CFG - flags */ 190 #define EMLXS_AUTH_CFG_ADD 0 191 #define EMLXS_AUTH_CFG_DELETE 1 192 193 /* ERROR Codes */ 194 #define DFC_ERRNO_START 0x200 195 196 #define DFC_SUCCESS 0 197 #define DFC_SYS_ERROR (DFC_ERRNO_START + 1) /* General system err */ 198 #define DFC_DRV_ERROR (DFC_ERRNO_START + 2) /* General driver err */ 199 #define DFC_HBA_ERROR (DFC_ERRNO_START + 3) /* General HBA err */ 200 #define DFC_IO_ERROR (DFC_ERRNO_START + 4) /* General IO err */ 201 202 #define DFC_ARG_INVALID (DFC_ERRNO_START + 5) /* Invalid Argument */ 203 #define DFC_ARG_MISALIGNED (DFC_ERRNO_START + 6) /* Misaligned Argument */ 204 #define DFC_ARG_NULL (DFC_ERRNO_START + 7) /* NULL Argument */ 205 #define DFC_ARG_TOOSMALL (DFC_ERRNO_START + 8) /* Argument too small */ 206 #define DFC_ARG_TOOBIG (DFC_ERRNO_START + 9) /* Argument too big */ 207 208 #define DFC_COPYIN_ERROR (DFC_ERRNO_START + 10) /* DDI copyin err */ 209 #define DFC_COPYOUT_ERROR (DFC_ERRNO_START + 11) /* DDI copyout err */ 210 211 #define DFC_TIMEOUT (DFC_ERRNO_START + 12) /* Resource timeout */ 212 #define DFC_SYSRES_ERROR (DFC_ERRNO_START + 13) /* Out of sys resource */ 213 #define DFC_DRVRES_ERROR (DFC_ERRNO_START + 14) /* Out of drv resource */ 214 #define DFC_HBARES_ERROR (DFC_ERRNO_START + 15) /* Out of HBA resource */ 215 216 #define DFC_OFFLINE_ERROR (DFC_ERRNO_START + 16) /* Driver offline */ 217 #define DFC_ONLINE_ERROR (DFC_ERRNO_START + 17) /* Driver offline */ 218 219 /* NPIV_SUPPORT */ 220 #define DFC_NPIV_DISABLED (DFC_ERRNO_START + 18) /* NPIV disabled */ 221 #define DFC_NPIV_UNSUPPORTED (DFC_ERRNO_START + 19) /* NPIV not supported */ 222 #define DFC_NPIV_ACTIVE (DFC_ERRNO_START + 20) /* NPIV active */ 223 224 /* DHCHAP_SUPPORT */ 225 #define DFC_AUTH_NOT_CONFIGURED (DFC_ERRNO_START + 30) 226 #define DFC_AUTH_FAILED_NO_SA_FOUND (DFC_ERRNO_START + 31) 227 #define DFC_AUTH_INIT_OK_AUTH_FAILED (DFC_ERRNO_START + 32) 228 #define DFC_AUTH_COMPARE_FAILED (DFC_ERRNO_START + 33) 229 #define DFC_AUTH_WWN_NOT_FOUND (DFC_ERRNO_START + 34) 230 #define DFC_AUTH_PASSWORD_INVALID (DFC_ERRNO_START + 35) 231 #define DFC_AUTH_INVALID_ENTITY (DFC_ERRNO_START + 36) 232 #define DFC_AUTH_ENTITY_NOT_ACTIVE (DFC_ERRNO_START + 37) 233 #define DFC_AUTH_INVALID_OPERATION (DFC_ERRNO_START + 38) 234 #define DFC_AUTH_AUTHENTICATION_GOINGON (DFC_ERRNO_START + 39) 235 #define DFC_AUTH_CREATE_STORKEY_ERROR (DFC_ERRNO_START + 40) 236 #define DFC_AUTH_CREATE_PARMKEY_ERROR (DFC_ERRNO_START + 41) 237 #define DFC_AUTH_CREATE_AUTHKEY_ERROR (DFC_ERRNO_START + 42) 238 #define DFC_AUTH_CREATE_BORDKEY_ERROR (DFC_ERRNO_START + 43) 239 #define DFC_AUTH_AUTHENTICATION_NOT_SUPPORTED (DFC_ERRNO_START + 44) 240 #define DFC_AUTH_AUTHENTICATION_DISABLED (DFC_ERRNO_START + 45) 241 #define DFC_AUTH_CONFIG_NOT_FOUND (DFC_ERRNO_START + 47) 242 #define DFC_AUTH_LOCAL_REMOTE_PWD_EQUAL (DFC_ERRNO_START + 48) 243 244 /* MENLO_SUPPORT */ 245 #define DFC_INVALID_ADAPTER (DFC_ERRNO_START + 50) 246 #define DFC_RSP_BUF_OVERRUN (DFC_ERRNO_START + 51) 247 #define DFC_LINKDOWN_ERROR (DFC_ERRNO_START + 52) 248 249 /* SAN_DIAG_SUPPORT */ 250 #define DFC_SD_STAT_START (DFC_ERRNO_START + 60) 251 252 #define DFC_SD_OK (DFC_ERRNO_START + 60) 253 #define DFC_SD_ERROR_GENERIC (DFC_ERRNO_START + 61) 254 #define DFC_SD_ERROR_INVALID_ARG (DFC_ERRNO_START + 62) 255 #define DFC_SD_ERROR_INVALID_BOARD_ID (DFC_ERRNO_START + 63) 256 #define DFC_SD_ERROR_INVALID_PORT (DFC_ERRNO_START + 64) 257 #define DFC_SD_ERROR_NOT_SUPPORTED (DFC_ERRNO_START + 65) 258 #define DFC_SD_ERROR_CATEGORY_NOT_SUPPORTED (DFC_ERRNO_START + 66) 259 #define DFC_SD_ERROR_SUBCAT_NOT_SUPPORTED (DFC_ERRNO_START + 67) 260 #define DFC_SD_ERROR_MORE_DATA_AVAIL (DFC_ERRNO_START + 68) 261 #define DFC_SD_ERROR_EVENT_ALREADY_REG (DFC_ERRNO_START + 69) 262 #define DFC_SD_ERROR_NO_ACTIVE_REG (DFC_ERRNO_START + 70) 263 #define DFC_SD_ERROR_ARG_MISSING (DFC_ERRNO_START + 71) 264 #define DFC_SD_ERROR_NO_MEM (DFC_ERRNO_START + 72) 265 #define DFC_SD_ERROR_BUCKET_NOT_SET (DFC_ERRNO_START + 73) 266 #define DFC_SD_ERROR_REG_HANDLE (DFC_ERRNO_START + 74) 267 #define DFC_SD_ERROR_INVALID_SEARCH_TYPE (DFC_ERRNO_START + 75) 268 #define DFC_SD_ERROR_FUNCTION_NOT_SUPPORTED (DFC_ERRNO_START + 76) 269 #define DFC_SD_ERROR_OUT_OF_HANDLES (DFC_ERRNO_START + 77) 270 #define DFC_SD_ERROR_LIB_NOT_INIT (DFC_ERRNO_START + 78) 271 #define DFC_SD_ERROR_DATA_COLLECTION_ACTIVE (DFC_ERRNO_START + 79) 272 #define DFC_SD_ERROR_DATA_COLLECTION_NOT_ACTIVE (DFC_ERRNO_START + 80) 273 274 275 #define DFC_ERRNO_END (DFC_ERRNO_START + 128) 276 277 typedef struct dfc_hbainfo 278 { 279 char vpd_serial_num[32]; 280 char vpd_part_num[32]; 281 char vpd_port_num[20]; 282 char vpd_eng_change[32]; 283 char vpd_manufacturer[80]; 284 char vpd_model[80]; 285 char vpd_model_desc[256]; 286 char vpd_prog_types[256]; 287 char vpd_id[80]; 288 289 uint32_t flags; 290 #define HBA_FLAG_SBUS 0x00000001 291 #define HBA_FLAG_OFFLINE 0x00000002 292 #define HBA_FLAG_NPIV 0x00000004 /* Supports NPIV */ 293 #define HBA_FLAG_DHCHAP 0x00000008 /* Supports DHCHAP */ 294 #define HBA_FLAG_DYN_WWN 0x00000010 /* Supports Dynamic WWN */ 295 #define HBA_FLAG_E2E_AUTH 0x00000020 /* Supports E2E Auth */ 296 #define HBA_FLAG_TARGET_MODE 0x00000040 /* Supports Target Mode */ 297 #define HBA_FLAG_TARGET_MODE_ENA 0x00000080 /* Target Mode is enabled */ 298 299 uint32_t device_id; 300 uint32_t vendor_id; 301 uint32_t ports; 302 uint32_t port_index; 303 304 uint32_t vpi_max; 305 uint32_t vpi_high; 306 307 char wwnn[8]; 308 char snn[256]; 309 310 char wwpn[8]; 311 char spn[256]; 312 313 char fw_version[256]; 314 char fcode_version[256]; 315 char boot_version[256]; 316 317 uint32_t biuRev; 318 uint32_t smRev; 319 uint32_t smFwRev; 320 uint32_t endecRev; 321 uint32_t rBit; 322 uint32_t fcphHigh; 323 uint32_t fcphLow; 324 uint32_t feaLevelHigh; 325 uint32_t feaLevelLow; 326 327 uint32_t kern_rev; 328 char kern_name[32]; 329 uint32_t stub_rev; 330 char stub_name[32]; 331 uint32_t sli1_rev; 332 char sli1_name[32]; 333 uint32_t sli2_rev; 334 char sli2_name[32]; 335 uint32_t sli3_rev; 336 char sli3_name[32]; 337 uint32_t sli4_rev; 338 char sli4_name[32]; 339 uint32_t sli_mode; 340 341 uint32_t drv_instance; 342 char drv_label[64]; 343 char drv_module[64]; 344 char drv_name[32]; 345 char drv_version[64]; 346 char drv_revision[64]; 347 348 char hostname[32]; 349 char os_devname[256]; 350 351 uint32_t port_id; 352 uint32_t port_type; 353 uint32_t port_state; 354 uint32_t topology; 355 uint32_t hard_alpa; 356 uint8_t alpa_count; 357 uint8_t alpa_map[128]; 358 359 uint32_t supported_cos; 360 uint32_t supported_types[8]; 361 uint32_t active_types[8]; 362 363 uint32_t supported_speeds; 364 uint32_t port_speed; 365 uint32_t max_frame_size; 366 367 uint8_t fabric_wwpn[8]; 368 uint8_t fabric_wwnn[8]; 369 uint32_t node_count; 370 } dfc_hbainfo_t; 371 372 373 374 typedef struct fc_class 375 { 376 #ifdef EMLXS_BIG_ENDIAN 377 uint8_t classValid:1; /* FC Word 0, bit 31 */ 378 uint8_t intermix:1; /* FC Word 0, bit 30 */ 379 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 380 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 381 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 382 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 383 #endif 384 #ifdef EMLXS_LITTLE_ENDIAN 385 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 386 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 387 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 388 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 389 uint8_t intermix:1; /* FC Word 0, bit 30 */ 390 uint8_t classValid:1; /* FC Word 0, bit 31 */ 391 #endif 392 uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */ 393 #ifdef EMLXS_BIG_ENDIAN 394 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 395 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 396 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 397 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 398 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 399 #endif 400 #ifdef EMLXS_LITTLE_ENDIAN 401 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 402 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 403 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 404 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 405 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 406 #endif 407 uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */ 408 #ifdef EMLXS_BIG_ENDIAN 409 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 410 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 411 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 412 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 413 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 414 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 415 #endif 416 #ifdef EMLXS_LITTLE_ENDIAN 417 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 418 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 419 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 420 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 421 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 422 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 423 #endif 424 uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */ 425 uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */ 426 uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */ 427 428 uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */ 429 uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */ 430 uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */ 431 uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */ 432 433 uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */ 434 uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */ 435 uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */ 436 uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */ 437 } fc_class_t; 438 439 typedef struct fc_csp 440 { 441 uint8_t fcphHigh; /* FC Word 0, byte 0 */ 442 uint8_t fcphLow; /* FC Word 0, byte 1 */ 443 uint8_t bbCreditMsb; /* FC Word 0, byte 2 */ 444 uint8_t bbCreditlsb; /* FC Word 0, byte 3 */ 445 446 #ifdef EMLXS_BIG_ENDIAN 447 uint16_t increasingOffset:1; /* FC Word 1, bit 31 */ 448 uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 449 uint16_t word1Reserved2:1; /* FC Word 1, bit 29 */ 450 uint16_t fPort:1; /* FC Word 1, bit 28 */ 451 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 452 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 453 uint16_t multicast:1; /* FC Word 1, bit 25 */ 454 uint16_t broadcast:1; /* FC Word 1, bit 24 */ 455 456 uint16_t huntgroup:1; /* FC Word 1, bit 23 */ 457 uint16_t simplex:1; /* FC Word 1, bit 22 */ 458 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */ 459 uint16_t dhd:1; /* FC Word 1, bit 18 */ 460 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 461 uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 462 #endif 463 #ifdef EMLXS_LITTLE_ENDIAN 464 uint16_t broadcast:1; /* FC Word 1, bit 24 */ 465 uint16_t multicast:1; /* FC Word 1, bit 25 */ 466 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 467 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 468 uint16_t fPort:1; /* FC Word 1, bit 28 */ 469 uint16_t word1Reserved2:1; /* FC Word 1, bit 29 */ 470 uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 471 uint16_t increasingOffset:1; /* FC Word 1, bit 31 */ 472 473 uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 474 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 475 uint16_t dhd:1; /* FC Word 1, bit 18 */ 476 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */ 477 uint16_t simplex:1; /* FC Word 1, bit 22 */ 478 uint16_t huntgroup:1; /* FC Word 1, bit 23 */ 479 #endif 480 481 uint8_t bbRcvSizeMsb; /* FC Word 1, byte 2 */ 482 uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */ 483 484 union 485 { 486 struct 487 { 488 uint8_t word2Reserved1; /* FC Word 2 byte 0 */ 489 uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */ 490 uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */ 491 uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */ 492 } nPort; 493 494 uint32_t r_a_tov; /* RATOV (Big Endian) */ 495 } w2; 496 497 uint32_t e_d_tov; /* E_D_TOV must be in B.E. format */ 498 } fc_csp_t; 499 500 501 typedef struct fc_sparm 502 { 503 fc_csp_t csp; 504 505 uint8_t wwpn[8]; 506 uint8_t wwnn[8]; 507 508 fc_class_t cls1; 509 fc_class_t cls2; 510 fc_class_t cls3; 511 fc_class_t cls4; 512 513 uint8_t vendorVersion[16]; 514 } fc_sparm_t; 515 516 517 typedef struct dfc_node 518 { 519 uint32_t port_id; 520 uint32_t rpi; 521 uint32_t xri; 522 uint32_t flags; 523 524 #define PORT_FLAG_FCP_TARGET 0x00000001 525 #define PORT_FLAG_FCP_INI 0x00000002 526 #define PORT_FLAG_FCP2 0x00000004 527 #define PORT_FLAG_IP 0x00000008 528 #define PORT_FLAG_VPORT 0x00000010 529 530 fc_sparm_t sparm; 531 532 } dfc_node_t; 533 534 535 typedef struct dfc_hbastats 536 { 537 uint32_t tx_frame_cnt; 538 uint32_t rx_frame_cnt; 539 uint32_t tx_kbyte_cnt; 540 uint32_t rx_kbyte_cnt; 541 uint32_t tx_seq_cnt; 542 uint32_t rx_seq_cnt; 543 uint32_t orig_exch_cnt; 544 uint32_t resp_exch_cnt; 545 uint32_t pbsy_cnt; 546 uint32_t fbsy_cnt; 547 uint32_t link_failure_cnt; 548 uint32_t loss_sync_cnt; 549 uint32_t loss_signal_cnt; 550 uint32_t seq_error_cnt; 551 uint32_t inval_tx_word_cnt; 552 uint32_t crc_error_cnt; 553 uint32_t seq_timeout_cnt; 554 uint32_t elastic_overrun_cnt; 555 uint32_t arb_timeout_cnt; 556 uint32_t rx_buf_credit; 557 uint32_t rx_buf_cnt; 558 uint32_t tx_buf_credit; 559 uint32_t tx_buf_cnt; 560 uint32_t EOFa_cnt; 561 uint32_t EOFdti_cnt; 562 uint32_t EOFni_cnt; 563 uint32_t SOFf_cnt; 564 uint32_t link_event_tag; 565 uint32_t last_reset_time; 566 uint32_t topology; 567 uint32_t port_type; 568 uint32_t link_speed; 569 } dfc_hbastats_t; 570 571 572 typedef struct dfc_drvstats 573 { 574 uint32_t LinkUp; 575 uint32_t LinkDown; 576 uint32_t LinkEvent; 577 uint32_t LinkMultiEvent; 578 579 uint32_t MboxIssued; 580 uint32_t MboxCompleted; /* = MboxError + MbxGood */ 581 uint32_t MboxGood; 582 uint32_t MboxError; 583 uint32_t MboxBusy; 584 uint32_t MboxInvalid; 585 586 uint32_t IocbIssued[4]; 587 uint32_t IocbReceived[4]; 588 uint32_t IocbTxPut[4]; 589 uint32_t IocbTxGet[4]; 590 uint32_t IocbRingFull[4]; 591 592 uint32_t IntrEvent[8]; 593 #define RESV_INTR 7 594 #define ERATT_INTR 6 595 #define MBATT_INTR 5 596 #define LKATT_INTR 4 597 #define R3ATT_INTR 3 598 #define R2ATT_INTR 2 599 #define R1ATT_INTR 1 600 #define R0ATT_INTR 0 601 602 uint32_t FcpIssued; 603 uint32_t FcpCompleted; /* FcpGood + FcpError */ 604 uint32_t FcpGood; 605 uint32_t FcpError; 606 607 uint32_t FcpEvent; /* FcpStray + FcpComplete */ 608 uint32_t FcpStray; 609 610 uint32_t ElsEvent; /* ElsStray + ElsComplete (cmd + rsp) */ 611 uint32_t ElsStray; 612 613 uint32_t ElsCmdIssued; 614 uint32_t ElsCmdCompleted; /* ElsCmdGood + ElsCmdError */ 615 uint32_t ElsCmdGood; 616 uint32_t ElsCmdError; 617 618 uint32_t ElsRspIssued; 619 uint32_t ElsRspCompleted; 620 621 uint32_t ElsRcvEvent; /* ElsRcvError + ElsRcvDrop + ElsCmdRcv */ 622 uint32_t ElsRcvError; 623 uint32_t ElsRcvDropped; 624 uint32_t ElsCmdReceived; /* ElsRscnRcv + ElsPlogiRcv + ... */ 625 uint32_t ElsRscnReceived; 626 uint32_t ElsPlogiReceived; 627 uint32_t ElsPrliReceived; 628 uint32_t ElsPrloReceived; 629 uint32_t ElsLogoReceived; 630 uint32_t ElsAdiscReceived; 631 uint32_t ElsGenReceived; 632 633 uint32_t CtEvent; /* CtStray + CtCmdComplete + CtRspComplete */ 634 uint32_t CtStray; 635 636 uint32_t CtCmdIssued; 637 uint32_t CtCmdCompleted; /* CtCmdGood + CtCmdError */ 638 uint32_t CtCmdGood; 639 uint32_t CtCmdError; 640 641 uint32_t CtRspIssued; 642 uint32_t CtRspCompleted; 643 644 uint32_t CtRcvEvent; /* CtRcvError + CtRcvDropp + CtCmdRcv */ 645 uint32_t CtRcvError; 646 uint32_t CtRcvDropped; 647 uint32_t CtCmdReceived; 648 649 uint32_t IpEvent; /* IpStray + IpSeqComplete + IpBcastComplete */ 650 uint32_t IpStray; 651 652 uint32_t IpSeqIssued; 653 uint32_t IpSeqCompleted; /* IpSeqGood + IpSeqError */ 654 uint32_t IpSeqGood; 655 uint32_t IpSeqError; 656 657 uint32_t IpBcastIssued; 658 uint32_t IpBcastCompleted; /* IpBcastGood + IpBcastError */ 659 uint32_t IpBcastGood; 660 uint32_t IpBcastError; 661 662 uint32_t IpRcvEvent; /* IpDrop + IpSeqRcv + IpBcastRcv */ 663 uint32_t IpDropped; 664 uint32_t IpSeqReceived; 665 uint32_t IpBcastReceived; 666 667 uint32_t IpUbPosted; 668 uint32_t ElsUbPosted; 669 uint32_t CtUbPosted; 670 671 #if (DFC_REV >= 2) 672 uint32_t IocbThrottled; 673 uint32_t ElsAuthReceived; 674 #endif 675 } dfc_drvstats_t; 676 677 #ifdef SFCT_SUPPORT 678 /* 679 * FctP2IOXcnt will count IOs by their fcpDL. Counters 680 * are for buckets of various power of 2 sizes. 681 * Bucket 0 < 512 > 0 682 * Bucket 1 >= 512 < 1024 683 * Bucket 2 >= 1024 < 2048 684 * Bucket 3 >= 2048 < 4096 685 * Bucket 4 >= 4096 < 8192 686 * Bucket 5 >= 8192 < 16K 687 * Bucket 6 >= 16K < 32K 688 * Bucket 7 >= 32K < 64K 689 * Bucket 8 >= 64K < 128K 690 * Bucket 9 >= 128K < 256K 691 * Bucket 10 >= 256K < 512K 692 * Bucket 11 >= 512K < 1MB 693 * Bucket 12 >= 1MB < 2MB 694 * Bucket 13 >= 2MB < 4MB 695 * Bucket 14 >= 4MB < 8MB 696 * Bucket 15 >= 8MB 697 */ 698 #define DFC_TGTPORT_STAT_VERSION 1 699 #define MAX_TGTPORT_IOCNT 16 700 typedef struct dfc_tgtport_stat 701 { 702 uint8_t Version; 703 uint8_t Reserved[7]; 704 705 /* IO counters */ 706 uint64_t FctP2IOWcnt[MAX_TGTPORT_IOCNT]; /* Writes */ 707 uint64_t FctP2IORcnt[MAX_TGTPORT_IOCNT]; /* Reads */ 708 uint64_t FctIOCmdCnt; /* Other, ie TUR */ 709 uint64_t FctCmdReceived; /* total I/O */ 710 uint64_t FctReadBytes; /* total read bytes */ 711 uint64_t FctWriteBytes; /* total write bytes */ 712 713 /* IOCB handling counters */ 714 uint64_t FctEvent; /* FctStray + FctCmpl */ 715 uint64_t FctCompleted; /* FctCmpl (Good+Err) */ 716 uint64_t FctCmplGood; 717 718 uint32_t FctCmplError; 719 uint32_t FctStray; 720 721 /* Fct event counters */ 722 uint32_t FctRcvDropped; 723 uint32_t FctOverQDepth; 724 uint32_t FctOutstandingIO; 725 uint32_t FctFailedPortRegister; 726 uint32_t FctPortRegister; 727 uint32_t FctPortDeregister; 728 729 uint32_t FctAbortSent; 730 uint32_t FctNoBuffer; 731 uint32_t FctScsiStatusErr; 732 uint32_t FctScsiQfullErr; 733 uint32_t FctScsiResidOver; 734 uint32_t FctScsiResidUnder; 735 uint32_t FctScsiSenseErr; 736 737 /* Additional info */ 738 uint32_t FctLinkState; 739 } dfc_tgtport_stat_t; 740 #endif /* SFCT_SUPPORT */ 741 742 /* DFC_REV >= 3 */ 743 typedef struct dfc_vportinfo 744 { 745 uint32_t flags; 746 #define VPORT_CONFIG 0x00000001 747 #define VPORT_ENABLED 0x00000002 748 #define VPORT_BOUND 0x00000004 749 #define VPORT_IP 0x00000008 750 #define VPORT_RESTRICTED 0x00000010 /* login restricted */ 751 752 uint32_t vpi; 753 uint32_t port_id; 754 uint8_t wwpn[8]; 755 uint8_t wwnn[8]; 756 757 char snn[256]; 758 char spn[256]; 759 760 uint32_t ulp_statec; 761 } dfc_vportinfo_t; 762 763 #ifdef __cplusplus 764 } 765 #endif 766 767 #endif /* _EMLXS_DFC_H */ 768