1 /****************************************************************************** 2 3 Copyright (c) 2013-2017, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #ifndef _I40E_TYPE_H_ 36 #define _I40E_TYPE_H_ 37 38 #include "i40e_status.h" 39 #include "i40e_osdep.h" 40 #include "i40e_register.h" 41 #include "i40e_adminq.h" 42 #include "i40e_hmc.h" 43 #include "i40e_lan_hmc.h" 44 #include "i40e_devids.h" 45 46 47 #define BIT(a) (1UL << (a)) 48 #define BIT_ULL(a) (1ULL << (a)) 49 50 #ifndef I40E_MASK 51 /* I40E_MASK is a macro used on 32 bit registers */ 52 #define I40E_MASK(mask, shift) (((uint32_t)(mask)) << ((uint32_t)(shift))) 53 #endif 54 55 #define I40E_MAX_PF 16 56 #define I40E_MAX_PF_VSI 64 57 #define I40E_MAX_PF_QP 128 58 #define I40E_MAX_VSI_QP 16 59 #define I40E_MAX_VF_VSI 3 60 #define I40E_MAX_CHAINED_RX_BUFFERS 5 61 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16 62 63 /* something less than 1 minute */ 64 #define I40E_HEARTBEAT_TIMEOUT (HZ * 50) 65 66 /* Max default timeout in ms, */ 67 #define I40E_MAX_NVM_TIMEOUT 18000 68 69 /* Max timeout in ms for the phy to respond */ 70 #define I40E_MAX_PHY_TIMEOUT 500 71 72 /* Check whether address is multicast. */ 73 #define I40E_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01)) 74 75 /* Check whether an address is broadcast. */ 76 #define I40E_IS_BROADCAST(address) \ 77 ((((u8 *)(address))[0] == ((u8)0xff)) && \ 78 (((u8 *)(address))[1] == ((u8)0xff))) 79 80 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */ 81 #define I40E_MS_TO_GTIME(time) ((time) * 1000) 82 83 /* forward declaration */ 84 struct i40e_hw; 85 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *); 86 87 #define ETH_ALEN 6 88 /* Data type manipulation macros. */ 89 #define I40E_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF)) 90 #define I40E_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF)) 91 92 #define I40E_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF)) 93 #define I40E_LO_WORD(x) ((u16)((x) & 0xFFFF)) 94 95 #define I40E_HI_BYTE(x) ((u8)(((x) >> 8) & 0xFF)) 96 #define I40E_LO_BYTE(x) ((u8)((x) & 0xFF)) 97 98 /* Number of Transmit Descriptors must be a multiple of 8. */ 99 #define I40E_REQ_TX_DESCRIPTOR_MULTIPLE 8 100 /* Number of Receive Descriptors must be a multiple of 32 if 101 * the number of descriptors is greater than 32. 102 */ 103 #define I40E_REQ_RX_DESCRIPTOR_MULTIPLE 32 104 105 #define I40E_DESC_UNUSED(R) \ 106 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \ 107 (R)->next_to_clean - (R)->next_to_use - 1) 108 109 /* bitfields for Tx queue mapping in QTX_CTL */ 110 #define I40E_QTX_CTL_VF_QUEUE 0x0 111 #define I40E_QTX_CTL_VM_QUEUE 0x1 112 #define I40E_QTX_CTL_PF_QUEUE 0x2 113 114 /* debug masks - set these bits in hw->debug_mask to control output */ 115 enum i40e_debug_mask { 116 I40E_DEBUG_INIT = 0x00000001, 117 I40E_DEBUG_RELEASE = 0x00000002, 118 119 I40E_DEBUG_LINK = 0x00000010, 120 I40E_DEBUG_PHY = 0x00000020, 121 I40E_DEBUG_HMC = 0x00000040, 122 I40E_DEBUG_NVM = 0x00000080, 123 I40E_DEBUG_LAN = 0x00000100, 124 I40E_DEBUG_FLOW = 0x00000200, 125 I40E_DEBUG_DCB = 0x00000400, 126 I40E_DEBUG_DIAG = 0x00000800, 127 I40E_DEBUG_FD = 0x00001000, 128 129 I40E_DEBUG_AQ_MESSAGE = 0x01000000, 130 I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000, 131 I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000, 132 I40E_DEBUG_AQ_COMMAND = 0x06000000, 133 I40E_DEBUG_AQ = 0x0F000000, 134 135 I40E_DEBUG_USER = 0xF0000000, 136 137 I40E_DEBUG_ALL = 0xFFFFFFFF 138 }; 139 140 /* PCI Bus Info */ 141 #define I40E_PCI_LINK_STATUS 0xB2 142 #define I40E_PCI_LINK_WIDTH 0x3F0 143 #define I40E_PCI_LINK_WIDTH_1 0x10 144 #define I40E_PCI_LINK_WIDTH_2 0x20 145 #define I40E_PCI_LINK_WIDTH_4 0x40 146 #define I40E_PCI_LINK_WIDTH_8 0x80 147 #define I40E_PCI_LINK_SPEED 0xF 148 #define I40E_PCI_LINK_SPEED_2500 0x1 149 #define I40E_PCI_LINK_SPEED_5000 0x2 150 #define I40E_PCI_LINK_SPEED_8000 0x3 151 152 #define I40E_MDIO_CLAUSE22_STCODE_MASK I40E_MASK(1, \ 153 I40E_GLGEN_MSCA_STCODE_SHIFT) 154 #define I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK I40E_MASK(1, \ 155 I40E_GLGEN_MSCA_OPCODE_SHIFT) 156 #define I40E_MDIO_CLAUSE22_OPCODE_READ_MASK I40E_MASK(2, \ 157 I40E_GLGEN_MSCA_OPCODE_SHIFT) 158 159 #define I40E_MDIO_CLAUSE45_STCODE_MASK I40E_MASK(0, \ 160 I40E_GLGEN_MSCA_STCODE_SHIFT) 161 #define I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK I40E_MASK(0, \ 162 I40E_GLGEN_MSCA_OPCODE_SHIFT) 163 #define I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK I40E_MASK(1, \ 164 I40E_GLGEN_MSCA_OPCODE_SHIFT) 165 #define I40E_MDIO_CLAUSE45_OPCODE_READ_INC_ADDR_MASK I40E_MASK(2, \ 166 I40E_GLGEN_MSCA_OPCODE_SHIFT) 167 #define I40E_MDIO_CLAUSE45_OPCODE_READ_MASK I40E_MASK(3, \ 168 I40E_GLGEN_MSCA_OPCODE_SHIFT) 169 170 #define I40E_PHY_COM_REG_PAGE 0x1E 171 #define I40E_PHY_LED_LINK_MODE_MASK 0xF0 172 #define I40E_PHY_LED_MANUAL_ON 0x100 173 #define I40E_PHY_LED_PROV_REG_1 0xC430 174 #define I40E_PHY_LED_MODE_MASK 0xFFFF 175 #define I40E_PHY_LED_MODE_ORIG 0x80000000 176 177 /* Memory types */ 178 enum i40e_memset_type { 179 I40E_NONDMA_MEM = 0, 180 I40E_DMA_MEM 181 }; 182 183 /* Memcpy types */ 184 enum i40e_memcpy_type { 185 I40E_NONDMA_TO_NONDMA = 0, 186 I40E_NONDMA_TO_DMA, 187 I40E_DMA_TO_DMA, 188 I40E_DMA_TO_NONDMA 189 }; 190 191 192 /* These are structs for managing the hardware information and the operations. 193 * The structures of function pointers are filled out at init time when we 194 * know for sure exactly which hardware we're working with. This gives us the 195 * flexibility of using the same main driver code but adapting to slightly 196 * different hardware needs as new parts are developed. For this architecture, 197 * the Firmware and AdminQ are intended to insulate the driver from most of the 198 * future changes, but these structures will also do part of the job. 199 */ 200 enum i40e_mac_type { 201 I40E_MAC_UNKNOWN = 0, 202 I40E_MAC_X710, 203 I40E_MAC_XL710, 204 I40E_MAC_VF, 205 I40E_MAC_X722, 206 I40E_MAC_X722_VF, 207 I40E_MAC_GENERIC, 208 }; 209 210 enum i40e_media_type { 211 I40E_MEDIA_TYPE_UNKNOWN = 0, 212 I40E_MEDIA_TYPE_FIBER, 213 I40E_MEDIA_TYPE_BASET, 214 I40E_MEDIA_TYPE_BACKPLANE, 215 I40E_MEDIA_TYPE_CX4, 216 I40E_MEDIA_TYPE_DA, 217 I40E_MEDIA_TYPE_VIRTUAL 218 }; 219 220 enum i40e_fc_mode { 221 I40E_FC_NONE = 0, 222 I40E_FC_RX_PAUSE, 223 I40E_FC_TX_PAUSE, 224 I40E_FC_FULL, 225 I40E_FC_PFC, 226 I40E_FC_DEFAULT 227 }; 228 229 enum i40e_set_fc_aq_failures { 230 I40E_SET_FC_AQ_FAIL_NONE = 0, 231 I40E_SET_FC_AQ_FAIL_GET = 1, 232 I40E_SET_FC_AQ_FAIL_SET = 2, 233 I40E_SET_FC_AQ_FAIL_UPDATE = 4, 234 I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6 235 }; 236 237 enum i40e_vsi_type { 238 I40E_VSI_MAIN = 0, 239 I40E_VSI_VMDQ1 = 1, 240 I40E_VSI_VMDQ2 = 2, 241 I40E_VSI_CTRL = 3, 242 I40E_VSI_FCOE = 4, 243 I40E_VSI_MIRROR = 5, 244 I40E_VSI_SRIOV = 6, 245 I40E_VSI_FDIR = 7, 246 I40E_VSI_TYPE_UNKNOWN 247 }; 248 249 enum i40e_queue_type { 250 I40E_QUEUE_TYPE_RX = 0, 251 I40E_QUEUE_TYPE_TX, 252 I40E_QUEUE_TYPE_PE_CEQ, 253 I40E_QUEUE_TYPE_UNKNOWN 254 }; 255 256 struct i40e_link_status { 257 enum i40e_aq_phy_type phy_type; 258 enum i40e_aq_link_speed link_speed; 259 u8 link_info; 260 u8 an_info; 261 u8 req_fec_info; 262 u8 fec_info; 263 u8 ext_info; 264 u8 loopback; 265 /* is Link Status Event notification to SW enabled */ 266 bool lse_enable; 267 u16 max_frame_size; 268 bool crc_enable; 269 u8 pacing; 270 u8 requested_speeds; 271 u8 module_type[3]; 272 /* 1st byte: module identifier */ 273 #define I40E_MODULE_TYPE_SFP 0x03 274 #define I40E_MODULE_TYPE_QSFP 0x0D 275 /* 2nd byte: ethernet compliance codes for 10/40G */ 276 #define I40E_MODULE_TYPE_40G_ACTIVE 0x01 277 #define I40E_MODULE_TYPE_40G_LR4 0x02 278 #define I40E_MODULE_TYPE_40G_SR4 0x04 279 #define I40E_MODULE_TYPE_40G_CR4 0x08 280 #define I40E_MODULE_TYPE_10G_BASE_SR 0x10 281 #define I40E_MODULE_TYPE_10G_BASE_LR 0x20 282 #define I40E_MODULE_TYPE_10G_BASE_LRM 0x40 283 #define I40E_MODULE_TYPE_10G_BASE_ER 0x80 284 /* 3rd byte: ethernet compliance codes for 1G */ 285 #define I40E_MODULE_TYPE_1000BASE_SX 0x01 286 #define I40E_MODULE_TYPE_1000BASE_LX 0x02 287 #define I40E_MODULE_TYPE_1000BASE_CX 0x04 288 #define I40E_MODULE_TYPE_1000BASE_T 0x08 289 }; 290 291 struct i40e_phy_info { 292 struct i40e_link_status link_info; 293 struct i40e_link_status link_info_old; 294 bool get_link_info; 295 enum i40e_media_type media_type; 296 /* all the phy types the NVM is capable of */ 297 u64 phy_types; 298 }; 299 300 #define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII) 301 #define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX) 302 #define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4) 303 #define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR) 304 #define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4) 305 #define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI) 306 #define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI) 307 #define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI) 308 #define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI) 309 #define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI) 310 #define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU) 311 #define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU) 312 #define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC) 313 #define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC) 314 #define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX) 315 #define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T) 316 #define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T) 317 #define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR) 318 #define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR) 319 #define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU) 320 #define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1) 321 #define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4) 322 #define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4) 323 #define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4) 324 #define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX) 325 #define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX) 326 #define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL \ 327 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL) 328 #define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2) 329 #define I40E_CAP_PHY_TYPE_25GBASE_KR I40E_MASK((u64)I40E_AQ_PHY_TYPE_EXT_25G_KR, 32) 330 #define I40E_CAP_PHY_TYPE_25GBASE_CR I40E_MASK((u64)I40E_AQ_PHY_TYPE_EXT_25G_CR, 32) 331 #define I40E_CAP_PHY_TYPE_25GBASE_SR I40E_MASK((u64)I40E_AQ_PHY_TYPE_EXT_25G_SR, 32) 332 #define I40E_CAP_PHY_TYPE_25GBASE_LR I40E_MASK((u64)I40E_AQ_PHY_TYPE_EXT_25G_LR, 32) 333 #define I40E_CAP_PHY_TYPE_25GBASE_AOC I40E_MASK((u64)I40E_AQ_PHY_TYPE_EXT_25G_AOLRC, 32) 334 #define I40E_CAP_PHY_TYPE_25GBASE_ACC I40E_MASK((u64)I40E_AQ_PHY_TYPE_EXT_25G_ACLRC, 32) 335 #define I40E_HW_CAP_MAX_GPIO 30 336 #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO 0 337 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C 1 338 339 enum i40e_acpi_programming_method { 340 I40E_ACPI_PROGRAMMING_METHOD_HW_FVL = 0, 341 I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK = 1 342 }; 343 344 #define I40E_WOL_SUPPORT_MASK 1 345 #define I40E_ACPI_PROGRAMMING_METHOD_MASK (1 << 1) 346 #define I40E_PROXY_SUPPORT_MASK (1 << 2) 347 348 /* Capabilities of a PF or a VF or the whole device */ 349 struct i40e_hw_capabilities { 350 u32 switch_mode; 351 #define I40E_NVM_IMAGE_TYPE_EVB 0x0 352 #define I40E_NVM_IMAGE_TYPE_CLOUD 0x2 353 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3 354 355 /* Cloud filter modes: 356 * Mode1: Filter on L4 port only 357 * Mode2: Filter for non-tunneled traffic 358 * Mode3: Filter for tunnel traffic 359 */ 360 #define I40E_CLOUD_FILTER_MODE1 0x6 361 #define I40E_CLOUD_FILTER_MODE2 0x7 362 #define I40E_CLOUD_FILTER_MODE3 0x8 363 364 u32 management_mode; 365 u32 mng_protocols_over_mctp; 366 #define I40E_MNG_PROTOCOL_PLDM 0x2 367 #define I40E_MNG_PROTOCOL_OEM_COMMANDS 0x4 368 #define I40E_MNG_PROTOCOL_NCSI 0x8 369 u32 npar_enable; 370 u32 os2bmc; 371 u32 valid_functions; 372 bool sr_iov_1_1; 373 bool vmdq; 374 bool evb_802_1_qbg; /* Edge Virtual Bridging */ 375 bool evb_802_1_qbh; /* Bridge Port Extension */ 376 bool dcb; 377 bool fcoe; 378 bool iscsi; /* Indicates iSCSI enabled */ 379 bool flex10_enable; 380 bool flex10_capable; 381 u32 flex10_mode; 382 #define I40E_FLEX10_MODE_UNKNOWN 0x0 383 #define I40E_FLEX10_MODE_DCC 0x1 384 #define I40E_FLEX10_MODE_DCI 0x2 385 386 u32 flex10_status; 387 #define I40E_FLEX10_STATUS_DCC_ERROR 0x1 388 #define I40E_FLEX10_STATUS_VC_MODE 0x2 389 390 bool sec_rev_disabled; 391 bool update_disabled; 392 #define I40E_NVM_MGMT_SEC_REV_DISABLED 0x1 393 #define I40E_NVM_MGMT_UPDATE_DISABLED 0x2 394 395 bool mgmt_cem; 396 bool ieee_1588; 397 bool iwarp; 398 bool fd; 399 u32 fd_filters_guaranteed; 400 u32 fd_filters_best_effort; 401 bool rss; 402 u32 rss_table_size; 403 u32 rss_table_entry_width; 404 bool led[I40E_HW_CAP_MAX_GPIO]; 405 bool sdp[I40E_HW_CAP_MAX_GPIO]; 406 u32 nvm_image_type; 407 u32 num_flow_director_filters; 408 u32 num_vfs; 409 u32 vf_base_id; 410 u32 num_vsis; 411 u32 num_rx_qp; 412 u32 num_tx_qp; 413 u32 base_queue; 414 u32 num_msix_vectors; 415 u32 num_msix_vectors_vf; 416 u32 led_pin_num; 417 u32 sdp_pin_num; 418 u32 mdio_port_num; 419 u32 mdio_port_mode; 420 u8 rx_buf_chain_len; 421 u32 enabled_tcmap; 422 u32 maxtc; 423 u64 wr_csr_prot; 424 bool apm_wol_support; 425 enum i40e_acpi_programming_method acpi_prog_method; 426 bool proxy_support; 427 }; 428 429 struct i40e_mac_info { 430 enum i40e_mac_type type; 431 u8 addr[ETH_ALEN]; 432 u8 perm_addr[ETH_ALEN]; 433 u8 san_addr[ETH_ALEN]; 434 u8 port_addr[ETH_ALEN]; 435 u16 max_fcoeq; 436 }; 437 438 enum i40e_aq_resources_ids { 439 I40E_NVM_RESOURCE_ID = 1 440 }; 441 442 enum i40e_aq_resource_access_type { 443 I40E_RESOURCE_READ = 1, 444 I40E_RESOURCE_WRITE 445 }; 446 447 struct i40e_nvm_info { 448 u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */ 449 u32 timeout; /* [ms] */ 450 u16 sr_size; /* Shadow RAM size in words */ 451 bool blank_nvm_mode; /* is NVM empty (no FW present)*/ 452 u16 version; /* NVM package version */ 453 u32 eetrack; /* NVM data version */ 454 u32 oem_ver; /* OEM version info */ 455 }; 456 457 /* definitions used in NVM update support */ 458 459 enum i40e_nvmupd_cmd { 460 I40E_NVMUPD_INVALID, 461 I40E_NVMUPD_READ_CON, 462 I40E_NVMUPD_READ_SNT, 463 I40E_NVMUPD_READ_LCB, 464 I40E_NVMUPD_READ_SA, 465 I40E_NVMUPD_WRITE_ERA, 466 I40E_NVMUPD_WRITE_CON, 467 I40E_NVMUPD_WRITE_SNT, 468 I40E_NVMUPD_WRITE_LCB, 469 I40E_NVMUPD_WRITE_SA, 470 I40E_NVMUPD_CSUM_CON, 471 I40E_NVMUPD_CSUM_SA, 472 I40E_NVMUPD_CSUM_LCB, 473 I40E_NVMUPD_STATUS, 474 I40E_NVMUPD_EXEC_AQ, 475 I40E_NVMUPD_GET_AQ_RESULT, 476 I40E_NVMUPD_GET_AQ_EVENT, 477 }; 478 479 enum i40e_nvmupd_state { 480 I40E_NVMUPD_STATE_INIT, 481 I40E_NVMUPD_STATE_READING, 482 I40E_NVMUPD_STATE_WRITING, 483 I40E_NVMUPD_STATE_INIT_WAIT, 484 I40E_NVMUPD_STATE_WRITE_WAIT, 485 I40E_NVMUPD_STATE_ERROR 486 }; 487 488 /* nvm_access definition and its masks/shifts need to be accessible to 489 * application, core driver, and shared code. Where is the right file? 490 */ 491 #define I40E_NVM_READ 0xB 492 #define I40E_NVM_WRITE 0xC 493 494 #define I40E_NVM_MOD_PNT_MASK 0xFF 495 496 #define I40E_NVM_TRANS_SHIFT 8 497 #define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT) 498 #define I40E_NVM_PRESERVATION_FLAGS_SHIFT 12 499 #define I40E_NVM_PRESERVATION_FLAGS_MASK \ 500 (0x3 << I40E_NVM_PRESERVATION_FLAGS_SHIFT) 501 #define I40E_NVM_PRESERVATION_FLAGS_SELECTED 0x01 502 #define I40E_NVM_PRESERVATION_FLAGS_ALL 0x02 503 #define I40E_NVM_CON 0x0 504 #define I40E_NVM_SNT 0x1 505 #define I40E_NVM_LCB 0x2 506 #define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB) 507 #define I40E_NVM_ERA 0x4 508 #define I40E_NVM_CSUM 0x8 509 #define I40E_NVM_AQE 0xe 510 #define I40E_NVM_EXEC 0xf 511 512 #define I40E_NVM_ADAPT_SHIFT 16 513 #define I40E_NVM_ADAPT_MASK (0xffffULL << I40E_NVM_ADAPT_SHIFT) 514 515 #define I40E_NVMUPD_MAX_DATA 4096 516 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */ 517 518 struct i40e_nvm_access { 519 u32 command; 520 u32 config; 521 u32 offset; /* in bytes */ 522 u32 data_size; /* in bytes */ 523 u8 data[1]; 524 }; 525 526 /* (Q)SFP module access definitions */ 527 #define I40E_I2C_EEPROM_DEV_ADDR 0xA0 528 #define I40E_I2C_EEPROM_DEV_ADDR2 0xA2 529 #define I40E_MODULE_TYPE_ADDR 0x00 530 #define I40E_MODULE_REVISION_ADDR 0x01 531 #define I40E_MODULE_SFF_8472_COMP 0x5E 532 #define I40E_MODULE_SFF_8472_SWAP 0x5C 533 #define I40E_MODULE_SFF_ADDR_MODE 0x04 534 #define I40E_MODULE_SFF_DIAG_CAPAB 0x40 535 #define I40E_MODULE_TYPE_QSFP_PLUS 0x0D 536 #define I40E_MODULE_TYPE_QSFP28 0x11 537 #define I40E_MODULE_QSFP_MAX_LEN 640 538 539 /* PCI bus types */ 540 enum i40e_bus_type { 541 i40e_bus_type_unknown = 0, 542 i40e_bus_type_pci, 543 i40e_bus_type_pcix, 544 i40e_bus_type_pci_express, 545 i40e_bus_type_reserved 546 }; 547 548 /* PCI bus speeds */ 549 enum i40e_bus_speed { 550 i40e_bus_speed_unknown = 0, 551 i40e_bus_speed_33 = 33, 552 i40e_bus_speed_66 = 66, 553 i40e_bus_speed_100 = 100, 554 i40e_bus_speed_120 = 120, 555 i40e_bus_speed_133 = 133, 556 i40e_bus_speed_2500 = 2500, 557 i40e_bus_speed_5000 = 5000, 558 i40e_bus_speed_8000 = 8000, 559 i40e_bus_speed_reserved 560 }; 561 562 /* PCI bus widths */ 563 enum i40e_bus_width { 564 i40e_bus_width_unknown = 0, 565 i40e_bus_width_pcie_x1 = 1, 566 i40e_bus_width_pcie_x2 = 2, 567 i40e_bus_width_pcie_x4 = 4, 568 i40e_bus_width_pcie_x8 = 8, 569 i40e_bus_width_32 = 32, 570 i40e_bus_width_64 = 64, 571 i40e_bus_width_reserved 572 }; 573 574 /* Bus parameters */ 575 struct i40e_bus_info { 576 enum i40e_bus_speed speed; 577 enum i40e_bus_width width; 578 enum i40e_bus_type type; 579 580 u16 func; 581 u16 device; 582 u16 lan_id; 583 u16 bus_id; 584 }; 585 586 /* Flow control (FC) parameters */ 587 struct i40e_fc_info { 588 enum i40e_fc_mode current_mode; /* FC mode in effect */ 589 enum i40e_fc_mode requested_mode; /* FC mode requested by caller */ 590 }; 591 592 #define I40E_MAX_TRAFFIC_CLASS 8 593 #define I40E_MAX_USER_PRIORITY 8 594 #define I40E_DCBX_MAX_APPS 32 595 #define I40E_LLDPDU_SIZE 1500 596 #define I40E_TLV_STATUS_OPER 0x1 597 #define I40E_TLV_STATUS_SYNC 0x2 598 #define I40E_TLV_STATUS_ERR 0x4 599 #define I40E_CEE_OPER_MAX_APPS 3 600 #define I40E_APP_PROTOID_FCOE 0x8906 601 #define I40E_APP_PROTOID_ISCSI 0x0cbc 602 #define I40E_APP_PROTOID_FIP 0x8914 603 #define I40E_APP_SEL_ETHTYPE 0x1 604 #define I40E_APP_SEL_TCPIP 0x2 605 #define I40E_CEE_APP_SEL_ETHTYPE 0x0 606 #define I40E_CEE_APP_SEL_TCPIP 0x1 607 608 /* CEE or IEEE 802.1Qaz ETS Configuration data */ 609 struct i40e_dcb_ets_config { 610 u8 willing; 611 u8 cbs; 612 u8 maxtcs; 613 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS]; 614 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS]; 615 u8 tsatable[I40E_MAX_TRAFFIC_CLASS]; 616 }; 617 618 /* CEE or IEEE 802.1Qaz PFC Configuration data */ 619 struct i40e_dcb_pfc_config { 620 u8 willing; 621 u8 mbc; 622 u8 pfccap; 623 u8 pfcenable; 624 }; 625 626 /* CEE or IEEE 802.1Qaz Application Priority data */ 627 struct i40e_dcb_app_priority_table { 628 u8 priority; 629 u8 selector; 630 u16 protocolid; 631 }; 632 633 struct i40e_dcbx_config { 634 u8 dcbx_mode; 635 #define I40E_DCBX_MODE_CEE 0x1 636 #define I40E_DCBX_MODE_IEEE 0x2 637 u8 app_mode; 638 #define I40E_DCBX_APPS_NON_WILLING 0x1 639 u32 numapps; 640 u32 tlv_status; /* CEE mode TLV status */ 641 struct i40e_dcb_ets_config etscfg; 642 struct i40e_dcb_ets_config etsrec; 643 struct i40e_dcb_pfc_config pfc; 644 struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS]; 645 }; 646 647 /* Port hardware description */ 648 struct i40e_hw { 649 u8 *hw_addr; 650 void *back; 651 652 /* subsystem structs */ 653 struct i40e_phy_info phy; 654 struct i40e_mac_info mac; 655 struct i40e_bus_info bus; 656 struct i40e_nvm_info nvm; 657 struct i40e_fc_info fc; 658 659 /* pci info */ 660 u16 device_id; 661 u16 vendor_id; 662 u16 subsystem_device_id; 663 u16 subsystem_vendor_id; 664 u8 revision_id; 665 u8 port; 666 bool adapter_stopped; 667 668 /* capabilities for entire device and PCI func */ 669 struct i40e_hw_capabilities dev_caps; 670 struct i40e_hw_capabilities func_caps; 671 672 /* Flow Director shared filter space */ 673 u16 fdir_shared_filter_count; 674 675 /* device profile info */ 676 u8 pf_id; 677 u16 main_vsi_seid; 678 679 /* for multi-function MACs */ 680 u16 partition_id; 681 u16 num_partitions; 682 u16 num_ports; 683 684 /* Closest numa node to the device */ 685 u16 numa_node; 686 687 /* Admin Queue info */ 688 struct i40e_adminq_info aq; 689 690 /* state of nvm update process */ 691 enum i40e_nvmupd_state nvmupd_state; 692 struct i40e_aq_desc nvm_wb_desc; 693 struct i40e_aq_desc nvm_aq_event_desc; 694 struct i40e_virt_mem nvm_buff; 695 bool nvm_release_on_done; 696 u16 nvm_wait_opcode; 697 698 /* HMC info */ 699 struct i40e_hmc_info hmc; /* HMC info struct */ 700 701 /* LLDP/DCBX Status */ 702 u16 dcbx_status; 703 704 /* DCBX info */ 705 struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */ 706 struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */ 707 struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */ 708 709 /* WoL and proxy support */ 710 u16 num_wol_proxy_filters; 711 u16 wol_proxy_vsi_seid; 712 713 #define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0) 714 #define I40E_HW_FLAG_802_1AD_CAPABLE BIT_ULL(1) 715 #define I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE BIT_ULL(2) 716 #define I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK BIT_ULL(3) 717 u64 flags; 718 719 /* Used in set switch config AQ command */ 720 u16 switch_tag; 721 u16 first_tag; 722 u16 second_tag; 723 724 /* debug mask */ 725 u32 debug_mask; 726 char err_str[16]; 727 }; 728 729 static INLINE bool i40e_is_vf(struct i40e_hw *hw) 730 { 731 return (hw->mac.type == I40E_MAC_VF || 732 hw->mac.type == I40E_MAC_X722_VF); 733 } 734 735 struct i40e_driver_version { 736 u8 major_version; 737 u8 minor_version; 738 u8 build_version; 739 u8 subbuild_version; 740 u8 driver_string[32]; 741 }; 742 743 /* RX Descriptors */ 744 union i40e_16byte_rx_desc { 745 struct { 746 __le64 pkt_addr; /* Packet buffer address */ 747 __le64 hdr_addr; /* Header buffer address */ 748 } read; 749 struct { 750 struct { 751 struct { 752 union { 753 __le16 mirroring_status; 754 __le16 fcoe_ctx_id; 755 } mirr_fcoe; 756 __le16 l2tag1; 757 } lo_dword; 758 union { 759 __le32 rss; /* RSS Hash */ 760 __le32 fd_id; /* Flow director filter id */ 761 __le32 fcoe_param; /* FCoE DDP Context id */ 762 } hi_dword; 763 } qword0; 764 struct { 765 /* ext status/error/pktype/length */ 766 __le64 status_error_len; 767 } qword1; 768 } wb; /* writeback */ 769 }; 770 771 union i40e_32byte_rx_desc { 772 struct { 773 __le64 pkt_addr; /* Packet buffer address */ 774 __le64 hdr_addr; /* Header buffer address */ 775 /* bit 0 of hdr_buffer_addr is DD bit */ 776 __le64 rsvd1; 777 __le64 rsvd2; 778 } read; 779 struct { 780 struct { 781 struct { 782 union { 783 __le16 mirroring_status; 784 __le16 fcoe_ctx_id; 785 } mirr_fcoe; 786 __le16 l2tag1; 787 } lo_dword; 788 union { 789 __le32 rss; /* RSS Hash */ 790 __le32 fcoe_param; /* FCoE DDP Context id */ 791 /* Flow director filter id in case of 792 * Programming status desc WB 793 */ 794 __le32 fd_id; 795 } hi_dword; 796 } qword0; 797 struct { 798 /* status/error/pktype/length */ 799 __le64 status_error_len; 800 } qword1; 801 struct { 802 __le16 ext_status; /* extended status */ 803 __le16 rsvd; 804 __le16 l2tag2_1; 805 __le16 l2tag2_2; 806 } qword2; 807 struct { 808 union { 809 __le32 flex_bytes_lo; 810 __le32 pe_status; 811 } lo_dword; 812 union { 813 __le32 flex_bytes_hi; 814 __le32 fd_id; 815 } hi_dword; 816 } qword3; 817 } wb; /* writeback */ 818 }; 819 820 #define I40E_RXD_QW0_MIRROR_STATUS_SHIFT 8 821 #define I40E_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \ 822 I40E_RXD_QW0_MIRROR_STATUS_SHIFT) 823 #define I40E_RXD_QW0_FCOEINDX_SHIFT 0 824 #define I40E_RXD_QW0_FCOEINDX_MASK (0xFFFUL << \ 825 I40E_RXD_QW0_FCOEINDX_SHIFT) 826 827 enum i40e_rx_desc_status_bits { 828 /* Note: These are predefined bit offsets */ 829 I40E_RX_DESC_STATUS_DD_SHIFT = 0, 830 I40E_RX_DESC_STATUS_EOF_SHIFT = 1, 831 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2, 832 I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3, 833 I40E_RX_DESC_STATUS_CRCP_SHIFT = 4, 834 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */ 835 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7, 836 I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT = 8, 837 838 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */ 839 I40E_RX_DESC_STATUS_FLM_SHIFT = 11, 840 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */ 841 I40E_RX_DESC_STATUS_LPBK_SHIFT = 14, 842 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15, 843 I40E_RX_DESC_STATUS_RESERVED2_SHIFT = 16, /* 2 BITS */ 844 I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT = 18, 845 I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */ 846 }; 847 848 #define I40E_RXD_QW1_STATUS_SHIFT 0 849 #define I40E_RXD_QW1_STATUS_MASK ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) << \ 850 I40E_RXD_QW1_STATUS_SHIFT) 851 852 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT 853 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \ 854 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT) 855 856 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT 857 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT) 858 859 #define I40E_RXD_QW1_STATUS_UMBCAST_SHIFT I40E_RX_DESC_STATUS_UMBCAST 860 #define I40E_RXD_QW1_STATUS_UMBCAST_MASK (0x3UL << \ 861 I40E_RXD_QW1_STATUS_UMBCAST_SHIFT) 862 863 enum i40e_rx_desc_fltstat_values { 864 I40E_RX_DESC_FLTSTAT_NO_DATA = 0, 865 I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */ 866 I40E_RX_DESC_FLTSTAT_RSV = 2, 867 I40E_RX_DESC_FLTSTAT_RSS_HASH = 3, 868 }; 869 870 #define I40E_RXD_PACKET_TYPE_UNICAST 0 871 #define I40E_RXD_PACKET_TYPE_MULTICAST 1 872 #define I40E_RXD_PACKET_TYPE_BROADCAST 2 873 #define I40E_RXD_PACKET_TYPE_MIRRORED 3 874 875 #define I40E_RXD_QW1_ERROR_SHIFT 19 876 #define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT) 877 878 enum i40e_rx_desc_error_bits { 879 /* Note: These are predefined bit offsets */ 880 I40E_RX_DESC_ERROR_RXE_SHIFT = 0, 881 I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1, 882 I40E_RX_DESC_ERROR_HBO_SHIFT = 2, 883 I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */ 884 I40E_RX_DESC_ERROR_IPE_SHIFT = 3, 885 I40E_RX_DESC_ERROR_L4E_SHIFT = 4, 886 I40E_RX_DESC_ERROR_EIPE_SHIFT = 5, 887 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6, 888 I40E_RX_DESC_ERROR_PPRS_SHIFT = 7 889 }; 890 891 enum i40e_rx_desc_error_l3l4e_fcoe_masks { 892 I40E_RX_DESC_ERROR_L3L4E_NONE = 0, 893 I40E_RX_DESC_ERROR_L3L4E_PROT = 1, 894 I40E_RX_DESC_ERROR_L3L4E_FC = 2, 895 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3, 896 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4 897 }; 898 899 #define I40E_RXD_QW1_PTYPE_SHIFT 30 900 #define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT) 901 902 /* Packet type non-ip values */ 903 enum i40e_rx_l2_ptype { 904 I40E_RX_PTYPE_L2_RESERVED = 0, 905 I40E_RX_PTYPE_L2_MAC_PAY2 = 1, 906 I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2, 907 I40E_RX_PTYPE_L2_FIP_PAY2 = 3, 908 I40E_RX_PTYPE_L2_OUI_PAY2 = 4, 909 I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5, 910 I40E_RX_PTYPE_L2_LLDP_PAY2 = 6, 911 I40E_RX_PTYPE_L2_ECP_PAY2 = 7, 912 I40E_RX_PTYPE_L2_EVB_PAY2 = 8, 913 I40E_RX_PTYPE_L2_QCN_PAY2 = 9, 914 I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10, 915 I40E_RX_PTYPE_L2_ARP = 11, 916 I40E_RX_PTYPE_L2_FCOE_PAY3 = 12, 917 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13, 918 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14, 919 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15, 920 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16, 921 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17, 922 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18, 923 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19, 924 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20, 925 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21, 926 I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58, 927 I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87, 928 I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124, 929 I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153 930 }; 931 932 struct i40e_rx_ptype_decoded { 933 u32 ptype:8; 934 u32 known:1; 935 u32 outer_ip:1; 936 u32 outer_ip_ver:1; 937 u32 outer_frag:1; 938 u32 tunnel_type:3; 939 u32 tunnel_end_prot:2; 940 u32 tunnel_end_frag:1; 941 u32 inner_prot:4; 942 u32 payload_layer:3; 943 }; 944 945 enum i40e_rx_ptype_outer_ip { 946 I40E_RX_PTYPE_OUTER_L2 = 0, 947 I40E_RX_PTYPE_OUTER_IP = 1 948 }; 949 950 enum i40e_rx_ptype_outer_ip_ver { 951 I40E_RX_PTYPE_OUTER_NONE = 0, 952 I40E_RX_PTYPE_OUTER_IPV4 = 0, 953 I40E_RX_PTYPE_OUTER_IPV6 = 1 954 }; 955 956 enum i40e_rx_ptype_outer_fragmented { 957 I40E_RX_PTYPE_NOT_FRAG = 0, 958 I40E_RX_PTYPE_FRAG = 1 959 }; 960 961 enum i40e_rx_ptype_tunnel_type { 962 I40E_RX_PTYPE_TUNNEL_NONE = 0, 963 I40E_RX_PTYPE_TUNNEL_IP_IP = 1, 964 I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2, 965 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3, 966 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4, 967 }; 968 969 enum i40e_rx_ptype_tunnel_end_prot { 970 I40E_RX_PTYPE_TUNNEL_END_NONE = 0, 971 I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1, 972 I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2, 973 }; 974 975 enum i40e_rx_ptype_inner_prot { 976 I40E_RX_PTYPE_INNER_PROT_NONE = 0, 977 I40E_RX_PTYPE_INNER_PROT_UDP = 1, 978 I40E_RX_PTYPE_INNER_PROT_TCP = 2, 979 I40E_RX_PTYPE_INNER_PROT_SCTP = 3, 980 I40E_RX_PTYPE_INNER_PROT_ICMP = 4, 981 I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5 982 }; 983 984 enum i40e_rx_ptype_payload_layer { 985 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0, 986 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1, 987 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2, 988 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3, 989 }; 990 991 #define I40E_RX_PTYPE_BIT_MASK 0x0FFFFFFF 992 #define I40E_RX_PTYPE_SHIFT 56 993 994 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38 995 #define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \ 996 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) 997 998 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52 999 #define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \ 1000 I40E_RXD_QW1_LENGTH_HBUF_SHIFT) 1001 1002 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63 1003 #define I40E_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT) 1004 1005 #define I40E_RXD_QW1_NEXTP_SHIFT 38 1006 #define I40E_RXD_QW1_NEXTP_MASK (0x1FFFULL << I40E_RXD_QW1_NEXTP_SHIFT) 1007 1008 #define I40E_RXD_QW2_EXT_STATUS_SHIFT 0 1009 #define I40E_RXD_QW2_EXT_STATUS_MASK (0xFFFFFUL << \ 1010 I40E_RXD_QW2_EXT_STATUS_SHIFT) 1011 1012 enum i40e_rx_desc_ext_status_bits { 1013 /* Note: These are predefined bit offsets */ 1014 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0, 1015 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1, 1016 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */ 1017 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */ 1018 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9, 1019 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10, 1020 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11, 1021 }; 1022 1023 #define I40E_RXD_QW2_L2TAG2_SHIFT 0 1024 #define I40E_RXD_QW2_L2TAG2_MASK (0xFFFFUL << I40E_RXD_QW2_L2TAG2_SHIFT) 1025 1026 #define I40E_RXD_QW2_L2TAG3_SHIFT 16 1027 #define I40E_RXD_QW2_L2TAG3_MASK (0xFFFFUL << I40E_RXD_QW2_L2TAG3_SHIFT) 1028 1029 enum i40e_rx_desc_pe_status_bits { 1030 /* Note: These are predefined bit offsets */ 1031 I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */ 1032 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */ 1033 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */ 1034 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24, 1035 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25, 1036 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26, 1037 I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27, 1038 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28, 1039 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29 1040 }; 1041 1042 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38 1043 #define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000 1044 1045 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2 1046 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \ 1047 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT) 1048 1049 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT 0 1050 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_MASK (0x7FFFUL << \ 1051 I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT) 1052 1053 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19 1054 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \ 1055 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT) 1056 1057 enum i40e_rx_prog_status_desc_status_bits { 1058 /* Note: These are predefined bit offsets */ 1059 I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0, 1060 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */ 1061 }; 1062 1063 enum i40e_rx_prog_status_desc_prog_id_masks { 1064 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1, 1065 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2, 1066 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4, 1067 }; 1068 1069 enum i40e_rx_prog_status_desc_error_bits { 1070 /* Note: These are predefined bit offsets */ 1071 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0, 1072 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1, 1073 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2, 1074 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3 1075 }; 1076 1077 #define I40E_TWO_BIT_MASK 0x3 1078 #define I40E_THREE_BIT_MASK 0x7 1079 #define I40E_FOUR_BIT_MASK 0xF 1080 #define I40E_EIGHTEEN_BIT_MASK 0x3FFFF 1081 1082 /* TX Descriptor */ 1083 struct i40e_tx_desc { 1084 __le64 buffer_addr; /* Address of descriptor's data buf */ 1085 __le64 cmd_type_offset_bsz; 1086 }; 1087 1088 #define I40E_TXD_QW1_DTYPE_SHIFT 0 1089 #define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT) 1090 1091 enum i40e_tx_desc_dtype_value { 1092 I40E_TX_DESC_DTYPE_DATA = 0x0, 1093 I40E_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */ 1094 I40E_TX_DESC_DTYPE_CONTEXT = 0x1, 1095 I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2, 1096 I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8, 1097 I40E_TX_DESC_DTYPE_DDP_CTX = 0x9, 1098 I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB, 1099 I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC, 1100 I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD, 1101 I40E_TX_DESC_DTYPE_DESC_DONE = 0xF 1102 }; 1103 1104 #define I40E_TXD_QW1_CMD_SHIFT 4 1105 #define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT) 1106 1107 enum i40e_tx_desc_cmd_bits { 1108 I40E_TX_DESC_CMD_EOP = 0x0001, 1109 I40E_TX_DESC_CMD_RS = 0x0002, 1110 I40E_TX_DESC_CMD_ICRC = 0x0004, 1111 I40E_TX_DESC_CMD_IL2TAG1 = 0x0008, 1112 I40E_TX_DESC_CMD_DUMMY = 0x0010, 1113 I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */ 1114 I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */ 1115 I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */ 1116 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */ 1117 I40E_TX_DESC_CMD_FCOET = 0x0080, 1118 I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */ 1119 I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */ 1120 I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */ 1121 I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */ 1122 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */ 1123 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */ 1124 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */ 1125 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */ 1126 }; 1127 1128 #define I40E_TXD_QW1_OFFSET_SHIFT 16 1129 #define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \ 1130 I40E_TXD_QW1_OFFSET_SHIFT) 1131 1132 enum i40e_tx_desc_length_fields { 1133 /* Note: These are predefined bit offsets */ 1134 I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */ 1135 I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */ 1136 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */ 1137 }; 1138 1139 #define I40E_TXD_QW1_MACLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_MACLEN_SHIFT) 1140 #define I40E_TXD_QW1_IPLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_IPLEN_SHIFT) 1141 #define I40E_TXD_QW1_L4LEN_MASK (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT) 1142 #define I40E_TXD_QW1_FCLEN_MASK (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT) 1143 1144 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34 1145 #define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \ 1146 I40E_TXD_QW1_TX_BUF_SZ_SHIFT) 1147 1148 #define I40E_TXD_QW1_L2TAG1_SHIFT 48 1149 #define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT) 1150 1151 /* Context descriptors */ 1152 struct i40e_tx_context_desc { 1153 __le32 tunneling_params; 1154 __le16 l2tag2; 1155 __le16 rsvd; 1156 __le64 type_cmd_tso_mss; 1157 }; 1158 1159 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0 1160 #define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT) 1161 1162 #define I40E_TXD_CTX_QW1_CMD_SHIFT 4 1163 #define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT) 1164 1165 enum i40e_tx_ctx_desc_cmd_bits { 1166 I40E_TX_CTX_DESC_TSO = 0x01, 1167 I40E_TX_CTX_DESC_TSYN = 0x02, 1168 I40E_TX_CTX_DESC_IL2TAG2 = 0x04, 1169 I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08, 1170 I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00, 1171 I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10, 1172 I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20, 1173 I40E_TX_CTX_DESC_SWTCH_VSI = 0x30, 1174 I40E_TX_CTX_DESC_SWPE = 0x40 1175 }; 1176 1177 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30 1178 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \ 1179 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) 1180 1181 #define I40E_TXD_CTX_QW1_MSS_SHIFT 50 1182 #define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \ 1183 I40E_TXD_CTX_QW1_MSS_SHIFT) 1184 1185 #define I40E_TXD_CTX_QW1_VSI_SHIFT 50 1186 #define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT) 1187 1188 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0 1189 #define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \ 1190 I40E_TXD_CTX_QW0_EXT_IP_SHIFT) 1191 1192 enum i40e_tx_ctx_desc_eipt_offload { 1193 I40E_TX_CTX_EXT_IP_NONE = 0x0, 1194 I40E_TX_CTX_EXT_IP_IPV6 = 0x1, 1195 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2, 1196 I40E_TX_CTX_EXT_IP_IPV4 = 0x3 1197 }; 1198 1199 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2 1200 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \ 1201 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT) 1202 1203 #define I40E_TXD_CTX_QW0_NATT_SHIFT 9 1204 #define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT) 1205 1206 #define I40E_TXD_CTX_UDP_TUNNELING BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT) 1207 #define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT) 1208 1209 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11 1210 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT) 1211 1212 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK 1213 1214 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12 1215 #define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \ 1216 I40E_TXD_CTX_QW0_NATLEN_SHIFT) 1217 1218 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19 1219 #define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \ 1220 I40E_TXD_CTX_QW0_DECTTL_SHIFT) 1221 1222 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT 23 1223 #define I40E_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT) 1224 struct i40e_nop_desc { 1225 __le64 rsvd; 1226 __le64 dtype_cmd; 1227 }; 1228 1229 #define I40E_TXD_NOP_QW1_DTYPE_SHIFT 0 1230 #define I40E_TXD_NOP_QW1_DTYPE_MASK (0xFUL << I40E_TXD_NOP_QW1_DTYPE_SHIFT) 1231 1232 #define I40E_TXD_NOP_QW1_CMD_SHIFT 4 1233 #define I40E_TXD_NOP_QW1_CMD_MASK (0x7FUL << I40E_TXD_NOP_QW1_CMD_SHIFT) 1234 1235 enum i40e_tx_nop_desc_cmd_bits { 1236 /* Note: These are predefined bit offsets */ 1237 I40E_TX_NOP_DESC_EOP_SHIFT = 0, 1238 I40E_TX_NOP_DESC_RS_SHIFT = 1, 1239 I40E_TX_NOP_DESC_RSV_SHIFT = 2 /* 5 bits */ 1240 }; 1241 1242 struct i40e_filter_program_desc { 1243 __le32 qindex_flex_ptype_vsi; 1244 __le32 rsvd; 1245 __le32 dtype_cmd_cntindex; 1246 __le32 fd_id; 1247 }; 1248 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0 1249 #define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \ 1250 I40E_TXD_FLTR_QW0_QINDEX_SHIFT) 1251 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11 1252 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \ 1253 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) 1254 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17 1255 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \ 1256 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) 1257 1258 /* Packet Classifier Types for filters */ 1259 enum i40e_filter_pctype { 1260 /* Note: Values 0-28 are reserved for future use. 1261 * Value 29, 30, 32 are not supported on XL710 and X710. 1262 */ 1263 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP = 29, 1264 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP = 30, 1265 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31, 1266 I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK = 32, 1267 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33, 1268 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34, 1269 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35, 1270 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36, 1271 /* Note: Values 37-38 are reserved for future use. 1272 * Value 39, 40, 42 are not supported on XL710 and X710. 1273 */ 1274 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP = 39, 1275 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP = 40, 1276 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41, 1277 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK = 42, 1278 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43, 1279 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44, 1280 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45, 1281 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46, 1282 /* Note: Value 47 is reserved for future use */ 1283 I40E_FILTER_PCTYPE_FCOE_OX = 48, 1284 I40E_FILTER_PCTYPE_FCOE_RX = 49, 1285 I40E_FILTER_PCTYPE_FCOE_OTHER = 50, 1286 /* Note: Values 51-62 are reserved for future use */ 1287 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63, 1288 }; 1289 1290 enum i40e_filter_program_desc_dest { 1291 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0, 1292 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1, 1293 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2, 1294 }; 1295 1296 enum i40e_filter_program_desc_fd_status { 1297 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0, 1298 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1, 1299 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2, 1300 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3, 1301 }; 1302 1303 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23 1304 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \ 1305 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) 1306 1307 #define I40E_TXD_FLTR_QW1_DTYPE_SHIFT 0 1308 #define I40E_TXD_FLTR_QW1_DTYPE_MASK (0xFUL << I40E_TXD_FLTR_QW1_DTYPE_SHIFT) 1309 1310 #define I40E_TXD_FLTR_QW1_CMD_SHIFT 4 1311 #define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \ 1312 I40E_TXD_FLTR_QW1_CMD_SHIFT) 1313 1314 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT) 1315 #define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT) 1316 1317 enum i40e_filter_program_desc_pcmd { 1318 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1, 1319 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2, 1320 }; 1321 1322 #define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT) 1323 #define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT) 1324 1325 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT) 1326 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT) 1327 1328 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \ 1329 I40E_TXD_FLTR_QW1_CMD_SHIFT) 1330 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \ 1331 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) 1332 1333 #define I40E_TXD_FLTR_QW1_ATR_SHIFT (0xEULL + \ 1334 I40E_TXD_FLTR_QW1_CMD_SHIFT) 1335 #define I40E_TXD_FLTR_QW1_ATR_MASK BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT) 1336 1337 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20 1338 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \ 1339 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) 1340 1341 enum i40e_filter_type { 1342 I40E_FLOW_DIRECTOR_FLTR = 0, 1343 I40E_PE_QUAD_HASH_FLTR = 1, 1344 I40E_ETHERTYPE_FLTR, 1345 I40E_FCOE_CTX_FLTR, 1346 I40E_MAC_VLAN_FLTR, 1347 I40E_HASH_FLTR 1348 }; 1349 1350 struct i40e_vsi_context { 1351 u16 seid; 1352 u16 uplink_seid; 1353 u16 vsi_number; 1354 u16 vsis_allocated; 1355 u16 vsis_unallocated; 1356 u16 flags; 1357 u8 pf_num; 1358 u8 vf_num; 1359 u8 connection_type; 1360 struct i40e_aqc_vsi_properties_data info; 1361 }; 1362 1363 struct i40e_veb_context { 1364 u16 seid; 1365 u16 uplink_seid; 1366 u16 veb_number; 1367 u16 vebs_allocated; 1368 u16 vebs_unallocated; 1369 u16 flags; 1370 struct i40e_aqc_get_veb_parameters_completion info; 1371 }; 1372 1373 /* Statistics collected by each port, VSI, VEB, and S-channel */ 1374 struct i40e_eth_stats { 1375 u64 rx_bytes; /* gorc */ 1376 u64 rx_unicast; /* uprc */ 1377 u64 rx_multicast; /* mprc */ 1378 u64 rx_broadcast; /* bprc */ 1379 u64 rx_discards; /* rdpc */ 1380 u64 rx_unknown_protocol; /* rupp */ 1381 u64 tx_bytes; /* gotc */ 1382 u64 tx_unicast; /* uptc */ 1383 u64 tx_multicast; /* mptc */ 1384 u64 tx_broadcast; /* bptc */ 1385 u64 tx_discards; /* tdpc */ 1386 u64 tx_errors; /* tepc */ 1387 }; 1388 1389 /* Statistics collected per VEB per TC */ 1390 struct i40e_veb_tc_stats { 1391 u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS]; 1392 u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS]; 1393 u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS]; 1394 u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS]; 1395 }; 1396 1397 /* Statistics collected by the MAC */ 1398 struct i40e_hw_port_stats { 1399 /* eth stats collected by the port */ 1400 struct i40e_eth_stats eth; 1401 1402 /* additional port specific stats */ 1403 u64 tx_dropped_link_down; /* tdold */ 1404 u64 crc_errors; /* crcerrs */ 1405 u64 illegal_bytes; /* illerrc */ 1406 u64 error_bytes; /* errbc */ 1407 u64 mac_local_faults; /* mlfc */ 1408 u64 mac_remote_faults; /* mrfc */ 1409 u64 rx_length_errors; /* rlec */ 1410 u64 link_xon_rx; /* lxonrxc */ 1411 u64 link_xoff_rx; /* lxoffrxc */ 1412 u64 priority_xon_rx[8]; /* pxonrxc[8] */ 1413 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */ 1414 u64 link_xon_tx; /* lxontxc */ 1415 u64 link_xoff_tx; /* lxofftxc */ 1416 u64 priority_xon_tx[8]; /* pxontxc[8] */ 1417 u64 priority_xoff_tx[8]; /* pxofftxc[8] */ 1418 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */ 1419 u64 rx_size_64; /* prc64 */ 1420 u64 rx_size_127; /* prc127 */ 1421 u64 rx_size_255; /* prc255 */ 1422 u64 rx_size_511; /* prc511 */ 1423 u64 rx_size_1023; /* prc1023 */ 1424 u64 rx_size_1522; /* prc1522 */ 1425 u64 rx_size_big; /* prc9522 */ 1426 u64 rx_undersize; /* ruc */ 1427 u64 rx_fragments; /* rfc */ 1428 u64 rx_oversize; /* roc */ 1429 u64 rx_jabber; /* rjc */ 1430 u64 tx_size_64; /* ptc64 */ 1431 u64 tx_size_127; /* ptc127 */ 1432 u64 tx_size_255; /* ptc255 */ 1433 u64 tx_size_511; /* ptc511 */ 1434 u64 tx_size_1023; /* ptc1023 */ 1435 u64 tx_size_1522; /* ptc1522 */ 1436 u64 tx_size_big; /* ptc9522 */ 1437 u64 mac_short_packet_dropped; /* mspdc */ 1438 u64 checksum_error; /* xec */ 1439 /* flow director stats */ 1440 u64 fd_atr_match; 1441 u64 fd_sb_match; 1442 u64 fd_atr_tunnel_match; 1443 u32 fd_atr_status; 1444 u32 fd_sb_status; 1445 /* EEE LPI */ 1446 u32 tx_lpi_status; 1447 u32 rx_lpi_status; 1448 u64 tx_lpi_count; /* etlpic */ 1449 u64 rx_lpi_count; /* erlpic */ 1450 }; 1451 1452 /* Checksum and Shadow RAM pointers */ 1453 #define I40E_SR_NVM_CONTROL_WORD 0x00 1454 #define I40E_SR_PCIE_ANALOG_CONFIG_PTR 0x03 1455 #define I40E_SR_PHY_ANALOG_CONFIG_PTR 0x04 1456 #define I40E_SR_OPTION_ROM_PTR 0x05 1457 #define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06 1458 #define I40E_SR_AUTO_GENERATED_POINTERS_PTR 0x07 1459 #define I40E_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08 1460 #define I40E_SR_EMP_GLOBAL_MODULE_PTR 0x09 1461 #define I40E_SR_RO_PCIE_LCB_PTR 0x0A 1462 #define I40E_SR_EMP_IMAGE_PTR 0x0B 1463 #define I40E_SR_PE_IMAGE_PTR 0x0C 1464 #define I40E_SR_CSR_PROTECTED_LIST_PTR 0x0D 1465 #define I40E_SR_MNG_CONFIG_PTR 0x0E 1466 #define I40E_EMP_MODULE_PTR 0x0F 1467 #define I40E_SR_EMP_MODULE_PTR 0x48 1468 #define I40E_SR_PBA_FLAGS 0x15 1469 #define I40E_SR_PBA_BLOCK_PTR 0x16 1470 #define I40E_SR_BOOT_CONFIG_PTR 0x17 1471 #define I40E_NVM_OEM_VER_OFF 0x83 1472 #define I40E_SR_NVM_DEV_STARTER_VERSION 0x18 1473 #define I40E_SR_NVM_WAKE_ON_LAN 0x19 1474 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27 1475 #define I40E_SR_PERMANENT_SAN_MAC_ADDRESS_PTR 0x28 1476 #define I40E_SR_NVM_MAP_VERSION 0x29 1477 #define I40E_SR_NVM_IMAGE_VERSION 0x2A 1478 #define I40E_SR_NVM_STRUCTURE_VERSION 0x2B 1479 #define I40E_SR_NVM_EETRACK_LO 0x2D 1480 #define I40E_SR_NVM_EETRACK_HI 0x2E 1481 #define I40E_SR_VPD_PTR 0x2F 1482 #define I40E_SR_PXE_SETUP_PTR 0x30 1483 #define I40E_SR_PXE_CONFIG_CUST_OPTIONS_PTR 0x31 1484 #define I40E_SR_NVM_ORIGINAL_EETRACK_LO 0x34 1485 #define I40E_SR_NVM_ORIGINAL_EETRACK_HI 0x35 1486 #define I40E_SR_SW_ETHERNET_MAC_ADDRESS_PTR 0x37 1487 #define I40E_SR_POR_REGS_AUTO_LOAD_PTR 0x38 1488 #define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A 1489 #define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B 1490 #define I40E_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C 1491 #define I40E_SR_PHY_ACTIVITY_LIST_PTR 0x3D 1492 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E 1493 #define I40E_SR_SW_CHECKSUM_WORD 0x3F 1494 #define I40E_SR_1ST_FREE_PROVISION_AREA_PTR 0x40 1495 #define I40E_SR_4TH_FREE_PROVISION_AREA_PTR 0x42 1496 #define I40E_SR_3RD_FREE_PROVISION_AREA_PTR 0x44 1497 #define I40E_SR_2ND_FREE_PROVISION_AREA_PTR 0x46 1498 #define I40E_SR_EMP_SR_SETTINGS_PTR 0x48 1499 #define I40E_SR_FEATURE_CONFIGURATION_PTR 0x49 1500 #define I40E_SR_CONFIGURATION_METADATA_PTR 0x4D 1501 #define I40E_SR_IMMEDIATE_VALUES_PTR 0x4E 1502 1503 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */ 1504 #define I40E_SR_VPD_MODULE_MAX_SIZE 1024 1505 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024 1506 #define I40E_SR_CONTROL_WORD_1_SHIFT 0x06 1507 #define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT) 1508 #define I40E_SR_CONTROL_WORD_1_NVM_BANK_VALID BIT(5) 1509 #define I40E_SR_NVM_MAP_STRUCTURE_TYPE BIT(12) 1510 #define I40E_PTR_TYPE BIT(15) 1511 #define I40E_SR_OCP_CFG_WORD0 0x2B 1512 #define I40E_SR_OCP_ENABLED BIT(15) 1513 1514 /* Shadow RAM related */ 1515 #define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800 1516 #define I40E_SR_BUF_ALIGNMENT 4096 1517 #define I40E_SR_WORDS_IN_1KB 512 1518 /* Checksum should be calculated such that after adding all the words, 1519 * including the checksum word itself, the sum should be 0xBABA. 1520 */ 1521 #define I40E_SR_SW_CHECKSUM_BASE 0xBABA 1522 1523 #define I40E_SRRD_SRCTL_ATTEMPTS 100000 1524 1525 enum i40e_switch_element_types { 1526 I40E_SWITCH_ELEMENT_TYPE_MAC = 1, 1527 I40E_SWITCH_ELEMENT_TYPE_PF = 2, 1528 I40E_SWITCH_ELEMENT_TYPE_VF = 3, 1529 I40E_SWITCH_ELEMENT_TYPE_EMP = 4, 1530 I40E_SWITCH_ELEMENT_TYPE_BMC = 6, 1531 I40E_SWITCH_ELEMENT_TYPE_PE = 16, 1532 I40E_SWITCH_ELEMENT_TYPE_VEB = 17, 1533 I40E_SWITCH_ELEMENT_TYPE_PA = 18, 1534 I40E_SWITCH_ELEMENT_TYPE_VSI = 19, 1535 }; 1536 1537 /* Supported EtherType filters */ 1538 enum i40e_ether_type_index { 1539 I40E_ETHER_TYPE_1588 = 0, 1540 I40E_ETHER_TYPE_FIP = 1, 1541 I40E_ETHER_TYPE_OUI_EXTENDED = 2, 1542 I40E_ETHER_TYPE_MAC_CONTROL = 3, 1543 I40E_ETHER_TYPE_LLDP = 4, 1544 I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5, 1545 I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6, 1546 I40E_ETHER_TYPE_QCN_CNM = 7, 1547 I40E_ETHER_TYPE_8021X = 8, 1548 I40E_ETHER_TYPE_ARP = 9, 1549 I40E_ETHER_TYPE_RSV1 = 10, 1550 I40E_ETHER_TYPE_RSV2 = 11, 1551 }; 1552 1553 /* Filter context base size is 1K */ 1554 #define I40E_HASH_FILTER_BASE_SIZE 1024 1555 /* Supported Hash filter values */ 1556 enum i40e_hash_filter_size { 1557 I40E_HASH_FILTER_SIZE_1K = 0, 1558 I40E_HASH_FILTER_SIZE_2K = 1, 1559 I40E_HASH_FILTER_SIZE_4K = 2, 1560 I40E_HASH_FILTER_SIZE_8K = 3, 1561 I40E_HASH_FILTER_SIZE_16K = 4, 1562 I40E_HASH_FILTER_SIZE_32K = 5, 1563 I40E_HASH_FILTER_SIZE_64K = 6, 1564 I40E_HASH_FILTER_SIZE_128K = 7, 1565 I40E_HASH_FILTER_SIZE_256K = 8, 1566 I40E_HASH_FILTER_SIZE_512K = 9, 1567 I40E_HASH_FILTER_SIZE_1M = 10, 1568 }; 1569 1570 /* DMA context base size is 0.5K */ 1571 #define I40E_DMA_CNTX_BASE_SIZE 512 1572 /* Supported DMA context values */ 1573 enum i40e_dma_cntx_size { 1574 I40E_DMA_CNTX_SIZE_512 = 0, 1575 I40E_DMA_CNTX_SIZE_1K = 1, 1576 I40E_DMA_CNTX_SIZE_2K = 2, 1577 I40E_DMA_CNTX_SIZE_4K = 3, 1578 I40E_DMA_CNTX_SIZE_8K = 4, 1579 I40E_DMA_CNTX_SIZE_16K = 5, 1580 I40E_DMA_CNTX_SIZE_32K = 6, 1581 I40E_DMA_CNTX_SIZE_64K = 7, 1582 I40E_DMA_CNTX_SIZE_128K = 8, 1583 I40E_DMA_CNTX_SIZE_256K = 9, 1584 }; 1585 1586 /* Supported Hash look up table (LUT) sizes */ 1587 enum i40e_hash_lut_size { 1588 I40E_HASH_LUT_SIZE_128 = 0, 1589 I40E_HASH_LUT_SIZE_512 = 1, 1590 }; 1591 1592 /* Structure to hold a per PF filter control settings */ 1593 struct i40e_filter_control_settings { 1594 /* number of PE Quad Hash filter buckets */ 1595 enum i40e_hash_filter_size pe_filt_num; 1596 /* number of PE Quad Hash contexts */ 1597 enum i40e_dma_cntx_size pe_cntx_num; 1598 /* number of FCoE filter buckets */ 1599 enum i40e_hash_filter_size fcoe_filt_num; 1600 /* number of FCoE DDP contexts */ 1601 enum i40e_dma_cntx_size fcoe_cntx_num; 1602 /* size of the Hash LUT */ 1603 enum i40e_hash_lut_size hash_lut_size; 1604 /* enable FDIR filters for PF and its VFs */ 1605 bool enable_fdir; 1606 /* enable Ethertype filters for PF and its VFs */ 1607 bool enable_ethtype; 1608 /* enable MAC/VLAN filters for PF and its VFs */ 1609 bool enable_macvlan; 1610 }; 1611 1612 /* Structure to hold device level control filter counts */ 1613 struct i40e_control_filter_stats { 1614 u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */ 1615 u16 etype_used; /* Used perfect EtherType filters */ 1616 u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */ 1617 u16 etype_free; /* Un-used perfect EtherType filters */ 1618 }; 1619 1620 enum i40e_reset_type { 1621 I40E_RESET_POR = 0, 1622 I40E_RESET_CORER = 1, 1623 I40E_RESET_GLOBR = 2, 1624 I40E_RESET_EMPR = 3, 1625 }; 1626 1627 /* IEEE 802.1AB LLDP Agent Variables from NVM */ 1628 #define I40E_NVM_LLDP_CFG_PTR 0x06 1629 #define I40E_SR_LLDP_CFG_PTR 0x31 1630 struct i40e_lldp_variables { 1631 u16 length; 1632 u16 adminstatus; 1633 u16 msgfasttx; 1634 u16 msgtxinterval; 1635 u16 txparams; 1636 u16 timers; 1637 u16 crc8; 1638 }; 1639 1640 /* Offsets into Alternate Ram */ 1641 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET 0 /* in dwords */ 1642 #define I40E_ALT_STRUCT_DWORDS_PER_PF 64 /* in dwords */ 1643 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET 0xD /* in dwords */ 1644 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET 0xC /* in dwords */ 1645 #define I40E_ALT_STRUCT_MIN_BW_OFFSET 0xE /* in dwords */ 1646 #define I40E_ALT_STRUCT_MAX_BW_OFFSET 0xF /* in dwords */ 1647 1648 /* Alternate Ram Bandwidth Masks */ 1649 #define I40E_ALT_BW_VALUE_MASK 0xFF 1650 #define I40E_ALT_BW_RELATIVE_MASK 0x40000000 1651 #define I40E_ALT_BW_VALID_MASK 0x80000000 1652 1653 /* RSS Hash Table Size */ 1654 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000 1655 1656 /* INPUT SET MASK for RSS, flow director, and flexible payload */ 1657 #define I40E_L3_SRC_SHIFT 47 1658 #define I40E_L3_SRC_MASK (0x3ULL << I40E_L3_SRC_SHIFT) 1659 #define I40E_L3_V6_SRC_SHIFT 43 1660 #define I40E_L3_V6_SRC_MASK (0xFFULL << I40E_L3_V6_SRC_SHIFT) 1661 #define I40E_L3_DST_SHIFT 35 1662 #define I40E_L3_DST_MASK (0x3ULL << I40E_L3_DST_SHIFT) 1663 #define I40E_L3_V6_DST_SHIFT 35 1664 #define I40E_L3_V6_DST_MASK (0xFFULL << I40E_L3_V6_DST_SHIFT) 1665 #define I40E_L4_SRC_SHIFT 34 1666 #define I40E_L4_SRC_MASK (0x1ULL << I40E_L4_SRC_SHIFT) 1667 #define I40E_L4_DST_SHIFT 33 1668 #define I40E_L4_DST_MASK (0x1ULL << I40E_L4_DST_SHIFT) 1669 #define I40E_VERIFY_TAG_SHIFT 31 1670 #define I40E_VERIFY_TAG_MASK (0x3ULL << I40E_VERIFY_TAG_SHIFT) 1671 1672 #define I40E_FLEX_50_SHIFT 13 1673 #define I40E_FLEX_50_MASK (0x1ULL << I40E_FLEX_50_SHIFT) 1674 #define I40E_FLEX_51_SHIFT 12 1675 #define I40E_FLEX_51_MASK (0x1ULL << I40E_FLEX_51_SHIFT) 1676 #define I40E_FLEX_52_SHIFT 11 1677 #define I40E_FLEX_52_MASK (0x1ULL << I40E_FLEX_52_SHIFT) 1678 #define I40E_FLEX_53_SHIFT 10 1679 #define I40E_FLEX_53_MASK (0x1ULL << I40E_FLEX_53_SHIFT) 1680 #define I40E_FLEX_54_SHIFT 9 1681 #define I40E_FLEX_54_MASK (0x1ULL << I40E_FLEX_54_SHIFT) 1682 #define I40E_FLEX_55_SHIFT 8 1683 #define I40E_FLEX_55_MASK (0x1ULL << I40E_FLEX_55_SHIFT) 1684 #define I40E_FLEX_56_SHIFT 7 1685 #define I40E_FLEX_56_MASK (0x1ULL << I40E_FLEX_56_SHIFT) 1686 #define I40E_FLEX_57_SHIFT 6 1687 #define I40E_FLEX_57_MASK (0x1ULL << I40E_FLEX_57_SHIFT) 1688 #endif /* _I40E_TYPE_H_ */ 1689