1 /****************************************************************************** 2 3 Copyright (c) 2013-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD: head/sys/dev/ixl/i40e_common.c 284049 2015-06-05 22:52:42Z jfv $*/ 34 35 #include "i40e_type.h" 36 #include "i40e_adminq.h" 37 #include "i40e_prototype.h" 38 #include "i40e_virtchnl.h" 39 40 41 /** 42 * i40e_set_mac_type - Sets MAC type 43 * @hw: pointer to the HW structure 44 * 45 * This function sets the mac type of the adapter based on the 46 * vendor ID and device ID stored in the hw structure. 47 **/ 48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw) 49 { 50 enum i40e_status_code status = I40E_SUCCESS; 51 52 DEBUGFUNC("i40e_set_mac_type\n"); 53 54 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) { 55 switch (hw->device_id) { 56 case I40E_DEV_ID_SFP_XL710: 57 case I40E_DEV_ID_QEMU: 58 case I40E_DEV_ID_KX_A: 59 case I40E_DEV_ID_KX_B: 60 case I40E_DEV_ID_KX_C: 61 case I40E_DEV_ID_QSFP_A: 62 case I40E_DEV_ID_QSFP_B: 63 case I40E_DEV_ID_QSFP_C: 64 case I40E_DEV_ID_10G_BASE_T: 65 case I40E_DEV_ID_10G_BASE_T4: 66 case I40E_DEV_ID_20G_KR2: 67 case I40E_DEV_ID_20G_KR2_A: 68 hw->mac.type = I40E_MAC_XL710; 69 break; 70 #ifdef X722_SUPPORT 71 case I40E_DEV_ID_SFP_X722: 72 case I40E_DEV_ID_1G_BASE_T_X722: 73 case I40E_DEV_ID_10G_BASE_T_X722: 74 hw->mac.type = I40E_MAC_X722; 75 break; 76 #endif 77 #ifdef X722_SUPPORT 78 case I40E_DEV_ID_X722_VF: 79 case I40E_DEV_ID_X722_VF_HV: 80 hw->mac.type = I40E_MAC_X722_VF; 81 break; 82 #endif 83 case I40E_DEV_ID_VF: 84 case I40E_DEV_ID_VF_HV: 85 hw->mac.type = I40E_MAC_VF; 86 break; 87 default: 88 hw->mac.type = I40E_MAC_GENERIC; 89 break; 90 } 91 } else { 92 status = I40E_ERR_DEVICE_NOT_SUPPORTED; 93 } 94 95 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n", 96 hw->mac.type, status); 97 return status; 98 } 99 100 /** 101 * i40e_aq_str - convert AQ err code to a string 102 * @hw: pointer to the HW structure 103 * @aq_err: the AQ error code to convert 104 **/ 105 char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err) 106 { 107 switch (aq_err) { 108 case I40E_AQ_RC_OK: 109 return "OK"; 110 case I40E_AQ_RC_EPERM: 111 return "I40E_AQ_RC_EPERM"; 112 case I40E_AQ_RC_ENOENT: 113 return "I40E_AQ_RC_ENOENT"; 114 case I40E_AQ_RC_ESRCH: 115 return "I40E_AQ_RC_ESRCH"; 116 case I40E_AQ_RC_EINTR: 117 return "I40E_AQ_RC_EINTR"; 118 case I40E_AQ_RC_EIO: 119 return "I40E_AQ_RC_EIO"; 120 case I40E_AQ_RC_ENXIO: 121 return "I40E_AQ_RC_ENXIO"; 122 case I40E_AQ_RC_E2BIG: 123 return "I40E_AQ_RC_E2BIG"; 124 case I40E_AQ_RC_EAGAIN: 125 return "I40E_AQ_RC_EAGAIN"; 126 case I40E_AQ_RC_ENOMEM: 127 return "I40E_AQ_RC_ENOMEM"; 128 case I40E_AQ_RC_EACCES: 129 return "I40E_AQ_RC_EACCES"; 130 case I40E_AQ_RC_EFAULT: 131 return "I40E_AQ_RC_EFAULT"; 132 case I40E_AQ_RC_EBUSY: 133 return "I40E_AQ_RC_EBUSY"; 134 case I40E_AQ_RC_EEXIST: 135 return "I40E_AQ_RC_EEXIST"; 136 case I40E_AQ_RC_EINVAL: 137 return "I40E_AQ_RC_EINVAL"; 138 case I40E_AQ_RC_ENOTTY: 139 return "I40E_AQ_RC_ENOTTY"; 140 case I40E_AQ_RC_ENOSPC: 141 return "I40E_AQ_RC_ENOSPC"; 142 case I40E_AQ_RC_ENOSYS: 143 return "I40E_AQ_RC_ENOSYS"; 144 case I40E_AQ_RC_ERANGE: 145 return "I40E_AQ_RC_ERANGE"; 146 case I40E_AQ_RC_EFLUSHED: 147 return "I40E_AQ_RC_EFLUSHED"; 148 case I40E_AQ_RC_BAD_ADDR: 149 return "I40E_AQ_RC_BAD_ADDR"; 150 case I40E_AQ_RC_EMODE: 151 return "I40E_AQ_RC_EMODE"; 152 case I40E_AQ_RC_EFBIG: 153 return "I40E_AQ_RC_EFBIG"; 154 } 155 156 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err); 157 return hw->err_str; 158 } 159 160 /** 161 * i40e_stat_str - convert status err code to a string 162 * @hw: pointer to the HW structure 163 * @stat_err: the status error code to convert 164 **/ 165 char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err) 166 { 167 switch (stat_err) { 168 case I40E_SUCCESS: 169 return "OK"; 170 case I40E_ERR_NVM: 171 return "I40E_ERR_NVM"; 172 case I40E_ERR_NVM_CHECKSUM: 173 return "I40E_ERR_NVM_CHECKSUM"; 174 case I40E_ERR_PHY: 175 return "I40E_ERR_PHY"; 176 case I40E_ERR_CONFIG: 177 return "I40E_ERR_CONFIG"; 178 case I40E_ERR_PARAM: 179 return "I40E_ERR_PARAM"; 180 case I40E_ERR_MAC_TYPE: 181 return "I40E_ERR_MAC_TYPE"; 182 case I40E_ERR_UNKNOWN_PHY: 183 return "I40E_ERR_UNKNOWN_PHY"; 184 case I40E_ERR_LINK_SETUP: 185 return "I40E_ERR_LINK_SETUP"; 186 case I40E_ERR_ADAPTER_STOPPED: 187 return "I40E_ERR_ADAPTER_STOPPED"; 188 case I40E_ERR_INVALID_MAC_ADDR: 189 return "I40E_ERR_INVALID_MAC_ADDR"; 190 case I40E_ERR_DEVICE_NOT_SUPPORTED: 191 return "I40E_ERR_DEVICE_NOT_SUPPORTED"; 192 case I40E_ERR_MASTER_REQUESTS_PENDING: 193 return "I40E_ERR_MASTER_REQUESTS_PENDING"; 194 case I40E_ERR_INVALID_LINK_SETTINGS: 195 return "I40E_ERR_INVALID_LINK_SETTINGS"; 196 case I40E_ERR_AUTONEG_NOT_COMPLETE: 197 return "I40E_ERR_AUTONEG_NOT_COMPLETE"; 198 case I40E_ERR_RESET_FAILED: 199 return "I40E_ERR_RESET_FAILED"; 200 case I40E_ERR_SWFW_SYNC: 201 return "I40E_ERR_SWFW_SYNC"; 202 case I40E_ERR_NO_AVAILABLE_VSI: 203 return "I40E_ERR_NO_AVAILABLE_VSI"; 204 case I40E_ERR_NO_MEMORY: 205 return "I40E_ERR_NO_MEMORY"; 206 case I40E_ERR_BAD_PTR: 207 return "I40E_ERR_BAD_PTR"; 208 case I40E_ERR_RING_FULL: 209 return "I40E_ERR_RING_FULL"; 210 case I40E_ERR_INVALID_PD_ID: 211 return "I40E_ERR_INVALID_PD_ID"; 212 case I40E_ERR_INVALID_QP_ID: 213 return "I40E_ERR_INVALID_QP_ID"; 214 case I40E_ERR_INVALID_CQ_ID: 215 return "I40E_ERR_INVALID_CQ_ID"; 216 case I40E_ERR_INVALID_CEQ_ID: 217 return "I40E_ERR_INVALID_CEQ_ID"; 218 case I40E_ERR_INVALID_AEQ_ID: 219 return "I40E_ERR_INVALID_AEQ_ID"; 220 case I40E_ERR_INVALID_SIZE: 221 return "I40E_ERR_INVALID_SIZE"; 222 case I40E_ERR_INVALID_ARP_INDEX: 223 return "I40E_ERR_INVALID_ARP_INDEX"; 224 case I40E_ERR_INVALID_FPM_FUNC_ID: 225 return "I40E_ERR_INVALID_FPM_FUNC_ID"; 226 case I40E_ERR_QP_INVALID_MSG_SIZE: 227 return "I40E_ERR_QP_INVALID_MSG_SIZE"; 228 case I40E_ERR_QP_TOOMANY_WRS_POSTED: 229 return "I40E_ERR_QP_TOOMANY_WRS_POSTED"; 230 case I40E_ERR_INVALID_FRAG_COUNT: 231 return "I40E_ERR_INVALID_FRAG_COUNT"; 232 case I40E_ERR_QUEUE_EMPTY: 233 return "I40E_ERR_QUEUE_EMPTY"; 234 case I40E_ERR_INVALID_ALIGNMENT: 235 return "I40E_ERR_INVALID_ALIGNMENT"; 236 case I40E_ERR_FLUSHED_QUEUE: 237 return "I40E_ERR_FLUSHED_QUEUE"; 238 case I40E_ERR_INVALID_PUSH_PAGE_INDEX: 239 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX"; 240 case I40E_ERR_INVALID_IMM_DATA_SIZE: 241 return "I40E_ERR_INVALID_IMM_DATA_SIZE"; 242 case I40E_ERR_TIMEOUT: 243 return "I40E_ERR_TIMEOUT"; 244 case I40E_ERR_OPCODE_MISMATCH: 245 return "I40E_ERR_OPCODE_MISMATCH"; 246 case I40E_ERR_CQP_COMPL_ERROR: 247 return "I40E_ERR_CQP_COMPL_ERROR"; 248 case I40E_ERR_INVALID_VF_ID: 249 return "I40E_ERR_INVALID_VF_ID"; 250 case I40E_ERR_INVALID_HMCFN_ID: 251 return "I40E_ERR_INVALID_HMCFN_ID"; 252 case I40E_ERR_BACKING_PAGE_ERROR: 253 return "I40E_ERR_BACKING_PAGE_ERROR"; 254 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE: 255 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE"; 256 case I40E_ERR_INVALID_PBLE_INDEX: 257 return "I40E_ERR_INVALID_PBLE_INDEX"; 258 case I40E_ERR_INVALID_SD_INDEX: 259 return "I40E_ERR_INVALID_SD_INDEX"; 260 case I40E_ERR_INVALID_PAGE_DESC_INDEX: 261 return "I40E_ERR_INVALID_PAGE_DESC_INDEX"; 262 case I40E_ERR_INVALID_SD_TYPE: 263 return "I40E_ERR_INVALID_SD_TYPE"; 264 case I40E_ERR_MEMCPY_FAILED: 265 return "I40E_ERR_MEMCPY_FAILED"; 266 case I40E_ERR_INVALID_HMC_OBJ_INDEX: 267 return "I40E_ERR_INVALID_HMC_OBJ_INDEX"; 268 case I40E_ERR_INVALID_HMC_OBJ_COUNT: 269 return "I40E_ERR_INVALID_HMC_OBJ_COUNT"; 270 case I40E_ERR_INVALID_SRQ_ARM_LIMIT: 271 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT"; 272 case I40E_ERR_SRQ_ENABLED: 273 return "I40E_ERR_SRQ_ENABLED"; 274 case I40E_ERR_ADMIN_QUEUE_ERROR: 275 return "I40E_ERR_ADMIN_QUEUE_ERROR"; 276 case I40E_ERR_ADMIN_QUEUE_TIMEOUT: 277 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT"; 278 case I40E_ERR_BUF_TOO_SHORT: 279 return "I40E_ERR_BUF_TOO_SHORT"; 280 case I40E_ERR_ADMIN_QUEUE_FULL: 281 return "I40E_ERR_ADMIN_QUEUE_FULL"; 282 case I40E_ERR_ADMIN_QUEUE_NO_WORK: 283 return "I40E_ERR_ADMIN_QUEUE_NO_WORK"; 284 case I40E_ERR_BAD_IWARP_CQE: 285 return "I40E_ERR_BAD_IWARP_CQE"; 286 case I40E_ERR_NVM_BLANK_MODE: 287 return "I40E_ERR_NVM_BLANK_MODE"; 288 case I40E_ERR_NOT_IMPLEMENTED: 289 return "I40E_ERR_NOT_IMPLEMENTED"; 290 case I40E_ERR_PE_DOORBELL_NOT_ENABLED: 291 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED"; 292 case I40E_ERR_DIAG_TEST_FAILED: 293 return "I40E_ERR_DIAG_TEST_FAILED"; 294 case I40E_ERR_NOT_READY: 295 return "I40E_ERR_NOT_READY"; 296 case I40E_NOT_SUPPORTED: 297 return "I40E_NOT_SUPPORTED"; 298 case I40E_ERR_FIRMWARE_API_VERSION: 299 return "I40E_ERR_FIRMWARE_API_VERSION"; 300 } 301 302 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err); 303 return hw->err_str; 304 } 305 306 /** 307 * i40e_debug_aq 308 * @hw: debug mask related to admin queue 309 * @mask: debug mask 310 * @desc: pointer to admin queue descriptor 311 * @buffer: pointer to command buffer 312 * @buf_len: max length of buffer 313 * 314 * Dumps debug log about adminq command with descriptor contents. 315 **/ 316 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc, 317 void *buffer, u16 buf_len) 318 { 319 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc; 320 u16 len = LE16_TO_CPU(aq_desc->datalen); 321 u8 *buf = (u8 *)buffer; 322 u16 i = 0; 323 324 if ((!(mask & hw->debug_mask)) || (desc == NULL)) 325 return; 326 327 i40e_debug(hw, mask, 328 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n", 329 LE16_TO_CPU(aq_desc->opcode), 330 LE16_TO_CPU(aq_desc->flags), 331 LE16_TO_CPU(aq_desc->datalen), 332 LE16_TO_CPU(aq_desc->retval)); 333 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n", 334 LE32_TO_CPU(aq_desc->cookie_high), 335 LE32_TO_CPU(aq_desc->cookie_low)); 336 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n", 337 LE32_TO_CPU(aq_desc->params.internal.param0), 338 LE32_TO_CPU(aq_desc->params.internal.param1)); 339 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n", 340 LE32_TO_CPU(aq_desc->params.external.addr_high), 341 LE32_TO_CPU(aq_desc->params.external.addr_low)); 342 343 if ((buffer != NULL) && (aq_desc->datalen != 0)) { 344 i40e_debug(hw, mask, "AQ CMD Buffer:\n"); 345 if (buf_len < len) 346 len = buf_len; 347 /* write the full 16-byte chunks */ 348 for (i = 0; i < (len - 16); i += 16) 349 i40e_debug(hw, mask, 350 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n", 351 i, buf[i], buf[i+1], buf[i+2], buf[i+3], 352 buf[i+4], buf[i+5], buf[i+6], buf[i+7], 353 buf[i+8], buf[i+9], buf[i+10], buf[i+11], 354 buf[i+12], buf[i+13], buf[i+14], buf[i+15]); 355 /* write whatever's left over without overrunning the buffer */ 356 if (i < len) { 357 char d_buf[80]; 358 int j = 0; 359 360 memset(d_buf, 0, sizeof(d_buf)); 361 #ifdef I40E_ILLUMOS 362 /* 363 * Sigh. 364 * 365 * The illumos DDI (inherited from OpenSolaris) says 366 * sprintf() returns the pointer to its first 367 * argument, NOT the length of bytes printed. A better 368 * solution would be to have the kernel provide 369 * something like real_sprintf() but for now, we 370 * hack around it. 371 */ 372 (void) sprintf(d_buf, "\t0x%04X ", i); 373 j += strlen(d_buf); 374 /* Bounds-check at 77, because " XX" emits 4 chars. */ 375 while (i < len && j < 77) { 376 (void) sprintf(&d_buf[j], " %02X", buf[i++]); 377 j += strlen(&d_buf[j]); 378 } 379 #else 380 j += sprintf(d_buf, "\t0x%04X ", i); 381 while (i < len) 382 j += sprintf(&d_buf[j], " %02X", buf[i++]); 383 #endif 384 i40e_debug(hw, mask, "%s\n", d_buf); 385 } 386 } 387 } 388 389 /** 390 * i40e_check_asq_alive 391 * @hw: pointer to the hw struct 392 * 393 * Returns TRUE if Queue is enabled else FALSE. 394 **/ 395 bool i40e_check_asq_alive(struct i40e_hw *hw) 396 { 397 if (hw->aq.asq.len) 398 if (!i40e_is_vf(hw)) 399 return !!(rd32(hw, hw->aq.asq.len) & 400 I40E_PF_ATQLEN_ATQENABLE_MASK); 401 if (i40e_is_vf(hw)) 402 return !!(rd32(hw, hw->aq.asq.len) & 403 I40E_VF_ATQLEN1_ATQENABLE_MASK); 404 return FALSE; 405 } 406 407 /** 408 * i40e_aq_queue_shutdown 409 * @hw: pointer to the hw struct 410 * @unloading: is the driver unloading itself 411 * 412 * Tell the Firmware that we're shutting down the AdminQ and whether 413 * or not the driver is unloading as well. 414 **/ 415 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw, 416 bool unloading) 417 { 418 struct i40e_aq_desc desc; 419 struct i40e_aqc_queue_shutdown *cmd = 420 (struct i40e_aqc_queue_shutdown *)&desc.params.raw; 421 enum i40e_status_code status; 422 423 i40e_fill_default_direct_cmd_desc(&desc, 424 i40e_aqc_opc_queue_shutdown); 425 426 if (unloading) 427 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING); 428 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 429 430 return status; 431 } 432 #ifdef X722_SUPPORT 433 434 /** 435 * i40e_aq_get_set_rss_lut 436 * @hw: pointer to the hardware structure 437 * @vsi_id: vsi fw index 438 * @pf_lut: for PF table set TRUE, for VSI table set FALSE 439 * @lut: pointer to the lut buffer provided by the caller 440 * @lut_size: size of the lut buffer 441 * @set: set TRUE to set the table, FALSE to get the table 442 * 443 * Internal function to get or set RSS look up table 444 **/ 445 static enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw, 446 u16 vsi_id, bool pf_lut, 447 u8 *lut, u16 lut_size, 448 bool set) 449 { 450 enum i40e_status_code status; 451 struct i40e_aq_desc desc; 452 struct i40e_aqc_get_set_rss_lut *cmd_resp = 453 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw; 454 455 if (set) 456 i40e_fill_default_direct_cmd_desc(&desc, 457 i40e_aqc_opc_set_rss_lut); 458 else 459 i40e_fill_default_direct_cmd_desc(&desc, 460 i40e_aqc_opc_get_rss_lut); 461 462 /* Indirect command */ 463 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 464 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 465 466 cmd_resp->vsi_id = 467 CPU_TO_LE16((u16)((vsi_id << 468 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) & 469 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK)); 470 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID); 471 472 if (pf_lut) 473 cmd_resp->flags |= CPU_TO_LE16((u16) 474 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF << 475 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) & 476 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK)); 477 else 478 cmd_resp->flags |= CPU_TO_LE16((u16) 479 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI << 480 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) & 481 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK)); 482 483 cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_WORD((u64)lut)); 484 cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)lut)); 485 486 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL); 487 488 return status; 489 } 490 491 /** 492 * i40e_aq_get_rss_lut 493 * @hw: pointer to the hardware structure 494 * @vsi_id: vsi fw index 495 * @pf_lut: for PF table set TRUE, for VSI table set FALSE 496 * @lut: pointer to the lut buffer provided by the caller 497 * @lut_size: size of the lut buffer 498 * 499 * get the RSS lookup table, PF or VSI type 500 **/ 501 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id, 502 bool pf_lut, u8 *lut, u16 lut_size) 503 { 504 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, 505 FALSE); 506 } 507 508 /** 509 * i40e_aq_set_rss_lut 510 * @hw: pointer to the hardware structure 511 * @vsi_id: vsi fw index 512 * @pf_lut: for PF table set TRUE, for VSI table set FALSE 513 * @lut: pointer to the lut buffer provided by the caller 514 * @lut_size: size of the lut buffer 515 * 516 * set the RSS lookup table, PF or VSI type 517 **/ 518 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id, 519 bool pf_lut, u8 *lut, u16 lut_size) 520 { 521 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, TRUE); 522 } 523 524 /** 525 * i40e_aq_get_set_rss_key 526 * @hw: pointer to the hw struct 527 * @vsi_id: vsi fw index 528 * @key: pointer to key info struct 529 * @set: set TRUE to set the key, FALSE to get the key 530 * 531 * get the RSS key per VSI 532 **/ 533 static enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw, 534 u16 vsi_id, 535 struct i40e_aqc_get_set_rss_key_data *key, 536 bool set) 537 { 538 enum i40e_status_code status; 539 struct i40e_aq_desc desc; 540 struct i40e_aqc_get_set_rss_key *cmd_resp = 541 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw; 542 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data); 543 544 if (set) 545 i40e_fill_default_direct_cmd_desc(&desc, 546 i40e_aqc_opc_set_rss_key); 547 else 548 i40e_fill_default_direct_cmd_desc(&desc, 549 i40e_aqc_opc_get_rss_key); 550 551 /* Indirect command */ 552 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 553 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 554 555 cmd_resp->vsi_id = 556 CPU_TO_LE16((u16)((vsi_id << 557 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) & 558 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK)); 559 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID); 560 cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_WORD((u64)key)); 561 cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)key)); 562 563 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL); 564 565 return status; 566 } 567 568 /** 569 * i40e_aq_get_rss_key 570 * @hw: pointer to the hw struct 571 * @vsi_id: vsi fw index 572 * @key: pointer to key info struct 573 * 574 **/ 575 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw, 576 u16 vsi_id, 577 struct i40e_aqc_get_set_rss_key_data *key) 578 { 579 return i40e_aq_get_set_rss_key(hw, vsi_id, key, FALSE); 580 } 581 582 /** 583 * i40e_aq_set_rss_key 584 * @hw: pointer to the hw struct 585 * @vsi_id: vsi fw index 586 * @key: pointer to key info struct 587 * 588 * set the RSS key per VSI 589 **/ 590 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw, 591 u16 vsi_id, 592 struct i40e_aqc_get_set_rss_key_data *key) 593 { 594 return i40e_aq_get_set_rss_key(hw, vsi_id, key, TRUE); 595 } 596 #endif /* X722_SUPPORT */ 597 598 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the 599 * hardware to a bit-field that can be used by SW to more easily determine the 600 * packet type. 601 * 602 * Macros are used to shorten the table lines and make this table human 603 * readable. 604 * 605 * We store the PTYPE in the top byte of the bit field - this is just so that 606 * we can check that the table doesn't have a row missing, as the index into 607 * the table should be the PTYPE. 608 * 609 * Typical work flow: 610 * 611 * IF NOT i40e_ptype_lookup[ptype].known 612 * THEN 613 * Packet is unknown 614 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP 615 * Use the rest of the fields to look at the tunnels, inner protocols, etc 616 * ELSE 617 * Use the enum i40e_rx_l2_ptype to decode the packet type 618 * ENDIF 619 */ 620 621 /* macro to make the table lines short */ 622 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\ 623 { PTYPE, \ 624 1, \ 625 I40E_RX_PTYPE_OUTER_##OUTER_IP, \ 626 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \ 627 I40E_RX_PTYPE_##OUTER_FRAG, \ 628 I40E_RX_PTYPE_TUNNEL_##T, \ 629 I40E_RX_PTYPE_TUNNEL_END_##TE, \ 630 I40E_RX_PTYPE_##TEF, \ 631 I40E_RX_PTYPE_INNER_PROT_##I, \ 632 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL } 633 634 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \ 635 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 636 637 /* shorter macros makes the table fit but are terse */ 638 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG 639 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG 640 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC 641 642 /* Lookup table mapping the HW PTYPE to the bit field for decoding */ 643 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = { 644 /* L2 Packet types */ 645 I40E_PTT_UNUSED_ENTRY(0), 646 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 647 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2), 648 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 649 I40E_PTT_UNUSED_ENTRY(4), 650 I40E_PTT_UNUSED_ENTRY(5), 651 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 652 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 653 I40E_PTT_UNUSED_ENTRY(8), 654 I40E_PTT_UNUSED_ENTRY(9), 655 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 656 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE), 657 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 658 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 659 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 660 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 661 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 662 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 663 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 664 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 665 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 666 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 667 668 /* Non Tunneled IPv4 */ 669 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3), 670 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3), 671 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4), 672 I40E_PTT_UNUSED_ENTRY(25), 673 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4), 674 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4), 675 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4), 676 677 /* IPv4 --> IPv4 */ 678 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 679 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 680 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 681 I40E_PTT_UNUSED_ENTRY(32), 682 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 683 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 684 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 685 686 /* IPv4 --> IPv6 */ 687 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 688 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 689 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 690 I40E_PTT_UNUSED_ENTRY(39), 691 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 692 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 693 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 694 695 /* IPv4 --> GRE/NAT */ 696 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 697 698 /* IPv4 --> GRE/NAT --> IPv4 */ 699 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 700 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 701 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 702 I40E_PTT_UNUSED_ENTRY(47), 703 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 704 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 705 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 706 707 /* IPv4 --> GRE/NAT --> IPv6 */ 708 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 709 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 710 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 711 I40E_PTT_UNUSED_ENTRY(54), 712 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 713 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 714 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 715 716 /* IPv4 --> GRE/NAT --> MAC */ 717 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 718 719 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */ 720 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 721 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 722 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 723 I40E_PTT_UNUSED_ENTRY(62), 724 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 725 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 726 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 727 728 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */ 729 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 730 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 731 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 732 I40E_PTT_UNUSED_ENTRY(69), 733 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 734 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 735 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 736 737 /* IPv4 --> GRE/NAT --> MAC/VLAN */ 738 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 739 740 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */ 741 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 742 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 743 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 744 I40E_PTT_UNUSED_ENTRY(77), 745 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 746 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 747 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 748 749 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */ 750 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 751 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 752 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 753 I40E_PTT_UNUSED_ENTRY(84), 754 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 755 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 756 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 757 758 /* Non Tunneled IPv6 */ 759 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3), 760 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3), 761 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4), 762 I40E_PTT_UNUSED_ENTRY(91), 763 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4), 764 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4), 765 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4), 766 767 /* IPv6 --> IPv4 */ 768 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 769 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 770 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 771 I40E_PTT_UNUSED_ENTRY(98), 772 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 773 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 774 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 775 776 /* IPv6 --> IPv6 */ 777 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 778 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 779 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 780 I40E_PTT_UNUSED_ENTRY(105), 781 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 782 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 783 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 784 785 /* IPv6 --> GRE/NAT */ 786 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 787 788 /* IPv6 --> GRE/NAT -> IPv4 */ 789 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 790 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 791 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 792 I40E_PTT_UNUSED_ENTRY(113), 793 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 794 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 795 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 796 797 /* IPv6 --> GRE/NAT -> IPv6 */ 798 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 799 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 800 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 801 I40E_PTT_UNUSED_ENTRY(120), 802 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 803 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 804 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 805 806 /* IPv6 --> GRE/NAT -> MAC */ 807 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 808 809 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */ 810 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 811 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 812 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 813 I40E_PTT_UNUSED_ENTRY(128), 814 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 815 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 816 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 817 818 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */ 819 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 820 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 821 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 822 I40E_PTT_UNUSED_ENTRY(135), 823 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 824 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 825 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 826 827 /* IPv6 --> GRE/NAT -> MAC/VLAN */ 828 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 829 830 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */ 831 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 832 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 833 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 834 I40E_PTT_UNUSED_ENTRY(143), 835 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 836 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 837 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 838 839 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */ 840 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 841 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 842 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 843 I40E_PTT_UNUSED_ENTRY(150), 844 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 845 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 846 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 847 848 /* unused entries */ 849 I40E_PTT_UNUSED_ENTRY(154), 850 I40E_PTT_UNUSED_ENTRY(155), 851 I40E_PTT_UNUSED_ENTRY(156), 852 I40E_PTT_UNUSED_ENTRY(157), 853 I40E_PTT_UNUSED_ENTRY(158), 854 I40E_PTT_UNUSED_ENTRY(159), 855 856 I40E_PTT_UNUSED_ENTRY(160), 857 I40E_PTT_UNUSED_ENTRY(161), 858 I40E_PTT_UNUSED_ENTRY(162), 859 I40E_PTT_UNUSED_ENTRY(163), 860 I40E_PTT_UNUSED_ENTRY(164), 861 I40E_PTT_UNUSED_ENTRY(165), 862 I40E_PTT_UNUSED_ENTRY(166), 863 I40E_PTT_UNUSED_ENTRY(167), 864 I40E_PTT_UNUSED_ENTRY(168), 865 I40E_PTT_UNUSED_ENTRY(169), 866 867 I40E_PTT_UNUSED_ENTRY(170), 868 I40E_PTT_UNUSED_ENTRY(171), 869 I40E_PTT_UNUSED_ENTRY(172), 870 I40E_PTT_UNUSED_ENTRY(173), 871 I40E_PTT_UNUSED_ENTRY(174), 872 I40E_PTT_UNUSED_ENTRY(175), 873 I40E_PTT_UNUSED_ENTRY(176), 874 I40E_PTT_UNUSED_ENTRY(177), 875 I40E_PTT_UNUSED_ENTRY(178), 876 I40E_PTT_UNUSED_ENTRY(179), 877 878 I40E_PTT_UNUSED_ENTRY(180), 879 I40E_PTT_UNUSED_ENTRY(181), 880 I40E_PTT_UNUSED_ENTRY(182), 881 I40E_PTT_UNUSED_ENTRY(183), 882 I40E_PTT_UNUSED_ENTRY(184), 883 I40E_PTT_UNUSED_ENTRY(185), 884 I40E_PTT_UNUSED_ENTRY(186), 885 I40E_PTT_UNUSED_ENTRY(187), 886 I40E_PTT_UNUSED_ENTRY(188), 887 I40E_PTT_UNUSED_ENTRY(189), 888 889 I40E_PTT_UNUSED_ENTRY(190), 890 I40E_PTT_UNUSED_ENTRY(191), 891 I40E_PTT_UNUSED_ENTRY(192), 892 I40E_PTT_UNUSED_ENTRY(193), 893 I40E_PTT_UNUSED_ENTRY(194), 894 I40E_PTT_UNUSED_ENTRY(195), 895 I40E_PTT_UNUSED_ENTRY(196), 896 I40E_PTT_UNUSED_ENTRY(197), 897 I40E_PTT_UNUSED_ENTRY(198), 898 I40E_PTT_UNUSED_ENTRY(199), 899 900 I40E_PTT_UNUSED_ENTRY(200), 901 I40E_PTT_UNUSED_ENTRY(201), 902 I40E_PTT_UNUSED_ENTRY(202), 903 I40E_PTT_UNUSED_ENTRY(203), 904 I40E_PTT_UNUSED_ENTRY(204), 905 I40E_PTT_UNUSED_ENTRY(205), 906 I40E_PTT_UNUSED_ENTRY(206), 907 I40E_PTT_UNUSED_ENTRY(207), 908 I40E_PTT_UNUSED_ENTRY(208), 909 I40E_PTT_UNUSED_ENTRY(209), 910 911 I40E_PTT_UNUSED_ENTRY(210), 912 I40E_PTT_UNUSED_ENTRY(211), 913 I40E_PTT_UNUSED_ENTRY(212), 914 I40E_PTT_UNUSED_ENTRY(213), 915 I40E_PTT_UNUSED_ENTRY(214), 916 I40E_PTT_UNUSED_ENTRY(215), 917 I40E_PTT_UNUSED_ENTRY(216), 918 I40E_PTT_UNUSED_ENTRY(217), 919 I40E_PTT_UNUSED_ENTRY(218), 920 I40E_PTT_UNUSED_ENTRY(219), 921 922 I40E_PTT_UNUSED_ENTRY(220), 923 I40E_PTT_UNUSED_ENTRY(221), 924 I40E_PTT_UNUSED_ENTRY(222), 925 I40E_PTT_UNUSED_ENTRY(223), 926 I40E_PTT_UNUSED_ENTRY(224), 927 I40E_PTT_UNUSED_ENTRY(225), 928 I40E_PTT_UNUSED_ENTRY(226), 929 I40E_PTT_UNUSED_ENTRY(227), 930 I40E_PTT_UNUSED_ENTRY(228), 931 I40E_PTT_UNUSED_ENTRY(229), 932 933 I40E_PTT_UNUSED_ENTRY(230), 934 I40E_PTT_UNUSED_ENTRY(231), 935 I40E_PTT_UNUSED_ENTRY(232), 936 I40E_PTT_UNUSED_ENTRY(233), 937 I40E_PTT_UNUSED_ENTRY(234), 938 I40E_PTT_UNUSED_ENTRY(235), 939 I40E_PTT_UNUSED_ENTRY(236), 940 I40E_PTT_UNUSED_ENTRY(237), 941 I40E_PTT_UNUSED_ENTRY(238), 942 I40E_PTT_UNUSED_ENTRY(239), 943 944 I40E_PTT_UNUSED_ENTRY(240), 945 I40E_PTT_UNUSED_ENTRY(241), 946 I40E_PTT_UNUSED_ENTRY(242), 947 I40E_PTT_UNUSED_ENTRY(243), 948 I40E_PTT_UNUSED_ENTRY(244), 949 I40E_PTT_UNUSED_ENTRY(245), 950 I40E_PTT_UNUSED_ENTRY(246), 951 I40E_PTT_UNUSED_ENTRY(247), 952 I40E_PTT_UNUSED_ENTRY(248), 953 I40E_PTT_UNUSED_ENTRY(249), 954 955 I40E_PTT_UNUSED_ENTRY(250), 956 I40E_PTT_UNUSED_ENTRY(251), 957 I40E_PTT_UNUSED_ENTRY(252), 958 I40E_PTT_UNUSED_ENTRY(253), 959 I40E_PTT_UNUSED_ENTRY(254), 960 I40E_PTT_UNUSED_ENTRY(255) 961 }; 962 963 964 /** 965 * i40e_validate_mac_addr - Validate unicast MAC address 966 * @mac_addr: pointer to MAC address 967 * 968 * Tests a MAC address to ensure it is a valid Individual Address 969 **/ 970 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr) 971 { 972 enum i40e_status_code status = I40E_SUCCESS; 973 974 DEBUGFUNC("i40e_validate_mac_addr"); 975 976 /* Broadcast addresses ARE multicast addresses 977 * Make sure it is not a multicast address 978 * Reject the zero address 979 */ 980 if (I40E_IS_MULTICAST(mac_addr) || 981 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && 982 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0)) 983 status = I40E_ERR_INVALID_MAC_ADDR; 984 985 return status; 986 } 987 988 /** 989 * i40e_init_shared_code - Initialize the shared code 990 * @hw: pointer to hardware structure 991 * 992 * This assigns the MAC type and PHY code and inits the NVM. 993 * Does not touch the hardware. This function must be called prior to any 994 * other function in the shared code. The i40e_hw structure should be 995 * memset to 0 prior to calling this function. The following fields in 996 * hw structure should be filled in prior to calling this function: 997 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 998 * subsystem_vendor_id, and revision_id 999 **/ 1000 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw) 1001 { 1002 enum i40e_status_code status = I40E_SUCCESS; 1003 u32 port, ari, func_rid; 1004 1005 DEBUGFUNC("i40e_init_shared_code"); 1006 1007 i40e_set_mac_type(hw); 1008 1009 switch (hw->mac.type) { 1010 case I40E_MAC_XL710: 1011 #ifdef X722_SUPPORT 1012 case I40E_MAC_X722: 1013 #endif 1014 break; 1015 default: 1016 return I40E_ERR_DEVICE_NOT_SUPPORTED; 1017 } 1018 1019 hw->phy.get_link_info = TRUE; 1020 1021 /* Determine port number and PF number*/ 1022 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) 1023 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT; 1024 hw->port = (u8)port; 1025 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >> 1026 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT; 1027 func_rid = rd32(hw, I40E_PF_FUNC_RID); 1028 if (ari) 1029 hw->pf_id = (u8)(func_rid & 0xff); 1030 else 1031 hw->pf_id = (u8)(func_rid & 0x7); 1032 1033 status = i40e_init_nvm(hw); 1034 return status; 1035 } 1036 1037 /** 1038 * i40e_aq_mac_address_read - Retrieve the MAC addresses 1039 * @hw: pointer to the hw struct 1040 * @flags: a return indicator of what addresses were added to the addr store 1041 * @addrs: the requestor's mac addr store 1042 * @cmd_details: pointer to command details structure or NULL 1043 **/ 1044 static enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw, 1045 u16 *flags, 1046 struct i40e_aqc_mac_address_read_data *addrs, 1047 struct i40e_asq_cmd_details *cmd_details) 1048 { 1049 struct i40e_aq_desc desc; 1050 struct i40e_aqc_mac_address_read *cmd_data = 1051 (struct i40e_aqc_mac_address_read *)&desc.params.raw; 1052 enum i40e_status_code status; 1053 1054 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read); 1055 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF); 1056 1057 status = i40e_asq_send_command(hw, &desc, addrs, 1058 sizeof(*addrs), cmd_details); 1059 *flags = LE16_TO_CPU(cmd_data->command_flags); 1060 1061 return status; 1062 } 1063 1064 /** 1065 * i40e_aq_mac_address_write - Change the MAC addresses 1066 * @hw: pointer to the hw struct 1067 * @flags: indicates which MAC to be written 1068 * @mac_addr: address to write 1069 * @cmd_details: pointer to command details structure or NULL 1070 **/ 1071 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw, 1072 u16 flags, u8 *mac_addr, 1073 struct i40e_asq_cmd_details *cmd_details) 1074 { 1075 struct i40e_aq_desc desc; 1076 struct i40e_aqc_mac_address_write *cmd_data = 1077 (struct i40e_aqc_mac_address_write *)&desc.params.raw; 1078 enum i40e_status_code status; 1079 1080 i40e_fill_default_direct_cmd_desc(&desc, 1081 i40e_aqc_opc_mac_address_write); 1082 cmd_data->command_flags = CPU_TO_LE16(flags); 1083 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]); 1084 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) | 1085 ((u32)mac_addr[3] << 16) | 1086 ((u32)mac_addr[4] << 8) | 1087 mac_addr[5]); 1088 1089 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1090 1091 return status; 1092 } 1093 1094 /** 1095 * i40e_get_mac_addr - get MAC address 1096 * @hw: pointer to the HW structure 1097 * @mac_addr: pointer to MAC address 1098 * 1099 * Reads the adapter's MAC address from register 1100 **/ 1101 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 1102 { 1103 struct i40e_aqc_mac_address_read_data addrs; 1104 enum i40e_status_code status; 1105 u16 flags = 0; 1106 1107 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 1108 1109 if (flags & I40E_AQC_LAN_ADDR_VALID) 1110 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac)); 1111 1112 return status; 1113 } 1114 1115 /** 1116 * i40e_get_port_mac_addr - get Port MAC address 1117 * @hw: pointer to the HW structure 1118 * @mac_addr: pointer to Port MAC address 1119 * 1120 * Reads the adapter's Port MAC address 1121 **/ 1122 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 1123 { 1124 struct i40e_aqc_mac_address_read_data addrs; 1125 enum i40e_status_code status; 1126 u16 flags = 0; 1127 1128 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 1129 if (status) 1130 return status; 1131 1132 if (flags & I40E_AQC_PORT_ADDR_VALID) 1133 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac)); 1134 else 1135 status = I40E_ERR_INVALID_MAC_ADDR; 1136 1137 return status; 1138 } 1139 1140 /** 1141 * i40e_pre_tx_queue_cfg - pre tx queue configure 1142 * @hw: pointer to the HW structure 1143 * @queue: target pf queue index 1144 * @enable: state change request 1145 * 1146 * Handles hw requirement to indicate intention to enable 1147 * or disable target queue. 1148 **/ 1149 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable) 1150 { 1151 u32 abs_queue_idx = hw->func_caps.base_queue + queue; 1152 u32 reg_block = 0; 1153 u32 reg_val; 1154 1155 if (abs_queue_idx >= 128) { 1156 reg_block = abs_queue_idx / 128; 1157 abs_queue_idx %= 128; 1158 } 1159 1160 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 1161 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 1162 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 1163 1164 if (enable) 1165 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK; 1166 else 1167 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 1168 1169 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val); 1170 } 1171 1172 /** 1173 * i40e_read_pba_string - Reads part number string from EEPROM 1174 * @hw: pointer to hardware structure 1175 * @pba_num: stores the part number string from the EEPROM 1176 * @pba_num_size: part number string buffer length 1177 * 1178 * Reads the part number string from the EEPROM. 1179 **/ 1180 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num, 1181 u32 pba_num_size) 1182 { 1183 enum i40e_status_code status = I40E_SUCCESS; 1184 u16 pba_word = 0; 1185 u16 pba_size = 0; 1186 u16 pba_ptr = 0; 1187 u16 i = 0; 1188 1189 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word); 1190 if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) { 1191 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n"); 1192 return status; 1193 } 1194 1195 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr); 1196 if (status != I40E_SUCCESS) { 1197 DEBUGOUT("Failed to read PBA Block pointer.\n"); 1198 return status; 1199 } 1200 1201 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size); 1202 if (status != I40E_SUCCESS) { 1203 DEBUGOUT("Failed to read PBA Block size.\n"); 1204 return status; 1205 } 1206 1207 /* Subtract one to get PBA word count (PBA Size word is included in 1208 * total size) 1209 */ 1210 pba_size--; 1211 if (pba_num_size < (((u32)pba_size * 2) + 1)) { 1212 DEBUGOUT("Buffer to small for PBA data.\n"); 1213 return I40E_ERR_PARAM; 1214 } 1215 1216 for (i = 0; i < pba_size; i++) { 1217 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word); 1218 if (status != I40E_SUCCESS) { 1219 DEBUGOUT1("Failed to read PBA Block word %d.\n", i); 1220 return status; 1221 } 1222 1223 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF; 1224 pba_num[(i * 2) + 1] = pba_word & 0xFF; 1225 } 1226 pba_num[(pba_size * 2)] = '\0'; 1227 1228 return status; 1229 } 1230 1231 /** 1232 * i40e_get_media_type - Gets media type 1233 * @hw: pointer to the hardware structure 1234 **/ 1235 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw) 1236 { 1237 enum i40e_media_type media; 1238 1239 switch (hw->phy.link_info.phy_type) { 1240 case I40E_PHY_TYPE_10GBASE_SR: 1241 case I40E_PHY_TYPE_10GBASE_LR: 1242 case I40E_PHY_TYPE_1000BASE_SX: 1243 case I40E_PHY_TYPE_1000BASE_LX: 1244 case I40E_PHY_TYPE_40GBASE_SR4: 1245 case I40E_PHY_TYPE_40GBASE_LR4: 1246 media = I40E_MEDIA_TYPE_FIBER; 1247 break; 1248 case I40E_PHY_TYPE_100BASE_TX: 1249 case I40E_PHY_TYPE_1000BASE_T: 1250 case I40E_PHY_TYPE_10GBASE_T: 1251 media = I40E_MEDIA_TYPE_BASET; 1252 break; 1253 case I40E_PHY_TYPE_10GBASE_CR1_CU: 1254 case I40E_PHY_TYPE_40GBASE_CR4_CU: 1255 case I40E_PHY_TYPE_10GBASE_CR1: 1256 case I40E_PHY_TYPE_40GBASE_CR4: 1257 case I40E_PHY_TYPE_10GBASE_SFPP_CU: 1258 case I40E_PHY_TYPE_40GBASE_AOC: 1259 case I40E_PHY_TYPE_10GBASE_AOC: 1260 media = I40E_MEDIA_TYPE_DA; 1261 break; 1262 case I40E_PHY_TYPE_1000BASE_KX: 1263 case I40E_PHY_TYPE_10GBASE_KX4: 1264 case I40E_PHY_TYPE_10GBASE_KR: 1265 case I40E_PHY_TYPE_40GBASE_KR4: 1266 case I40E_PHY_TYPE_20GBASE_KR2: 1267 media = I40E_MEDIA_TYPE_BACKPLANE; 1268 break; 1269 case I40E_PHY_TYPE_SGMII: 1270 case I40E_PHY_TYPE_XAUI: 1271 case I40E_PHY_TYPE_XFI: 1272 case I40E_PHY_TYPE_XLAUI: 1273 case I40E_PHY_TYPE_XLPPI: 1274 default: 1275 media = I40E_MEDIA_TYPE_UNKNOWN; 1276 break; 1277 } 1278 1279 return media; 1280 } 1281 1282 #define I40E_PF_RESET_WAIT_COUNT 200 1283 /** 1284 * i40e_pf_reset - Reset the PF 1285 * @hw: pointer to the hardware structure 1286 * 1287 * Assuming someone else has triggered a global reset, 1288 * assure the global reset is complete and then reset the PF 1289 **/ 1290 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw) 1291 { 1292 u32 cnt = 0; 1293 u32 cnt1 = 0; 1294 u32 reg = 0; 1295 u32 grst_del; 1296 1297 /* Poll for Global Reset steady state in case of recent GRST. 1298 * The grst delay value is in 100ms units, and we'll wait a 1299 * couple counts longer to be sure we don't just miss the end. 1300 */ 1301 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) & 1302 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >> 1303 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT; 1304 for (cnt = 0; cnt < grst_del + 10; cnt++) { 1305 reg = rd32(hw, I40E_GLGEN_RSTAT); 1306 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 1307 break; 1308 i40e_msec_delay(100); 1309 } 1310 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 1311 DEBUGOUT("Global reset polling failed to complete.\n"); 1312 return I40E_ERR_RESET_FAILED; 1313 } 1314 1315 /* Now Wait for the FW to be ready */ 1316 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) { 1317 reg = rd32(hw, I40E_GLNVM_ULD); 1318 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1319 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK); 1320 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1321 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) { 1322 DEBUGOUT1("Core and Global modules ready %d\n", cnt1); 1323 break; 1324 } 1325 i40e_msec_delay(10); 1326 } 1327 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1328 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) { 1329 DEBUGOUT("wait for FW Reset complete timedout\n"); 1330 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg); 1331 return I40E_ERR_RESET_FAILED; 1332 } 1333 1334 /* If there was a Global Reset in progress when we got here, 1335 * we don't need to do the PF Reset 1336 */ 1337 if (!cnt) { 1338 reg = rd32(hw, I40E_PFGEN_CTRL); 1339 wr32(hw, I40E_PFGEN_CTRL, 1340 (reg | I40E_PFGEN_CTRL_PFSWR_MASK)); 1341 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) { 1342 reg = rd32(hw, I40E_PFGEN_CTRL); 1343 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK)) 1344 break; 1345 i40e_msec_delay(1); 1346 } 1347 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) { 1348 DEBUGOUT("PF reset polling failed to complete.\n"); 1349 return I40E_ERR_RESET_FAILED; 1350 } 1351 } 1352 1353 i40e_clear_pxe_mode(hw); 1354 1355 1356 return I40E_SUCCESS; 1357 } 1358 1359 /** 1360 * i40e_clear_hw - clear out any left over hw state 1361 * @hw: pointer to the hw struct 1362 * 1363 * Clear queues and interrupts, typically called at init time, 1364 * but after the capabilities have been found so we know how many 1365 * queues and msix vectors have been allocated. 1366 **/ 1367 void i40e_clear_hw(struct i40e_hw *hw) 1368 { 1369 u32 num_queues, base_queue; 1370 u32 num_pf_int; 1371 u32 num_vf_int; 1372 u32 num_vfs; 1373 u32 i, j; 1374 u32 val; 1375 u32 eol = 0x7ff; 1376 1377 /* get number of interrupts, queues, and vfs */ 1378 val = rd32(hw, I40E_GLPCI_CNF2); 1379 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >> 1380 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT; 1381 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >> 1382 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT; 1383 1384 val = rd32(hw, I40E_PFLAN_QALLOC); 1385 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >> 1386 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT; 1387 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >> 1388 I40E_PFLAN_QALLOC_LASTQ_SHIFT; 1389 if (val & I40E_PFLAN_QALLOC_VALID_MASK) 1390 num_queues = (j - base_queue) + 1; 1391 else 1392 num_queues = 0; 1393 1394 val = rd32(hw, I40E_PF_VT_PFALLOC); 1395 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >> 1396 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT; 1397 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >> 1398 I40E_PF_VT_PFALLOC_LASTVF_SHIFT; 1399 if (val & I40E_PF_VT_PFALLOC_VALID_MASK) 1400 num_vfs = (j - i) + 1; 1401 else 1402 num_vfs = 0; 1403 1404 /* stop all the interrupts */ 1405 wr32(hw, I40E_PFINT_ICR0_ENA, 0); 1406 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT; 1407 for (i = 0; i < num_pf_int - 2; i++) 1408 wr32(hw, I40E_PFINT_DYN_CTLN(i), val); 1409 1410 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */ 1411 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT; 1412 wr32(hw, I40E_PFINT_LNKLST0, val); 1413 for (i = 0; i < num_pf_int - 2; i++) 1414 wr32(hw, I40E_PFINT_LNKLSTN(i), val); 1415 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT; 1416 for (i = 0; i < num_vfs; i++) 1417 wr32(hw, I40E_VPINT_LNKLST0(i), val); 1418 for (i = 0; i < num_vf_int - 2; i++) 1419 wr32(hw, I40E_VPINT_LNKLSTN(i), val); 1420 1421 /* warn the HW of the coming Tx disables */ 1422 for (i = 0; i < num_queues; i++) { 1423 u32 abs_queue_idx = base_queue + i; 1424 u32 reg_block = 0; 1425 1426 if (abs_queue_idx >= 128) { 1427 reg_block = abs_queue_idx / 128; 1428 abs_queue_idx %= 128; 1429 } 1430 1431 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 1432 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 1433 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 1434 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 1435 1436 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val); 1437 } 1438 i40e_usec_delay(400); 1439 1440 /* stop all the queues */ 1441 for (i = 0; i < num_queues; i++) { 1442 wr32(hw, I40E_QINT_TQCTL(i), 0); 1443 wr32(hw, I40E_QTX_ENA(i), 0); 1444 wr32(hw, I40E_QINT_RQCTL(i), 0); 1445 wr32(hw, I40E_QRX_ENA(i), 0); 1446 } 1447 1448 /* short wait for all queue disables to settle */ 1449 i40e_usec_delay(50); 1450 } 1451 1452 /** 1453 * i40e_clear_pxe_mode - clear pxe operations mode 1454 * @hw: pointer to the hw struct 1455 * 1456 * Make sure all PXE mode settings are cleared, including things 1457 * like descriptor fetch/write-back mode. 1458 **/ 1459 void i40e_clear_pxe_mode(struct i40e_hw *hw) 1460 { 1461 if (i40e_check_asq_alive(hw)) 1462 i40e_aq_clear_pxe_mode(hw, NULL); 1463 } 1464 1465 /** 1466 * i40e_led_is_mine - helper to find matching led 1467 * @hw: pointer to the hw struct 1468 * @idx: index into GPIO registers 1469 * 1470 * returns: 0 if no match, otherwise the value of the GPIO_CTL register 1471 */ 1472 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx) 1473 { 1474 u32 gpio_val = 0; 1475 u32 port; 1476 1477 if (!hw->func_caps.led[idx]) 1478 return 0; 1479 1480 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx)); 1481 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >> 1482 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT; 1483 1484 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR 1485 * if it is not our port then ignore 1486 */ 1487 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) || 1488 (port != hw->port)) 1489 return 0; 1490 1491 return gpio_val; 1492 } 1493 1494 #define I40E_COMBINED_ACTIVITY 0xA 1495 #define I40E_FILTER_ACTIVITY 0xE 1496 #define I40E_LINK_ACTIVITY 0xC 1497 #define I40E_MAC_ACTIVITY 0xD 1498 #define I40E_LED0 22 1499 1500 /** 1501 * i40e_led_get - return current on/off mode 1502 * @hw: pointer to the hw struct 1503 * 1504 * The value returned is the 'mode' field as defined in the 1505 * GPIO register definitions: 0x0 = off, 0xf = on, and other 1506 * values are variations of possible behaviors relating to 1507 * blink, link, and wire. 1508 **/ 1509 u32 i40e_led_get(struct i40e_hw *hw) 1510 { 1511 u32 current_mode = 0; 1512 u32 mode = 0; 1513 int i; 1514 1515 /* as per the documentation GPIO 22-29 are the LED 1516 * GPIO pins named LED0..LED7 1517 */ 1518 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1519 u32 gpio_val = i40e_led_is_mine(hw, i); 1520 1521 if (!gpio_val) 1522 continue; 1523 1524 /* ignore gpio LED src mode entries related to the activity 1525 * LEDs 1526 */ 1527 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) 1528 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); 1529 switch (current_mode) { 1530 case I40E_COMBINED_ACTIVITY: 1531 case I40E_FILTER_ACTIVITY: 1532 case I40E_MAC_ACTIVITY: 1533 continue; 1534 default: 1535 break; 1536 } 1537 1538 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >> 1539 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT; 1540 break; 1541 } 1542 1543 return mode; 1544 } 1545 1546 /** 1547 * i40e_led_set - set new on/off mode 1548 * @hw: pointer to the hw struct 1549 * @mode: 0=off, 0xf=on (else see manual for mode details) 1550 * @blink: TRUE if the LED should blink when on, FALSE if steady 1551 * 1552 * if this function is used to turn on the blink it should 1553 * be used to disable the blink when restoring the original state. 1554 **/ 1555 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink) 1556 { 1557 u32 current_mode = 0; 1558 int i; 1559 1560 if (mode & 0xfffffff0) { 1561 DEBUGOUT1("invalid mode passed in %X\n", mode); 1562 } 1563 1564 /* as per the documentation GPIO 22-29 are the LED 1565 * GPIO pins named LED0..LED7 1566 */ 1567 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1568 u32 gpio_val = i40e_led_is_mine(hw, i); 1569 1570 if (!gpio_val) 1571 continue; 1572 1573 /* ignore gpio LED src mode entries related to the activity 1574 * LEDs 1575 */ 1576 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) 1577 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); 1578 switch (current_mode) { 1579 case I40E_COMBINED_ACTIVITY: 1580 case I40E_FILTER_ACTIVITY: 1581 case I40E_MAC_ACTIVITY: 1582 continue; 1583 default: 1584 break; 1585 } 1586 1587 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK; 1588 /* this & is a bit of paranoia, but serves as a range check */ 1589 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) & 1590 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK); 1591 1592 if (mode == I40E_LINK_ACTIVITY) 1593 blink = FALSE; 1594 1595 if (blink) 1596 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1597 else 1598 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1599 1600 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val); 1601 break; 1602 } 1603 } 1604 1605 /* Admin command wrappers */ 1606 1607 /** 1608 * i40e_aq_get_phy_capabilities 1609 * @hw: pointer to the hw struct 1610 * @abilities: structure for PHY capabilities to be filled 1611 * @qualified_modules: report Qualified Modules 1612 * @report_init: report init capabilities (active are default) 1613 * @cmd_details: pointer to command details structure or NULL 1614 * 1615 * Returns the various PHY abilities supported on the Port. 1616 **/ 1617 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw, 1618 bool qualified_modules, bool report_init, 1619 struct i40e_aq_get_phy_abilities_resp *abilities, 1620 struct i40e_asq_cmd_details *cmd_details) 1621 { 1622 struct i40e_aq_desc desc; 1623 enum i40e_status_code status; 1624 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp); 1625 1626 if (!abilities) 1627 return I40E_ERR_PARAM; 1628 1629 i40e_fill_default_direct_cmd_desc(&desc, 1630 i40e_aqc_opc_get_phy_abilities); 1631 1632 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 1633 if (abilities_size > I40E_AQ_LARGE_BUF) 1634 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 1635 1636 if (qualified_modules) 1637 desc.params.external.param0 |= 1638 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES); 1639 1640 if (report_init) 1641 desc.params.external.param0 |= 1642 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES); 1643 1644 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size, 1645 cmd_details); 1646 1647 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) 1648 status = I40E_ERR_UNKNOWN_PHY; 1649 1650 return status; 1651 } 1652 1653 /** 1654 * i40e_aq_set_phy_config 1655 * @hw: pointer to the hw struct 1656 * @config: structure with PHY configuration to be set 1657 * @cmd_details: pointer to command details structure or NULL 1658 * 1659 * Set the various PHY configuration parameters 1660 * supported on the Port.One or more of the Set PHY config parameters may be 1661 * ignored in an MFP mode as the PF may not have the privilege to set some 1662 * of the PHY Config parameters. This status will be indicated by the 1663 * command response. 1664 **/ 1665 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw, 1666 struct i40e_aq_set_phy_config *config, 1667 struct i40e_asq_cmd_details *cmd_details) 1668 { 1669 struct i40e_aq_desc desc; 1670 struct i40e_aq_set_phy_config *cmd = 1671 (struct i40e_aq_set_phy_config *)&desc.params.raw; 1672 enum i40e_status_code status; 1673 1674 if (!config) 1675 return I40E_ERR_PARAM; 1676 1677 i40e_fill_default_direct_cmd_desc(&desc, 1678 i40e_aqc_opc_set_phy_config); 1679 1680 *cmd = *config; 1681 1682 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1683 1684 return status; 1685 } 1686 1687 /** 1688 * i40e_set_fc 1689 * @hw: pointer to the hw struct 1690 * 1691 * Set the requested flow control mode using set_phy_config. 1692 **/ 1693 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures, 1694 bool atomic_restart) 1695 { 1696 enum i40e_fc_mode fc_mode = hw->fc.requested_mode; 1697 struct i40e_aq_get_phy_abilities_resp abilities; 1698 struct i40e_aq_set_phy_config config; 1699 enum i40e_status_code status; 1700 u8 pause_mask = 0x0; 1701 1702 *aq_failures = 0x0; 1703 1704 switch (fc_mode) { 1705 case I40E_FC_FULL: 1706 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1707 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1708 break; 1709 case I40E_FC_RX_PAUSE: 1710 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1711 break; 1712 case I40E_FC_TX_PAUSE: 1713 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1714 break; 1715 default: 1716 break; 1717 } 1718 1719 /* Get the current phy config */ 1720 status = i40e_aq_get_phy_capabilities(hw, FALSE, false, &abilities, 1721 NULL); 1722 if (status) { 1723 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET; 1724 return status; 1725 } 1726 1727 memset(&config, 0, sizeof(config)); 1728 /* clear the old pause settings */ 1729 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) & 1730 ~(I40E_AQ_PHY_FLAG_PAUSE_RX); 1731 /* set the new abilities */ 1732 config.abilities |= pause_mask; 1733 /* If the abilities have changed, then set the new config */ 1734 if (config.abilities != abilities.abilities) { 1735 /* Auto restart link so settings take effect */ 1736 if (atomic_restart) 1737 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK; 1738 /* Copy over all the old settings */ 1739 config.phy_type = abilities.phy_type; 1740 config.link_speed = abilities.link_speed; 1741 config.eee_capability = abilities.eee_capability; 1742 config.eeer = abilities.eeer_val; 1743 config.low_power_ctrl = abilities.d3_lpan; 1744 status = i40e_aq_set_phy_config(hw, &config, NULL); 1745 1746 if (status) 1747 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET; 1748 } 1749 /* Update the link info */ 1750 status = i40e_update_link_info(hw); 1751 if (status) { 1752 /* Wait a little bit (on 40G cards it sometimes takes a really 1753 * long time for link to come back from the atomic reset) 1754 * and try once more 1755 */ 1756 i40e_msec_delay(1000); 1757 status = i40e_update_link_info(hw); 1758 } 1759 if (status) 1760 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE; 1761 1762 return status; 1763 } 1764 1765 /** 1766 * i40e_aq_set_mac_config 1767 * @hw: pointer to the hw struct 1768 * @max_frame_size: Maximum Frame Size to be supported by the port 1769 * @crc_en: Tell HW to append a CRC to outgoing frames 1770 * @pacing: Pacing configurations 1771 * @cmd_details: pointer to command details structure or NULL 1772 * 1773 * Configure MAC settings for frame size, jumbo frame support and the 1774 * addition of a CRC by the hardware. 1775 **/ 1776 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw, 1777 u16 max_frame_size, 1778 bool crc_en, u16 pacing, 1779 struct i40e_asq_cmd_details *cmd_details) 1780 { 1781 struct i40e_aq_desc desc; 1782 struct i40e_aq_set_mac_config *cmd = 1783 (struct i40e_aq_set_mac_config *)&desc.params.raw; 1784 enum i40e_status_code status; 1785 1786 if (max_frame_size == 0) 1787 return I40E_ERR_PARAM; 1788 1789 i40e_fill_default_direct_cmd_desc(&desc, 1790 i40e_aqc_opc_set_mac_config); 1791 1792 cmd->max_frame_size = CPU_TO_LE16(max_frame_size); 1793 cmd->params = ((u8)pacing & 0x0F) << 3; 1794 if (crc_en) 1795 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN; 1796 1797 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1798 1799 return status; 1800 } 1801 1802 /** 1803 * i40e_aq_clear_pxe_mode 1804 * @hw: pointer to the hw struct 1805 * @cmd_details: pointer to command details structure or NULL 1806 * 1807 * Tell the firmware that the driver is taking over from PXE 1808 **/ 1809 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw, 1810 struct i40e_asq_cmd_details *cmd_details) 1811 { 1812 enum i40e_status_code status; 1813 struct i40e_aq_desc desc; 1814 struct i40e_aqc_clear_pxe *cmd = 1815 (struct i40e_aqc_clear_pxe *)&desc.params.raw; 1816 1817 i40e_fill_default_direct_cmd_desc(&desc, 1818 i40e_aqc_opc_clear_pxe_mode); 1819 1820 cmd->rx_cnt = 0x2; 1821 1822 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1823 1824 wr32(hw, I40E_GLLAN_RCTL_0, 0x1); 1825 1826 return status; 1827 } 1828 1829 /** 1830 * i40e_aq_set_link_restart_an 1831 * @hw: pointer to the hw struct 1832 * @enable_link: if TRUE: enable link, if FALSE: disable link 1833 * @cmd_details: pointer to command details structure or NULL 1834 * 1835 * Sets up the link and restarts the Auto-Negotiation over the link. 1836 **/ 1837 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw, 1838 bool enable_link, struct i40e_asq_cmd_details *cmd_details) 1839 { 1840 struct i40e_aq_desc desc; 1841 struct i40e_aqc_set_link_restart_an *cmd = 1842 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw; 1843 enum i40e_status_code status; 1844 1845 i40e_fill_default_direct_cmd_desc(&desc, 1846 i40e_aqc_opc_set_link_restart_an); 1847 1848 cmd->command = I40E_AQ_PHY_RESTART_AN; 1849 if (enable_link) 1850 cmd->command |= I40E_AQ_PHY_LINK_ENABLE; 1851 else 1852 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE; 1853 1854 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1855 1856 return status; 1857 } 1858 1859 /** 1860 * i40e_aq_get_link_info 1861 * @hw: pointer to the hw struct 1862 * @enable_lse: enable/disable LinkStatusEvent reporting 1863 * @link: pointer to link status structure - optional 1864 * @cmd_details: pointer to command details structure or NULL 1865 * 1866 * Returns the link status of the adapter. 1867 **/ 1868 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw, 1869 bool enable_lse, struct i40e_link_status *link, 1870 struct i40e_asq_cmd_details *cmd_details) 1871 { 1872 struct i40e_aq_desc desc; 1873 struct i40e_aqc_get_link_status *resp = 1874 (struct i40e_aqc_get_link_status *)&desc.params.raw; 1875 struct i40e_link_status *hw_link_info = &hw->phy.link_info; 1876 enum i40e_status_code status; 1877 bool tx_pause, rx_pause; 1878 u16 command_flags; 1879 1880 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status); 1881 1882 if (enable_lse) 1883 command_flags = I40E_AQ_LSE_ENABLE; 1884 else 1885 command_flags = I40E_AQ_LSE_DISABLE; 1886 resp->command_flags = CPU_TO_LE16(command_flags); 1887 1888 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1889 1890 if (status != I40E_SUCCESS) 1891 goto aq_get_link_info_exit; 1892 1893 /* save off old link status information */ 1894 i40e_memcpy(&hw->phy.link_info_old, hw_link_info, 1895 sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA); 1896 1897 /* update link status */ 1898 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type; 1899 hw->phy.media_type = i40e_get_media_type(hw); 1900 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed; 1901 hw_link_info->link_info = resp->link_info; 1902 hw_link_info->an_info = resp->an_info; 1903 hw_link_info->ext_info = resp->ext_info; 1904 hw_link_info->loopback = resp->loopback; 1905 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size); 1906 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK; 1907 1908 /* update fc info */ 1909 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX); 1910 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX); 1911 if (tx_pause & rx_pause) 1912 hw->fc.current_mode = I40E_FC_FULL; 1913 else if (tx_pause) 1914 hw->fc.current_mode = I40E_FC_TX_PAUSE; 1915 else if (rx_pause) 1916 hw->fc.current_mode = I40E_FC_RX_PAUSE; 1917 else 1918 hw->fc.current_mode = I40E_FC_NONE; 1919 1920 if (resp->config & I40E_AQ_CONFIG_CRC_ENA) 1921 hw_link_info->crc_enable = TRUE; 1922 else 1923 hw_link_info->crc_enable = FALSE; 1924 1925 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_ENABLE)) 1926 hw_link_info->lse_enable = TRUE; 1927 else 1928 hw_link_info->lse_enable = FALSE; 1929 1930 if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 && 1931 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE) 1932 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU; 1933 1934 /* save link status information */ 1935 if (link) 1936 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info), 1937 I40E_NONDMA_TO_NONDMA); 1938 1939 /* flag cleared so helper functions don't call AQ again */ 1940 hw->phy.get_link_info = FALSE; 1941 1942 aq_get_link_info_exit: 1943 return status; 1944 } 1945 1946 /** 1947 * i40e_aq_set_phy_int_mask 1948 * @hw: pointer to the hw struct 1949 * @mask: interrupt mask to be set 1950 * @cmd_details: pointer to command details structure or NULL 1951 * 1952 * Set link interrupt mask. 1953 **/ 1954 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw, 1955 u16 mask, 1956 struct i40e_asq_cmd_details *cmd_details) 1957 { 1958 struct i40e_aq_desc desc; 1959 struct i40e_aqc_set_phy_int_mask *cmd = 1960 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw; 1961 enum i40e_status_code status; 1962 1963 i40e_fill_default_direct_cmd_desc(&desc, 1964 i40e_aqc_opc_set_phy_int_mask); 1965 1966 cmd->event_mask = CPU_TO_LE16(mask); 1967 1968 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1969 1970 return status; 1971 } 1972 1973 /** 1974 * i40e_aq_get_local_advt_reg 1975 * @hw: pointer to the hw struct 1976 * @advt_reg: local AN advertisement register value 1977 * @cmd_details: pointer to command details structure or NULL 1978 * 1979 * Get the Local AN advertisement register value. 1980 **/ 1981 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw, 1982 u64 *advt_reg, 1983 struct i40e_asq_cmd_details *cmd_details) 1984 { 1985 struct i40e_aq_desc desc; 1986 struct i40e_aqc_an_advt_reg *resp = 1987 (struct i40e_aqc_an_advt_reg *)&desc.params.raw; 1988 enum i40e_status_code status; 1989 1990 i40e_fill_default_direct_cmd_desc(&desc, 1991 i40e_aqc_opc_get_local_advt_reg); 1992 1993 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1994 1995 if (status != I40E_SUCCESS) 1996 goto aq_get_local_advt_reg_exit; 1997 1998 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32; 1999 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0); 2000 2001 aq_get_local_advt_reg_exit: 2002 return status; 2003 } 2004 2005 /** 2006 * i40e_aq_set_local_advt_reg 2007 * @hw: pointer to the hw struct 2008 * @advt_reg: local AN advertisement register value 2009 * @cmd_details: pointer to command details structure or NULL 2010 * 2011 * Get the Local AN advertisement register value. 2012 **/ 2013 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw, 2014 u64 advt_reg, 2015 struct i40e_asq_cmd_details *cmd_details) 2016 { 2017 struct i40e_aq_desc desc; 2018 struct i40e_aqc_an_advt_reg *cmd = 2019 (struct i40e_aqc_an_advt_reg *)&desc.params.raw; 2020 enum i40e_status_code status; 2021 2022 i40e_fill_default_direct_cmd_desc(&desc, 2023 i40e_aqc_opc_get_local_advt_reg); 2024 2025 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg)); 2026 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg)); 2027 2028 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2029 2030 return status; 2031 } 2032 2033 /** 2034 * i40e_aq_get_partner_advt 2035 * @hw: pointer to the hw struct 2036 * @advt_reg: AN partner advertisement register value 2037 * @cmd_details: pointer to command details structure or NULL 2038 * 2039 * Get the link partner AN advertisement register value. 2040 **/ 2041 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw, 2042 u64 *advt_reg, 2043 struct i40e_asq_cmd_details *cmd_details) 2044 { 2045 struct i40e_aq_desc desc; 2046 struct i40e_aqc_an_advt_reg *resp = 2047 (struct i40e_aqc_an_advt_reg *)&desc.params.raw; 2048 enum i40e_status_code status; 2049 2050 i40e_fill_default_direct_cmd_desc(&desc, 2051 i40e_aqc_opc_get_partner_advt); 2052 2053 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2054 2055 if (status != I40E_SUCCESS) 2056 goto aq_get_partner_advt_exit; 2057 2058 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32; 2059 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0); 2060 2061 aq_get_partner_advt_exit: 2062 return status; 2063 } 2064 2065 /** 2066 * i40e_aq_set_lb_modes 2067 * @hw: pointer to the hw struct 2068 * @lb_modes: loopback mode to be set 2069 * @cmd_details: pointer to command details structure or NULL 2070 * 2071 * Sets loopback modes. 2072 **/ 2073 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw, 2074 u16 lb_modes, 2075 struct i40e_asq_cmd_details *cmd_details) 2076 { 2077 struct i40e_aq_desc desc; 2078 struct i40e_aqc_set_lb_mode *cmd = 2079 (struct i40e_aqc_set_lb_mode *)&desc.params.raw; 2080 enum i40e_status_code status; 2081 2082 i40e_fill_default_direct_cmd_desc(&desc, 2083 i40e_aqc_opc_set_lb_modes); 2084 2085 cmd->lb_mode = CPU_TO_LE16(lb_modes); 2086 2087 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2088 2089 return status; 2090 } 2091 2092 /** 2093 * i40e_aq_set_phy_debug 2094 * @hw: pointer to the hw struct 2095 * @cmd_flags: debug command flags 2096 * @cmd_details: pointer to command details structure or NULL 2097 * 2098 * Reset the external PHY. 2099 **/ 2100 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags, 2101 struct i40e_asq_cmd_details *cmd_details) 2102 { 2103 struct i40e_aq_desc desc; 2104 struct i40e_aqc_set_phy_debug *cmd = 2105 (struct i40e_aqc_set_phy_debug *)&desc.params.raw; 2106 enum i40e_status_code status; 2107 2108 i40e_fill_default_direct_cmd_desc(&desc, 2109 i40e_aqc_opc_set_phy_debug); 2110 2111 cmd->command_flags = cmd_flags; 2112 2113 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2114 2115 return status; 2116 } 2117 2118 /** 2119 * i40e_aq_add_vsi 2120 * @hw: pointer to the hw struct 2121 * @vsi_ctx: pointer to a vsi context struct 2122 * @cmd_details: pointer to command details structure or NULL 2123 * 2124 * Add a VSI context to the hardware. 2125 **/ 2126 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw, 2127 struct i40e_vsi_context *vsi_ctx, 2128 struct i40e_asq_cmd_details *cmd_details) 2129 { 2130 struct i40e_aq_desc desc; 2131 struct i40e_aqc_add_get_update_vsi *cmd = 2132 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2133 struct i40e_aqc_add_get_update_vsi_completion *resp = 2134 (struct i40e_aqc_add_get_update_vsi_completion *) 2135 &desc.params.raw; 2136 enum i40e_status_code status; 2137 2138 i40e_fill_default_direct_cmd_desc(&desc, 2139 i40e_aqc_opc_add_vsi); 2140 2141 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid); 2142 cmd->connection_type = vsi_ctx->connection_type; 2143 cmd->vf_id = vsi_ctx->vf_num; 2144 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags); 2145 2146 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2147 2148 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2149 sizeof(vsi_ctx->info), cmd_details); 2150 2151 if (status != I40E_SUCCESS) 2152 goto aq_add_vsi_exit; 2153 2154 vsi_ctx->seid = LE16_TO_CPU(resp->seid); 2155 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number); 2156 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used); 2157 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free); 2158 2159 aq_add_vsi_exit: 2160 return status; 2161 } 2162 2163 /** 2164 * i40e_aq_set_default_vsi 2165 * @hw: pointer to the hw struct 2166 * @seid: vsi number 2167 * @cmd_details: pointer to command details structure or NULL 2168 **/ 2169 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw, 2170 u16 seid, 2171 struct i40e_asq_cmd_details *cmd_details) 2172 { 2173 struct i40e_aq_desc desc; 2174 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2175 (struct i40e_aqc_set_vsi_promiscuous_modes *) 2176 &desc.params.raw; 2177 enum i40e_status_code status; 2178 2179 i40e_fill_default_direct_cmd_desc(&desc, 2180 i40e_aqc_opc_set_vsi_promiscuous_modes); 2181 2182 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT); 2183 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT); 2184 cmd->seid = CPU_TO_LE16(seid); 2185 2186 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2187 2188 return status; 2189 } 2190 2191 /** 2192 * i40e_aq_set_vsi_unicast_promiscuous 2193 * @hw: pointer to the hw struct 2194 * @seid: vsi number 2195 * @set: set unicast promiscuous enable/disable 2196 * @cmd_details: pointer to command details structure or NULL 2197 **/ 2198 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw, 2199 u16 seid, bool set, 2200 struct i40e_asq_cmd_details *cmd_details) 2201 { 2202 struct i40e_aq_desc desc; 2203 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2204 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2205 enum i40e_status_code status; 2206 u16 flags = 0; 2207 2208 i40e_fill_default_direct_cmd_desc(&desc, 2209 i40e_aqc_opc_set_vsi_promiscuous_modes); 2210 2211 if (set) 2212 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 2213 2214 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2215 2216 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 2217 2218 cmd->seid = CPU_TO_LE16(seid); 2219 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2220 2221 return status; 2222 } 2223 2224 /** 2225 * i40e_aq_set_vsi_multicast_promiscuous 2226 * @hw: pointer to the hw struct 2227 * @seid: vsi number 2228 * @set: set multicast promiscuous enable/disable 2229 * @cmd_details: pointer to command details structure or NULL 2230 **/ 2231 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw, 2232 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details) 2233 { 2234 struct i40e_aq_desc desc; 2235 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2236 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2237 enum i40e_status_code status; 2238 u16 flags = 0; 2239 2240 i40e_fill_default_direct_cmd_desc(&desc, 2241 i40e_aqc_opc_set_vsi_promiscuous_modes); 2242 2243 if (set) 2244 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 2245 2246 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2247 2248 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 2249 2250 cmd->seid = CPU_TO_LE16(seid); 2251 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2252 2253 return status; 2254 } 2255 2256 /** 2257 * i40e_aq_set_vsi_mc_promisc_on_vlan 2258 * @hw: pointer to the hw struct 2259 * @seid: vsi number 2260 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2261 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag 2262 * @cmd_details: pointer to command details structure or NULL 2263 **/ 2264 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw, 2265 u16 seid, bool enable, u16 vid, 2266 struct i40e_asq_cmd_details *cmd_details) 2267 { 2268 struct i40e_aq_desc desc; 2269 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2270 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2271 enum i40e_status_code status; 2272 u16 flags = 0; 2273 2274 i40e_fill_default_direct_cmd_desc(&desc, 2275 i40e_aqc_opc_set_vsi_promiscuous_modes); 2276 2277 if (enable) 2278 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 2279 2280 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2281 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 2282 cmd->seid = CPU_TO_LE16(seid); 2283 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2284 2285 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2286 2287 return status; 2288 } 2289 2290 /** 2291 * i40e_aq_set_vsi_uc_promisc_on_vlan 2292 * @hw: pointer to the hw struct 2293 * @seid: vsi number 2294 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2295 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag 2296 * @cmd_details: pointer to command details structure or NULL 2297 **/ 2298 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw, 2299 u16 seid, bool enable, u16 vid, 2300 struct i40e_asq_cmd_details *cmd_details) 2301 { 2302 struct i40e_aq_desc desc; 2303 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2304 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2305 enum i40e_status_code status; 2306 u16 flags = 0; 2307 2308 i40e_fill_default_direct_cmd_desc(&desc, 2309 i40e_aqc_opc_set_vsi_promiscuous_modes); 2310 2311 if (enable) 2312 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 2313 2314 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2315 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 2316 cmd->seid = CPU_TO_LE16(seid); 2317 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2318 2319 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2320 2321 return status; 2322 } 2323 2324 /** 2325 * i40e_aq_set_vsi_broadcast 2326 * @hw: pointer to the hw struct 2327 * @seid: vsi number 2328 * @set_filter: TRUE to set filter, FALSE to clear filter 2329 * @cmd_details: pointer to command details structure or NULL 2330 * 2331 * Set or clear the broadcast promiscuous flag (filter) for a given VSI. 2332 **/ 2333 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw, 2334 u16 seid, bool set_filter, 2335 struct i40e_asq_cmd_details *cmd_details) 2336 { 2337 struct i40e_aq_desc desc; 2338 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2339 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2340 enum i40e_status_code status; 2341 2342 i40e_fill_default_direct_cmd_desc(&desc, 2343 i40e_aqc_opc_set_vsi_promiscuous_modes); 2344 2345 if (set_filter) 2346 cmd->promiscuous_flags 2347 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2348 else 2349 cmd->promiscuous_flags 2350 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2351 2352 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2353 cmd->seid = CPU_TO_LE16(seid); 2354 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2355 2356 return status; 2357 } 2358 2359 /** 2360 * i40e_get_vsi_params - get VSI configuration info 2361 * @hw: pointer to the hw struct 2362 * @vsi_ctx: pointer to a vsi context struct 2363 * @cmd_details: pointer to command details structure or NULL 2364 **/ 2365 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw, 2366 struct i40e_vsi_context *vsi_ctx, 2367 struct i40e_asq_cmd_details *cmd_details) 2368 { 2369 struct i40e_aq_desc desc; 2370 struct i40e_aqc_add_get_update_vsi *cmd = 2371 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2372 struct i40e_aqc_add_get_update_vsi_completion *resp = 2373 (struct i40e_aqc_add_get_update_vsi_completion *) 2374 &desc.params.raw; 2375 enum i40e_status_code status; 2376 2377 i40e_fill_default_direct_cmd_desc(&desc, 2378 i40e_aqc_opc_get_vsi_parameters); 2379 2380 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid); 2381 2382 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 2383 2384 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2385 sizeof(vsi_ctx->info), NULL); 2386 2387 if (status != I40E_SUCCESS) 2388 goto aq_get_vsi_params_exit; 2389 2390 vsi_ctx->seid = LE16_TO_CPU(resp->seid); 2391 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number); 2392 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used); 2393 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free); 2394 2395 aq_get_vsi_params_exit: 2396 return status; 2397 } 2398 2399 /** 2400 * i40e_aq_update_vsi_params 2401 * @hw: pointer to the hw struct 2402 * @vsi_ctx: pointer to a vsi context struct 2403 * @cmd_details: pointer to command details structure or NULL 2404 * 2405 * Update a VSI context. 2406 **/ 2407 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw, 2408 struct i40e_vsi_context *vsi_ctx, 2409 struct i40e_asq_cmd_details *cmd_details) 2410 { 2411 struct i40e_aq_desc desc; 2412 struct i40e_aqc_add_get_update_vsi *cmd = 2413 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2414 enum i40e_status_code status; 2415 2416 i40e_fill_default_direct_cmd_desc(&desc, 2417 i40e_aqc_opc_update_vsi_parameters); 2418 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid); 2419 2420 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2421 2422 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2423 sizeof(vsi_ctx->info), cmd_details); 2424 2425 return status; 2426 } 2427 2428 /** 2429 * i40e_aq_get_switch_config 2430 * @hw: pointer to the hardware structure 2431 * @buf: pointer to the result buffer 2432 * @buf_size: length of input buffer 2433 * @start_seid: seid to start for the report, 0 == beginning 2434 * @cmd_details: pointer to command details structure or NULL 2435 * 2436 * Fill the buf with switch configuration returned from AdminQ command 2437 **/ 2438 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw, 2439 struct i40e_aqc_get_switch_config_resp *buf, 2440 u16 buf_size, u16 *start_seid, 2441 struct i40e_asq_cmd_details *cmd_details) 2442 { 2443 struct i40e_aq_desc desc; 2444 struct i40e_aqc_switch_seid *scfg = 2445 (struct i40e_aqc_switch_seid *)&desc.params.raw; 2446 enum i40e_status_code status; 2447 2448 i40e_fill_default_direct_cmd_desc(&desc, 2449 i40e_aqc_opc_get_switch_config); 2450 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 2451 if (buf_size > I40E_AQ_LARGE_BUF) 2452 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2453 scfg->seid = CPU_TO_LE16(*start_seid); 2454 2455 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details); 2456 *start_seid = LE16_TO_CPU(scfg->seid); 2457 2458 return status; 2459 } 2460 2461 /** 2462 * i40e_aq_get_firmware_version 2463 * @hw: pointer to the hw struct 2464 * @fw_major_version: firmware major version 2465 * @fw_minor_version: firmware minor version 2466 * @fw_build: firmware build number 2467 * @api_major_version: major queue version 2468 * @api_minor_version: minor queue version 2469 * @cmd_details: pointer to command details structure or NULL 2470 * 2471 * Get the firmware version from the admin queue commands 2472 **/ 2473 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw, 2474 u16 *fw_major_version, u16 *fw_minor_version, 2475 u32 *fw_build, 2476 u16 *api_major_version, u16 *api_minor_version, 2477 struct i40e_asq_cmd_details *cmd_details) 2478 { 2479 struct i40e_aq_desc desc; 2480 struct i40e_aqc_get_version *resp = 2481 (struct i40e_aqc_get_version *)&desc.params.raw; 2482 enum i40e_status_code status; 2483 2484 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version); 2485 2486 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2487 2488 if (status == I40E_SUCCESS) { 2489 if (fw_major_version != NULL) 2490 *fw_major_version = LE16_TO_CPU(resp->fw_major); 2491 if (fw_minor_version != NULL) 2492 *fw_minor_version = LE16_TO_CPU(resp->fw_minor); 2493 if (fw_build != NULL) 2494 *fw_build = LE32_TO_CPU(resp->fw_build); 2495 if (api_major_version != NULL) 2496 *api_major_version = LE16_TO_CPU(resp->api_major); 2497 if (api_minor_version != NULL) 2498 *api_minor_version = LE16_TO_CPU(resp->api_minor); 2499 2500 /* A workaround to fix the API version in SW */ 2501 if (api_major_version && api_minor_version && 2502 fw_major_version && fw_minor_version && 2503 ((*api_major_version == 1) && (*api_minor_version == 1)) && 2504 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) || 2505 (*fw_major_version > 4))) 2506 *api_minor_version = 2; 2507 } 2508 2509 return status; 2510 } 2511 2512 /** 2513 * i40e_aq_send_driver_version 2514 * @hw: pointer to the hw struct 2515 * @dv: driver's major, minor version 2516 * @cmd_details: pointer to command details structure or NULL 2517 * 2518 * Send the driver version to the firmware 2519 **/ 2520 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw, 2521 struct i40e_driver_version *dv, 2522 struct i40e_asq_cmd_details *cmd_details) 2523 { 2524 struct i40e_aq_desc desc; 2525 struct i40e_aqc_driver_version *cmd = 2526 (struct i40e_aqc_driver_version *)&desc.params.raw; 2527 enum i40e_status_code status; 2528 u16 len; 2529 2530 if (dv == NULL) 2531 return I40E_ERR_PARAM; 2532 2533 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version); 2534 2535 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD); 2536 cmd->driver_major_ver = dv->major_version; 2537 cmd->driver_minor_ver = dv->minor_version; 2538 cmd->driver_build_ver = dv->build_version; 2539 cmd->driver_subbuild_ver = dv->subbuild_version; 2540 2541 len = 0; 2542 while (len < sizeof(dv->driver_string) && 2543 (dv->driver_string[len] < 0x80) && 2544 dv->driver_string[len]) 2545 len++; 2546 status = i40e_asq_send_command(hw, &desc, dv->driver_string, 2547 len, cmd_details); 2548 2549 return status; 2550 } 2551 2552 /** 2553 * i40e_get_link_status - get status of the HW network link 2554 * @hw: pointer to the hw struct 2555 * @link_up: pointer to bool (TRUE/FALSE = linkup/linkdown) 2556 * 2557 * Variable link_up TRUE if link is up, FALSE if link is down. 2558 * The variable link_up is invalid if returned value of status != I40E_SUCCESS 2559 * 2560 * Side effect: LinkStatusEvent reporting becomes enabled 2561 **/ 2562 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up) 2563 { 2564 enum i40e_status_code status = I40E_SUCCESS; 2565 2566 if (hw->phy.get_link_info) { 2567 status = i40e_update_link_info(hw); 2568 2569 if (status != I40E_SUCCESS) 2570 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n", 2571 status); 2572 } 2573 2574 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP; 2575 2576 return status; 2577 } 2578 2579 /** 2580 * i40e_updatelink_status - update status of the HW network link 2581 * @hw: pointer to the hw struct 2582 **/ 2583 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw) 2584 { 2585 struct i40e_aq_get_phy_abilities_resp abilities; 2586 enum i40e_status_code status = I40E_SUCCESS; 2587 2588 status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL); 2589 if (status) 2590 return status; 2591 2592 status = i40e_aq_get_phy_capabilities(hw, FALSE, false, &abilities, 2593 NULL); 2594 if (status) 2595 return status; 2596 2597 memcpy(hw->phy.link_info.module_type, &abilities.module_type, 2598 sizeof(hw->phy.link_info.module_type)); 2599 2600 return status; 2601 } 2602 2603 2604 /** 2605 * i40e_get_link_speed 2606 * @hw: pointer to the hw struct 2607 * 2608 * Returns the link speed of the adapter. 2609 **/ 2610 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw) 2611 { 2612 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN; 2613 enum i40e_status_code status = I40E_SUCCESS; 2614 2615 if (hw->phy.get_link_info) { 2616 status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL); 2617 2618 if (status != I40E_SUCCESS) 2619 goto i40e_link_speed_exit; 2620 } 2621 2622 speed = hw->phy.link_info.link_speed; 2623 2624 i40e_link_speed_exit: 2625 return speed; 2626 } 2627 2628 /** 2629 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC 2630 * @hw: pointer to the hw struct 2631 * @uplink_seid: the MAC or other gizmo SEID 2632 * @downlink_seid: the VSI SEID 2633 * @enabled_tc: bitmap of TCs to be enabled 2634 * @default_port: TRUE for default port VSI, FALSE for control port 2635 * @enable_l2_filtering: TRUE to add L2 filter table rules to regular forwarding rules for cloud support 2636 * @veb_seid: pointer to where to put the resulting VEB SEID 2637 * @cmd_details: pointer to command details structure or NULL 2638 * 2639 * This asks the FW to add a VEB between the uplink and downlink 2640 * elements. If the uplink SEID is 0, this will be a floating VEB. 2641 **/ 2642 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid, 2643 u16 downlink_seid, u8 enabled_tc, 2644 bool default_port, bool enable_l2_filtering, 2645 u16 *veb_seid, 2646 struct i40e_asq_cmd_details *cmd_details) 2647 { 2648 struct i40e_aq_desc desc; 2649 struct i40e_aqc_add_veb *cmd = 2650 (struct i40e_aqc_add_veb *)&desc.params.raw; 2651 struct i40e_aqc_add_veb_completion *resp = 2652 (struct i40e_aqc_add_veb_completion *)&desc.params.raw; 2653 enum i40e_status_code status; 2654 u16 veb_flags = 0; 2655 2656 /* SEIDs need to either both be set or both be 0 for floating VEB */ 2657 if (!!uplink_seid != !!downlink_seid) 2658 return I40E_ERR_PARAM; 2659 2660 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb); 2661 2662 cmd->uplink_seid = CPU_TO_LE16(uplink_seid); 2663 cmd->downlink_seid = CPU_TO_LE16(downlink_seid); 2664 cmd->enable_tcs = enabled_tc; 2665 if (!uplink_seid) 2666 veb_flags |= I40E_AQC_ADD_VEB_FLOATING; 2667 if (default_port) 2668 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT; 2669 else 2670 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA; 2671 2672 if (enable_l2_filtering) 2673 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER; 2674 2675 cmd->veb_flags = CPU_TO_LE16(veb_flags); 2676 2677 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2678 2679 if (!status && veb_seid) 2680 *veb_seid = LE16_TO_CPU(resp->veb_seid); 2681 2682 return status; 2683 } 2684 2685 /** 2686 * i40e_aq_get_veb_parameters - Retrieve VEB parameters 2687 * @hw: pointer to the hw struct 2688 * @veb_seid: the SEID of the VEB to query 2689 * @switch_id: the uplink switch id 2690 * @floating: set to TRUE if the VEB is floating 2691 * @statistic_index: index of the stats counter block for this VEB 2692 * @vebs_used: number of VEB's used by function 2693 * @vebs_free: total VEB's not reserved by any function 2694 * @cmd_details: pointer to command details structure or NULL 2695 * 2696 * This retrieves the parameters for a particular VEB, specified by 2697 * uplink_seid, and returns them to the caller. 2698 **/ 2699 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw, 2700 u16 veb_seid, u16 *switch_id, 2701 bool *floating, u16 *statistic_index, 2702 u16 *vebs_used, u16 *vebs_free, 2703 struct i40e_asq_cmd_details *cmd_details) 2704 { 2705 struct i40e_aq_desc desc; 2706 struct i40e_aqc_get_veb_parameters_completion *cmd_resp = 2707 (struct i40e_aqc_get_veb_parameters_completion *) 2708 &desc.params.raw; 2709 enum i40e_status_code status; 2710 2711 if (veb_seid == 0) 2712 return I40E_ERR_PARAM; 2713 2714 i40e_fill_default_direct_cmd_desc(&desc, 2715 i40e_aqc_opc_get_veb_parameters); 2716 cmd_resp->seid = CPU_TO_LE16(veb_seid); 2717 2718 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2719 if (status) 2720 goto get_veb_exit; 2721 2722 if (switch_id) 2723 *switch_id = LE16_TO_CPU(cmd_resp->switch_id); 2724 if (statistic_index) 2725 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index); 2726 if (vebs_used) 2727 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used); 2728 if (vebs_free) 2729 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free); 2730 if (floating) { 2731 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags); 2732 2733 if (flags & I40E_AQC_ADD_VEB_FLOATING) 2734 *floating = TRUE; 2735 else 2736 *floating = FALSE; 2737 } 2738 2739 get_veb_exit: 2740 return status; 2741 } 2742 2743 /** 2744 * i40e_aq_add_macvlan 2745 * @hw: pointer to the hw struct 2746 * @seid: VSI for the mac address 2747 * @mv_list: list of macvlans to be added 2748 * @count: length of the list 2749 * @cmd_details: pointer to command details structure or NULL 2750 * 2751 * Add MAC/VLAN addresses to the HW filtering 2752 **/ 2753 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid, 2754 struct i40e_aqc_add_macvlan_element_data *mv_list, 2755 u16 count, struct i40e_asq_cmd_details *cmd_details) 2756 { 2757 struct i40e_aq_desc desc; 2758 struct i40e_aqc_macvlan *cmd = 2759 (struct i40e_aqc_macvlan *)&desc.params.raw; 2760 enum i40e_status_code status; 2761 u16 buf_size; 2762 2763 if (count == 0 || !mv_list || !hw) 2764 return I40E_ERR_PARAM; 2765 2766 buf_size = count * sizeof(*mv_list); 2767 2768 /* prep the rest of the request */ 2769 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan); 2770 cmd->num_addresses = CPU_TO_LE16(count); 2771 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2772 cmd->seid[1] = 0; 2773 cmd->seid[2] = 0; 2774 2775 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2776 if (buf_size > I40E_AQ_LARGE_BUF) 2777 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2778 2779 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 2780 cmd_details); 2781 2782 return status; 2783 } 2784 2785 /** 2786 * i40e_aq_remove_macvlan 2787 * @hw: pointer to the hw struct 2788 * @seid: VSI for the mac address 2789 * @mv_list: list of macvlans to be removed 2790 * @count: length of the list 2791 * @cmd_details: pointer to command details structure or NULL 2792 * 2793 * Remove MAC/VLAN addresses from the HW filtering 2794 **/ 2795 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid, 2796 struct i40e_aqc_remove_macvlan_element_data *mv_list, 2797 u16 count, struct i40e_asq_cmd_details *cmd_details) 2798 { 2799 struct i40e_aq_desc desc; 2800 struct i40e_aqc_macvlan *cmd = 2801 (struct i40e_aqc_macvlan *)&desc.params.raw; 2802 enum i40e_status_code status; 2803 u16 buf_size; 2804 2805 if (count == 0 || !mv_list || !hw) 2806 return I40E_ERR_PARAM; 2807 2808 buf_size = count * sizeof(*mv_list); 2809 2810 /* prep the rest of the request */ 2811 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan); 2812 cmd->num_addresses = CPU_TO_LE16(count); 2813 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2814 cmd->seid[1] = 0; 2815 cmd->seid[2] = 0; 2816 2817 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2818 if (buf_size > I40E_AQ_LARGE_BUF) 2819 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2820 2821 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 2822 cmd_details); 2823 2824 return status; 2825 } 2826 2827 /** 2828 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering 2829 * @hw: pointer to the hw struct 2830 * @seid: VSI for the vlan filters 2831 * @v_list: list of vlan filters to be added 2832 * @count: length of the list 2833 * @cmd_details: pointer to command details structure or NULL 2834 **/ 2835 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid, 2836 struct i40e_aqc_add_remove_vlan_element_data *v_list, 2837 u8 count, struct i40e_asq_cmd_details *cmd_details) 2838 { 2839 struct i40e_aq_desc desc; 2840 struct i40e_aqc_macvlan *cmd = 2841 (struct i40e_aqc_macvlan *)&desc.params.raw; 2842 enum i40e_status_code status; 2843 u16 buf_size; 2844 2845 if (count == 0 || !v_list || !hw) 2846 return I40E_ERR_PARAM; 2847 2848 buf_size = count * sizeof(*v_list); 2849 2850 /* prep the rest of the request */ 2851 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan); 2852 cmd->num_addresses = CPU_TO_LE16(count); 2853 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID); 2854 cmd->seid[1] = 0; 2855 cmd->seid[2] = 0; 2856 2857 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2858 if (buf_size > I40E_AQ_LARGE_BUF) 2859 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2860 2861 status = i40e_asq_send_command(hw, &desc, v_list, buf_size, 2862 cmd_details); 2863 2864 return status; 2865 } 2866 2867 /** 2868 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering 2869 * @hw: pointer to the hw struct 2870 * @seid: VSI for the vlan filters 2871 * @v_list: list of macvlans to be removed 2872 * @count: length of the list 2873 * @cmd_details: pointer to command details structure or NULL 2874 **/ 2875 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid, 2876 struct i40e_aqc_add_remove_vlan_element_data *v_list, 2877 u8 count, struct i40e_asq_cmd_details *cmd_details) 2878 { 2879 struct i40e_aq_desc desc; 2880 struct i40e_aqc_macvlan *cmd = 2881 (struct i40e_aqc_macvlan *)&desc.params.raw; 2882 enum i40e_status_code status; 2883 u16 buf_size; 2884 2885 if (count == 0 || !v_list || !hw) 2886 return I40E_ERR_PARAM; 2887 2888 buf_size = count * sizeof(*v_list); 2889 2890 /* prep the rest of the request */ 2891 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan); 2892 cmd->num_addresses = CPU_TO_LE16(count); 2893 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID); 2894 cmd->seid[1] = 0; 2895 cmd->seid[2] = 0; 2896 2897 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2898 if (buf_size > I40E_AQ_LARGE_BUF) 2899 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2900 2901 status = i40e_asq_send_command(hw, &desc, v_list, buf_size, 2902 cmd_details); 2903 2904 return status; 2905 } 2906 2907 /** 2908 * i40e_aq_send_msg_to_vf 2909 * @hw: pointer to the hardware structure 2910 * @vfid: vf id to send msg 2911 * @v_opcode: opcodes for VF-PF communication 2912 * @v_retval: return error code 2913 * @msg: pointer to the msg buffer 2914 * @msglen: msg length 2915 * @cmd_details: pointer to command details 2916 * 2917 * send msg to vf 2918 **/ 2919 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid, 2920 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen, 2921 struct i40e_asq_cmd_details *cmd_details) 2922 { 2923 struct i40e_aq_desc desc; 2924 struct i40e_aqc_pf_vf_message *cmd = 2925 (struct i40e_aqc_pf_vf_message *)&desc.params.raw; 2926 enum i40e_status_code status; 2927 2928 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf); 2929 cmd->id = CPU_TO_LE32(vfid); 2930 desc.cookie_high = CPU_TO_LE32(v_opcode); 2931 desc.cookie_low = CPU_TO_LE32(v_retval); 2932 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI); 2933 if (msglen) { 2934 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | 2935 I40E_AQ_FLAG_RD)); 2936 if (msglen > I40E_AQ_LARGE_BUF) 2937 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2938 desc.datalen = CPU_TO_LE16(msglen); 2939 } 2940 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details); 2941 2942 return status; 2943 } 2944 2945 /** 2946 * i40e_aq_debug_read_register 2947 * @hw: pointer to the hw struct 2948 * @reg_addr: register address 2949 * @reg_val: register value 2950 * @cmd_details: pointer to command details structure or NULL 2951 * 2952 * Read the register using the admin queue commands 2953 **/ 2954 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw, 2955 u32 reg_addr, u64 *reg_val, 2956 struct i40e_asq_cmd_details *cmd_details) 2957 { 2958 struct i40e_aq_desc desc; 2959 struct i40e_aqc_debug_reg_read_write *cmd_resp = 2960 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 2961 enum i40e_status_code status; 2962 2963 if (reg_val == NULL) 2964 return I40E_ERR_PARAM; 2965 2966 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg); 2967 2968 cmd_resp->address = CPU_TO_LE32(reg_addr); 2969 2970 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2971 2972 if (status == I40E_SUCCESS) { 2973 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) | 2974 (u64)LE32_TO_CPU(cmd_resp->value_low); 2975 } 2976 2977 return status; 2978 } 2979 2980 /** 2981 * i40e_aq_debug_write_register 2982 * @hw: pointer to the hw struct 2983 * @reg_addr: register address 2984 * @reg_val: register value 2985 * @cmd_details: pointer to command details structure or NULL 2986 * 2987 * Write to a register using the admin queue commands 2988 **/ 2989 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw, 2990 u32 reg_addr, u64 reg_val, 2991 struct i40e_asq_cmd_details *cmd_details) 2992 { 2993 struct i40e_aq_desc desc; 2994 struct i40e_aqc_debug_reg_read_write *cmd = 2995 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 2996 enum i40e_status_code status; 2997 2998 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg); 2999 3000 cmd->address = CPU_TO_LE32(reg_addr); 3001 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32)); 3002 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF)); 3003 3004 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3005 3006 return status; 3007 } 3008 3009 /** 3010 * i40e_aq_get_hmc_resource_profile 3011 * @hw: pointer to the hw struct 3012 * @profile: type of profile the HMC is to be set as 3013 * @pe_vf_enabled_count: the number of PE enabled VFs the system has 3014 * @cmd_details: pointer to command details structure or NULL 3015 * 3016 * query the HMC profile of the device. 3017 **/ 3018 enum i40e_status_code i40e_aq_get_hmc_resource_profile(struct i40e_hw *hw, 3019 enum i40e_aq_hmc_profile *profile, 3020 u8 *pe_vf_enabled_count, 3021 struct i40e_asq_cmd_details *cmd_details) 3022 { 3023 struct i40e_aq_desc desc; 3024 struct i40e_aq_get_set_hmc_resource_profile *resp = 3025 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw; 3026 enum i40e_status_code status; 3027 3028 i40e_fill_default_direct_cmd_desc(&desc, 3029 i40e_aqc_opc_query_hmc_resource_profile); 3030 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3031 3032 *profile = (enum i40e_aq_hmc_profile)(resp->pm_profile & 3033 I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK); 3034 *pe_vf_enabled_count = resp->pe_vf_enabled & 3035 I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK; 3036 3037 return status; 3038 } 3039 3040 /** 3041 * i40e_aq_set_hmc_resource_profile 3042 * @hw: pointer to the hw struct 3043 * @profile: type of profile the HMC is to be set as 3044 * @pe_vf_enabled_count: the number of PE enabled VFs the system has 3045 * @cmd_details: pointer to command details structure or NULL 3046 * 3047 * set the HMC profile of the device. 3048 **/ 3049 enum i40e_status_code i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw, 3050 enum i40e_aq_hmc_profile profile, 3051 u8 pe_vf_enabled_count, 3052 struct i40e_asq_cmd_details *cmd_details) 3053 { 3054 struct i40e_aq_desc desc; 3055 struct i40e_aq_get_set_hmc_resource_profile *cmd = 3056 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw; 3057 enum i40e_status_code status; 3058 3059 i40e_fill_default_direct_cmd_desc(&desc, 3060 i40e_aqc_opc_set_hmc_resource_profile); 3061 3062 cmd->pm_profile = (u8)profile; 3063 cmd->pe_vf_enabled = pe_vf_enabled_count; 3064 3065 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3066 3067 return status; 3068 } 3069 3070 /** 3071 * i40e_aq_request_resource 3072 * @hw: pointer to the hw struct 3073 * @resource: resource id 3074 * @access: access type 3075 * @sdp_number: resource number 3076 * @timeout: the maximum time in ms that the driver may hold the resource 3077 * @cmd_details: pointer to command details structure or NULL 3078 * 3079 * requests common resource using the admin queue commands 3080 **/ 3081 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw, 3082 enum i40e_aq_resources_ids resource, 3083 enum i40e_aq_resource_access_type access, 3084 u8 sdp_number, u64 *timeout, 3085 struct i40e_asq_cmd_details *cmd_details) 3086 { 3087 struct i40e_aq_desc desc; 3088 struct i40e_aqc_request_resource *cmd_resp = 3089 (struct i40e_aqc_request_resource *)&desc.params.raw; 3090 enum i40e_status_code status; 3091 3092 DEBUGFUNC("i40e_aq_request_resource"); 3093 3094 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource); 3095 3096 cmd_resp->resource_id = CPU_TO_LE16(resource); 3097 cmd_resp->access_type = CPU_TO_LE16(access); 3098 cmd_resp->resource_number = CPU_TO_LE32(sdp_number); 3099 3100 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3101 /* The completion specifies the maximum time in ms that the driver 3102 * may hold the resource in the Timeout field. 3103 * If the resource is held by someone else, the command completes with 3104 * busy return value and the timeout field indicates the maximum time 3105 * the current owner of the resource has to free it. 3106 */ 3107 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) 3108 *timeout = LE32_TO_CPU(cmd_resp->timeout); 3109 3110 return status; 3111 } 3112 3113 /** 3114 * i40e_aq_release_resource 3115 * @hw: pointer to the hw struct 3116 * @resource: resource id 3117 * @sdp_number: resource number 3118 * @cmd_details: pointer to command details structure or NULL 3119 * 3120 * release common resource using the admin queue commands 3121 **/ 3122 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw, 3123 enum i40e_aq_resources_ids resource, 3124 u8 sdp_number, 3125 struct i40e_asq_cmd_details *cmd_details) 3126 { 3127 struct i40e_aq_desc desc; 3128 struct i40e_aqc_request_resource *cmd = 3129 (struct i40e_aqc_request_resource *)&desc.params.raw; 3130 enum i40e_status_code status; 3131 3132 DEBUGFUNC("i40e_aq_release_resource"); 3133 3134 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource); 3135 3136 cmd->resource_id = CPU_TO_LE16(resource); 3137 cmd->resource_number = CPU_TO_LE32(sdp_number); 3138 3139 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3140 3141 return status; 3142 } 3143 3144 /** 3145 * i40e_aq_read_nvm 3146 * @hw: pointer to the hw struct 3147 * @module_pointer: module pointer location in words from the NVM beginning 3148 * @offset: byte offset from the module beginning 3149 * @length: length of the section to be read (in bytes from the offset) 3150 * @data: command buffer (size [bytes] = length) 3151 * @last_command: tells if this is the last command in a series 3152 * @cmd_details: pointer to command details structure or NULL 3153 * 3154 * Read the NVM using the admin queue commands 3155 **/ 3156 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer, 3157 u32 offset, u16 length, void *data, 3158 bool last_command, 3159 struct i40e_asq_cmd_details *cmd_details) 3160 { 3161 struct i40e_aq_desc desc; 3162 struct i40e_aqc_nvm_update *cmd = 3163 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3164 enum i40e_status_code status; 3165 3166 DEBUGFUNC("i40e_aq_read_nvm"); 3167 3168 /* In offset the highest byte must be zeroed. */ 3169 if (offset & 0xFF000000) { 3170 status = I40E_ERR_PARAM; 3171 goto i40e_aq_read_nvm_exit; 3172 } 3173 3174 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read); 3175 3176 /* If this is the last command in a series, set the proper flag. */ 3177 if (last_command) 3178 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3179 cmd->module_pointer = module_pointer; 3180 cmd->offset = CPU_TO_LE32(offset); 3181 cmd->length = CPU_TO_LE16(length); 3182 3183 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 3184 if (length > I40E_AQ_LARGE_BUF) 3185 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3186 3187 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 3188 3189 i40e_aq_read_nvm_exit: 3190 return status; 3191 } 3192 3193 /** 3194 * i40e_aq_read_nvm_config - read an nvm config block 3195 * @hw: pointer to the hw struct 3196 * @cmd_flags: NVM access admin command bits 3197 * @field_id: field or feature id 3198 * @data: buffer for result 3199 * @buf_size: buffer size 3200 * @element_count: pointer to count of elements read by FW 3201 * @cmd_details: pointer to command details structure or NULL 3202 **/ 3203 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw, 3204 u8 cmd_flags, u32 field_id, void *data, 3205 u16 buf_size, u16 *element_count, 3206 struct i40e_asq_cmd_details *cmd_details) 3207 { 3208 struct i40e_aq_desc desc; 3209 struct i40e_aqc_nvm_config_read *cmd = 3210 (struct i40e_aqc_nvm_config_read *)&desc.params.raw; 3211 enum i40e_status_code status; 3212 3213 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read); 3214 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF)); 3215 if (buf_size > I40E_AQ_LARGE_BUF) 3216 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3217 3218 cmd->cmd_flags = CPU_TO_LE16(cmd_flags); 3219 cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id)); 3220 if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK) 3221 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16)); 3222 else 3223 cmd->element_id_msw = 0; 3224 3225 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details); 3226 3227 if (!status && element_count) 3228 *element_count = LE16_TO_CPU(cmd->element_count); 3229 3230 return status; 3231 } 3232 3233 /** 3234 * i40e_aq_write_nvm_config - write an nvm config block 3235 * @hw: pointer to the hw struct 3236 * @cmd_flags: NVM access admin command bits 3237 * @data: buffer for result 3238 * @buf_size: buffer size 3239 * @element_count: count of elements to be written 3240 * @cmd_details: pointer to command details structure or NULL 3241 **/ 3242 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw, 3243 u8 cmd_flags, void *data, u16 buf_size, 3244 u16 element_count, 3245 struct i40e_asq_cmd_details *cmd_details) 3246 { 3247 struct i40e_aq_desc desc; 3248 struct i40e_aqc_nvm_config_write *cmd = 3249 (struct i40e_aqc_nvm_config_write *)&desc.params.raw; 3250 enum i40e_status_code status; 3251 3252 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write); 3253 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3254 if (buf_size > I40E_AQ_LARGE_BUF) 3255 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3256 3257 cmd->element_count = CPU_TO_LE16(element_count); 3258 cmd->cmd_flags = CPU_TO_LE16(cmd_flags); 3259 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details); 3260 3261 return status; 3262 } 3263 3264 /** 3265 * i40e_aq_oem_post_update - triggers an OEM specific flow after update 3266 * @hw: pointer to the hw struct 3267 * @cmd_details: pointer to command details structure or NULL 3268 **/ 3269 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw, 3270 void *buff, u16 buff_size, 3271 struct i40e_asq_cmd_details *cmd_details) 3272 { 3273 struct i40e_aq_desc desc; 3274 enum i40e_status_code status; 3275 3276 3277 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update); 3278 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3279 if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH) 3280 status = I40E_ERR_NOT_IMPLEMENTED; 3281 3282 return status; 3283 } 3284 3285 /** 3286 * i40e_aq_erase_nvm 3287 * @hw: pointer to the hw struct 3288 * @module_pointer: module pointer location in words from the NVM beginning 3289 * @offset: offset in the module (expressed in 4 KB from module's beginning) 3290 * @length: length of the section to be erased (expressed in 4 KB) 3291 * @last_command: tells if this is the last command in a series 3292 * @cmd_details: pointer to command details structure or NULL 3293 * 3294 * Erase the NVM sector using the admin queue commands 3295 **/ 3296 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer, 3297 u32 offset, u16 length, bool last_command, 3298 struct i40e_asq_cmd_details *cmd_details) 3299 { 3300 struct i40e_aq_desc desc; 3301 struct i40e_aqc_nvm_update *cmd = 3302 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3303 enum i40e_status_code status; 3304 3305 DEBUGFUNC("i40e_aq_erase_nvm"); 3306 3307 /* In offset the highest byte must be zeroed. */ 3308 if (offset & 0xFF000000) { 3309 status = I40E_ERR_PARAM; 3310 goto i40e_aq_erase_nvm_exit; 3311 } 3312 3313 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase); 3314 3315 /* If this is the last command in a series, set the proper flag. */ 3316 if (last_command) 3317 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3318 cmd->module_pointer = module_pointer; 3319 cmd->offset = CPU_TO_LE32(offset); 3320 cmd->length = CPU_TO_LE16(length); 3321 3322 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3323 3324 i40e_aq_erase_nvm_exit: 3325 return status; 3326 } 3327 3328 #define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01 3329 #define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02 3330 #define I40E_DEV_FUNC_CAP_NPAR 0x03 3331 #define I40E_DEV_FUNC_CAP_OS2BMC 0x04 3332 #define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05 3333 #define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12 3334 #define I40E_DEV_FUNC_CAP_VF 0x13 3335 #define I40E_DEV_FUNC_CAP_VMDQ 0x14 3336 #define I40E_DEV_FUNC_CAP_802_1_QBG 0x15 3337 #define I40E_DEV_FUNC_CAP_802_1_QBH 0x16 3338 #define I40E_DEV_FUNC_CAP_VSI 0x17 3339 #define I40E_DEV_FUNC_CAP_DCB 0x18 3340 #define I40E_DEV_FUNC_CAP_FCOE 0x21 3341 #define I40E_DEV_FUNC_CAP_ISCSI 0x22 3342 #define I40E_DEV_FUNC_CAP_RSS 0x40 3343 #define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41 3344 #define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42 3345 #define I40E_DEV_FUNC_CAP_MSIX 0x43 3346 #define I40E_DEV_FUNC_CAP_MSIX_VF 0x44 3347 #define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45 3348 #define I40E_DEV_FUNC_CAP_IEEE_1588 0x46 3349 #define I40E_DEV_FUNC_CAP_FLEX10 0xF1 3350 #define I40E_DEV_FUNC_CAP_CEM 0xF2 3351 #define I40E_DEV_FUNC_CAP_IWARP 0x51 3352 #define I40E_DEV_FUNC_CAP_LED 0x61 3353 #define I40E_DEV_FUNC_CAP_SDP 0x62 3354 #define I40E_DEV_FUNC_CAP_MDIO 0x63 3355 #define I40E_DEV_FUNC_CAP_WR_CSR_PROT 0x64 3356 3357 /** 3358 * i40e_parse_discover_capabilities 3359 * @hw: pointer to the hw struct 3360 * @buff: pointer to a buffer containing device/function capability records 3361 * @cap_count: number of capability records in the list 3362 * @list_type_opc: type of capabilities list to parse 3363 * 3364 * Parse the device/function capabilities list. 3365 **/ 3366 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff, 3367 u32 cap_count, 3368 enum i40e_admin_queue_opc list_type_opc) 3369 { 3370 struct i40e_aqc_list_capabilities_element_resp *cap; 3371 u32 valid_functions, num_functions; 3372 u32 number, logical_id, phys_id; 3373 struct i40e_hw_capabilities *p; 3374 u8 major_rev; 3375 u32 i = 0; 3376 u16 id; 3377 3378 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff; 3379 3380 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities) 3381 p = (struct i40e_hw_capabilities *)&hw->dev_caps; 3382 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities) 3383 p = (struct i40e_hw_capabilities *)&hw->func_caps; 3384 else 3385 return; 3386 3387 for (i = 0; i < cap_count; i++, cap++) { 3388 id = LE16_TO_CPU(cap->id); 3389 number = LE32_TO_CPU(cap->number); 3390 logical_id = LE32_TO_CPU(cap->logical_id); 3391 phys_id = LE32_TO_CPU(cap->phys_id); 3392 major_rev = cap->major_rev; 3393 3394 switch (id) { 3395 case I40E_DEV_FUNC_CAP_SWITCH_MODE: 3396 p->switch_mode = number; 3397 break; 3398 case I40E_DEV_FUNC_CAP_MGMT_MODE: 3399 p->management_mode = number; 3400 break; 3401 case I40E_DEV_FUNC_CAP_NPAR: 3402 p->npar_enable = number; 3403 break; 3404 case I40E_DEV_FUNC_CAP_OS2BMC: 3405 p->os2bmc = number; 3406 break; 3407 case I40E_DEV_FUNC_CAP_VALID_FUNC: 3408 p->valid_functions = number; 3409 break; 3410 case I40E_DEV_FUNC_CAP_SRIOV_1_1: 3411 if (number == 1) 3412 p->sr_iov_1_1 = TRUE; 3413 break; 3414 case I40E_DEV_FUNC_CAP_VF: 3415 p->num_vfs = number; 3416 p->vf_base_id = logical_id; 3417 break; 3418 case I40E_DEV_FUNC_CAP_VMDQ: 3419 if (number == 1) 3420 p->vmdq = TRUE; 3421 break; 3422 case I40E_DEV_FUNC_CAP_802_1_QBG: 3423 if (number == 1) 3424 p->evb_802_1_qbg = TRUE; 3425 break; 3426 case I40E_DEV_FUNC_CAP_802_1_QBH: 3427 if (number == 1) 3428 p->evb_802_1_qbh = TRUE; 3429 break; 3430 case I40E_DEV_FUNC_CAP_VSI: 3431 p->num_vsis = number; 3432 break; 3433 case I40E_DEV_FUNC_CAP_DCB: 3434 if (number == 1) { 3435 p->dcb = TRUE; 3436 p->enabled_tcmap = logical_id; 3437 p->maxtc = phys_id; 3438 } 3439 break; 3440 case I40E_DEV_FUNC_CAP_FCOE: 3441 if (number == 1) 3442 p->fcoe = TRUE; 3443 break; 3444 case I40E_DEV_FUNC_CAP_ISCSI: 3445 if (number == 1) 3446 p->iscsi = TRUE; 3447 break; 3448 case I40E_DEV_FUNC_CAP_RSS: 3449 p->rss = TRUE; 3450 p->rss_table_size = number; 3451 p->rss_table_entry_width = logical_id; 3452 break; 3453 case I40E_DEV_FUNC_CAP_RX_QUEUES: 3454 p->num_rx_qp = number; 3455 p->base_queue = phys_id; 3456 break; 3457 case I40E_DEV_FUNC_CAP_TX_QUEUES: 3458 p->num_tx_qp = number; 3459 p->base_queue = phys_id; 3460 break; 3461 case I40E_DEV_FUNC_CAP_MSIX: 3462 p->num_msix_vectors = number; 3463 break; 3464 case I40E_DEV_FUNC_CAP_MSIX_VF: 3465 p->num_msix_vectors_vf = number; 3466 break; 3467 case I40E_DEV_FUNC_CAP_FLEX10: 3468 if (major_rev == 1) { 3469 if (number == 1) { 3470 p->flex10_enable = TRUE; 3471 p->flex10_capable = TRUE; 3472 } 3473 } else { 3474 /* Capability revision >= 2 */ 3475 if (number & 1) 3476 p->flex10_enable = TRUE; 3477 if (number & 2) 3478 p->flex10_capable = TRUE; 3479 } 3480 p->flex10_mode = logical_id; 3481 p->flex10_status = phys_id; 3482 break; 3483 case I40E_DEV_FUNC_CAP_CEM: 3484 if (number == 1) 3485 p->mgmt_cem = TRUE; 3486 break; 3487 case I40E_DEV_FUNC_CAP_IWARP: 3488 if (number == 1) 3489 p->iwarp = TRUE; 3490 break; 3491 case I40E_DEV_FUNC_CAP_LED: 3492 if (phys_id < I40E_HW_CAP_MAX_GPIO) 3493 p->led[phys_id] = TRUE; 3494 break; 3495 case I40E_DEV_FUNC_CAP_SDP: 3496 if (phys_id < I40E_HW_CAP_MAX_GPIO) 3497 p->sdp[phys_id] = TRUE; 3498 break; 3499 case I40E_DEV_FUNC_CAP_MDIO: 3500 if (number == 1) { 3501 p->mdio_port_num = phys_id; 3502 p->mdio_port_mode = logical_id; 3503 } 3504 break; 3505 case I40E_DEV_FUNC_CAP_IEEE_1588: 3506 if (number == 1) 3507 p->ieee_1588 = TRUE; 3508 break; 3509 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR: 3510 p->fd = TRUE; 3511 p->fd_filters_guaranteed = number; 3512 p->fd_filters_best_effort = logical_id; 3513 break; 3514 case I40E_DEV_FUNC_CAP_WR_CSR_PROT: 3515 p->wr_csr_prot = (u64)number; 3516 p->wr_csr_prot |= (u64)logical_id << 32; 3517 break; 3518 default: 3519 break; 3520 } 3521 } 3522 3523 if (p->fcoe) 3524 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n"); 3525 3526 /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */ 3527 p->fcoe = FALSE; 3528 3529 /* count the enabled ports (aka the "not disabled" ports) */ 3530 hw->num_ports = 0; 3531 for (i = 0; i < 4; i++) { 3532 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i); 3533 u64 port_cfg = 0; 3534 3535 /* use AQ read to get the physical register offset instead 3536 * of the port relative offset 3537 */ 3538 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL); 3539 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK)) 3540 hw->num_ports++; 3541 } 3542 3543 valid_functions = p->valid_functions; 3544 num_functions = 0; 3545 while (valid_functions) { 3546 if (valid_functions & 1) 3547 num_functions++; 3548 valid_functions >>= 1; 3549 } 3550 3551 /* partition id is 1-based, and functions are evenly spread 3552 * across the ports as partitions 3553 */ 3554 hw->partition_id = (hw->pf_id / hw->num_ports) + 1; 3555 hw->num_partitions = num_functions / hw->num_ports; 3556 3557 /* additional HW specific goodies that might 3558 * someday be HW version specific 3559 */ 3560 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS; 3561 } 3562 3563 /** 3564 * i40e_aq_discover_capabilities 3565 * @hw: pointer to the hw struct 3566 * @buff: a virtual buffer to hold the capabilities 3567 * @buff_size: Size of the virtual buffer 3568 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM 3569 * @list_type_opc: capabilities type to discover - pass in the command opcode 3570 * @cmd_details: pointer to command details structure or NULL 3571 * 3572 * Get the device capabilities descriptions from the firmware 3573 **/ 3574 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw, 3575 void *buff, u16 buff_size, u16 *data_size, 3576 enum i40e_admin_queue_opc list_type_opc, 3577 struct i40e_asq_cmd_details *cmd_details) 3578 { 3579 struct i40e_aqc_list_capabilites *cmd; 3580 struct i40e_aq_desc desc; 3581 enum i40e_status_code status = I40E_SUCCESS; 3582 3583 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw; 3584 3585 if (list_type_opc != i40e_aqc_opc_list_func_capabilities && 3586 list_type_opc != i40e_aqc_opc_list_dev_capabilities) { 3587 status = I40E_ERR_PARAM; 3588 goto exit; 3589 } 3590 3591 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc); 3592 3593 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 3594 if (buff_size > I40E_AQ_LARGE_BUF) 3595 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3596 3597 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3598 *data_size = LE16_TO_CPU(desc.datalen); 3599 3600 if (status) 3601 goto exit; 3602 3603 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count), 3604 list_type_opc); 3605 3606 exit: 3607 return status; 3608 } 3609 3610 /** 3611 * i40e_aq_update_nvm 3612 * @hw: pointer to the hw struct 3613 * @module_pointer: module pointer location in words from the NVM beginning 3614 * @offset: byte offset from the module beginning 3615 * @length: length of the section to be written (in bytes from the offset) 3616 * @data: command buffer (size [bytes] = length) 3617 * @last_command: tells if this is the last command in a series 3618 * @cmd_details: pointer to command details structure or NULL 3619 * 3620 * Update the NVM using the admin queue commands 3621 **/ 3622 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer, 3623 u32 offset, u16 length, void *data, 3624 bool last_command, 3625 struct i40e_asq_cmd_details *cmd_details) 3626 { 3627 struct i40e_aq_desc desc; 3628 struct i40e_aqc_nvm_update *cmd = 3629 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3630 enum i40e_status_code status; 3631 3632 DEBUGFUNC("i40e_aq_update_nvm"); 3633 3634 /* In offset the highest byte must be zeroed. */ 3635 if (offset & 0xFF000000) { 3636 status = I40E_ERR_PARAM; 3637 goto i40e_aq_update_nvm_exit; 3638 } 3639 3640 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update); 3641 3642 /* If this is the last command in a series, set the proper flag. */ 3643 if (last_command) 3644 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3645 cmd->module_pointer = module_pointer; 3646 cmd->offset = CPU_TO_LE32(offset); 3647 cmd->length = CPU_TO_LE16(length); 3648 3649 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3650 if (length > I40E_AQ_LARGE_BUF) 3651 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3652 3653 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 3654 3655 i40e_aq_update_nvm_exit: 3656 return status; 3657 } 3658 3659 /** 3660 * i40e_aq_get_lldp_mib 3661 * @hw: pointer to the hw struct 3662 * @bridge_type: type of bridge requested 3663 * @mib_type: Local, Remote or both Local and Remote MIBs 3664 * @buff: pointer to a user supplied buffer to store the MIB block 3665 * @buff_size: size of the buffer (in bytes) 3666 * @local_len : length of the returned Local LLDP MIB 3667 * @remote_len: length of the returned Remote LLDP MIB 3668 * @cmd_details: pointer to command details structure or NULL 3669 * 3670 * Requests the complete LLDP MIB (entire packet). 3671 **/ 3672 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type, 3673 u8 mib_type, void *buff, u16 buff_size, 3674 u16 *local_len, u16 *remote_len, 3675 struct i40e_asq_cmd_details *cmd_details) 3676 { 3677 struct i40e_aq_desc desc; 3678 struct i40e_aqc_lldp_get_mib *cmd = 3679 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 3680 struct i40e_aqc_lldp_get_mib *resp = 3681 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 3682 enum i40e_status_code status; 3683 3684 if (buff_size == 0 || !buff) 3685 return I40E_ERR_PARAM; 3686 3687 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib); 3688 /* Indirect Command */ 3689 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 3690 3691 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK; 3692 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 3693 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 3694 3695 desc.datalen = CPU_TO_LE16(buff_size); 3696 3697 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 3698 if (buff_size > I40E_AQ_LARGE_BUF) 3699 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3700 3701 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3702 if (!status) { 3703 if (local_len != NULL) 3704 *local_len = LE16_TO_CPU(resp->local_len); 3705 if (remote_len != NULL) 3706 *remote_len = LE16_TO_CPU(resp->remote_len); 3707 } 3708 3709 return status; 3710 } 3711 3712 /** 3713 * i40e_aq_set_lldp_mib - Set the LLDP MIB 3714 * @hw: pointer to the hw struct 3715 * @mib_type: Local, Remote or both Local and Remote MIBs 3716 * @buff: pointer to a user supplied buffer to store the MIB block 3717 * @buff_size: size of the buffer (in bytes) 3718 * @cmd_details: pointer to command details structure or NULL 3719 * 3720 * Set the LLDP MIB. 3721 **/ 3722 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw, 3723 u8 mib_type, void *buff, u16 buff_size, 3724 struct i40e_asq_cmd_details *cmd_details) 3725 { 3726 struct i40e_aq_desc desc; 3727 struct i40e_aqc_lldp_set_local_mib *cmd = 3728 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw; 3729 enum i40e_status_code status; 3730 3731 if (buff_size == 0 || !buff) 3732 return I40E_ERR_PARAM; 3733 3734 i40e_fill_default_direct_cmd_desc(&desc, 3735 i40e_aqc_opc_lldp_set_local_mib); 3736 /* Indirect Command */ 3737 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3738 if (buff_size > I40E_AQ_LARGE_BUF) 3739 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3740 desc.datalen = CPU_TO_LE16(buff_size); 3741 3742 cmd->type = mib_type; 3743 cmd->length = CPU_TO_LE16(buff_size); 3744 cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((uintptr_t)buff)); 3745 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((uintptr_t)buff)); 3746 3747 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3748 return status; 3749 } 3750 3751 /** 3752 * i40e_aq_cfg_lldp_mib_change_event 3753 * @hw: pointer to the hw struct 3754 * @enable_update: Enable or Disable event posting 3755 * @cmd_details: pointer to command details structure or NULL 3756 * 3757 * Enable or Disable posting of an event on ARQ when LLDP MIB 3758 * associated with the interface changes 3759 **/ 3760 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw, 3761 bool enable_update, 3762 struct i40e_asq_cmd_details *cmd_details) 3763 { 3764 struct i40e_aq_desc desc; 3765 struct i40e_aqc_lldp_update_mib *cmd = 3766 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw; 3767 enum i40e_status_code status; 3768 3769 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib); 3770 3771 if (!enable_update) 3772 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE; 3773 3774 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3775 3776 return status; 3777 } 3778 3779 /** 3780 * i40e_aq_add_lldp_tlv 3781 * @hw: pointer to the hw struct 3782 * @bridge_type: type of bridge 3783 * @buff: buffer with TLV to add 3784 * @buff_size: length of the buffer 3785 * @tlv_len: length of the TLV to be added 3786 * @mib_len: length of the LLDP MIB returned in response 3787 * @cmd_details: pointer to command details structure or NULL 3788 * 3789 * Add the specified TLV to LLDP Local MIB for the given bridge type, 3790 * it is responsibility of the caller to make sure that the TLV is not 3791 * already present in the LLDPDU. 3792 * In return firmware will write the complete LLDP MIB with the newly 3793 * added TLV in the response buffer. 3794 **/ 3795 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type, 3796 void *buff, u16 buff_size, u16 tlv_len, 3797 u16 *mib_len, 3798 struct i40e_asq_cmd_details *cmd_details) 3799 { 3800 struct i40e_aq_desc desc; 3801 struct i40e_aqc_lldp_add_tlv *cmd = 3802 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw; 3803 enum i40e_status_code status; 3804 3805 if (buff_size == 0 || !buff || tlv_len == 0) 3806 return I40E_ERR_PARAM; 3807 3808 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv); 3809 3810 /* Indirect Command */ 3811 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3812 if (buff_size > I40E_AQ_LARGE_BUF) 3813 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3814 desc.datalen = CPU_TO_LE16(buff_size); 3815 3816 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 3817 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 3818 cmd->len = CPU_TO_LE16(tlv_len); 3819 3820 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3821 if (!status) { 3822 if (mib_len != NULL) 3823 *mib_len = LE16_TO_CPU(desc.datalen); 3824 } 3825 3826 return status; 3827 } 3828 3829 /** 3830 * i40e_aq_update_lldp_tlv 3831 * @hw: pointer to the hw struct 3832 * @bridge_type: type of bridge 3833 * @buff: buffer with TLV to update 3834 * @buff_size: size of the buffer holding original and updated TLVs 3835 * @old_len: Length of the Original TLV 3836 * @new_len: Length of the Updated TLV 3837 * @offset: offset of the updated TLV in the buff 3838 * @mib_len: length of the returned LLDP MIB 3839 * @cmd_details: pointer to command details structure or NULL 3840 * 3841 * Update the specified TLV to the LLDP Local MIB for the given bridge type. 3842 * Firmware will place the complete LLDP MIB in response buffer with the 3843 * updated TLV. 3844 **/ 3845 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw, 3846 u8 bridge_type, void *buff, u16 buff_size, 3847 u16 old_len, u16 new_len, u16 offset, 3848 u16 *mib_len, 3849 struct i40e_asq_cmd_details *cmd_details) 3850 { 3851 struct i40e_aq_desc desc; 3852 struct i40e_aqc_lldp_update_tlv *cmd = 3853 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw; 3854 enum i40e_status_code status; 3855 3856 if (buff_size == 0 || !buff || offset == 0 || 3857 old_len == 0 || new_len == 0) 3858 return I40E_ERR_PARAM; 3859 3860 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv); 3861 3862 /* Indirect Command */ 3863 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3864 if (buff_size > I40E_AQ_LARGE_BUF) 3865 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3866 desc.datalen = CPU_TO_LE16(buff_size); 3867 3868 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 3869 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 3870 cmd->old_len = CPU_TO_LE16(old_len); 3871 cmd->new_offset = CPU_TO_LE16(offset); 3872 cmd->new_len = CPU_TO_LE16(new_len); 3873 3874 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3875 if (!status) { 3876 if (mib_len != NULL) 3877 *mib_len = LE16_TO_CPU(desc.datalen); 3878 } 3879 3880 return status; 3881 } 3882 3883 /** 3884 * i40e_aq_delete_lldp_tlv 3885 * @hw: pointer to the hw struct 3886 * @bridge_type: type of bridge 3887 * @buff: pointer to a user supplied buffer that has the TLV 3888 * @buff_size: length of the buffer 3889 * @tlv_len: length of the TLV to be deleted 3890 * @mib_len: length of the returned LLDP MIB 3891 * @cmd_details: pointer to command details structure or NULL 3892 * 3893 * Delete the specified TLV from LLDP Local MIB for the given bridge type. 3894 * The firmware places the entire LLDP MIB in the response buffer. 3895 **/ 3896 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw, 3897 u8 bridge_type, void *buff, u16 buff_size, 3898 u16 tlv_len, u16 *mib_len, 3899 struct i40e_asq_cmd_details *cmd_details) 3900 { 3901 struct i40e_aq_desc desc; 3902 struct i40e_aqc_lldp_add_tlv *cmd = 3903 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw; 3904 enum i40e_status_code status; 3905 3906 if (buff_size == 0 || !buff) 3907 return I40E_ERR_PARAM; 3908 3909 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv); 3910 3911 /* Indirect Command */ 3912 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3913 if (buff_size > I40E_AQ_LARGE_BUF) 3914 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3915 desc.datalen = CPU_TO_LE16(buff_size); 3916 cmd->len = CPU_TO_LE16(tlv_len); 3917 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 3918 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 3919 3920 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3921 if (!status) { 3922 if (mib_len != NULL) 3923 *mib_len = LE16_TO_CPU(desc.datalen); 3924 } 3925 3926 return status; 3927 } 3928 3929 /** 3930 * i40e_aq_stop_lldp 3931 * @hw: pointer to the hw struct 3932 * @shutdown_agent: True if LLDP Agent needs to be Shutdown 3933 * @cmd_details: pointer to command details structure or NULL 3934 * 3935 * Stop or Shutdown the embedded LLDP Agent 3936 **/ 3937 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent, 3938 struct i40e_asq_cmd_details *cmd_details) 3939 { 3940 struct i40e_aq_desc desc; 3941 struct i40e_aqc_lldp_stop *cmd = 3942 (struct i40e_aqc_lldp_stop *)&desc.params.raw; 3943 enum i40e_status_code status; 3944 3945 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop); 3946 3947 if (shutdown_agent) 3948 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN; 3949 3950 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3951 3952 return status; 3953 } 3954 3955 /** 3956 * i40e_aq_start_lldp 3957 * @hw: pointer to the hw struct 3958 * @cmd_details: pointer to command details structure or NULL 3959 * 3960 * Start the embedded LLDP Agent on all ports. 3961 **/ 3962 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw, 3963 struct i40e_asq_cmd_details *cmd_details) 3964 { 3965 struct i40e_aq_desc desc; 3966 struct i40e_aqc_lldp_start *cmd = 3967 (struct i40e_aqc_lldp_start *)&desc.params.raw; 3968 enum i40e_status_code status; 3969 3970 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start); 3971 3972 cmd->command = I40E_AQ_LLDP_AGENT_START; 3973 3974 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3975 3976 return status; 3977 } 3978 3979 /** 3980 * i40e_aq_get_cee_dcb_config 3981 * @hw: pointer to the hw struct 3982 * @buff: response buffer that stores CEE operational configuration 3983 * @buff_size: size of the buffer passed 3984 * @cmd_details: pointer to command details structure or NULL 3985 * 3986 * Get CEE DCBX mode operational configuration from firmware 3987 **/ 3988 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw, 3989 void *buff, u16 buff_size, 3990 struct i40e_asq_cmd_details *cmd_details) 3991 { 3992 struct i40e_aq_desc desc; 3993 enum i40e_status_code status; 3994 3995 if (buff_size == 0 || !buff) 3996 return I40E_ERR_PARAM; 3997 3998 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg); 3999 4000 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4001 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size, 4002 cmd_details); 4003 4004 return status; 4005 } 4006 4007 /** 4008 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW 4009 * @hw: pointer to the hw struct 4010 * @start_agent: True if DCBx Agent needs to be Started 4011 * False if DCBx Agent needs to be Stopped 4012 * @cmd_details: pointer to command details structure or NULL 4013 * 4014 * Start/Stop the embedded dcbx Agent 4015 **/ 4016 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw, 4017 bool start_agent, 4018 struct i40e_asq_cmd_details *cmd_details) 4019 { 4020 struct i40e_aq_desc desc; 4021 struct i40e_aqc_lldp_stop_start_specific_agent *cmd = 4022 (struct i40e_aqc_lldp_stop_start_specific_agent *) 4023 &desc.params.raw; 4024 enum i40e_status_code status; 4025 4026 i40e_fill_default_direct_cmd_desc(&desc, 4027 i40e_aqc_opc_lldp_stop_start_spec_agent); 4028 4029 if (start_agent) 4030 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK; 4031 4032 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4033 4034 return status; 4035 } 4036 4037 /** 4038 * i40e_aq_add_udp_tunnel 4039 * @hw: pointer to the hw struct 4040 * @udp_port: the UDP port to add 4041 * @header_len: length of the tunneling header length in DWords 4042 * @protocol_index: protocol index type 4043 * @filter_index: pointer to filter index 4044 * @cmd_details: pointer to command details structure or NULL 4045 **/ 4046 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw, 4047 u16 udp_port, u8 protocol_index, 4048 u8 *filter_index, 4049 struct i40e_asq_cmd_details *cmd_details) 4050 { 4051 struct i40e_aq_desc desc; 4052 struct i40e_aqc_add_udp_tunnel *cmd = 4053 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw; 4054 struct i40e_aqc_del_udp_tunnel_completion *resp = 4055 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw; 4056 enum i40e_status_code status; 4057 4058 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel); 4059 4060 cmd->udp_port = CPU_TO_LE16(udp_port); 4061 cmd->protocol_type = protocol_index; 4062 4063 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4064 4065 if (!status && filter_index) 4066 *filter_index = resp->index; 4067 4068 return status; 4069 } 4070 4071 /** 4072 * i40e_aq_del_udp_tunnel 4073 * @hw: pointer to the hw struct 4074 * @index: filter index 4075 * @cmd_details: pointer to command details structure or NULL 4076 **/ 4077 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index, 4078 struct i40e_asq_cmd_details *cmd_details) 4079 { 4080 struct i40e_aq_desc desc; 4081 struct i40e_aqc_remove_udp_tunnel *cmd = 4082 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw; 4083 enum i40e_status_code status; 4084 4085 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel); 4086 4087 cmd->index = index; 4088 4089 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4090 4091 return status; 4092 } 4093 4094 /** 4095 * i40e_aq_get_switch_resource_alloc (0x0204) 4096 * @hw: pointer to the hw struct 4097 * @num_entries: pointer to u8 to store the number of resource entries returned 4098 * @buf: pointer to a user supplied buffer. This buffer must be large enough 4099 * to store the resource information for all resource types. Each 4100 * resource type is a i40e_aqc_switch_resource_alloc_data structure. 4101 * @count: size, in bytes, of the buffer provided 4102 * @cmd_details: pointer to command details structure or NULL 4103 * 4104 * Query the resources allocated to a function. 4105 **/ 4106 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw, 4107 u8 *num_entries, 4108 struct i40e_aqc_switch_resource_alloc_element_resp *buf, 4109 u16 count, 4110 struct i40e_asq_cmd_details *cmd_details) 4111 { 4112 struct i40e_aq_desc desc; 4113 struct i40e_aqc_get_switch_resource_alloc *cmd_resp = 4114 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw; 4115 enum i40e_status_code status; 4116 u16 length = count * sizeof(*buf); 4117 4118 i40e_fill_default_direct_cmd_desc(&desc, 4119 i40e_aqc_opc_get_switch_resource_alloc); 4120 4121 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4122 if (length > I40E_AQ_LARGE_BUF) 4123 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4124 4125 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details); 4126 4127 if (!status && num_entries) 4128 *num_entries = cmd_resp->num_entries; 4129 4130 return status; 4131 } 4132 4133 /** 4134 * i40e_aq_delete_element - Delete switch element 4135 * @hw: pointer to the hw struct 4136 * @seid: the SEID to delete from the switch 4137 * @cmd_details: pointer to command details structure or NULL 4138 * 4139 * This deletes a switch element from the switch. 4140 **/ 4141 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid, 4142 struct i40e_asq_cmd_details *cmd_details) 4143 { 4144 struct i40e_aq_desc desc; 4145 struct i40e_aqc_switch_seid *cmd = 4146 (struct i40e_aqc_switch_seid *)&desc.params.raw; 4147 enum i40e_status_code status; 4148 4149 if (seid == 0) 4150 return I40E_ERR_PARAM; 4151 4152 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element); 4153 4154 cmd->seid = CPU_TO_LE16(seid); 4155 4156 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4157 4158 return status; 4159 } 4160 4161 /** 4162 * i40_aq_add_pvirt - Instantiate a Port Virtualizer on a port 4163 * @hw: pointer to the hw struct 4164 * @flags: component flags 4165 * @mac_seid: uplink seid (MAC SEID) 4166 * @vsi_seid: connected vsi seid 4167 * @ret_seid: seid of create pv component 4168 * 4169 * This instantiates an i40e port virtualizer with specified flags. 4170 * Depending on specified flags the port virtualizer can act as a 4171 * 802.1Qbr port virtualizer or a 802.1Qbg S-component. 4172 */ 4173 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags, 4174 u16 mac_seid, u16 vsi_seid, 4175 u16 *ret_seid) 4176 { 4177 struct i40e_aq_desc desc; 4178 struct i40e_aqc_add_update_pv *cmd = 4179 (struct i40e_aqc_add_update_pv *)&desc.params.raw; 4180 struct i40e_aqc_add_update_pv_completion *resp = 4181 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw; 4182 enum i40e_status_code status; 4183 4184 if (vsi_seid == 0) 4185 return I40E_ERR_PARAM; 4186 4187 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv); 4188 cmd->command_flags = CPU_TO_LE16(flags); 4189 cmd->uplink_seid = CPU_TO_LE16(mac_seid); 4190 cmd->connected_seid = CPU_TO_LE16(vsi_seid); 4191 4192 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 4193 if (!status && ret_seid) 4194 *ret_seid = LE16_TO_CPU(resp->pv_seid); 4195 4196 return status; 4197 } 4198 4199 /** 4200 * i40e_aq_add_tag - Add an S/E-tag 4201 * @hw: pointer to the hw struct 4202 * @direct_to_queue: should s-tag direct flow to a specific queue 4203 * @vsi_seid: VSI SEID to use this tag 4204 * @tag: value of the tag 4205 * @queue_num: queue number, only valid is direct_to_queue is TRUE 4206 * @tags_used: return value, number of tags in use by this PF 4207 * @tags_free: return value, number of unallocated tags 4208 * @cmd_details: pointer to command details structure or NULL 4209 * 4210 * This associates an S- or E-tag to a VSI in the switch complex. It returns 4211 * the number of tags allocated by the PF, and the number of unallocated 4212 * tags available. 4213 **/ 4214 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue, 4215 u16 vsi_seid, u16 tag, u16 queue_num, 4216 u16 *tags_used, u16 *tags_free, 4217 struct i40e_asq_cmd_details *cmd_details) 4218 { 4219 struct i40e_aq_desc desc; 4220 struct i40e_aqc_add_tag *cmd = 4221 (struct i40e_aqc_add_tag *)&desc.params.raw; 4222 struct i40e_aqc_add_remove_tag_completion *resp = 4223 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw; 4224 enum i40e_status_code status; 4225 4226 if (vsi_seid == 0) 4227 return I40E_ERR_PARAM; 4228 4229 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag); 4230 4231 cmd->seid = CPU_TO_LE16(vsi_seid); 4232 cmd->tag = CPU_TO_LE16(tag); 4233 if (direct_to_queue) { 4234 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE); 4235 cmd->queue_number = CPU_TO_LE16(queue_num); 4236 } 4237 4238 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4239 4240 if (!status) { 4241 if (tags_used != NULL) 4242 *tags_used = LE16_TO_CPU(resp->tags_used); 4243 if (tags_free != NULL) 4244 *tags_free = LE16_TO_CPU(resp->tags_free); 4245 } 4246 4247 return status; 4248 } 4249 4250 /** 4251 * i40e_aq_remove_tag - Remove an S- or E-tag 4252 * @hw: pointer to the hw struct 4253 * @vsi_seid: VSI SEID this tag is associated with 4254 * @tag: value of the S-tag to delete 4255 * @tags_used: return value, number of tags in use by this PF 4256 * @tags_free: return value, number of unallocated tags 4257 * @cmd_details: pointer to command details structure or NULL 4258 * 4259 * This deletes an S- or E-tag from a VSI in the switch complex. It returns 4260 * the number of tags allocated by the PF, and the number of unallocated 4261 * tags available. 4262 **/ 4263 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid, 4264 u16 tag, u16 *tags_used, u16 *tags_free, 4265 struct i40e_asq_cmd_details *cmd_details) 4266 { 4267 struct i40e_aq_desc desc; 4268 struct i40e_aqc_remove_tag *cmd = 4269 (struct i40e_aqc_remove_tag *)&desc.params.raw; 4270 struct i40e_aqc_add_remove_tag_completion *resp = 4271 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw; 4272 enum i40e_status_code status; 4273 4274 if (vsi_seid == 0) 4275 return I40E_ERR_PARAM; 4276 4277 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag); 4278 4279 cmd->seid = CPU_TO_LE16(vsi_seid); 4280 cmd->tag = CPU_TO_LE16(tag); 4281 4282 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4283 4284 if (!status) { 4285 if (tags_used != NULL) 4286 *tags_used = LE16_TO_CPU(resp->tags_used); 4287 if (tags_free != NULL) 4288 *tags_free = LE16_TO_CPU(resp->tags_free); 4289 } 4290 4291 return status; 4292 } 4293 4294 /** 4295 * i40e_aq_add_mcast_etag - Add a multicast E-tag 4296 * @hw: pointer to the hw struct 4297 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with 4298 * @etag: value of E-tag to add 4299 * @num_tags_in_buf: number of unicast E-tags in indirect buffer 4300 * @buf: address of indirect buffer 4301 * @tags_used: return value, number of E-tags in use by this port 4302 * @tags_free: return value, number of unallocated M-tags 4303 * @cmd_details: pointer to command details structure or NULL 4304 * 4305 * This associates a multicast E-tag to a port virtualizer. It will return 4306 * the number of tags allocated by the PF, and the number of unallocated 4307 * tags available. 4308 * 4309 * The indirect buffer pointed to by buf is a list of 2-byte E-tags, 4310 * num_tags_in_buf long. 4311 **/ 4312 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid, 4313 u16 etag, u8 num_tags_in_buf, void *buf, 4314 u16 *tags_used, u16 *tags_free, 4315 struct i40e_asq_cmd_details *cmd_details) 4316 { 4317 struct i40e_aq_desc desc; 4318 struct i40e_aqc_add_remove_mcast_etag *cmd = 4319 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw; 4320 struct i40e_aqc_add_remove_mcast_etag_completion *resp = 4321 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw; 4322 enum i40e_status_code status; 4323 u16 length = sizeof(u16) * num_tags_in_buf; 4324 4325 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0)) 4326 return I40E_ERR_PARAM; 4327 4328 i40e_fill_default_direct_cmd_desc(&desc, 4329 i40e_aqc_opc_add_multicast_etag); 4330 4331 cmd->pv_seid = CPU_TO_LE16(pv_seid); 4332 cmd->etag = CPU_TO_LE16(etag); 4333 cmd->num_unicast_etags = num_tags_in_buf; 4334 4335 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4336 if (length > I40E_AQ_LARGE_BUF) 4337 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4338 4339 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details); 4340 4341 if (!status) { 4342 if (tags_used != NULL) 4343 *tags_used = LE16_TO_CPU(resp->mcast_etags_used); 4344 if (tags_free != NULL) 4345 *tags_free = LE16_TO_CPU(resp->mcast_etags_free); 4346 } 4347 4348 return status; 4349 } 4350 4351 /** 4352 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag 4353 * @hw: pointer to the hw struct 4354 * @pv_seid: Port Virtualizer SEID this M-tag is associated with 4355 * @etag: value of the E-tag to remove 4356 * @tags_used: return value, number of tags in use by this port 4357 * @tags_free: return value, number of unallocated tags 4358 * @cmd_details: pointer to command details structure or NULL 4359 * 4360 * This deletes an E-tag from the port virtualizer. It will return 4361 * the number of tags allocated by the port, and the number of unallocated 4362 * tags available. 4363 **/ 4364 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid, 4365 u16 etag, u16 *tags_used, u16 *tags_free, 4366 struct i40e_asq_cmd_details *cmd_details) 4367 { 4368 struct i40e_aq_desc desc; 4369 struct i40e_aqc_add_remove_mcast_etag *cmd = 4370 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw; 4371 struct i40e_aqc_add_remove_mcast_etag_completion *resp = 4372 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw; 4373 enum i40e_status_code status; 4374 4375 4376 if (pv_seid == 0) 4377 return I40E_ERR_PARAM; 4378 4379 i40e_fill_default_direct_cmd_desc(&desc, 4380 i40e_aqc_opc_remove_multicast_etag); 4381 4382 cmd->pv_seid = CPU_TO_LE16(pv_seid); 4383 cmd->etag = CPU_TO_LE16(etag); 4384 4385 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4386 4387 if (!status) { 4388 if (tags_used != NULL) 4389 *tags_used = LE16_TO_CPU(resp->mcast_etags_used); 4390 if (tags_free != NULL) 4391 *tags_free = LE16_TO_CPU(resp->mcast_etags_free); 4392 } 4393 4394 return status; 4395 } 4396 4397 /** 4398 * i40e_aq_update_tag - Update an S/E-tag 4399 * @hw: pointer to the hw struct 4400 * @vsi_seid: VSI SEID using this S-tag 4401 * @old_tag: old tag value 4402 * @new_tag: new tag value 4403 * @tags_used: return value, number of tags in use by this PF 4404 * @tags_free: return value, number of unallocated tags 4405 * @cmd_details: pointer to command details structure or NULL 4406 * 4407 * This updates the value of the tag currently attached to this VSI 4408 * in the switch complex. It will return the number of tags allocated 4409 * by the PF, and the number of unallocated tags available. 4410 **/ 4411 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid, 4412 u16 old_tag, u16 new_tag, u16 *tags_used, 4413 u16 *tags_free, 4414 struct i40e_asq_cmd_details *cmd_details) 4415 { 4416 struct i40e_aq_desc desc; 4417 struct i40e_aqc_update_tag *cmd = 4418 (struct i40e_aqc_update_tag *)&desc.params.raw; 4419 struct i40e_aqc_update_tag_completion *resp = 4420 (struct i40e_aqc_update_tag_completion *)&desc.params.raw; 4421 enum i40e_status_code status; 4422 4423 if (vsi_seid == 0) 4424 return I40E_ERR_PARAM; 4425 4426 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag); 4427 4428 cmd->seid = CPU_TO_LE16(vsi_seid); 4429 cmd->old_tag = CPU_TO_LE16(old_tag); 4430 cmd->new_tag = CPU_TO_LE16(new_tag); 4431 4432 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4433 4434 if (!status) { 4435 if (tags_used != NULL) 4436 *tags_used = LE16_TO_CPU(resp->tags_used); 4437 if (tags_free != NULL) 4438 *tags_free = LE16_TO_CPU(resp->tags_free); 4439 } 4440 4441 return status; 4442 } 4443 4444 /** 4445 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs 4446 * @hw: pointer to the hw struct 4447 * @tcmap: TC map for request/release any ignore PFC condition 4448 * @request: request or release ignore PFC condition 4449 * @tcmap_ret: return TCs for which PFC is currently ignored 4450 * @cmd_details: pointer to command details structure or NULL 4451 * 4452 * This sends out request/release to ignore PFC condition for a TC. 4453 * It will return the TCs for which PFC is currently ignored. 4454 **/ 4455 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap, 4456 bool request, u8 *tcmap_ret, 4457 struct i40e_asq_cmd_details *cmd_details) 4458 { 4459 struct i40e_aq_desc desc; 4460 struct i40e_aqc_pfc_ignore *cmd_resp = 4461 (struct i40e_aqc_pfc_ignore *)&desc.params.raw; 4462 enum i40e_status_code status; 4463 4464 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc); 4465 4466 if (request) 4467 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET; 4468 4469 cmd_resp->tc_bitmap = tcmap; 4470 4471 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4472 4473 if (!status) { 4474 if (tcmap_ret != NULL) 4475 *tcmap_ret = cmd_resp->tc_bitmap; 4476 } 4477 4478 return status; 4479 } 4480 4481 /** 4482 * i40e_aq_dcb_updated - DCB Updated Command 4483 * @hw: pointer to the hw struct 4484 * @cmd_details: pointer to command details structure or NULL 4485 * 4486 * When LLDP is handled in PF this command is used by the PF 4487 * to notify EMP that a DCB setting is modified. 4488 * When LLDP is handled in EMP this command is used by the PF 4489 * to notify EMP whenever one of the following parameters get 4490 * modified: 4491 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA 4492 * - PCIRTT in PRTDCB_GENC.PCIRTT 4493 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME. 4494 * EMP will return when the shared RPB settings have been 4495 * recomputed and modified. The retval field in the descriptor 4496 * will be set to 0 when RPB is modified. 4497 **/ 4498 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw, 4499 struct i40e_asq_cmd_details *cmd_details) 4500 { 4501 struct i40e_aq_desc desc; 4502 enum i40e_status_code status; 4503 4504 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated); 4505 4506 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4507 4508 return status; 4509 } 4510 4511 /** 4512 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch. 4513 * @hw: pointer to the hw struct 4514 * @seid: defines the SEID of the switch for which the stats are requested 4515 * @vlan_id: the VLAN ID for which the statistics are requested 4516 * @stat_index: index of the statistics counters block assigned to this VLAN 4517 * @cmd_details: pointer to command details structure or NULL 4518 * 4519 * XL710 supports 128 smonVlanStats counters.This command is used to 4520 * allocate a set of smonVlanStats counters to a specific VLAN in a specific 4521 * switch. 4522 **/ 4523 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid, 4524 u16 vlan_id, u16 *stat_index, 4525 struct i40e_asq_cmd_details *cmd_details) 4526 { 4527 struct i40e_aq_desc desc; 4528 struct i40e_aqc_add_remove_statistics *cmd_resp = 4529 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw; 4530 enum i40e_status_code status; 4531 4532 if ((seid == 0) || (stat_index == NULL)) 4533 return I40E_ERR_PARAM; 4534 4535 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics); 4536 4537 cmd_resp->seid = CPU_TO_LE16(seid); 4538 cmd_resp->vlan = CPU_TO_LE16(vlan_id); 4539 4540 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4541 4542 if (!status && stat_index) 4543 *stat_index = LE16_TO_CPU(cmd_resp->stat_index); 4544 4545 return status; 4546 } 4547 4548 /** 4549 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch. 4550 * @hw: pointer to the hw struct 4551 * @seid: defines the SEID of the switch for which the stats are requested 4552 * @vlan_id: the VLAN ID for which the statistics are requested 4553 * @stat_index: index of the statistics counters block assigned to this VLAN 4554 * @cmd_details: pointer to command details structure or NULL 4555 * 4556 * XL710 supports 128 smonVlanStats counters.This command is used to 4557 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific 4558 * switch. 4559 **/ 4560 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid, 4561 u16 vlan_id, u16 stat_index, 4562 struct i40e_asq_cmd_details *cmd_details) 4563 { 4564 struct i40e_aq_desc desc; 4565 struct i40e_aqc_add_remove_statistics *cmd = 4566 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw; 4567 enum i40e_status_code status; 4568 4569 if (seid == 0) 4570 return I40E_ERR_PARAM; 4571 4572 i40e_fill_default_direct_cmd_desc(&desc, 4573 i40e_aqc_opc_remove_statistics); 4574 4575 cmd->seid = CPU_TO_LE16(seid); 4576 cmd->vlan = CPU_TO_LE16(vlan_id); 4577 cmd->stat_index = CPU_TO_LE16(stat_index); 4578 4579 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4580 4581 return status; 4582 } 4583 4584 /** 4585 * i40e_aq_set_port_parameters - set physical port parameters. 4586 * @hw: pointer to the hw struct 4587 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded 4588 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI 4589 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded 4590 * @double_vlan: if set double VLAN is enabled 4591 * @cmd_details: pointer to command details structure or NULL 4592 **/ 4593 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw, 4594 u16 bad_frame_vsi, bool save_bad_pac, 4595 bool pad_short_pac, bool double_vlan, 4596 struct i40e_asq_cmd_details *cmd_details) 4597 { 4598 struct i40e_aqc_set_port_parameters *cmd; 4599 enum i40e_status_code status; 4600 struct i40e_aq_desc desc; 4601 u16 command_flags = 0; 4602 4603 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw; 4604 4605 i40e_fill_default_direct_cmd_desc(&desc, 4606 i40e_aqc_opc_set_port_parameters); 4607 4608 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi); 4609 if (save_bad_pac) 4610 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS; 4611 if (pad_short_pac) 4612 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS; 4613 if (double_vlan) 4614 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA; 4615 cmd->command_flags = CPU_TO_LE16(command_flags); 4616 4617 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4618 4619 return status; 4620 } 4621 4622 /** 4623 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler 4624 * @hw: pointer to the hw struct 4625 * @seid: seid for the physical port/switching component/vsi 4626 * @buff: Indirect buffer to hold data parameters and response 4627 * @buff_size: Indirect buffer size 4628 * @opcode: Tx scheduler AQ command opcode 4629 * @cmd_details: pointer to command details structure or NULL 4630 * 4631 * Generic command handler for Tx scheduler AQ commands 4632 **/ 4633 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid, 4634 void *buff, u16 buff_size, 4635 enum i40e_admin_queue_opc opcode, 4636 struct i40e_asq_cmd_details *cmd_details) 4637 { 4638 struct i40e_aq_desc desc; 4639 struct i40e_aqc_tx_sched_ind *cmd = 4640 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw; 4641 enum i40e_status_code status; 4642 bool cmd_param_flag = FALSE; 4643 4644 switch (opcode) { 4645 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit: 4646 case i40e_aqc_opc_configure_vsi_tc_bw: 4647 case i40e_aqc_opc_enable_switching_comp_ets: 4648 case i40e_aqc_opc_modify_switching_comp_ets: 4649 case i40e_aqc_opc_disable_switching_comp_ets: 4650 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit: 4651 case i40e_aqc_opc_configure_switching_comp_bw_config: 4652 cmd_param_flag = TRUE; 4653 break; 4654 case i40e_aqc_opc_query_vsi_bw_config: 4655 case i40e_aqc_opc_query_vsi_ets_sla_config: 4656 case i40e_aqc_opc_query_switching_comp_ets_config: 4657 case i40e_aqc_opc_query_port_ets_config: 4658 case i40e_aqc_opc_query_switching_comp_bw_config: 4659 cmd_param_flag = FALSE; 4660 break; 4661 default: 4662 return I40E_ERR_PARAM; 4663 } 4664 4665 i40e_fill_default_direct_cmd_desc(&desc, opcode); 4666 4667 /* Indirect command */ 4668 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4669 if (cmd_param_flag) 4670 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 4671 if (buff_size > I40E_AQ_LARGE_BUF) 4672 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4673 4674 desc.datalen = CPU_TO_LE16(buff_size); 4675 4676 cmd->vsi_seid = CPU_TO_LE16(seid); 4677 4678 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4679 4680 return status; 4681 } 4682 4683 /** 4684 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit 4685 * @hw: pointer to the hw struct 4686 * @seid: VSI seid 4687 * @credit: BW limit credits (0 = disabled) 4688 * @max_credit: Max BW limit credits 4689 * @cmd_details: pointer to command details structure or NULL 4690 **/ 4691 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw, 4692 u16 seid, u16 credit, u8 max_credit, 4693 struct i40e_asq_cmd_details *cmd_details) 4694 { 4695 struct i40e_aq_desc desc; 4696 struct i40e_aqc_configure_vsi_bw_limit *cmd = 4697 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw; 4698 enum i40e_status_code status; 4699 4700 i40e_fill_default_direct_cmd_desc(&desc, 4701 i40e_aqc_opc_configure_vsi_bw_limit); 4702 4703 cmd->vsi_seid = CPU_TO_LE16(seid); 4704 cmd->credit = CPU_TO_LE16(credit); 4705 cmd->max_credit = max_credit; 4706 4707 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4708 4709 return status; 4710 } 4711 4712 /** 4713 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit 4714 * @hw: pointer to the hw struct 4715 * @seid: switching component seid 4716 * @credit: BW limit credits (0 = disabled) 4717 * @max_bw: Max BW limit credits 4718 * @cmd_details: pointer to command details structure or NULL 4719 **/ 4720 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw, 4721 u16 seid, u16 credit, u8 max_bw, 4722 struct i40e_asq_cmd_details *cmd_details) 4723 { 4724 struct i40e_aq_desc desc; 4725 struct i40e_aqc_configure_switching_comp_bw_limit *cmd = 4726 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw; 4727 enum i40e_status_code status; 4728 4729 i40e_fill_default_direct_cmd_desc(&desc, 4730 i40e_aqc_opc_configure_switching_comp_bw_limit); 4731 4732 cmd->seid = CPU_TO_LE16(seid); 4733 cmd->credit = CPU_TO_LE16(credit); 4734 cmd->max_bw = max_bw; 4735 4736 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4737 4738 return status; 4739 } 4740 4741 /** 4742 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC 4743 * @hw: pointer to the hw struct 4744 * @seid: VSI seid 4745 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits 4746 * @cmd_details: pointer to command details structure or NULL 4747 **/ 4748 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw, 4749 u16 seid, 4750 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data, 4751 struct i40e_asq_cmd_details *cmd_details) 4752 { 4753 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4754 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit, 4755 cmd_details); 4756 } 4757 4758 /** 4759 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC 4760 * @hw: pointer to the hw struct 4761 * @seid: VSI seid 4762 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits 4763 * @cmd_details: pointer to command details structure or NULL 4764 **/ 4765 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw, 4766 u16 seid, 4767 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data, 4768 struct i40e_asq_cmd_details *cmd_details) 4769 { 4770 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4771 i40e_aqc_opc_configure_vsi_tc_bw, 4772 cmd_details); 4773 } 4774 4775 /** 4776 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC 4777 * @hw: pointer to the hw struct 4778 * @seid: seid of the switching component 4779 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits 4780 * @cmd_details: pointer to command details structure or NULL 4781 **/ 4782 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit( 4783 struct i40e_hw *hw, u16 seid, 4784 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data, 4785 struct i40e_asq_cmd_details *cmd_details) 4786 { 4787 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4788 i40e_aqc_opc_configure_switching_comp_ets_bw_limit, 4789 cmd_details); 4790 } 4791 4792 /** 4793 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration 4794 * @hw: pointer to the hw struct 4795 * @seid: seid of the VSI 4796 * @bw_data: Buffer to hold VSI BW configuration 4797 * @cmd_details: pointer to command details structure or NULL 4798 **/ 4799 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw, 4800 u16 seid, 4801 struct i40e_aqc_query_vsi_bw_config_resp *bw_data, 4802 struct i40e_asq_cmd_details *cmd_details) 4803 { 4804 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4805 i40e_aqc_opc_query_vsi_bw_config, 4806 cmd_details); 4807 } 4808 4809 /** 4810 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC 4811 * @hw: pointer to the hw struct 4812 * @seid: seid of the VSI 4813 * @bw_data: Buffer to hold VSI BW configuration per TC 4814 * @cmd_details: pointer to command details structure or NULL 4815 **/ 4816 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw, 4817 u16 seid, 4818 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data, 4819 struct i40e_asq_cmd_details *cmd_details) 4820 { 4821 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4822 i40e_aqc_opc_query_vsi_ets_sla_config, 4823 cmd_details); 4824 } 4825 4826 /** 4827 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC 4828 * @hw: pointer to the hw struct 4829 * @seid: seid of the switching component 4830 * @bw_data: Buffer to hold switching component's per TC BW config 4831 * @cmd_details: pointer to command details structure or NULL 4832 **/ 4833 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw, 4834 u16 seid, 4835 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data, 4836 struct i40e_asq_cmd_details *cmd_details) 4837 { 4838 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4839 i40e_aqc_opc_query_switching_comp_ets_config, 4840 cmd_details); 4841 } 4842 4843 /** 4844 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration 4845 * @hw: pointer to the hw struct 4846 * @seid: seid of the VSI or switching component connected to Physical Port 4847 * @bw_data: Buffer to hold current ETS configuration for the Physical Port 4848 * @cmd_details: pointer to command details structure or NULL 4849 **/ 4850 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw, 4851 u16 seid, 4852 struct i40e_aqc_query_port_ets_config_resp *bw_data, 4853 struct i40e_asq_cmd_details *cmd_details) 4854 { 4855 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4856 i40e_aqc_opc_query_port_ets_config, 4857 cmd_details); 4858 } 4859 4860 /** 4861 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration 4862 * @hw: pointer to the hw struct 4863 * @seid: seid of the switching component 4864 * @bw_data: Buffer to hold switching component's BW configuration 4865 * @cmd_details: pointer to command details structure or NULL 4866 **/ 4867 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw, 4868 u16 seid, 4869 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data, 4870 struct i40e_asq_cmd_details *cmd_details) 4871 { 4872 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4873 i40e_aqc_opc_query_switching_comp_bw_config, 4874 cmd_details); 4875 } 4876 4877 /** 4878 * i40e_validate_filter_settings 4879 * @hw: pointer to the hardware structure 4880 * @settings: Filter control settings 4881 * 4882 * Check and validate the filter control settings passed. 4883 * The function checks for the valid filter/context sizes being 4884 * passed for FCoE and PE. 4885 * 4886 * Returns I40E_SUCCESS if the values passed are valid and within 4887 * range else returns an error. 4888 **/ 4889 static enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw, 4890 struct i40e_filter_control_settings *settings) 4891 { 4892 u32 fcoe_cntx_size, fcoe_filt_size; 4893 u32 pe_cntx_size, pe_filt_size; 4894 u32 fcoe_fmax; 4895 4896 u32 val; 4897 4898 /* Validate FCoE settings passed */ 4899 switch (settings->fcoe_filt_num) { 4900 case I40E_HASH_FILTER_SIZE_1K: 4901 case I40E_HASH_FILTER_SIZE_2K: 4902 case I40E_HASH_FILTER_SIZE_4K: 4903 case I40E_HASH_FILTER_SIZE_8K: 4904 case I40E_HASH_FILTER_SIZE_16K: 4905 case I40E_HASH_FILTER_SIZE_32K: 4906 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 4907 fcoe_filt_size <<= (u32)settings->fcoe_filt_num; 4908 break; 4909 default: 4910 return I40E_ERR_PARAM; 4911 } 4912 4913 switch (settings->fcoe_cntx_num) { 4914 case I40E_DMA_CNTX_SIZE_512: 4915 case I40E_DMA_CNTX_SIZE_1K: 4916 case I40E_DMA_CNTX_SIZE_2K: 4917 case I40E_DMA_CNTX_SIZE_4K: 4918 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 4919 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num; 4920 break; 4921 default: 4922 return I40E_ERR_PARAM; 4923 } 4924 4925 /* Validate PE settings passed */ 4926 switch (settings->pe_filt_num) { 4927 case I40E_HASH_FILTER_SIZE_1K: 4928 case I40E_HASH_FILTER_SIZE_2K: 4929 case I40E_HASH_FILTER_SIZE_4K: 4930 case I40E_HASH_FILTER_SIZE_8K: 4931 case I40E_HASH_FILTER_SIZE_16K: 4932 case I40E_HASH_FILTER_SIZE_32K: 4933 case I40E_HASH_FILTER_SIZE_64K: 4934 case I40E_HASH_FILTER_SIZE_128K: 4935 case I40E_HASH_FILTER_SIZE_256K: 4936 case I40E_HASH_FILTER_SIZE_512K: 4937 case I40E_HASH_FILTER_SIZE_1M: 4938 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 4939 pe_filt_size <<= (u32)settings->pe_filt_num; 4940 break; 4941 default: 4942 return I40E_ERR_PARAM; 4943 } 4944 4945 switch (settings->pe_cntx_num) { 4946 case I40E_DMA_CNTX_SIZE_512: 4947 case I40E_DMA_CNTX_SIZE_1K: 4948 case I40E_DMA_CNTX_SIZE_2K: 4949 case I40E_DMA_CNTX_SIZE_4K: 4950 case I40E_DMA_CNTX_SIZE_8K: 4951 case I40E_DMA_CNTX_SIZE_16K: 4952 case I40E_DMA_CNTX_SIZE_32K: 4953 case I40E_DMA_CNTX_SIZE_64K: 4954 case I40E_DMA_CNTX_SIZE_128K: 4955 case I40E_DMA_CNTX_SIZE_256K: 4956 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 4957 pe_cntx_size <<= (u32)settings->pe_cntx_num; 4958 break; 4959 default: 4960 return I40E_ERR_PARAM; 4961 } 4962 4963 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */ 4964 val = rd32(hw, I40E_GLHMC_FCOEFMAX); 4965 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK) 4966 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT; 4967 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax) 4968 return I40E_ERR_INVALID_SIZE; 4969 4970 return I40E_SUCCESS; 4971 } 4972 4973 /** 4974 * i40e_set_filter_control 4975 * @hw: pointer to the hardware structure 4976 * @settings: Filter control settings 4977 * 4978 * Set the Queue Filters for PE/FCoE and enable filters required 4979 * for a single PF. It is expected that these settings are programmed 4980 * at the driver initialization time. 4981 **/ 4982 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw, 4983 struct i40e_filter_control_settings *settings) 4984 { 4985 enum i40e_status_code ret = I40E_SUCCESS; 4986 u32 hash_lut_size = 0; 4987 u32 val; 4988 4989 if (!settings) 4990 return I40E_ERR_PARAM; 4991 4992 /* Validate the input settings */ 4993 ret = i40e_validate_filter_settings(hw, settings); 4994 if (ret) 4995 return ret; 4996 4997 /* Read the PF Queue Filter control register */ 4998 val = rd32(hw, I40E_PFQF_CTL_0); 4999 5000 /* Program required PE hash buckets for the PF */ 5001 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK; 5002 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) & 5003 I40E_PFQF_CTL_0_PEHSIZE_MASK; 5004 /* Program required PE contexts for the PF */ 5005 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK; 5006 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) & 5007 I40E_PFQF_CTL_0_PEDSIZE_MASK; 5008 5009 /* Program required FCoE hash buckets for the PF */ 5010 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 5011 val |= ((u32)settings->fcoe_filt_num << 5012 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) & 5013 I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 5014 /* Program required FCoE DDP contexts for the PF */ 5015 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 5016 val |= ((u32)settings->fcoe_cntx_num << 5017 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) & 5018 I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 5019 5020 /* Program Hash LUT size for the PF */ 5021 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 5022 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512) 5023 hash_lut_size = 1; 5024 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) & 5025 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 5026 5027 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */ 5028 if (settings->enable_fdir) 5029 val |= I40E_PFQF_CTL_0_FD_ENA_MASK; 5030 if (settings->enable_ethtype) 5031 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK; 5032 if (settings->enable_macvlan) 5033 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK; 5034 5035 wr32(hw, I40E_PFQF_CTL_0, val); 5036 5037 return I40E_SUCCESS; 5038 } 5039 5040 /** 5041 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter 5042 * @hw: pointer to the hw struct 5043 * @mac_addr: MAC address to use in the filter 5044 * @ethtype: Ethertype to use in the filter 5045 * @flags: Flags that needs to be applied to the filter 5046 * @vsi_seid: seid of the control VSI 5047 * @queue: VSI queue number to send the packet to 5048 * @is_add: Add control packet filter if True else remove 5049 * @stats: Structure to hold information on control filter counts 5050 * @cmd_details: pointer to command details structure or NULL 5051 * 5052 * This command will Add or Remove control packet filter for a control VSI. 5053 * In return it will update the total number of perfect filter count in 5054 * the stats member. 5055 **/ 5056 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw, 5057 u8 *mac_addr, u16 ethtype, u16 flags, 5058 u16 vsi_seid, u16 queue, bool is_add, 5059 struct i40e_control_filter_stats *stats, 5060 struct i40e_asq_cmd_details *cmd_details) 5061 { 5062 struct i40e_aq_desc desc; 5063 struct i40e_aqc_add_remove_control_packet_filter *cmd = 5064 (struct i40e_aqc_add_remove_control_packet_filter *) 5065 &desc.params.raw; 5066 struct i40e_aqc_add_remove_control_packet_filter_completion *resp = 5067 (struct i40e_aqc_add_remove_control_packet_filter_completion *) 5068 &desc.params.raw; 5069 enum i40e_status_code status; 5070 5071 if (vsi_seid == 0) 5072 return I40E_ERR_PARAM; 5073 5074 if (is_add) { 5075 i40e_fill_default_direct_cmd_desc(&desc, 5076 i40e_aqc_opc_add_control_packet_filter); 5077 cmd->queue = CPU_TO_LE16(queue); 5078 } else { 5079 i40e_fill_default_direct_cmd_desc(&desc, 5080 i40e_aqc_opc_remove_control_packet_filter); 5081 } 5082 5083 if (mac_addr) 5084 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS, 5085 I40E_NONDMA_TO_NONDMA); 5086 5087 cmd->etype = CPU_TO_LE16(ethtype); 5088 cmd->flags = CPU_TO_LE16(flags); 5089 cmd->seid = CPU_TO_LE16(vsi_seid); 5090 5091 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5092 5093 if (!status && stats) { 5094 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used); 5095 stats->etype_used = LE16_TO_CPU(resp->etype_used); 5096 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free); 5097 stats->etype_free = LE16_TO_CPU(resp->etype_free); 5098 } 5099 5100 return status; 5101 } 5102 5103 /** 5104 * i40e_aq_add_cloud_filters 5105 * @hw: pointer to the hardware structure 5106 * @seid: VSI seid to add cloud filters from 5107 * @filters: Buffer which contains the filters to be added 5108 * @filter_count: number of filters contained in the buffer 5109 * 5110 * Set the cloud filters for a given VSI. The contents of the 5111 * i40e_aqc_add_remove_cloud_filters_element_data are filled 5112 * in by the caller of the function. 5113 * 5114 **/ 5115 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw, 5116 u16 seid, 5117 struct i40e_aqc_add_remove_cloud_filters_element_data *filters, 5118 u8 filter_count) 5119 { 5120 struct i40e_aq_desc desc; 5121 struct i40e_aqc_add_remove_cloud_filters *cmd = 5122 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5123 u16 buff_len; 5124 enum i40e_status_code status; 5125 5126 i40e_fill_default_direct_cmd_desc(&desc, 5127 i40e_aqc_opc_add_cloud_filters); 5128 5129 buff_len = filter_count * sizeof(*filters); 5130 desc.datalen = CPU_TO_LE16(buff_len); 5131 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5132 cmd->num_filters = filter_count; 5133 cmd->seid = CPU_TO_LE16(seid); 5134 5135 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5136 5137 return status; 5138 } 5139 5140 /** 5141 * i40e_aq_remove_cloud_filters 5142 * @hw: pointer to the hardware structure 5143 * @seid: VSI seid to remove cloud filters from 5144 * @filters: Buffer which contains the filters to be removed 5145 * @filter_count: number of filters contained in the buffer 5146 * 5147 * Remove the cloud filters for a given VSI. The contents of the 5148 * i40e_aqc_add_remove_cloud_filters_element_data are filled 5149 * in by the caller of the function. 5150 * 5151 **/ 5152 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw, 5153 u16 seid, 5154 struct i40e_aqc_add_remove_cloud_filters_element_data *filters, 5155 u8 filter_count) 5156 { 5157 struct i40e_aq_desc desc; 5158 struct i40e_aqc_add_remove_cloud_filters *cmd = 5159 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5160 enum i40e_status_code status; 5161 u16 buff_len; 5162 5163 i40e_fill_default_direct_cmd_desc(&desc, 5164 i40e_aqc_opc_remove_cloud_filters); 5165 5166 buff_len = filter_count * sizeof(*filters); 5167 desc.datalen = CPU_TO_LE16(buff_len); 5168 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5169 cmd->num_filters = filter_count; 5170 cmd->seid = CPU_TO_LE16(seid); 5171 5172 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5173 5174 return status; 5175 } 5176 5177 /** 5178 * i40e_aq_alternate_write 5179 * @hw: pointer to the hardware structure 5180 * @reg_addr0: address of first dword to be read 5181 * @reg_val0: value to be written under 'reg_addr0' 5182 * @reg_addr1: address of second dword to be read 5183 * @reg_val1: value to be written under 'reg_addr1' 5184 * 5185 * Write one or two dwords to alternate structure. Fields are indicated 5186 * by 'reg_addr0' and 'reg_addr1' register numbers. 5187 * 5188 **/ 5189 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw, 5190 u32 reg_addr0, u32 reg_val0, 5191 u32 reg_addr1, u32 reg_val1) 5192 { 5193 struct i40e_aq_desc desc; 5194 struct i40e_aqc_alternate_write *cmd_resp = 5195 (struct i40e_aqc_alternate_write *)&desc.params.raw; 5196 enum i40e_status_code status; 5197 5198 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write); 5199 cmd_resp->address0 = CPU_TO_LE32(reg_addr0); 5200 cmd_resp->address1 = CPU_TO_LE32(reg_addr1); 5201 cmd_resp->data0 = CPU_TO_LE32(reg_val0); 5202 cmd_resp->data1 = CPU_TO_LE32(reg_val1); 5203 5204 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 5205 5206 return status; 5207 } 5208 5209 /** 5210 * i40e_aq_alternate_write_indirect 5211 * @hw: pointer to the hardware structure 5212 * @addr: address of a first register to be modified 5213 * @dw_count: number of alternate structure fields to write 5214 * @buffer: pointer to the command buffer 5215 * 5216 * Write 'dw_count' dwords from 'buffer' to alternate structure 5217 * starting at 'addr'. 5218 * 5219 **/ 5220 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw, 5221 u32 addr, u32 dw_count, void *buffer) 5222 { 5223 struct i40e_aq_desc desc; 5224 struct i40e_aqc_alternate_ind_write *cmd_resp = 5225 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw; 5226 enum i40e_status_code status; 5227 5228 if (buffer == NULL) 5229 return I40E_ERR_PARAM; 5230 5231 /* Indirect command */ 5232 i40e_fill_default_direct_cmd_desc(&desc, 5233 i40e_aqc_opc_alternate_write_indirect); 5234 5235 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD); 5236 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF); 5237 if (dw_count > (I40E_AQ_LARGE_BUF/4)) 5238 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 5239 5240 cmd_resp->address = CPU_TO_LE32(addr); 5241 cmd_resp->length = CPU_TO_LE32(dw_count); 5242 cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_WORD((uintptr_t)buffer)); 5243 cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((uintptr_t)buffer)); 5244 5245 status = i40e_asq_send_command(hw, &desc, buffer, 5246 I40E_LO_DWORD(4*dw_count), NULL); 5247 5248 return status; 5249 } 5250 5251 /** 5252 * i40e_aq_alternate_read 5253 * @hw: pointer to the hardware structure 5254 * @reg_addr0: address of first dword to be read 5255 * @reg_val0: pointer for data read from 'reg_addr0' 5256 * @reg_addr1: address of second dword to be read 5257 * @reg_val1: pointer for data read from 'reg_addr1' 5258 * 5259 * Read one or two dwords from alternate structure. Fields are indicated 5260 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer 5261 * is not passed then only register at 'reg_addr0' is read. 5262 * 5263 **/ 5264 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw, 5265 u32 reg_addr0, u32 *reg_val0, 5266 u32 reg_addr1, u32 *reg_val1) 5267 { 5268 struct i40e_aq_desc desc; 5269 struct i40e_aqc_alternate_write *cmd_resp = 5270 (struct i40e_aqc_alternate_write *)&desc.params.raw; 5271 enum i40e_status_code status; 5272 5273 if (reg_val0 == NULL) 5274 return I40E_ERR_PARAM; 5275 5276 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read); 5277 cmd_resp->address0 = CPU_TO_LE32(reg_addr0); 5278 cmd_resp->address1 = CPU_TO_LE32(reg_addr1); 5279 5280 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 5281 5282 if (status == I40E_SUCCESS) { 5283 *reg_val0 = LE32_TO_CPU(cmd_resp->data0); 5284 5285 if (reg_val1 != NULL) 5286 *reg_val1 = LE32_TO_CPU(cmd_resp->data1); 5287 } 5288 5289 return status; 5290 } 5291 5292 /** 5293 * i40e_aq_alternate_read_indirect 5294 * @hw: pointer to the hardware structure 5295 * @addr: address of the alternate structure field 5296 * @dw_count: number of alternate structure fields to read 5297 * @buffer: pointer to the command buffer 5298 * 5299 * Read 'dw_count' dwords from alternate structure starting at 'addr' and 5300 * place them in 'buffer'. The buffer should be allocated by caller. 5301 * 5302 **/ 5303 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw, 5304 u32 addr, u32 dw_count, void *buffer) 5305 { 5306 struct i40e_aq_desc desc; 5307 struct i40e_aqc_alternate_ind_write *cmd_resp = 5308 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw; 5309 enum i40e_status_code status; 5310 5311 if (buffer == NULL) 5312 return I40E_ERR_PARAM; 5313 5314 /* Indirect command */ 5315 i40e_fill_default_direct_cmd_desc(&desc, 5316 i40e_aqc_opc_alternate_read_indirect); 5317 5318 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD); 5319 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF); 5320 if (dw_count > (I40E_AQ_LARGE_BUF/4)) 5321 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 5322 5323 cmd_resp->address = CPU_TO_LE32(addr); 5324 cmd_resp->length = CPU_TO_LE32(dw_count); 5325 cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_DWORD((uintptr_t)buffer)); 5326 cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((uintptr_t)buffer)); 5327 5328 status = i40e_asq_send_command(hw, &desc, buffer, 5329 I40E_LO_DWORD(4*dw_count), NULL); 5330 5331 return status; 5332 } 5333 5334 /** 5335 * i40e_aq_alternate_clear 5336 * @hw: pointer to the HW structure. 5337 * 5338 * Clear the alternate structures of the port from which the function 5339 * is called. 5340 * 5341 **/ 5342 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw) 5343 { 5344 struct i40e_aq_desc desc; 5345 enum i40e_status_code status; 5346 5347 i40e_fill_default_direct_cmd_desc(&desc, 5348 i40e_aqc_opc_alternate_clear_port); 5349 5350 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 5351 5352 return status; 5353 } 5354 5355 /** 5356 * i40e_aq_alternate_write_done 5357 * @hw: pointer to the HW structure. 5358 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS 5359 * @reset_needed: indicates the SW should trigger GLOBAL reset 5360 * 5361 * Indicates to the FW that alternate structures have been changed. 5362 * 5363 **/ 5364 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw, 5365 u8 bios_mode, bool *reset_needed) 5366 { 5367 struct i40e_aq_desc desc; 5368 struct i40e_aqc_alternate_write_done *cmd = 5369 (struct i40e_aqc_alternate_write_done *)&desc.params.raw; 5370 enum i40e_status_code status; 5371 5372 if (reset_needed == NULL) 5373 return I40E_ERR_PARAM; 5374 5375 i40e_fill_default_direct_cmd_desc(&desc, 5376 i40e_aqc_opc_alternate_write_done); 5377 5378 cmd->cmd_flags = CPU_TO_LE16(bios_mode); 5379 5380 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 5381 if (!status && reset_needed) 5382 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) & 5383 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0); 5384 5385 return status; 5386 } 5387 5388 /** 5389 * i40e_aq_set_oem_mode 5390 * @hw: pointer to the HW structure. 5391 * @oem_mode: the OEM mode to be used 5392 * 5393 * Sets the device to a specific operating mode. Currently the only supported 5394 * mode is no_clp, which causes FW to refrain from using Alternate RAM. 5395 * 5396 **/ 5397 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw, 5398 u8 oem_mode) 5399 { 5400 struct i40e_aq_desc desc; 5401 struct i40e_aqc_alternate_write_done *cmd = 5402 (struct i40e_aqc_alternate_write_done *)&desc.params.raw; 5403 enum i40e_status_code status; 5404 5405 i40e_fill_default_direct_cmd_desc(&desc, 5406 i40e_aqc_opc_alternate_set_mode); 5407 5408 cmd->cmd_flags = CPU_TO_LE16(oem_mode); 5409 5410 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 5411 5412 return status; 5413 } 5414 5415 /** 5416 * i40e_aq_resume_port_tx 5417 * @hw: pointer to the hardware structure 5418 * @cmd_details: pointer to command details structure or NULL 5419 * 5420 * Resume port's Tx traffic 5421 **/ 5422 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw, 5423 struct i40e_asq_cmd_details *cmd_details) 5424 { 5425 struct i40e_aq_desc desc; 5426 enum i40e_status_code status; 5427 5428 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx); 5429 5430 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5431 5432 return status; 5433 } 5434 5435 /** 5436 * i40e_set_pci_config_data - store PCI bus info 5437 * @hw: pointer to hardware structure 5438 * @link_status: the link status word from PCI config space 5439 * 5440 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure 5441 **/ 5442 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status) 5443 { 5444 hw->bus.type = i40e_bus_type_pci_express; 5445 5446 switch (link_status & I40E_PCI_LINK_WIDTH) { 5447 case I40E_PCI_LINK_WIDTH_1: 5448 hw->bus.width = i40e_bus_width_pcie_x1; 5449 break; 5450 case I40E_PCI_LINK_WIDTH_2: 5451 hw->bus.width = i40e_bus_width_pcie_x2; 5452 break; 5453 case I40E_PCI_LINK_WIDTH_4: 5454 hw->bus.width = i40e_bus_width_pcie_x4; 5455 break; 5456 case I40E_PCI_LINK_WIDTH_8: 5457 hw->bus.width = i40e_bus_width_pcie_x8; 5458 break; 5459 default: 5460 hw->bus.width = i40e_bus_width_unknown; 5461 break; 5462 } 5463 5464 switch (link_status & I40E_PCI_LINK_SPEED) { 5465 case I40E_PCI_LINK_SPEED_2500: 5466 hw->bus.speed = i40e_bus_speed_2500; 5467 break; 5468 case I40E_PCI_LINK_SPEED_5000: 5469 hw->bus.speed = i40e_bus_speed_5000; 5470 break; 5471 case I40E_PCI_LINK_SPEED_8000: 5472 hw->bus.speed = i40e_bus_speed_8000; 5473 break; 5474 default: 5475 hw->bus.speed = i40e_bus_speed_unknown; 5476 break; 5477 } 5478 } 5479 5480 /** 5481 * i40e_aq_debug_dump 5482 * @hw: pointer to the hardware structure 5483 * @cluster_id: specific cluster to dump 5484 * @table_id: table id within cluster 5485 * @start_index: index of line in the block to read 5486 * @buff_size: dump buffer size 5487 * @buff: dump buffer 5488 * @ret_buff_size: actual buffer size returned 5489 * @ret_next_table: next block to read 5490 * @ret_next_index: next index to read 5491 * 5492 * Dump internal FW/HW data for debug purposes. 5493 * 5494 **/ 5495 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id, 5496 u8 table_id, u32 start_index, u16 buff_size, 5497 void *buff, u16 *ret_buff_size, 5498 u8 *ret_next_table, u32 *ret_next_index, 5499 struct i40e_asq_cmd_details *cmd_details) 5500 { 5501 struct i40e_aq_desc desc; 5502 struct i40e_aqc_debug_dump_internals *cmd = 5503 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 5504 struct i40e_aqc_debug_dump_internals *resp = 5505 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 5506 enum i40e_status_code status; 5507 5508 if (buff_size == 0 || !buff) 5509 return I40E_ERR_PARAM; 5510 5511 i40e_fill_default_direct_cmd_desc(&desc, 5512 i40e_aqc_opc_debug_dump_internals); 5513 /* Indirect Command */ 5514 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 5515 if (buff_size > I40E_AQ_LARGE_BUF) 5516 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 5517 5518 cmd->cluster_id = cluster_id; 5519 cmd->table_id = table_id; 5520 cmd->idx = CPU_TO_LE32(start_index); 5521 5522 desc.datalen = CPU_TO_LE16(buff_size); 5523 5524 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 5525 if (!status) { 5526 if (ret_buff_size != NULL) 5527 *ret_buff_size = LE16_TO_CPU(desc.datalen); 5528 if (ret_next_table != NULL) 5529 *ret_next_table = resp->table_id; 5530 if (ret_next_index != NULL) 5531 *ret_next_index = LE32_TO_CPU(resp->idx); 5532 } 5533 5534 return status; 5535 } 5536 5537 /** 5538 * i40e_read_bw_from_alt_ram 5539 * @hw: pointer to the hardware structure 5540 * @max_bw: pointer for max_bw read 5541 * @min_bw: pointer for min_bw read 5542 * @min_valid: pointer for bool that is TRUE if min_bw is a valid value 5543 * @max_valid: pointer for bool that is TRUE if max_bw is a valid value 5544 * 5545 * Read bw from the alternate ram for the given pf 5546 **/ 5547 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw, 5548 u32 *max_bw, u32 *min_bw, 5549 bool *min_valid, bool *max_valid) 5550 { 5551 enum i40e_status_code status; 5552 u32 max_bw_addr, min_bw_addr; 5553 5554 /* Calculate the address of the min/max bw registers */ 5555 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 5556 I40E_ALT_STRUCT_MAX_BW_OFFSET + 5557 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 5558 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 5559 I40E_ALT_STRUCT_MIN_BW_OFFSET + 5560 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 5561 5562 /* Read the bandwidths from alt ram */ 5563 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw, 5564 min_bw_addr, min_bw); 5565 5566 if (*min_bw & I40E_ALT_BW_VALID_MASK) 5567 *min_valid = TRUE; 5568 else 5569 *min_valid = FALSE; 5570 5571 if (*max_bw & I40E_ALT_BW_VALID_MASK) 5572 *max_valid = TRUE; 5573 else 5574 *max_valid = FALSE; 5575 5576 return status; 5577 } 5578 5579 /** 5580 * i40e_aq_configure_partition_bw 5581 * @hw: pointer to the hardware structure 5582 * @bw_data: Buffer holding valid pfs and bw limits 5583 * @cmd_details: pointer to command details 5584 * 5585 * Configure partitions guaranteed/max bw 5586 **/ 5587 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw, 5588 struct i40e_aqc_configure_partition_bw_data *bw_data, 5589 struct i40e_asq_cmd_details *cmd_details) 5590 { 5591 enum i40e_status_code status; 5592 struct i40e_aq_desc desc; 5593 u16 bwd_size = sizeof(*bw_data); 5594 5595 i40e_fill_default_direct_cmd_desc(&desc, 5596 i40e_aqc_opc_configure_partition_bw); 5597 5598 /* Indirect command */ 5599 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 5600 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 5601 5602 if (bwd_size > I40E_AQ_LARGE_BUF) 5603 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 5604 5605 desc.datalen = CPU_TO_LE16(bwd_size); 5606 5607 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details); 5608 5609 return status; 5610 } 5611 5612 /** 5613 * i40e_aq_send_msg_to_pf 5614 * @hw: pointer to the hardware structure 5615 * @v_opcode: opcodes for VF-PF communication 5616 * @v_retval: return error code 5617 * @msg: pointer to the msg buffer 5618 * @msglen: msg length 5619 * @cmd_details: pointer to command details 5620 * 5621 * Send message to PF driver using admin queue. By default, this message 5622 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for 5623 * completion before returning. 5624 **/ 5625 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw, 5626 enum i40e_virtchnl_ops v_opcode, 5627 enum i40e_status_code v_retval, 5628 u8 *msg, u16 msglen, 5629 struct i40e_asq_cmd_details *cmd_details) 5630 { 5631 struct i40e_aq_desc desc; 5632 struct i40e_asq_cmd_details details; 5633 enum i40e_status_code status; 5634 5635 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf); 5636 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI); 5637 desc.cookie_high = CPU_TO_LE32(v_opcode); 5638 desc.cookie_low = CPU_TO_LE32(v_retval); 5639 if (msglen) { 5640 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF 5641 | I40E_AQ_FLAG_RD)); 5642 if (msglen > I40E_AQ_LARGE_BUF) 5643 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 5644 desc.datalen = CPU_TO_LE16(msglen); 5645 } 5646 if (!cmd_details) { 5647 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM); 5648 details.async = TRUE; 5649 cmd_details = &details; 5650 } 5651 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg, 5652 msglen, cmd_details); 5653 return status; 5654 } 5655 5656 /** 5657 * i40e_vf_parse_hw_config 5658 * @hw: pointer to the hardware structure 5659 * @msg: pointer to the virtual channel VF resource structure 5660 * 5661 * Given a VF resource message from the PF, populate the hw struct 5662 * with appropriate information. 5663 **/ 5664 void i40e_vf_parse_hw_config(struct i40e_hw *hw, 5665 struct i40e_virtchnl_vf_resource *msg) 5666 { 5667 struct i40e_virtchnl_vsi_resource *vsi_res; 5668 int i; 5669 5670 vsi_res = &msg->vsi_res[0]; 5671 5672 hw->dev_caps.num_vsis = msg->num_vsis; 5673 hw->dev_caps.num_rx_qp = msg->num_queue_pairs; 5674 hw->dev_caps.num_tx_qp = msg->num_queue_pairs; 5675 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors; 5676 hw->dev_caps.dcb = msg->vf_offload_flags & 5677 I40E_VIRTCHNL_VF_OFFLOAD_L2; 5678 hw->dev_caps.fcoe = (msg->vf_offload_flags & 5679 I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0; 5680 hw->dev_caps.iwarp = (msg->vf_offload_flags & 5681 I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0; 5682 for (i = 0; i < msg->num_vsis; i++) { 5683 if (vsi_res->vsi_type == I40E_VSI_SRIOV) { 5684 i40e_memcpy(hw->mac.perm_addr, 5685 vsi_res->default_mac_addr, 5686 I40E_ETH_LENGTH_OF_ADDRESS, 5687 I40E_NONDMA_TO_NONDMA); 5688 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr, 5689 I40E_ETH_LENGTH_OF_ADDRESS, 5690 I40E_NONDMA_TO_NONDMA); 5691 } 5692 vsi_res++; 5693 } 5694 } 5695 5696 /** 5697 * i40e_vf_reset 5698 * @hw: pointer to the hardware structure 5699 * 5700 * Send a VF_RESET message to the PF. Does not wait for response from PF 5701 * as none will be forthcoming. Immediately after calling this function, 5702 * the admin queue should be shut down and (optionally) reinitialized. 5703 **/ 5704 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw) 5705 { 5706 return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF, 5707 I40E_SUCCESS, NULL, 0, NULL); 5708 } 5709