1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * This file is part of the Chelsio T4/T5/T6 Ethernet driver. 14 * 15 * Copyright (C) 2003-2017 Chelsio Communications. All rights reserved. 16 * 17 * This program is distributed in the hope that it will be useful, but WITHOUT 18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 19 * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this 20 * release for licensing terms and conditions. 21 */ 22 #ifndef __T4_CHIP_TYPE_H__ 23 #define __T4_CHIP_TYPE_H__ 24 25 /* 26 * All T4 and later chips have their PCI-E Device IDs encoded as 0xVFPP where: 27 * 28 * V = "4" for T4; "5" for T5, etc. or 29 * = "a" for T4 FPGA; "b" for T4 FPGA, etc. 30 * F = "0" for PF 0..3; "4".."7" for PF4..7; and "8" for VFs 31 * PP = adapter product designation 32 * 33 * We use the "version" (V) of the adpater to code the Chip Version above 34 * but separate out the FPGA as a separate boolean as per above. 35 */ 36 #define CHELSIO_PCI_ID_VER(__DeviceID) ((__DeviceID) >> 12) 37 #define CHELSIO_PCI_ID_FUNC(__DeviceID) (((__DeviceID) >> 8) & 0xf) 38 #define CHELSIO_PCI_ID_PROD(__DeviceID) ((__DeviceID) & 0xff) 39 40 #define CHELSIO_T4 0x4 41 #define CHELSIO_T4_FPGA 0xa 42 #define CHELSIO_T5 0x5 43 #define CHELSIO_T5_FPGA 0xb 44 #define CHELSIO_T6 0x6 45 #define CHELSIO_T6_FPGA 0xc 46 47 /* 48 * Translate a PCI Device ID to a base Chelsio Chip Version -- CHELSIO_T4, 49 * CHELSIO_T5, etc. If it weren't for the screwed up numbering of the FPGAs 50 * we could do this simply as DeviceID >> 12 (because we know the real 51 * encoding oc CHELSIO_Tx identifiers). However, the FPGAs _do_ have weird 52 * Device IDs so we need to do this translation here. Note that only constant 53 * arithmetic and comparisons can be done here since this is being used to 54 * initialize static tables, etc. 55 * 56 * Finally: This will of course need to be expanded as future chips are 57 * developed. 58 */ 59 static inline unsigned int 60 CHELSIO_PCI_ID_CHIP_VERSION(unsigned int DeviceID) 61 { 62 switch (CHELSIO_PCI_ID_VER(DeviceID)) { 63 case CHELSIO_T4: 64 case CHELSIO_T4_FPGA: 65 return CHELSIO_T4; 66 67 case CHELSIO_T5: 68 case CHELSIO_T5_FPGA: 69 return CHELSIO_T5; 70 71 case CHELSIO_T6: 72 case CHELSIO_T6_FPGA: 73 return CHELSIO_T6; 74 } 75 76 return 0; 77 } 78 79 /* 80 * Internally we code the Chelsio T4 Family "Chip Code" as a tuple: 81 * 82 * (Is FPGA, Chip Version, Chip Revision) 83 * 84 * where: 85 * 86 * Is FPGA: is 0/1 indicating whether we're working with an FPGA 87 * Chip Version: is T4, T5, etc. 88 * Chip Revision: is the FAB "spin" of the Chip Version. 89 */ 90 #define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision)) 91 #define CHELSIO_CHIP_FPGA 0x100 92 #define CHELSIO_CHIP_VERSION(code) (((code) >> 4) & 0xf) 93 #define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf) 94 95 enum chip_type { 96 T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1), 97 T4_A2 = CHELSIO_CHIP_CODE(CHELSIO_T4, 2), 98 T4_FIRST_REV = T4_A1, 99 T4_LAST_REV = T4_A2, 100 101 T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0), 102 T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1), 103 T5_FIRST_REV = T5_A0, 104 T5_LAST_REV = T5_A1, 105 106 T6_A0 = CHELSIO_CHIP_CODE(CHELSIO_T6, 0), 107 T6_FIRST_REV = T6_A0, 108 T6_LAST_REV = T6_A0, 109 }; 110 111 static inline int is_t4(enum chip_type chip) 112 { 113 return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T4); 114 } 115 116 static inline int is_t5(enum chip_type chip) 117 { 118 119 return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5); 120 } 121 122 static inline int is_t6(enum chip_type chip) 123 { 124 return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6); 125 } 126 127 static inline int is_fpga(enum chip_type chip) 128 { 129 return chip & CHELSIO_CHIP_FPGA; 130 } 131 132 #endif /* __T4_CHIP_TYPE_H__ */ 133