1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * This file is part of the Chelsio T4/T5/T6 Ethernet driver. 14 * 15 * Copyright (C) 2005-2019 Chelsio Communications. All rights reserved. 16 * 17 * This program is distributed in the hope that it will be useful, but WITHOUT 18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 19 * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this 20 * release for licensing terms and conditions. 21 */ 22 23 /* 24 * Copyright 2020 RackTop Systems, Inc. 25 */ 26 27 #ifndef __CHELSIO_COMMON_H 28 #define __CHELSIO_COMMON_H 29 30 #include "t4_hw.h" 31 #include "t4_chip_type.h" 32 #include "t4fw_version.h" 33 #include "t5fw_version.h" 34 #include "t6fw_version.h" 35 36 #define GLBL_INTR_MASK (F_CIM | F_MPS | F_PL | F_PCIE | F_MC0 | F_EDC0 | \ 37 F_EDC1 | F_LE | F_TP | F_MA | F_PM_TX | F_PM_RX | F_ULP_RX | \ 38 F_CPL_SWITCH | F_SGE | F_ULP_TX | F_SF) 39 40 #ifdef __cplusplus 41 extern "C" { 42 #endif 43 44 #ifndef __linux__ 45 #define __force 46 #define usleep_range(_min, _max) msleep(_max / 1000) 47 #endif 48 49 /* 50 * Firmware minimum version macros are used by t4_check_fw_version() to check 51 * if the FW is supported by the driver. 52 * Initially these macros were in t4fw_interface.h, but was removed, as the 53 * file is automatically replaced during a new FW commit. So untill these 54 * macros moves to one of the firmware header files, it has to be here. 55 */ 56 #define T4FW_MIN_VERSION_MAJOR 0x01 57 #define T4FW_MIN_VERSION_MINOR 0x04 58 #define T4FW_MIN_VERSION_MICRO 0x00 59 60 #define T5FW_MIN_VERSION_MAJOR 0x00 61 #define T5FW_MIN_VERSION_MINOR 0x00 62 #define T5FW_MIN_VERSION_MICRO 0x00 63 64 #define T6FW_MIN_VERSION_MAJOR 0x00 65 #define T6FW_MIN_VERSION_MINOR 0x00 66 #define T6FW_MIN_VERSION_MICRO 0x00 67 68 enum { 69 MAX_NPORTS = 4, /* max # of ports */ 70 SERNUM_LEN = 24, /* Serial # length */ 71 EC_LEN = 16, /* E/C length */ 72 ID_LEN = 16, /* ID length */ 73 PN_LEN = 16, /* Part Number length */ 74 MACADDR_LEN = 12, /* MAC Address length */ 75 }; 76 77 enum { 78 T4_REGMAP_SIZE = (160 * 1024), 79 T5_REGMAP_SIZE = (332 * 1024), 80 }; 81 82 enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1, MEM_HMA }; 83 84 enum { 85 MEMWIN0_APERTURE = 2048, 86 MEMWIN0_BASE = 0x1b800, 87 88 MEMWIN1_APERTURE = 32768, 89 MEMWIN1_BASE = 0x28000, 90 91 MEMWIN2_APERTURE = 65536, 92 MEMWIN2_BASE = 0x30000, 93 94 MEMWIN2_APERTURE_T5 = 128 * 1024, 95 MEMWIN2_BASE_T5 = 0x60000, 96 }; 97 98 enum dev_master { MASTER_CANT, MASTER_MAY, MASTER_MUST }; 99 100 enum dev_state { DEV_STATE_UNINIT, DEV_STATE_INIT, DEV_STATE_ERR }; 101 102 enum { 103 PAUSE_RX = 1 << 0, 104 PAUSE_TX = 1 << 1, 105 PAUSE_AUTONEG = 1 << 2 106 }; 107 typedef unsigned char cc_pause_t; 108 109 enum { 110 FEC_RS = 1 << 0, /* Reed-Solomon */ 111 FEC_BASER_RS = 1 << 1, /* Base-R, aka Firecode */ 112 FEC_NONE = 1 << 2, /* no FEC */ 113 FEC_FORCE = 1 << 3, /* Force specified FEC */ 114 115 /* 116 * Pseudo FECs that translate to real FECs. The firmware knows nothing 117 * about these and they start at M_FW_PORT_CAP32_FEC + 1. AUTO should 118 * be set all by itself. 119 */ 120 FEC_AUTO = 1 << 5, 121 }; 122 typedef unsigned char cc_fec_t; 123 124 enum { 125 ULP_T10DIF_ISCSI = 1 << 0, 126 ULP_T10DIF_FCOE = 1 << 1 127 }; 128 129 enum { 130 ULP_CRYPTO_LOOKASIDE = 1 << 0, 131 ULP_CRYPTO_INLINE_TLS = 1 << 1 132 }; 133 134 struct port_stats { 135 u64 tx_octets; /* total # of octets in good frames */ 136 u64 tx_frames; /* all good frames */ 137 u64 tx_bcast_frames; /* all broadcast frames */ 138 u64 tx_mcast_frames; /* all multicast frames */ 139 u64 tx_ucast_frames; /* all unicast frames */ 140 u64 tx_error_frames; /* all error frames */ 141 142 u64 tx_frames_64; /* # of Tx frames in a particular range */ 143 u64 tx_frames_65_127; 144 u64 tx_frames_128_255; 145 u64 tx_frames_256_511; 146 u64 tx_frames_512_1023; 147 u64 tx_frames_1024_1518; 148 u64 tx_frames_1519_max; 149 150 u64 tx_drop; /* # of dropped Tx frames */ 151 u64 tx_pause; /* # of transmitted pause frames */ 152 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 153 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 154 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 155 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 156 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 157 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 158 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 159 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 160 161 u64 rx_octets; /* total # of octets in good frames */ 162 u64 rx_frames; /* all good frames */ 163 u64 rx_bcast_frames; /* all broadcast frames */ 164 u64 rx_mcast_frames; /* all multicast frames */ 165 u64 rx_ucast_frames; /* all unicast frames */ 166 u64 rx_too_long; /* # of frames exceeding MTU */ 167 u64 rx_jabber; /* # of jabber frames */ 168 u64 rx_fcs_err; /* # of received frames with bad FCS */ 169 u64 rx_len_err; /* # of received frames with length error */ 170 u64 rx_symbol_err; /* symbol errors */ 171 u64 rx_runt; /* # of short frames */ 172 173 u64 rx_frames_64; /* # of Rx frames in a particular range */ 174 u64 rx_frames_65_127; 175 u64 rx_frames_128_255; 176 u64 rx_frames_256_511; 177 u64 rx_frames_512_1023; 178 u64 rx_frames_1024_1518; 179 u64 rx_frames_1519_max; 180 181 u64 rx_pause; /* # of received pause frames */ 182 u64 rx_ppp0; /* # of received PPP prio 0 frames */ 183 u64 rx_ppp1; /* # of received PPP prio 1 frames */ 184 u64 rx_ppp2; /* # of received PPP prio 2 frames */ 185 u64 rx_ppp3; /* # of received PPP prio 3 frames */ 186 u64 rx_ppp4; /* # of received PPP prio 4 frames */ 187 u64 rx_ppp5; /* # of received PPP prio 5 frames */ 188 u64 rx_ppp6; /* # of received PPP prio 6 frames */ 189 u64 rx_ppp7; /* # of received PPP prio 7 frames */ 190 191 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 192 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 193 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 194 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 195 u64 rx_trunc0; /* buffer-group 0 truncated packets */ 196 u64 rx_trunc1; /* buffer-group 1 truncated packets */ 197 u64 rx_trunc2; /* buffer-group 2 truncated packets */ 198 u64 rx_trunc3; /* buffer-group 3 truncated packets */ 199 }; 200 201 struct lb_port_stats { 202 u64 octets; 203 u64 frames; 204 u64 bcast_frames; 205 u64 mcast_frames; 206 u64 ucast_frames; 207 u64 error_frames; 208 209 u64 frames_64; 210 u64 frames_65_127; 211 u64 frames_128_255; 212 u64 frames_256_511; 213 u64 frames_512_1023; 214 u64 frames_1024_1518; 215 u64 frames_1519_max; 216 217 u64 drop; 218 219 u64 ovflow0; 220 u64 ovflow1; 221 u64 ovflow2; 222 u64 ovflow3; 223 u64 trunc0; 224 u64 trunc1; 225 u64 trunc2; 226 u64 trunc3; 227 }; 228 229 struct tp_tcp_stats { 230 u32 tcp_out_rsts; 231 u64 tcp_in_segs; 232 u64 tcp_out_segs; 233 u64 tcp_retrans_segs; 234 }; 235 236 struct tp_usm_stats { 237 u32 frames; 238 u32 drops; 239 u64 octets; 240 }; 241 242 struct tp_fcoe_stats { 243 u32 frames_ddp; 244 u32 frames_drop; 245 u64 octets_ddp; 246 }; 247 248 struct tp_err_stats { 249 u32 mac_in_errs[4]; 250 u32 hdr_in_errs[4]; 251 u32 tcp_in_errs[4]; 252 u32 tnl_cong_drops[4]; 253 u32 ofld_chan_drops[4]; 254 u32 tnl_tx_drops[4]; 255 u32 ofld_vlan_drops[4]; 256 u32 tcp6_in_errs[4]; 257 u32 ofld_no_neigh; 258 u32 ofld_cong_defer; 259 }; 260 261 struct tp_proxy_stats { 262 u32 proxy[4]; 263 }; 264 265 struct tp_cpl_stats { 266 u32 req[4]; 267 u32 rsp[4]; 268 }; 269 270 struct tp_rdma_stats { 271 u32 rqe_dfr_pkt; 272 u32 rqe_dfr_mod; 273 }; 274 275 struct sge_params { 276 u32 hps; /* host page size for our PF/VF */ 277 u32 eq_qpp; /* egress queues/page for our PF/VF */ 278 u32 iq_qpp; /* egress queues/page for our PF/VF */ 279 }; 280 281 struct tp_params { 282 unsigned int tre; /* log2 of core clocks per TP tick */ 283 unsigned int dack_re; /* DACK timer resolution */ 284 unsigned int la_mask; /* what events are recorded by TP LA */ 285 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 286 287 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 288 u32 filter_mask; 289 u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 290 /* cached TP_OUT_CONFIG compressed error vector 291 * and passing outer header info for encapsulated packets. 292 */ 293 int rx_pkt_encap; 294 295 /* 296 * TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 297 * subset of the set of fields which may be present in the Compressed 298 * Filter Tuple portion of filters and TCP TCB connections. The 299 * fields which are present are controlled by the TP_VLAN_PRI_MAP. 300 * Since a variable number of fields may or may not be present, their 301 * shifted field positions within the Compressed Filter Tuple may 302 * vary, or not even be present if the field isn't selected in 303 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 304 * places we store their offsets here, or a -1 if the field isn't 305 * present. 306 */ 307 int fcoe_shift; 308 int port_shift; 309 int vnic_shift; 310 int vlan_shift; 311 int tos_shift; 312 int protocol_shift; 313 int ethertype_shift; 314 int macmatch_shift; 315 int matchtype_shift; 316 int frag_shift; 317 }; 318 319 struct vpd_params { 320 unsigned int cclk; 321 u8 ec[EC_LEN + 1]; 322 u8 sn[SERNUM_LEN + 1]; 323 u8 id[ID_LEN + 1]; 324 u8 pn[PN_LEN + 1]; 325 u8 na[MACADDR_LEN + 1]; 326 }; 327 328 /* 329 * Maximum resources provisioned for a PCI PF. 330 */ 331 struct pf_resources { 332 unsigned int nvi; /* N virtual interfaces */ 333 unsigned int neq; /* N egress Qs */ 334 unsigned int nethctrl; /* N egress ETH or CTRL Qs */ 335 unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */ 336 unsigned int tc; /* PCI-E traffic class */ 337 unsigned int pmask; /* port access rights mask */ 338 unsigned int nexactf; /* N exact MPS filters */ 339 unsigned int r_caps; /* read capabilities */ 340 unsigned int wx_caps; /* write/execute capabilities */ 341 }; 342 343 struct pci_params { 344 uint16_t vendor_id; 345 uint16_t device_id; 346 uint32_t vpd_cap_addr; 347 uint16_t speed; 348 uint8_t width; 349 }; 350 351 /* 352 * Firmware device log. 353 */ 354 struct devlog_params { 355 u32 memtype; /* which memory (EDC0, EDC1, MC) */ 356 u32 start; /* start of log in firmware memory */ 357 u32 size; /* size of log */ 358 }; 359 360 /* Stores chip specific parameters */ 361 struct arch_specific_params { 362 u8 nchan; 363 u8 pm_stats_cnt; 364 u8 cng_ch_bits_log; /* congestion channel map bits width */ 365 u16 mps_rplc_size; 366 u16 vfcount; 367 u32 sge_fl_db; 368 u16 mps_tcam_size; 369 }; 370 371 struct adapter_params { 372 struct sge_params sge; 373 struct tp_params tp; 374 struct vpd_params vpd; 375 struct pf_resources pfres; 376 struct pci_params pci; 377 struct devlog_params devlog; 378 enum pcie_memwin drv_memwin; 379 380 unsigned int sf_size; /* serial flash size in bytes */ 381 unsigned int sf_nsec; /* # of flash sectors */ 382 383 unsigned int fw_vers; /* firmware version */ 384 unsigned int bs_vers; /* bootstrap version */ 385 unsigned int tp_vers; /* TP microcode version */ 386 unsigned int er_vers; /* expansion ROM version */ 387 unsigned int scfg_vers; /* Serial Configuration version */ 388 unsigned int vpd_vers; /* VPD version */ 389 390 unsigned short mtus[NMTUS]; 391 unsigned short a_wnd[NCCTRL_WIN]; 392 unsigned short b_wnd[NCCTRL_WIN]; 393 394 unsigned int mc_size; /* MC memory size */ 395 unsigned int nfilters; /* size of filter region */ 396 397 unsigned int cim_la_size; 398 399 unsigned char nports; /* # of ethernet ports */ 400 unsigned char portvec; 401 unsigned char offload; 402 403 unsigned char bypass; 404 unsigned char hash_filter; 405 406 enum chip_type chip; /* chip code */ 407 struct arch_specific_params arch; /* chip specific params */ 408 409 unsigned int ofldq_wr_cred; 410 411 unsigned int nsched_cls; /* number of traffic classes */ 412 413 unsigned int max_ordird_qp; /* Max read depth per RDMA QP */ 414 unsigned int max_ird_adapter; /* Max read depth per adapter */ 415 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 416 unsigned char ulp_t10dif; /* t10dif support for ulp */ 417 unsigned char ulp_crypto; /* Crypto support */ 418 bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */ 419 bool filter2_wr_support; /* FW support for FILTER2_WR */ 420 bool viid_smt_extn_support; /* FW returns vin and smt index? */ 421 u8 fw_caps_support; /* 32-bit Port Capabilities */ 422 423 /* 424 * MPS Buffer Group Map[per Port]. Bit i is set if buffer group i is 425 * used by the Port 426 */ 427 u8 mps_bg_map[MAX_NPORTS]; /* MPS Buffer Group Map */ 428 bool write_w_imm_support; /* FW supports WRITE_WITH_IMMEDIATE */ 429 bool write_cmpl_support; /* FW supports WRITE_CMPL */ 430 /* FW supports adding source mac address to TCAM */ 431 bool smac_add_support; 432 }; 433 434 /* 435 * State needed to monitor the forward progress of SGE Ingress DMA activities 436 * and possible hangs. 437 */ 438 struct sge_idma_monitor_state { 439 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ 440 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ 441 unsigned int idma_state[2]; /* IDMA Hang detect state */ 442 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ 443 unsigned int idma_warn[2]; /* time to warning in HZ */ 444 }; 445 446 /* 447 * Firmware Mailbox Command/Reply log. All values are in Host-Endian format. 448 * The access and execute times are signed in order to accommodate negative 449 * error returns. 450 */ 451 struct mbox_cmd { 452 u64 cmd[MBOX_LEN/8]; /* a Firmware Mailbox Command/Reply */ 453 u64 timestamp; /* OS-dependent timestamp */ 454 u32 seqno; /* sequence number */ 455 s16 access; /* time (ms) to access mailbox */ 456 s16 execute; /* time (ms) to execute */ 457 }; 458 459 struct mbox_cmd_log { 460 unsigned int size; /* number of entries in the log */ 461 unsigned int cursor; /* next position in the log to write */ 462 u32 seqno; /* next sequence number */ 463 /* variable length mailbox command log starts here */ 464 }; 465 466 struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log, 467 unsigned int entry_idx); 468 469 #include <t4fw_interface.h> 470 471 #define FW_VERSION(chip) ( \ 472 V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \ 473 V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \ 474 V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \ 475 V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD)) 476 #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf) 477 478 struct fw_info { 479 u8 chip; 480 char *fs_name; 481 char *fw_mod_name; 482 struct fw_hdr fw_hdr; /* XXX: waste of space, need a sparse struct */ 483 }; 484 485 struct trace_params { 486 u32 data[TRACE_LEN / 4]; 487 u32 mask[TRACE_LEN / 4]; 488 unsigned short snap_len; 489 unsigned short min_len; 490 unsigned char skip_ofst; 491 unsigned char skip_len; 492 unsigned char invert; 493 unsigned char port; 494 }; 495 496 /* 497 * Firmware Port Capabilities types. 498 */ 499 typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */ 500 typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */ 501 502 enum fw_caps { 503 FW_CAPS_UNKNOWN = 0, /* 0'ed out initial state */ 504 FW_CAPS16 = 1, /* old Firmware: 16-bit Port Capabilities */ 505 FW_CAPS32 = 2, /* new Firmware: 32-bit Port Capabilities */ 506 }; 507 508 struct link_config { 509 fw_port_cap32_t pcaps; /* link capabilities */ 510 fw_port_cap32_t acaps; /* advertised capabilities */ 511 fw_port_cap32_t lpacaps; /* peer advertised capabilities */ 512 513 fw_port_cap32_t link_caps; /* current link capabilities */ 514 fw_port_cap32_t admin_caps; /* admin configured link capabilities */ 515 516 unsigned char link_ok; /* link up? */ 517 unsigned char link_down_rc; /* link down reason */ 518 519 /* 520 * State variables between Common Code and OS-dependent "contract" 521 * routines. These are used to communicate information and desired 522 * actions out-of-band. 523 */ 524 bool new_module; /* ->OS Transceiver Module inserted */ 525 bool redo_l1cfg; /* ->CC redo current "sticky" L1 CFG */ 526 }; 527 528 /* 529 * Partial EEPROM Vital Product Data structure. Includes only the ID and 530 * VPD-R sections. 531 */ 532 struct t4_vpd_hdr { 533 u8 id_tag; 534 u8 id_len[2]; 535 u8 id_data[ID_LEN]; 536 u8 vpdr_tag; 537 u8 vpdr_len[2]; 538 }; 539 540 #if _KERNEL 541 #include "adapter.h" 542 543 #ifndef PCI_VENDOR_ID_CHELSIO 544 # define PCI_VENDOR_ID_CHELSIO 0x1425 545 #endif 546 547 #define for_each_port(adapter, iter) \ 548 for (iter = 0; iter < (adapter)->params.nports; ++iter) 549 550 int is_offload(const struct adapter *adap); 551 unsigned int core_ticks_per_usec(const struct adapter *adap); 552 unsigned int us_to_core_ticks(const struct adapter *adap, 553 unsigned int us); 554 unsigned int dack_ticks_to_usec(const struct adapter *adap, 555 unsigned int ticks); 556 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, u32 val); 557 558 void t4_record_mbox_marker(struct adapter *adapter, 559 const void *marker, unsigned int size); 560 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 561 int size, void *rpl, bool sleep_ok, int timeout); 562 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 563 void *rpl, bool sleep_ok); 564 565 int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 566 const void *cmd, int size, void *rpl, 567 int timeout); 568 int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 569 int size, void *rpl); 570 int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 571 int size, void *rpl); 572 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 573 unsigned int data_reg, u32 *vals, unsigned int nregs, 574 unsigned int start_idx); 575 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 576 unsigned int data_reg, const u32 *vals, 577 unsigned int nregs, unsigned int start_idx); 578 579 void t4_hw_pci_read_cfg4(adapter_t *adapter, int reg, u32 *val); 580 581 struct fw_filter_wr; 582 583 void t4_intr_enable(struct adapter *adapter); 584 void t4_intr_disable(struct adapter *adapter); 585 int t4_slow_intr_handler(struct adapter *adapter); 586 587 int t4_hash_mac_addr(const u8 *addr); 588 589 unsigned int t4_link_fwcap_to_speed(fw_port_cap32_t caps); 590 int t4_link_set_autoneg(struct port_info *pi, u8 autoneg, 591 fw_port_cap32_t *new_caps); 592 int t4_link_set_pause(struct port_info *pi, cc_pause_t pause, 593 fw_port_cap32_t *new_caps); 594 int t4_link_set_fec(struct port_info *pi, cc_fec_t fec, 595 fw_port_cap32_t *new_caps); 596 int t4_link_set_speed(struct port_info *pi, fw_port_cap32_t speed, u8 en, 597 fw_port_cap32_t *new_caps); 598 int t4_link_l1cfg_core(struct adapter *adapter, unsigned int mbox, 599 unsigned int port, struct link_config *lc, 600 fw_port_cap32_t rcap, bool sleep_ok, int timeout); 601 static inline int t4_link_l1cfg(struct adapter *adapter, unsigned int mbox, 602 unsigned int port, struct link_config *lc, 603 fw_port_cap32_t rcap) 604 { 605 return t4_link_l1cfg_core(adapter, mbox, port, lc, rcap, 606 true, FW_CMD_MAX_TIMEOUT); 607 } 608 static inline int t4_link_l1cfg_ns(struct adapter *adapter, unsigned int mbox, 609 unsigned int port, struct link_config *lc, 610 fw_port_cap32_t rcap) 611 { 612 return t4_link_l1cfg_core(adapter, mbox, port, lc, rcap, 613 false, FW_CMD_MAX_TIMEOUT); 614 } 615 616 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 617 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data); 618 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data); 619 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz); 620 int t4_seeprom_wp(struct adapter *adapter, int enable); 621 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p); 622 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p); 623 int t4_get_pfres(struct adapter *adapter); 624 int t4_read_flash(struct adapter *adapter, unsigned int addr, unsigned int nwords, 625 u32 *data, int byte_oriented); 626 int t4_write_flash(struct adapter *adapter, unsigned int addr, 627 unsigned int n, const u8 *data, int byte_oriented); 628 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size, 629 unsigned int bootstrap); 630 int t4_load_phy_fw(struct adapter *adap, 631 int win, t4_os_lock_t *lock, 632 int (*phy_fw_version)(const u8 *, size_t), 633 const u8 *phy_fw_data, size_t phy_fw_size); 634 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver); 635 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); 636 int t5_fw_init_extern_mem(struct adapter *adap); 637 #ifdef CHELSIO_T4_DIAGS 638 int t4_erase_sf(struct adapter *adapter); 639 #endif 640 int t4_load_bootcfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); 641 int t4_read_bootcfg(struct adapter *adap, u8 *cfg_data, unsigned int size); 642 int t4_load_boot(struct adapter *adap, u8 *boot_data, 643 unsigned int boot_addr, unsigned int size); 644 int t4_flash_erase_sectors(struct adapter *adapter, int start, int end); 645 int t4_flash_cfg_addr(struct adapter *adapter); 646 int t4_check_fw_version(struct adapter *adap); 647 int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); 648 int t4_get_fw_version(struct adapter *adapter, u32 *vers); 649 int t4_get_bs_version(struct adapter *adapter, u32 *vers); 650 int t4_get_tp_version(struct adapter *adapter, u32 *vers); 651 int t4_get_exprom_version(struct adapter *adapter, u32 *vers); 652 int t4_get_scfg_version(struct adapter *adapter, u32 *vers); 653 int t4_get_vpd_version(struct adapter *adapter, u32 *vers); 654 int t4_get_version_info(struct adapter *adapter); 655 void t4_dump_version_info(struct adapter *adapter); 656 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, 657 const u8 *fw_data, unsigned int fw_size, 658 struct fw_hdr *card_fw, const int t4_fw_install, 659 enum dev_state state, int *reset); 660 int t4_wait_dev_ready(struct adapter *adapter); 661 enum chip_type t4_get_chip_type(struct adapter *adap, int ver); 662 int t4_prep_adapter(struct adapter *adapter, bool reset); 663 int t4_prep_pf(struct adapter *adapter); 664 int t4_prep_master_pf(struct adapter *adapter); 665 int t4_shutdown_adapter(struct adapter *adapter); 666 667 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 668 int t4_bar2_sge_qregs(struct adapter *adapter, 669 unsigned int qid, 670 enum t4_bar2_qtype qtype, 671 int user, 672 u64 *pbar2_qoffset, 673 unsigned int *pbar2_qid); 674 675 int t4_init_devlog_params(struct adapter *adapter, int fw_attach); 676 int t4_init_sge_params(struct adapter *adapter); 677 int t4_init_tp_params(struct adapter *adap, bool sleep_ok); 678 int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 679 int t4_create_filter_info(const struct adapter *adapter, 680 u64 *filter_value, u64 *filter_mask, 681 int fcoe, int port, int vnic_id, 682 int vlan, int vlan_pcp, int vlan_dei, 683 int tos, int protocol, int ethertype, 684 int macmatch, int mpshittype, int fragmentation); 685 int t4_init_rss_mode(struct adapter *adap, int mbox); 686 int t4_init_portinfo_viid(struct port_info *pi, int mbox, 687 int port, int pf, int vf, u8 mac[], bool alloc_vi); 688 int t4_init_portinfo(struct port_info *pi, int mbox, 689 int port, int pf, int vf, u8 mac[]); 690 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 691 int t4_mirror_init(struct adapter *adap, int mbox, int pf, int vf, 692 bool enable_mirror); 693 void t4_fatal_err(struct adapter *adapter); 694 void t4_db_full(struct adapter *adapter); 695 void t4_db_dropped(struct adapter *adapter); 696 int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, 697 int filter_index, int enable); 698 void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, 699 int filter_index, int *enabled); 700 unsigned int t4_chip_rss_size(struct adapter *adapter); 701 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 702 int start, int n, const u16 *rspq, unsigned int nrspq); 703 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 704 unsigned int flags); 705 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 706 unsigned int flags, unsigned int defq, unsigned int skeyidx, 707 unsigned int skey); 708 int t4_read_rss(struct adapter *adapter, u16 *entries); 709 void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok); 710 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx, 711 bool sleep_ok); 712 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 713 u32 *valp, bool sleep_ok); 714 void t4_write_rss_pf_config(struct adapter *adapter, unsigned int index, 715 u32 val, bool sleep_ok); 716 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 717 u32 *vfl, u32 *vfh, bool sleep_ok); 718 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok); 719 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok); 720 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx); 721 unsigned int t4_get_tp_e2c_map(struct adapter *adapter, int pidx); 722 unsigned int t4_get_tp_ch_map(struct adapter *adapter, int pidx); 723 int t4_mps_set_active_ports(struct adapter *adap, unsigned int port_mask); 724 int t4_read_tcb(struct adapter *adap, int win, int tid, u32 tcb[TCB_SIZE/4]); 725 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 726 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 727 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 728 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n); 729 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n); 730 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 731 unsigned int *valp); 732 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 733 const unsigned int *valp); 734 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 735 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 736 unsigned int *pif_req_wrptr, unsigned int *pif_rsp_wrptr); 737 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); 738 int t4_get_flash_params(struct adapter *adapter); 739 740 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg, int drv_fw_attach); 741 int t4_get_util_window(struct adapter *adap, int drv_fw_attach); 742 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window); 743 void t4_idma_monitor_init(struct adapter *adapter, 744 struct sge_idma_monitor_state *idma); 745 void t4_idma_monitor(struct adapter *adapter, 746 struct sge_idma_monitor_state *idma, 747 int hz, int ticks); 748 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf, 749 unsigned int naddr, u8 *addr); 750 751 #define T4_MEMORY_WRITE 0 752 #define T4_MEMORY_READ 1 753 int t4_memory_rw_addr(struct adapter *adap, int win, 754 u32 addr, u32 len, 755 void *hbuf, int dir); 756 int t4_memory_rw_mtype(struct adapter *adap, int win, 757 int mtype, u32 maddr, u32 len, 758 void *hbuf, int dir); 759 760 int t4_memory_rw(struct adapter *adap, int win, 761 int mtype, u32 maddr, u32 len, 762 void *hbuf, int dir); 763 int hash_mac_addr(const u8 *addr); 764 765 bool t4_is_inserted_mod_type(unsigned int fw_mod_type); 766 extern unsigned int t4_get_regs_len(struct adapter *adapter); 767 extern void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); 768 769 const char *t4_get_port_type_description(enum fw_port_type port_type); 770 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 771 void t4_get_port_stats_offset(struct adapter *adap, int idx, 772 struct port_stats *stats, 773 struct port_stats *offset); 774 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 775 void t4_clr_port_stats(struct adapter *adap, int idx); 776 777 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 778 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 779 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]); 780 void t4_get_tx_sched(struct adapter *adap, unsigned int sched, unsigned int *kbps, 781 unsigned int *ipg, bool sleep_ok); 782 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 783 unsigned int mask, unsigned int val); 784 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 785 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st, 786 bool sleep_ok); 787 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st, 788 bool sleep_ok); 789 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st, 790 bool sleep_ok); 791 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st, 792 bool sleep_ok); 793 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 794 struct tp_tcp_stats *v6, bool sleep_ok); 795 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 796 struct tp_fcoe_stats *st, bool sleep_ok); 797 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 798 const unsigned short *alpha, const unsigned short *beta); 799 800 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 801 802 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); 803 int t4_set_filter_mode(struct adapter *adap, unsigned int mode_map, 804 bool sleep_ok); 805 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, 806 int rqtype, int qid); 807 808 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 809 enum dev_master master, enum dev_state *state); 810 int t4_fw_bye(struct adapter *adap, unsigned int mbox); 811 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 812 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 813 const u8 *fw_data, unsigned int size, int force); 814 int t4_fl_pkt_align(struct adapter *adap, bool is_packed); 815 int t4_fixup_host_params_compat(struct adapter *adap, unsigned int page_size, 816 unsigned int cache_line_size, 817 enum chip_type chip_compat); 818 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 819 unsigned int cache_line_size); 820 int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 821 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 822 unsigned int vf, unsigned int nparams, const u32 *params, 823 u32 *val); 824 int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf, 825 unsigned int vf, unsigned int nparams, const u32 *params, 826 u32 *val); 827 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 828 unsigned int vf, unsigned int nparams, const u32 *params, 829 u32 *val, int rw, bool sleep_ok); 830 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 831 unsigned int pf, unsigned int vf, 832 unsigned int nparams, const u32 *params, 833 const u32 *val, int timeout); 834 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 835 unsigned int vf, unsigned int nparams, const u32 *params, 836 const u32 *val); 837 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 838 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 839 unsigned int rxqi, unsigned int rxq, unsigned int tc, 840 unsigned int vi, unsigned int cmask, unsigned int pmask, 841 unsigned int exactf, unsigned int rcaps, unsigned int wxcaps); 842 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox, 843 unsigned int port, unsigned int pf, unsigned int vf, 844 unsigned int nmac, u8 *mac, unsigned int *rss_size, 845 u8 *vivld, u8 *vin, 846 unsigned int portfunc, unsigned int idstype); 847 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 848 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 849 unsigned int *rss_size, u8 *vivld, u8 *vin); 850 int t4_free_vi(struct adapter *adap, unsigned int mbox, 851 unsigned int pf, unsigned int vf, 852 unsigned int viid); 853 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 854 int mtu, int promisc, int all_multi, int bcast, int vlanex, 855 bool sleep_ok); 856 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, unsigned int viid, 857 bool free, unsigned int naddr, const u8 **addr, u16 *idx, 858 u64 *hash, bool sleep_ok); 859 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox, 860 unsigned int viid, unsigned int naddr, 861 const u8 **addr, bool sleep_ok); 862 int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid, 863 int idx, bool sleep_ok); 864 int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid, 865 const u8 *addr, const u8 *mask, unsigned int idx, 866 u8 lookup_type, u8 port_id, bool sleep_ok); 867 int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid, 868 const u8 *addr, const u8 *mask, unsigned int idx, 869 u8 lookup_type, u8 port_id, bool sleep_ok); 870 int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid, 871 const u8 *addr, const u8 *mask, unsigned int vni, 872 unsigned int vni_mask, u8 dip_hit, u8 lookup_type, 873 bool sleep_ok); 874 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 875 int idx, const u8 *addr, bool persist, u8 *smt_idx); 876 int t4_del_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 877 const u8 *addr, bool smac); 878 int t4_add_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 879 int idx, const u8 *addr, bool persist, u8 *smt_idx, bool smac); 880 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 881 bool ucast, u64 vec, bool sleep_ok); 882 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 883 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 884 int t4_enable_pi_params(struct adapter *adap, unsigned int mbox, 885 struct port_info *pi, 886 bool rx_en, bool tx_en, bool dcb_en); 887 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 888 bool rx_en, bool tx_en); 889 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 890 unsigned int nblinks); 891 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 892 unsigned int mmd, unsigned int reg, unsigned int *valp); 893 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 894 unsigned int mmd, unsigned int reg, unsigned int val); 895 int t4_i2c_io(struct adapter *adap, unsigned int mbox, 896 int port, unsigned int devid, 897 unsigned int offset, unsigned int len, 898 u8 *buf, bool write); 899 int t4_i2c_rd(struct adapter *adap, unsigned int mbox, 900 int port, unsigned int devid, 901 unsigned int offset, unsigned int len, 902 u8 *buf); 903 int t4_i2c_wr(struct adapter *adap, unsigned int mbox, 904 int port, unsigned int devid, 905 unsigned int offset, unsigned int len, 906 u8 *buf); 907 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 908 unsigned int vf, unsigned int iqtype, unsigned int iqid, 909 unsigned int fl0id, unsigned int fl1id); 910 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 911 unsigned int vf, unsigned int iqtype, unsigned int iqid, 912 unsigned int fl0id, unsigned int fl1id); 913 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 914 unsigned int vf, unsigned int eqid); 915 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 916 unsigned int vf, unsigned int eqid); 917 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 918 unsigned int vf, unsigned int eqid); 919 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, 920 enum ctxt_type ctype, u32 *data); 921 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type ctype, 922 u32 *data); 923 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type); 924 int t4_read_sge_dbqtimers(struct adapter *adap, unsigned int ndbqtimers, 925 u16 *dbqtimers); 926 const char *t4_link_down_rc_str(unsigned char link_down_rc); 927 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl); 928 int t4_update_port_info(struct port_info *pi); 929 int t4_get_link_params(struct port_info *pi, unsigned int *link_okp, 930 unsigned int *speedp, unsigned int *mtup); 931 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 932 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, u32 addr, u32 val); 933 934 int t4_sched_config(struct adapter *adapter, int type, int minmaxen); 935 int t4_sched_params(struct adapter *adapter, 936 int channel, int cls, 937 int level, int mode, int type, 938 int rateunit, int ratemode, 939 int minrate, int maxrate, int weight, 940 int pktsize, int burstsize); 941 int t4_read_sched_params(struct adapter *adapter, 942 int channel, int cls, 943 int *level, int *mode, int *type, 944 int *rateunit, int *ratemode, 945 int *minrate, int *maxrate, int *weight, 946 int *pktsize, int *burstsize); 947 int t4_config_watchdog(struct adapter *adapter, unsigned int mbox, 948 unsigned int pf, unsigned int vf, 949 unsigned int timeout, unsigned int action); 950 int t4_get_devlog_level(struct adapter *adapter, unsigned int *level); 951 int t4_set_devlog_level(struct adapter *adapter, unsigned int level); 952 953 void t4_sge_decode_idma_state(struct adapter *adapter, int state); 954 955 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 956 u32 start_index, bool sleep_ok); 957 void t4_tp_pio_write(struct adapter *adap, u32 *buff, u32 nregs, 958 u32 start_index, bool sleep_ok); 959 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 960 u32 start_index, bool sleep_ok); 961 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, 962 u32 start_index, bool sleep_ok); 963 int t4_configure_ringbb(struct adapter *adap); 964 int t4_configure_add_smac(struct adapter *adap); 965 int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf, 966 u16 vlan); 967 #endif 968 #ifdef __cplusplus 969 } 970 #endif 971 #endif /* __CHELSIO_COMMON_H */ 972