1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 /* 28 * Copyright (C) 4Front Technologies 1996-2009. 29 */ 30 31 /* 32 * Purpose: Driver for the Creative Sound Blaster Live! and Audigy/2/4 33 * sound cards 34 */ 35 36 #include <sys/types.h> 37 #include <sys/modctl.h> 38 #include <sys/kmem.h> 39 #include <sys/conf.h> 40 #include <sys/ddi.h> 41 #include <sys/sunddi.h> 42 #include <sys/pci.h> 43 #include <sys/note.h> 44 #include <sys/stdbool.h> 45 #include <sys/audio/audio_driver.h> 46 #include <sys/audio/ac97.h> 47 48 #include "audioemu10k.h" 49 #include <sys/promif.h> 50 51 /* 52 * Include the DSP files for emu10k1 (Live!) and emu10k2 (Audigy) 53 */ 54 #include "emu10k_gpr.h" 55 #include "emu10k1_dsp.h" 56 #include "emu10k2_dsp.h" 57 58 static struct ddi_device_acc_attr dev_attr = { 59 DDI_DEVICE_ATTR_V0, 60 DDI_STRUCTURE_LE_ACC, 61 DDI_STRICTORDER_ACC 62 }; 63 64 static struct ddi_device_acc_attr buf_attr = { 65 DDI_DEVICE_ATTR_V0, 66 DDI_NEVERSWAP_ACC, 67 DDI_STRICTORDER_ACC 68 }; 69 70 71 /* 72 * EMU10K routing stuff. 73 */ 74 #define MAX_SENDS 4 75 #define SEND_L 0 76 #define SEND_R 1 77 #define SEND_SURRL 2 78 #define SEND_SURRR 3 79 #define SEND_CEN 4 80 #define SEND_LFE 5 81 #define SEND_SIDEL 6 82 #define SEND_SIDER 7 83 84 #define SPDIF_L 20 85 #define SPDIF_R 21 86 87 /* 88 * Recording sources... we start from 16 to ensure that the 89 * record sources don't collide with AC'97 record sources in 90 * the control value. 91 */ 92 #define INPUT_AC97 1 93 #define INPUT_SPD1 2 94 #define INPUT_SPD2 3 95 #define INPUT_DIGCD 4 96 #define INPUT_AUX2 5 97 #define INPUT_LINE2 6 98 #define INPUT_STEREOMIX 7 99 100 static uint8_t front_routing[MAX_SENDS] = { 101 SEND_L, SEND_R, 0x3f, 0x3f 102 }; 103 static uint8_t surr_routing[MAX_SENDS] = { 104 SEND_SURRL, SEND_SURRR, 0x3f, 0x3f 105 }; 106 static uint8_t clfe_routing[MAX_SENDS] = { 107 SEND_CEN, SEND_LFE, 0x3f, 0x3f 108 }; 109 static uint8_t side_routing[MAX_SENDS] = { 110 SEND_SIDEL, SEND_SIDER, 0x3f, 0x3f 111 }; 112 static uint8_t no_routing[MAX_SENDS] = { 113 0x3f, 0x3f, 0x3f, 0x3f 114 }; 115 116 /* 117 * SB Live! cannot do DMA above 2G addresses. Audigy/2/4 have special 8k page 118 * mode that supports high addresses. However, we should not need this except 119 * on SPARC. For simplicity's sake, we are only delivering this driver for 120 * x86 platforms. If SPARC support is desired, then the code will have to 121 * be modified to support full 32-bit addressing. (And again, SB Live! 122 * can't do it anyway.) 123 */ 124 125 static ddi_dma_attr_t dma_attr_buf = { 126 DMA_ATTR_V0, /* Version */ 127 0x00000000ULL, /* Address low */ 128 0x7ffffff0ULL, /* Address high */ 129 0xffffffffULL, /* Counter max */ 130 1ULL, /* Default byte align */ 131 0x7f, /* Burst size */ 132 0x1, /* Minimum xfer size */ 133 0xffffffffULL, /* Maximum xfer size */ 134 0xffffffffULL, /* Max segment size */ 135 1, /* S/G list length */ 136 1, /* Granularity */ 137 0 /* Flag */ 138 }; 139 140 static int emu10k_attach(dev_info_t *); 141 static int emu10k_resume(dev_info_t *); 142 static int emu10k_detach(emu10k_devc_t *); 143 static int emu10k_suspend(emu10k_devc_t *); 144 145 static int emu10k_open(void *, int, unsigned *, unsigned *, caddr_t *); 146 static void emu10k_close(void *); 147 static int emu10k_start(void *); 148 static void emu10k_stop(void *); 149 static int emu10k_format(void *); 150 static int emu10k_channels(void *); 151 static int emu10k_rate(void *); 152 static uint64_t emu10k_count(void *); 153 static void emu10k_sync(void *, unsigned); 154 static void emu10k_chinfo(void *, int, unsigned *, unsigned *); 155 156 static uint16_t emu10k_read_ac97(void *, uint8_t); 157 static void emu10k_write_ac97(void *, uint8_t, uint16_t); 158 static int emu10k_alloc_port(emu10k_devc_t *, int); 159 static void emu10k_destroy(emu10k_devc_t *); 160 static int emu10k_setup_intrs(emu10k_devc_t *); 161 static int emu10k_hwinit(emu10k_devc_t *); 162 static uint_t emu10k_intr(caddr_t, caddr_t); 163 static void emu10k_init_effects(emu10k_devc_t *); 164 165 static audio_engine_ops_t emu10k_engine_ops = { 166 AUDIO_ENGINE_VERSION, 167 emu10k_open, 168 emu10k_close, 169 emu10k_start, 170 emu10k_stop, 171 emu10k_count, 172 emu10k_format, 173 emu10k_channels, 174 emu10k_rate, 175 emu10k_sync, 176 NULL, 177 emu10k_chinfo, 178 NULL 179 }; 180 181 static uint16_t 182 emu10k_read_ac97(void *arg, uint8_t index) 183 { 184 emu10k_devc_t *devc = arg; 185 int dtemp = 0, i; 186 187 mutex_enter(&devc->mutex); 188 OUTB(devc, index, devc->regs + 0x1e); 189 for (i = 0; i < 10000; i++) 190 if (INB(devc, devc->regs + 0x1e) & 0x80) 191 break; 192 193 if (i == 1000) { 194 mutex_exit(&devc->mutex); 195 return (0); /* Timeout */ 196 } 197 dtemp = INW(devc, devc->regs + 0x1c); 198 199 mutex_exit(&devc->mutex); 200 201 return (dtemp & 0xffff); 202 } 203 204 static void 205 emu10k_write_ac97(void *arg, uint8_t index, uint16_t data) 206 { 207 emu10k_devc_t *devc = arg; 208 int i; 209 210 mutex_enter(&devc->mutex); 211 212 OUTB(devc, index, devc->regs + 0x1e); 213 for (i = 0; i < 10000; i++) 214 if (INB(devc, devc->regs + 0x1e) & 0x80) 215 break; 216 OUTW(devc, data, devc->regs + 0x1c); 217 218 mutex_exit(&devc->mutex); 219 } 220 221 static uint32_t 222 emu10k_read_reg(emu10k_devc_t *devc, int reg, int chn) 223 { 224 uint32_t ptr, ptr_addr_mask, val, mask, size, offset; 225 226 ptr_addr_mask = (devc->feature_mask & 227 (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL)) ? 228 0x0fff0000 : 0x07ff0000; 229 ptr = ((reg << 16) & ptr_addr_mask) | (chn & 0x3f); 230 OUTL(devc, ptr, devc->regs + 0x00); /* Pointer */ 231 val = INL(devc, devc->regs + 0x04); /* Data */ 232 if (reg & 0xff000000) { 233 size = (reg >> 24) & 0x3f; 234 offset = (reg >> 16) & 0x1f; 235 mask = ((1 << size) - 1) << offset; 236 val &= mask; 237 val >>= offset; 238 } 239 240 return (val); 241 } 242 243 static void 244 emu10k_write_reg(emu10k_devc_t *devc, int reg, int chn, uint32_t value) 245 { 246 uint32_t ptr, ptr_addr_mask, mask, size, offset; 247 248 ptr_addr_mask = (devc->feature_mask & 249 (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL)) ? 250 0x0fff0000 : 0x07ff0000; 251 ptr = ((reg << 16) & ptr_addr_mask) | (chn & 0x3f); 252 OUTL(devc, ptr, devc->regs + 0x00); /* Pointer */ 253 if (reg & 0xff000000) { 254 size = (reg >> 24) & 0x3f; 255 offset = (reg >> 16) & 0x1f; 256 mask = ((1 << size) - 1) << offset; 257 value <<= offset; 258 value &= mask; 259 value |= INL(devc, devc->regs + 0x04) & ~mask; /* data */ 260 } 261 OUTL(devc, value, devc->regs + 0x04); /* Data */ 262 } 263 264 static void 265 emu10k_write_routing(emu10k_devc_t *devc, int voice, unsigned char *routing) 266 { 267 int i; 268 269 ASSERT(routing != NULL); 270 271 if (devc->feature_mask & (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL)) { 272 unsigned int srda = 0; 273 274 for (i = 0; i < 4; i++) 275 srda |= routing[i] << (i * 8); 276 277 emu10k_write_reg(devc, SRDA, voice, srda); 278 } else { 279 int fxrt = 0; 280 281 for (i = 0; i < 4; i++) 282 fxrt |= routing[i] << ((i * 4) + 16); 283 emu10k_write_reg(devc, FXRT, voice, fxrt); 284 } 285 } 286 287 static void 288 emu10k_write_efx(emu10k_devc_t *devc, int reg, unsigned int value) 289 { 290 emu10k_write_reg(devc, reg, 0, value); 291 } 292 293 static uint_t 294 emu10k_intr(caddr_t argp, caddr_t nocare) 295 { 296 emu10k_devc_t *devc = (void *) argp; 297 emu10k_portc_t *portc; 298 uint32_t status; 299 audio_engine_t *cons = NULL, *prod = NULL; 300 301 302 _NOTE(ARGUNUSED (nocare)); 303 304 mutex_enter(&devc->mutex); 305 if (devc->suspended) { 306 mutex_exit(&devc->mutex); 307 return (DDI_INTR_UNCLAIMED); 308 } 309 310 status = INL(devc, devc->regs + INTPEND); 311 312 if (status == 0) { 313 mutex_exit(&devc->mutex); 314 return (DDI_INTR_UNCLAIMED); 315 } 316 317 if (status & INT_CL) { /* channel loop */ 318 emu10k_write_reg(devc, CLIPL, 0, (1U << 8)); 319 OUTL(devc, INT_CL, devc->regs + INTPEND); 320 portc = devc->portc[EMU10K_PLAY]; 321 if (portc->active) { 322 cons = portc->engine; 323 } 324 } 325 if (status & (INT_AF|INT_AH|INT_MF|INT_MH)) { /* ADC interrupt */ 326 OUTL(devc, INT_AF|INT_AH|INT_MF|INT_MH, devc->regs + INTPEND); 327 portc = devc->portc[EMU10K_REC]; 328 if (portc->active) { 329 prod = portc->engine; 330 } 331 } 332 333 mutex_exit(&devc->mutex); 334 335 if (cons) { 336 audio_engine_consume(cons); 337 } 338 if (prod) { 339 audio_engine_produce(prod); 340 } 341 342 return (DDI_INTR_CLAIMED); 343 } 344 345 /* 346 * Audio routines 347 */ 348 349 static void 350 emu10k_update_output_volume(emu10k_portc_t *portc, int voice, int chn) 351 { 352 emu10k_devc_t *devc = portc->devc; 353 unsigned int tmp; 354 unsigned char send[2]; 355 356 /* 357 * Each voice operator of EMU10k has 4 sends (0=left, 1=right, 358 * 2=surround_left, 3=surround_right). The original OSS driver 359 * used all of them to spread stereo output to two different 360 * speaker pairs. This Boomer version uses only the first two 361 * sends. The other sends are set to 0. 362 * 363 * Boomer uses multiple voice pairs to play multichannel 364 * audio. This function is used to update only one of these 365 * pairs. 366 */ 367 368 send[0] = 0xff; /* Max */ 369 send[1] = 0xff; /* Max */ 370 371 /* Analog voice */ 372 if (chn == LEFT_CH) { 373 send[1] = 0; 374 } else { 375 send[0] = 0; 376 } 377 378 tmp = emu10k_read_reg(devc, PTAB, voice) & 0xffff0000; 379 emu10k_write_reg(devc, PTAB, voice, tmp | (send[0] << 8) | send[1]); 380 } 381 382 static void 383 emu10k_setup_voice(emu10k_portc_t *portc, int voice, int chn, int buf_offset) 384 { 385 emu10k_devc_t *devc = portc->devc; 386 unsigned int nCRA = 0; 387 388 unsigned int loop_start, loop_end, buf_size; 389 390 int sz; 391 int start_pos; 392 393 emu10k_write_reg(devc, VEDS, voice, 0x0); /* OFF */ 394 emu10k_write_reg(devc, VTFT, voice, 0xffff); 395 emu10k_write_reg(devc, CVCF, voice, 0xffff); 396 397 sz = 2; /* Shift value for 16 bits stereo */ 398 399 /* Size of one stereo sub buffer */ 400 buf_size = (portc->buf_size / portc->channels) * 2; 401 loop_start = (portc->memptr + buf_offset) >> sz; 402 loop_end = (portc->memptr + buf_offset + buf_size) >> sz; 403 404 /* set stereo */ 405 emu10k_write_reg(devc, CPF, voice, 0x8000); 406 407 nCRA = 28; /* Stereo (16 bits) */ 408 start_pos = loop_start + nCRA; 409 410 /* SDL, ST, CA */ 411 412 emu10k_write_reg(devc, SDL, voice, loop_end); 413 emu10k_write_reg(devc, SCSA, voice, loop_start); 414 emu10k_write_reg(devc, PTAB, voice, 0); 415 416 emu10k_update_output_volume(portc, voice, chn); /* Set volume */ 417 418 emu10k_write_reg(devc, QKBCA, voice, start_pos); 419 420 emu10k_write_reg(devc, Z1, voice, 0); 421 emu10k_write_reg(devc, Z2, voice, 0); 422 423 /* This is really a physical address */ 424 emu10k_write_reg(devc, MAPA, voice, 425 0x1fff | (devc->silence_paddr << 1)); 426 emu10k_write_reg(devc, MAPB, voice, 427 0x1fff | (devc->silence_paddr << 1)); 428 429 emu10k_write_reg(devc, VTFT, voice, 0x0000ffff); 430 emu10k_write_reg(devc, CVCF, voice, 0x0000ffff); 431 emu10k_write_reg(devc, MEHA, voice, 0); 432 emu10k_write_reg(devc, MEDS, voice, 0x7f); 433 emu10k_write_reg(devc, MLV, voice, 0x8000); 434 emu10k_write_reg(devc, VLV, voice, 0x8000); 435 emu10k_write_reg(devc, VFM, voice, 0); 436 emu10k_write_reg(devc, TMFQ, voice, 0); 437 emu10k_write_reg(devc, VVFQ, voice, 0); 438 emu10k_write_reg(devc, MEV, voice, 0x8000); 439 emu10k_write_reg(devc, VEHA, voice, 0x7f7f); /* OK */ 440 /* No volume envelope delay (OK) */ 441 emu10k_write_reg(devc, VEV, voice, 0x8000); 442 emu10k_write_reg(devc, PEFE_FILTERAMOUNT, voice, 0x7f); 443 emu10k_write_reg(devc, PEFE_PITCHAMOUNT, voice, 0x00); 444 } 445 446 static void 447 emu10k_setup_silence(emu10k_portc_t *portc, int voice) 448 { 449 emu10k_devc_t *devc = portc->devc; 450 451 emu10k_write_reg(devc, VEDS, voice, 0x0); /* OFF */ 452 emu10k_write_reg(devc, VTFT, voice, 0xffff); 453 emu10k_write_reg(devc, CVCF, voice, 0xffff); 454 455 /* set stereo */ 456 emu10k_write_reg(devc, CPF, voice, 0x8000); 457 458 /* SDL, ST, CA */ 459 emu10k_write_reg(devc, SDL, voice, portc->fragfr); 460 emu10k_write_reg(devc, SCSA, voice, 0); 461 emu10k_write_reg(devc, PTAB, voice, 0); 462 emu10k_write_reg(devc, QKBCA, voice, 0); 463 464 emu10k_write_reg(devc, Z1, voice, 0); 465 emu10k_write_reg(devc, Z2, voice, 0); 466 467 /* This is really a physical address */ 468 emu10k_write_reg(devc, MAPA, voice, 469 0x1fff | (devc->silence_paddr << 1)); 470 emu10k_write_reg(devc, MAPB, voice, 471 0x1fff | (devc->silence_paddr << 1)); 472 473 emu10k_write_reg(devc, VTFT, voice, 0x0000ffff); 474 emu10k_write_reg(devc, CVCF, voice, 0x0000ffff); 475 emu10k_write_reg(devc, MEHA, voice, 0); 476 emu10k_write_reg(devc, MEDS, voice, 0x7f); 477 emu10k_write_reg(devc, MLV, voice, 0x8000); 478 emu10k_write_reg(devc, VLV, voice, 0x8000); 479 emu10k_write_reg(devc, VFM, voice, 0); 480 emu10k_write_reg(devc, TMFQ, voice, 0); 481 emu10k_write_reg(devc, VVFQ, voice, 0); 482 emu10k_write_reg(devc, MEV, voice, 0x8000); 483 emu10k_write_reg(devc, VEHA, voice, 0x7f7f); /* OK */ 484 /* No volume envelope delay (OK) */ 485 emu10k_write_reg(devc, VEV, voice, 0x8000); 486 emu10k_write_reg(devc, PEFE_FILTERAMOUNT, voice, 0x7f); 487 emu10k_write_reg(devc, PEFE_PITCHAMOUNT, voice, 0x00); 488 } 489 490 int 491 emu10k_open(void *arg, int flag, 492 unsigned *fragfrp, unsigned *nfragsp, caddr_t *bufp) 493 { 494 emu10k_portc_t *portc = arg; 495 emu10k_devc_t *devc = portc->devc; 496 497 _NOTE(ARGUNUSED(flag)); 498 499 portc->started = B_FALSE; 500 portc->active = B_FALSE; 501 *fragfrp = portc->fragfr; 502 *nfragsp = portc->nfrags; 503 *bufp = portc->buf_kaddr; 504 505 mutex_enter(&devc->mutex); 506 if (!devc->suspended) 507 portc->reset_port(portc); 508 portc->count = 0; 509 mutex_exit(&devc->mutex); 510 511 return (0); 512 } 513 514 void 515 emu10k_close(void *arg) 516 { 517 emu10k_portc_t *portc = arg; 518 emu10k_devc_t *devc = portc->devc; 519 520 mutex_enter(&devc->mutex); 521 if (!devc->suspended) 522 portc->stop_port(portc); 523 portc->started = B_FALSE; 524 mutex_exit(&devc->mutex); 525 } 526 527 int 528 emu10k_start(void *arg) 529 { 530 emu10k_portc_t *portc = arg; 531 emu10k_devc_t *devc = portc->devc; 532 533 mutex_enter(&devc->mutex); 534 if (!portc->started) { 535 if (!devc->suspended) 536 portc->start_port(portc); 537 portc->started = B_TRUE; 538 } 539 mutex_exit(&devc->mutex); 540 return (0); 541 } 542 543 void 544 emu10k_stop(void *arg) 545 { 546 emu10k_portc_t *portc = arg; 547 emu10k_devc_t *devc = portc->devc; 548 549 mutex_enter(&devc->mutex); 550 if (portc->started) { 551 if (!devc->suspended) 552 portc->stop_port(portc); 553 portc->started = B_FALSE; 554 } 555 mutex_exit(&devc->mutex); 556 } 557 558 int 559 emu10k_format(void *arg) 560 { 561 _NOTE(ARGUNUSED(arg)); 562 563 return (AUDIO_FORMAT_S16_LE); 564 } 565 566 int 567 emu10k_channels(void *arg) 568 { 569 emu10k_portc_t *portc = arg; 570 571 return (portc->channels); 572 } 573 574 int 575 emu10k_rate(void *arg) 576 { 577 _NOTE(ARGUNUSED(arg)); 578 579 return (SAMPLE_RATE); 580 } 581 582 void 583 emu10k_sync(void *arg, unsigned nframes) 584 { 585 emu10k_portc_t *portc = arg; 586 _NOTE(ARGUNUSED(nframes)); 587 588 (void) ddi_dma_sync(portc->buf_dmah, 0, 0, portc->syncdir); 589 } 590 591 uint64_t 592 emu10k_count(void *arg) 593 { 594 emu10k_portc_t *portc = arg; 595 emu10k_devc_t *devc = portc->devc; 596 uint64_t count; 597 598 mutex_enter(&devc->mutex); 599 if (!devc->suspended) 600 portc->update_port(portc); 601 count = portc->count; 602 mutex_exit(&devc->mutex); 603 604 return (count); 605 } 606 607 static void 608 emu10k_chinfo(void *arg, int chan, unsigned *offset, unsigned *incr) 609 { 610 emu10k_portc_t *portc = arg; 611 612 *offset = portc->nframes * (chan / 2) * 2 + (chan % 2); 613 *incr = 2; 614 } 615 616 /* private implementation bits */ 617 618 static void 619 emu10k_set_loop_stop(emu10k_devc_t *devc, int voice, int s) 620 { 621 unsigned int tmp; 622 int offs, bit; 623 624 offs = voice / 32; 625 bit = voice % 32; 626 s = !!s; 627 628 tmp = emu10k_read_reg(devc, SOLL + offs, 0); 629 tmp &= ~(1 << bit); 630 631 if (s) 632 tmp |= (1 << bit); 633 emu10k_write_reg(devc, SOLL + offs, 0, tmp); 634 } 635 636 static unsigned int 637 emu10k_rate_to_pitch(unsigned int rate) 638 { 639 static unsigned int logMagTable[128] = { 640 0x00000, 0x02dfc, 0x05b9e, 0x088e6, 641 0x0b5d6, 0x0e26f, 0x10eb3, 0x13aa2, 642 0x1663f, 0x1918a, 0x1bc84, 0x1e72e, 643 0x2118b, 0x23b9a, 0x2655d, 0x28ed5, 644 0x2b803, 0x2e0e8, 0x30985, 0x331db, 645 0x359eb, 0x381b6, 0x3a93d, 0x3d081, 646 0x3f782, 0x41e42, 0x444c1, 0x46b01, 647 0x49101, 0x4b6c4, 0x4dc49, 0x50191, 648 0x5269e, 0x54b6f, 0x57006, 0x59463, 649 0x5b888, 0x5dc74, 0x60029, 0x623a7, 650 0x646ee, 0x66a00, 0x68cdd, 0x6af86, 651 0x6d1fa, 0x6f43c, 0x7164b, 0x73829, 652 0x759d4, 0x77b4f, 0x79c9a, 0x7bdb5, 653 0x7dea1, 0x7ff5e, 0x81fed, 0x8404e, 654 0x86082, 0x88089, 0x8a064, 0x8c014, 655 0x8df98, 0x8fef1, 0x91e20, 0x93d26, 656 0x95c01, 0x97ab4, 0x9993e, 0x9b79f, 657 0x9d5d9, 0x9f3ec, 0xa11d8, 0xa2f9d, 658 0xa4d3c, 0xa6ab5, 0xa8808, 0xaa537, 659 0xac241, 0xadf26, 0xafbe7, 0xb1885, 660 0xb3500, 0xb5157, 0xb6d8c, 0xb899f, 661 0xba58f, 0xbc15e, 0xbdd0c, 0xbf899, 662 0xc1404, 0xc2f50, 0xc4a7b, 0xc6587, 663 0xc8073, 0xc9b3f, 0xcb5ed, 0xcd07c, 664 0xceaec, 0xd053f, 0xd1f73, 0xd398a, 665 0xd5384, 0xd6d60, 0xd8720, 0xda0c3, 666 0xdba4a, 0xdd3b4, 0xded03, 0xe0636, 667 0xe1f4e, 0xe384a, 0xe512c, 0xe69f3, 668 0xe829f, 0xe9b31, 0xeb3a9, 0xecc08, 669 0xee44c, 0xefc78, 0xf148a, 0xf2c83, 670 0xf4463, 0xf5c2a, 0xf73da, 0xf8b71, 671 0xfa2f0, 0xfba57, 0xfd1a7, 0xfe8df 672 }; 673 static char logSlopeTable[128] = { 674 0x5c, 0x5c, 0x5b, 0x5a, 0x5a, 0x59, 0x58, 0x58, 675 0x57, 0x56, 0x56, 0x55, 0x55, 0x54, 0x53, 0x53, 676 0x52, 0x52, 0x51, 0x51, 0x50, 0x50, 0x4f, 0x4f, 677 0x4e, 0x4d, 0x4d, 0x4d, 0x4c, 0x4c, 0x4b, 0x4b, 678 0x4a, 0x4a, 0x49, 0x49, 0x48, 0x48, 0x47, 0x47, 679 0x47, 0x46, 0x46, 0x45, 0x45, 0x45, 0x44, 0x44, 680 0x43, 0x43, 0x43, 0x42, 0x42, 0x42, 0x41, 0x41, 681 0x41, 0x40, 0x40, 0x40, 0x3f, 0x3f, 0x3f, 0x3e, 682 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c, 0x3c, 683 0x3b, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 684 0x39, 0x39, 0x39, 0x38, 0x38, 0x38, 0x38, 0x37, 685 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x36, 0x35, 686 0x35, 0x35, 0x35, 0x34, 0x34, 0x34, 0x34, 0x34, 687 0x33, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x32, 688 0x32, 0x31, 0x31, 0x31, 0x31, 0x31, 0x30, 0x30, 689 0x30, 0x30, 0x30, 0x2f, 0x2f, 0x2f, 0x2f, 0x2f 690 }; 691 int i; 692 693 if (rate == 0) 694 return (0); /* Bail out if no leading "1" */ 695 rate *= 11185; /* Scale 48000 to 0x20002380 */ 696 for (i = 31; i > 0; i--) { 697 if (rate & 0x80000000) { /* Detect leading "1" */ 698 return (((unsigned int) (i - 15) << 20) + 699 logMagTable[0x7f & (rate >> 24)] + 700 (0x7f & (rate >> 17)) * 701 logSlopeTable[0x7f & (rate >> 24)]); 702 } 703 rate <<= 1; 704 } 705 706 return (0); /* Should never reach this point */ 707 } 708 709 static unsigned int 710 emu10k_rate_to_linearpitch(unsigned int rate) 711 { 712 rate = (rate << 8) / 375; 713 return (rate >> 1) + (rate & 1); 714 } 715 716 static void 717 emu10k_prepare_voice(emu10k_devc_t *devc, int voice) 718 { 719 unsigned int sample, initial_pitch, pitch_target; 720 unsigned int cra, cs, ccis, i; 721 722 /* setup CCR regs */ 723 cra = 64; 724 cs = 4; /* Stereo */ 725 ccis = 28; /* Stereo */ 726 sample = 0; /* 16 bit silence */ 727 728 for (i = 0; i < cs; i++) 729 emu10k_write_reg(devc, CD0 + i, voice, sample); 730 731 emu10k_write_reg(devc, CCR_CACHEINVALIDSIZE, voice, 0); 732 emu10k_write_reg(devc, CCR_READADDRESS, voice, cra); 733 emu10k_write_reg(devc, CCR_CACHEINVALIDSIZE, voice, ccis); 734 735 /* Set current pitch */ 736 emu10k_write_reg(devc, IFA, voice, 0xff00); 737 emu10k_write_reg(devc, VTFT, voice, 0xffffffff); 738 emu10k_write_reg(devc, CVCF, voice, 0xffffffff); 739 emu10k_set_loop_stop(devc, voice, 0); 740 741 pitch_target = emu10k_rate_to_linearpitch(SAMPLE_RATE); 742 initial_pitch = emu10k_rate_to_pitch(SAMPLE_RATE) >> 8; 743 emu10k_write_reg(devc, PTRX_PITCHTARGET, voice, pitch_target); 744 emu10k_write_reg(devc, CPF_CURRENTPITCH, voice, pitch_target); 745 emu10k_write_reg(devc, IP, voice, initial_pitch); 746 } 747 748 static void 749 emu10k_stop_voice(emu10k_devc_t *devc, int voice) 750 { 751 emu10k_write_reg(devc, IFA, voice, 0xffff); 752 emu10k_write_reg(devc, VTFT, voice, 0xffff); 753 emu10k_write_reg(devc, PTRX_PITCHTARGET, voice, 0); 754 emu10k_write_reg(devc, CPF_CURRENTPITCH, voice, 0); 755 emu10k_write_reg(devc, IP, voice, 0); 756 emu10k_set_loop_stop(devc, voice, 1); 757 } 758 759 static void 760 emu10k_reset_pair(emu10k_portc_t *portc, int voice, uint8_t *routing, 761 int buf_offset) 762 { 763 emu10k_devc_t *devc = portc->devc; 764 765 /* Left channel */ 766 /* Intial filter cutoff and attenuation */ 767 emu10k_write_reg(devc, IFA, voice, 0xffff); 768 /* Volume envelope decay and sustain */ 769 emu10k_write_reg(devc, VEDS, voice, 0x0); 770 /* Volume target and Filter cutoff target */ 771 emu10k_write_reg(devc, VTFT, voice, 0xffff); 772 /* Pitch target and sends A and B */ 773 emu10k_write_reg(devc, PTAB, voice, 0x0); 774 775 /* The same for right channel */ 776 emu10k_write_reg(devc, IFA, voice + 1, 0xffff); 777 emu10k_write_reg(devc, VEDS, voice + 1, 0x0); 778 emu10k_write_reg(devc, VTFT, voice + 1, 0xffff); 779 emu10k_write_reg(devc, PTAB, voice + 1, 0x0); 780 781 /* now setup the voices and go! */ 782 emu10k_setup_voice(portc, voice, LEFT_CH, buf_offset); 783 emu10k_setup_voice(portc, voice + 1, RIGHT_CH, buf_offset); 784 785 emu10k_write_routing(devc, voice, routing); 786 emu10k_write_routing(devc, voice + 1, routing); 787 } 788 789 void 790 emu10k_start_play(emu10k_portc_t *portc) 791 { 792 emu10k_devc_t *devc = portc->devc; 793 794 ASSERT(mutex_owned(&devc->mutex)); 795 emu10k_prepare_voice(devc, 0); 796 emu10k_prepare_voice(devc, 1); 797 798 emu10k_prepare_voice(devc, 2); 799 emu10k_prepare_voice(devc, 3); 800 801 emu10k_prepare_voice(devc, 4); 802 emu10k_prepare_voice(devc, 5); 803 804 emu10k_prepare_voice(devc, 6); 805 emu10k_prepare_voice(devc, 7); 806 807 emu10k_prepare_voice(devc, 8); 808 emu10k_prepare_voice(devc, 9); 809 810 /* arrange to receive full loop interrupts on channel 8 */ 811 emu10k_write_reg(devc, CLIEL, 0, (1U << 8)); 812 813 /* initialize our position counter... */ 814 portc->pos = 815 (emu10k_read_reg(devc, QKBCA, 0) & 0xffffff) - 816 (portc->memptr >> 2); 817 818 /* Trigger playback on all voices */ 819 emu10k_write_reg(devc, VEDS, 0, 0x7f7f); 820 emu10k_write_reg(devc, VEDS, 1, 0x7f7f); 821 emu10k_write_reg(devc, VEDS, 2, 0x7f7f); 822 emu10k_write_reg(devc, VEDS, 3, 0x7f7f); 823 emu10k_write_reg(devc, VEDS, 4, 0x7f7f); 824 emu10k_write_reg(devc, VEDS, 5, 0x7f7f); 825 emu10k_write_reg(devc, VEDS, 6, 0x7f7f); 826 emu10k_write_reg(devc, VEDS, 7, 0x7f7f); 827 emu10k_write_reg(devc, VEDS, 8, 0x7f7f); 828 emu10k_write_reg(devc, VEDS, 9, 0x7f7f); 829 830 portc->active = B_TRUE; 831 } 832 833 void 834 emu10k_stop_play(emu10k_portc_t *portc) 835 { 836 emu10k_devc_t *devc = portc->devc; 837 838 emu10k_stop_voice(devc, 0); 839 emu10k_stop_voice(devc, 1); 840 emu10k_stop_voice(devc, 2); 841 emu10k_stop_voice(devc, 3); 842 emu10k_stop_voice(devc, 4); 843 emu10k_stop_voice(devc, 5); 844 emu10k_stop_voice(devc, 6); 845 emu10k_stop_voice(devc, 7); 846 emu10k_stop_voice(devc, 8); 847 emu10k_stop_voice(devc, 9); 848 849 portc->active = B_FALSE; 850 } 851 852 void 853 emu10k_reset_play(emu10k_portc_t *portc) 854 { 855 emu10k_devc_t *devc = portc->devc; 856 uint32_t offs; 857 858 offs = (portc->buf_size / portc->channels) * 2; 859 860 if (devc->feature_mask & SB_71) { 861 emu10k_reset_pair(portc, 0, front_routing, 0); 862 emu10k_reset_pair(portc, 2, clfe_routing, offs); 863 emu10k_reset_pair(portc, 4, surr_routing, 2 * offs); 864 emu10k_reset_pair(portc, 6, side_routing, 3 * offs); 865 } else if (devc->feature_mask & SB_51) { 866 emu10k_reset_pair(portc, 0, front_routing, 0); 867 emu10k_reset_pair(portc, 2, clfe_routing, offs); 868 emu10k_reset_pair(portc, 4, surr_routing, 2 * offs); 869 } else { 870 emu10k_reset_pair(portc, 0, front_routing, 0); 871 emu10k_reset_pair(portc, 2, surr_routing, offs); 872 } 873 emu10k_setup_silence(portc, 8); 874 emu10k_setup_silence(portc, 9); 875 876 /* 877 * This way we can use voices 8 and 9 for timing, we have 878 * programmed them to be just the size of a single fragment, 879 * that way when they loop we get a clean interrupt. 880 */ 881 emu10k_write_routing(devc, 8, no_routing); 882 emu10k_write_routing(devc, 9, no_routing); 883 portc->pos = 0; 884 } 885 886 uint32_t emu10k_vars[5]; 887 888 void 889 emu10k_update_play(emu10k_portc_t *portc) 890 { 891 emu10k_devc_t *devc = portc->devc; 892 uint32_t cnt, pos; 893 894 /* 895 * Note: position is given as stereo samples, i.e. frames. 896 */ 897 pos = emu10k_read_reg(devc, QKBCA, 0) & 0xffffff; 898 pos -= (portc->memptr >> 2); 899 900 if (pos <= portc->pos) { 901 cnt = portc->nframes - portc->pos; 902 cnt += pos; 903 } else { 904 cnt = (pos - portc->pos); 905 } 906 if (portc->dopos) { 907 emu10k_vars[0] = portc->pos; 908 emu10k_vars[1] = pos; 909 emu10k_vars[2] = (uint32_t)portc->count; 910 emu10k_vars[3] = cnt; 911 portc->dopos = 0; 912 } 913 if (cnt > portc->nframes) { 914 printf("Got bogus count %u\n", cnt); 915 cnt = portc->fragfr; 916 } 917 ASSERT(cnt <= portc->nframes); 918 portc->count += cnt; 919 portc->pos = pos; 920 } 921 922 void 923 emu10k_start_rec(emu10k_portc_t *portc) 924 { 925 emu10k_devc_t *devc = portc->devc; 926 uint32_t tmp; 927 928 /* Intr enable */ 929 OUTL(devc, INL(devc, devc->regs + IE) | IE_MB | IE_AB, 930 devc->regs + IE); 931 932 tmp = 0; /* setup 48Kz */ 933 if (devc->feature_mask & (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL)) 934 tmp |= 0x30; /* Left/right channel enable */ 935 else 936 tmp |= 0x18; /* Left/right channel enable */ 937 emu10k_write_reg(devc, ADCSR, 0, tmp); /* GO */ 938 939 portc->active = B_TRUE; 940 } 941 942 void 943 emu10k_stop_rec(emu10k_portc_t *portc) 944 { 945 emu10k_devc_t *devc = portc->devc; 946 947 ASSERT(mutex_owned(&devc->mutex)); 948 emu10k_write_reg(devc, ADCSR, 0, 0); 949 950 portc->active = B_FALSE; 951 } 952 void 953 emu10k_reset_rec(emu10k_portc_t *portc) 954 { 955 emu10k_devc_t *devc = portc->devc; 956 uint32_t sz; 957 958 switch (portc->buf_size) { 959 case 4096: 960 sz = 15; 961 break; 962 case 8192: 963 sz = 19; 964 break; 965 case 16384: 966 sz = 23; 967 break; 968 case 32768: 969 sz = 27; 970 break; 971 case 65536: 972 sz = 31; 973 break; 974 } 975 emu10k_write_reg(devc, ADCBA, 0, portc->buf_paddr); 976 emu10k_write_reg(devc, ADCBS, 0, sz); 977 emu10k_write_reg(devc, ADCSR, 0, 0); /* reset for phase */ 978 portc->pos = 0; 979 OUTL(devc, INL(devc, devc->regs + IE) & ~(IE_MB | IE_AB), 980 devc->regs + IE); 981 } 982 983 void 984 emu10k_update_rec(emu10k_portc_t *portc) 985 { 986 emu10k_devc_t *devc = portc->devc; 987 uint32_t cnt, pos; 988 989 /* given in bytes, we divide all counts by 4 to get samples */ 990 pos = emu10k_read_reg(devc, 991 (devc->feature_mask & SB_LIVE) ? MIDX : ADCIDX, 0); 992 if (pos <= portc->pos) { 993 cnt = ((portc->buf_size) - portc->pos) >> 2; 994 cnt += (pos >> 2); 995 } else { 996 cnt = ((pos - portc->pos) >> 2); 997 } 998 portc->count += cnt; 999 portc->pos = pos; 1000 } 1001 1002 int 1003 emu10k_alloc_port(emu10k_devc_t *devc, int num) 1004 { 1005 emu10k_portc_t *portc; 1006 size_t len; 1007 ddi_dma_cookie_t cookie; 1008 uint_t count; 1009 int dir; 1010 unsigned caps; 1011 audio_dev_t *adev; 1012 int i, n; 1013 1014 adev = devc->adev; 1015 portc = kmem_zalloc(sizeof (*portc), KM_SLEEP); 1016 devc->portc[num] = portc; 1017 portc->devc = devc; 1018 portc->started = B_FALSE; 1019 1020 portc->memptr = devc->audio_memptr; 1021 devc->audio_memptr += (DMABUF_SIZE + 4095) & ~4095; 1022 1023 switch (num) { 1024 case EMU10K_REC: 1025 portc->syncdir = DDI_DMA_SYNC_FORKERNEL; 1026 caps = ENGINE_INPUT_CAP; 1027 dir = DDI_DMA_READ; 1028 portc->channels = 2; 1029 portc->start_port = emu10k_start_rec; 1030 portc->stop_port = emu10k_stop_rec; 1031 portc->reset_port = emu10k_reset_rec; 1032 portc->update_port = emu10k_update_rec; 1033 /* This is the minimum record buffer size. */ 1034 portc->buf_size = 4096; 1035 portc->nfrags = 2; 1036 portc->nframes = 4096 / 4; 1037 portc->fragfr = portc->nframes / portc->nfrags; 1038 break; 1039 case EMU10K_PLAY: 1040 portc->syncdir = DDI_DMA_SYNC_FORDEV; 1041 caps = ENGINE_OUTPUT_CAP; 1042 dir = DDI_DMA_WRITE; 1043 portc->channels = 8; 1044 portc->start_port = emu10k_start_play; 1045 portc->stop_port = emu10k_stop_play; 1046 portc->reset_port = emu10k_reset_play; 1047 portc->update_port = emu10k_update_play; 1048 /* XXX: this could probably be tunable */ 1049 portc->nfrags = 2; 1050 portc->fragfr = 288; 1051 portc->nframes = portc->nfrags * portc->fragfr; 1052 portc->buf_size = portc->nframes * portc->channels * 2; 1053 break; 1054 default: 1055 return (DDI_FAILURE); 1056 } 1057 1058 /* 1059 * Fragments that are not powers of two don't seem to work 1060 * at all with EMU10K. For simplicity's sake, we eliminate 1061 * the question and fix the interrupt rate. This is also the 1062 * logical minimum for record, which requires at least 4K for 1063 * the record size. 1064 */ 1065 1066 if (portc->buf_size > DMABUF_SIZE) { 1067 cmn_err(CE_NOTE, "Buffer size %d is too large (max %d)", 1068 (int)portc->buf_size, DMABUF_SIZE); 1069 portc->buf_size = DMABUF_SIZE; 1070 } 1071 1072 /* Alloc buffers */ 1073 if (ddi_dma_alloc_handle(devc->dip, &dma_attr_buf, DDI_DMA_SLEEP, NULL, 1074 &portc->buf_dmah) != DDI_SUCCESS) { 1075 audio_dev_warn(adev, "failed to allocate BUF handle"); 1076 return (DDI_FAILURE); 1077 } 1078 1079 if (ddi_dma_mem_alloc(portc->buf_dmah, portc->buf_size, 1080 &dev_attr, DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, 1081 &portc->buf_kaddr, &len, &portc->buf_acch) != DDI_SUCCESS) { 1082 audio_dev_warn(adev, "failed to allocate BUF memory"); 1083 return (DDI_FAILURE); 1084 } 1085 1086 if (ddi_dma_addr_bind_handle(portc->buf_dmah, NULL, portc->buf_kaddr, 1087 len, DDI_DMA_CONSISTENT | dir, DDI_DMA_SLEEP, 1088 NULL, &cookie, &count) != DDI_SUCCESS) { 1089 audio_dev_warn(adev, "failed binding BUF DMA handle"); 1090 return (DDI_FAILURE); 1091 } 1092 portc->buf_paddr = cookie.dmac_address; 1093 1094 if ((devc->feature_mask & SB_LIVE) && 1095 (portc->buf_paddr & 0x80000000)) { 1096 audio_dev_warn(adev, "Got DMA buffer beyond 2G limit."); 1097 return (DDI_FAILURE); 1098 } 1099 1100 if (num == EMU10K_PLAY) { /* Output device */ 1101 n = portc->memptr / 4096; 1102 /* 1103 * Fill the page table 1104 */ 1105 for (i = 0; i < portc->buf_size / 4096; i++) { 1106 FILL_PAGE_MAP_ENTRY(n + i, 1107 portc->buf_paddr + i * 4096); 1108 } 1109 1110 (void) ddi_dma_sync(devc->pt_dmah, 0, 0, DDI_DMA_SYNC_FORDEV); 1111 } 1112 1113 portc->engine = audio_engine_alloc(&emu10k_engine_ops, caps); 1114 if (portc->engine == NULL) { 1115 audio_dev_warn(adev, "audio_engine_alloc failed"); 1116 return (DDI_FAILURE); 1117 } 1118 1119 audio_engine_set_private(portc->engine, portc); 1120 audio_dev_add_engine(adev, portc->engine); 1121 1122 return (DDI_SUCCESS); 1123 } 1124 1125 int 1126 emu10k_setup_intrs(emu10k_devc_t *devc) 1127 { 1128 uint_t ipri; 1129 int actual; 1130 int rv; 1131 ddi_intr_handle_t ih[1]; 1132 1133 rv = ddi_intr_alloc(devc->dip, ih, DDI_INTR_TYPE_FIXED, 1134 0, 1, &actual, DDI_INTR_ALLOC_STRICT); 1135 if ((rv != DDI_SUCCESS) || (actual != 1)) { 1136 audio_dev_warn(devc->adev, 1137 "Can't alloc interrupt handle (rv %d actual %d)", 1138 rv, actual); 1139 return (DDI_FAILURE); 1140 } 1141 1142 if (ddi_intr_get_pri(ih[0], &ipri) != DDI_SUCCESS) { 1143 audio_dev_warn(devc->adev, "Can't get interrupt priority"); 1144 (void) ddi_intr_free(ih[0]); 1145 return (DDI_FAILURE); 1146 } 1147 1148 if (ddi_intr_add_handler(ih[0], emu10k_intr, devc, NULL) != 1149 DDI_SUCCESS) { 1150 audio_dev_warn(devc->adev, "Can't add interrupt handler"); 1151 (void) ddi_intr_free(ih[0]); 1152 return (DDI_FAILURE); 1153 } 1154 1155 devc->ih = ih[0]; 1156 mutex_init(&devc->mutex, NULL, MUTEX_DRIVER, DDI_INTR_PRI(ipri)); 1157 return (DDI_SUCCESS); 1158 } 1159 1160 void 1161 emu10k_destroy(emu10k_devc_t *devc) 1162 { 1163 if (devc->ih != NULL) { 1164 (void) ddi_intr_disable(devc->ih); 1165 (void) ddi_intr_remove_handler(devc->ih); 1166 (void) ddi_intr_free(devc->ih); 1167 mutex_destroy(&devc->mutex); 1168 } 1169 1170 if (devc->ksp) { 1171 kstat_delete(devc->ksp); 1172 } 1173 1174 if (devc->silence_paddr) { 1175 (void) ddi_dma_unbind_handle(devc->silence_dmah); 1176 } 1177 if (devc->silence_acch) { 1178 ddi_dma_mem_free(&devc->silence_acch); 1179 } 1180 if (devc->silence_dmah) { 1181 ddi_dma_free_handle(&devc->silence_dmah); 1182 } 1183 1184 if (devc->pt_paddr) { 1185 (void) ddi_dma_unbind_handle(devc->pt_dmah); 1186 } 1187 if (devc->pt_acch) { 1188 ddi_dma_mem_free(&devc->pt_acch); 1189 } 1190 if (devc->pt_dmah) { 1191 ddi_dma_free_handle(&devc->pt_dmah); 1192 } 1193 1194 1195 for (int i = 0; i < CTL_MAX; i++) { 1196 emu10k_ctrl_t *ec = &devc->ctrls[i]; 1197 if (ec->ctrl != NULL) { 1198 audio_dev_del_control(ec->ctrl); 1199 ec->ctrl = NULL; 1200 } 1201 } 1202 1203 for (int i = 0; i < EMU10K_NUM_PORTC; i++) { 1204 emu10k_portc_t *portc = devc->portc[i]; 1205 if (!portc) 1206 continue; 1207 if (portc->engine) { 1208 audio_dev_remove_engine(devc->adev, portc->engine); 1209 audio_engine_free(portc->engine); 1210 } 1211 if (portc->buf_paddr) { 1212 (void) ddi_dma_unbind_handle(portc->buf_dmah); 1213 } 1214 if (portc->buf_acch) { 1215 ddi_dma_mem_free(&portc->buf_acch); 1216 } 1217 if (portc->buf_dmah) { 1218 ddi_dma_free_handle(&portc->buf_dmah); 1219 } 1220 kmem_free(portc, sizeof (*portc)); 1221 } 1222 1223 if (devc->ac97 != NULL) { 1224 ac97_free(devc->ac97); 1225 } 1226 if (devc->adev != NULL) { 1227 audio_dev_free(devc->adev); 1228 } 1229 if (devc->regsh != NULL) { 1230 ddi_regs_map_free(&devc->regsh); 1231 } 1232 if (devc->pcih != NULL) { 1233 pci_config_teardown(&devc->pcih); 1234 } 1235 1236 kmem_free(devc, sizeof (*devc)); 1237 } 1238 1239 static void 1240 emu10k_init_voice(emu10k_devc_t *devc, int voice) 1241 { 1242 emu10k_set_loop_stop(devc, voice, 1); 1243 1244 emu10k_write_reg(devc, VEDS, voice, 0x0); 1245 emu10k_write_reg(devc, IP, voice, 0x0); 1246 emu10k_write_reg(devc, VTFT, voice, 0xffff); 1247 emu10k_write_reg(devc, CVCF, voice, 0xffff); 1248 emu10k_write_reg(devc, PTAB, voice, 0x0); 1249 emu10k_write_reg(devc, CPF, voice, 0x0); 1250 emu10k_write_reg(devc, CCR, voice, 0x0); 1251 emu10k_write_reg(devc, SCSA, voice, 0x0); 1252 emu10k_write_reg(devc, SDL, voice, 0x10); 1253 emu10k_write_reg(devc, QKBCA, voice, 0x0); 1254 emu10k_write_reg(devc, Z1, voice, 0x0); 1255 emu10k_write_reg(devc, Z2, voice, 0x0); 1256 1257 if (devc->feature_mask & (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL)) 1258 emu10k_write_reg(devc, SRDA, voice, 0x03020100); 1259 else 1260 emu10k_write_reg(devc, FXRT, voice, 0x32100000); 1261 1262 emu10k_write_reg(devc, MEHA, voice, 0x0); 1263 emu10k_write_reg(devc, MEDS, voice, 0x0); 1264 emu10k_write_reg(devc, IFA, voice, 0xffff); 1265 emu10k_write_reg(devc, PEFE, voice, 0x0); 1266 emu10k_write_reg(devc, VFM, voice, 0x0); 1267 emu10k_write_reg(devc, TMFQ, voice, 24); 1268 emu10k_write_reg(devc, VVFQ, voice, 24); 1269 emu10k_write_reg(devc, TMPE, voice, 0x0); 1270 emu10k_write_reg(devc, VLV, voice, 0x0); 1271 emu10k_write_reg(devc, MLV, voice, 0x0); 1272 emu10k_write_reg(devc, VEHA, voice, 0x0); 1273 emu10k_write_reg(devc, VEV, voice, 0x0); 1274 emu10k_write_reg(devc, MEV, voice, 0x0); 1275 1276 if (devc->feature_mask & (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL)) { 1277 emu10k_write_reg(devc, CSBA, voice, 0x0); 1278 emu10k_write_reg(devc, CSDC, voice, 0x0); 1279 emu10k_write_reg(devc, CSFE, voice, 0x0); 1280 emu10k_write_reg(devc, CSHG, voice, 0x0); 1281 emu10k_write_reg(devc, SRHE, voice, 0x3f3f3f3f); 1282 } 1283 } 1284 1285 static void 1286 emu10k_refresh_mixer(emu10k_devc_t *devc) 1287 { 1288 uint32_t val; 1289 uint32_t set; 1290 1291 for (int gpr = 0; gpr < MAX_GPR; gpr++) { 1292 if (devc->gpr_shadow[gpr].valid) { 1293 emu10k_write_reg(devc, gpr + GPR0, 0, 1294 devc->gpr_shadow[gpr].value); 1295 } 1296 } 1297 1298 set = devc->ctrls[CTL_JACK3].val; 1299 if (devc->feature_mask & SB_INVSP) { 1300 set = !set; 1301 } 1302 1303 if (devc->feature_mask & (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL)) { 1304 val = INL(devc, devc->regs + 0x18); 1305 val &= ~A_IOCFG_GPOUT0; 1306 val |= set ? 0x44 : 0x40; 1307 OUTL(devc, val, devc->regs + 0x18); 1308 1309 } else if (devc->feature_mask & SB_LIVE) { 1310 val = INL(devc, devc->regs + HCFG); 1311 val &= ~HCFG_GPOUT0; 1312 val |= set ? HCFG_GPOUT0 : 0; 1313 OUTL(devc, val, devc->regs + HCFG); 1314 } 1315 } 1316 1317 int 1318 emu10k_hwinit(emu10k_devc_t *devc) 1319 { 1320 1321 unsigned int tmp, i; 1322 unsigned int reg; 1323 1324 ASSERT(mutex_owned(&devc->mutex)); 1325 1326 emu10k_write_reg(devc, AC97SLOT, 0, AC97SLOT_CENTER | AC97SLOT_LFE); 1327 1328 OUTL(devc, 0x00000000, devc->regs + 0x0c); /* Intr disable */ 1329 OUTL(devc, HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK | 1330 HCFG_MUTEBUTTONENABLE, 1331 devc->regs + HCFG); 1332 1333 emu10k_write_reg(devc, MBS, 0, 0x0); 1334 emu10k_write_reg(devc, MBA, 0, 0x0); 1335 emu10k_write_reg(devc, FXBS, 0, 0x0); 1336 emu10k_write_reg(devc, FXBA, 0, 0x0); 1337 emu10k_write_reg(devc, ADCBS, 0, 0x0); 1338 emu10k_write_reg(devc, ADCBA, 0, 0x0); 1339 1340 OUTL(devc, 0, devc->regs + IE); 1341 emu10k_write_reg(devc, CLIEL, 0, 0x0); 1342 emu10k_write_reg(devc, CLIEH, 0, 0x0); 1343 if (!(devc->feature_mask & SB_LIVE)) { 1344 emu10k_write_reg(devc, HLIEL, 0, 0x0); 1345 emu10k_write_reg(devc, HLIEH, 0, 0x0); 1346 } 1347 emu10k_write_reg(devc, CLIPL, 0, 0xffffffff); 1348 emu10k_write_reg(devc, CLIPH, 0, 0xffffffff); 1349 emu10k_write_reg(devc, SOLL, 0, 0xffffffff); 1350 emu10k_write_reg(devc, SOLH, 0, 0xffffffff); 1351 1352 1353 if (devc->feature_mask & (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL)) { 1354 emu10k_write_reg(devc, SOC, 0, 0xf00); /* ?? */ 1355 emu10k_write_reg(devc, AC97SLOT, 0, 0x3); /* ?? */ 1356 } 1357 1358 for (i = 0; i < 64; i++) 1359 emu10k_init_voice(devc, i); 1360 1361 emu10k_write_reg(devc, SCS0, 0, 0x2109204); 1362 emu10k_write_reg(devc, SCS1, 0, 0x2109204); 1363 emu10k_write_reg(devc, SCS2, 0, 0x2109204); 1364 1365 emu10k_write_reg(devc, PTBA, 0, devc->pt_paddr); 1366 tmp = emu10k_read_reg(devc, PTBA, 0); 1367 1368 emu10k_write_reg(devc, TCBA, 0, 0x0); 1369 emu10k_write_reg(devc, TCBS, 0, 0x4); 1370 1371 reg = 0; 1372 if (devc->feature_mask & SB_71) { 1373 reg = AC97SLOT_CENTER | AC97SLOT_LFE | AC97SLOT_REAR_LEFT | 1374 AC97SLOT_REAR_RIGHT; 1375 } else if (devc->feature_mask & SB_51) { 1376 reg = AC97SLOT_CENTER | AC97SLOT_LFE; 1377 } 1378 if (devc->feature_mask & (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL)) 1379 reg |= 0x40; 1380 emu10k_write_reg(devc, AC97SLOT, 0, reg); 1381 1382 if (devc->feature_mask & SB_AUDIGY2) { 1383 /* Enable analog outputs on Audigy2 */ 1384 int tmp; 1385 1386 /* Setup SRCMulti_I2S SamplingRate */ 1387 tmp = emu10k_read_reg(devc, EHC, 0); 1388 tmp &= 0xfffff1ff; 1389 tmp |= (0x2 << 9); 1390 emu10k_write_reg(devc, EHC, 0, tmp); 1391 /* emu10k_write_reg (devc, SOC, 0, 0x00000000); */ 1392 1393 /* Setup SRCSel (Enable Spdif,I2S SRCMulti) */ 1394 OUTL(devc, 0x600000, devc->regs + 0x20); 1395 OUTL(devc, 0x14, devc->regs + 0x24); 1396 1397 /* Setup SRCMulti Input Audio Enable */ 1398 OUTL(devc, 0x6E0000, devc->regs + 0x20); 1399 1400 OUTL(devc, 0xFF00FF00, devc->regs + 0x24); 1401 1402 /* Setup I2S ASRC Enable (HC register) */ 1403 tmp = INL(devc, devc->regs + HCFG); 1404 tmp |= 0x00000070; 1405 OUTL(devc, tmp, devc->regs + HCFG); 1406 1407 /* 1408 * Unmute Analog now. Set GPO6 to 1 for Apollo. 1409 * This has to be done after init ALice3 I2SOut beyond 48KHz. 1410 * So, sequence is important 1411 */ 1412 tmp = INL(devc, devc->regs + 0x18); 1413 tmp |= 0x0040; 1414 1415 OUTL(devc, tmp, devc->regs + 0x18); 1416 } 1417 1418 if (devc->feature_mask & SB_AUDIGY2VAL) { 1419 /* Enable analog outputs on Audigy2 */ 1420 int tmp; 1421 1422 /* Setup SRCMulti_I2S SamplingRate */ 1423 tmp = emu10k_read_reg(devc, EHC, 0); 1424 tmp &= 0xfffff1ff; 1425 tmp |= (0x2 << 9); 1426 emu10k_write_reg(devc, EHC, 0, tmp); 1427 1428 /* Setup SRCSel (Enable Spdif,I2S SRCMulti) */ 1429 OUTL(devc, 0x600000, devc->regs + 0x20); 1430 OUTL(devc, 0x14, devc->regs + 0x24); 1431 1432 /* Setup SRCMulti Input Audio Enable */ 1433 OUTL(devc, 0x7B0000, devc->regs + 0x20); 1434 OUTL(devc, 0xFF000000, devc->regs + 0x24); 1435 1436 /* SPDIF output enable */ 1437 OUTL(devc, 0x7A0000, devc->regs + 0x20); 1438 OUTL(devc, 0xFF000000, devc->regs + 0x24); 1439 1440 tmp = INL(devc, devc->regs + 0x18) & ~0x8; 1441 OUTL(devc, tmp, devc->regs + 0x18); 1442 } 1443 1444 emu10k_write_reg(devc, SOLL, 0, 0xffffffff); 1445 emu10k_write_reg(devc, SOLH, 0, 0xffffffff); 1446 1447 if (devc->feature_mask & (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL)) { 1448 unsigned int mode = 0; 1449 1450 if (devc->feature_mask & (SB_AUDIGY2|SB_AUDIGY2VAL)) 1451 mode |= HCFG_AC3ENABLE_GPSPDIF | HCFG_AC3ENABLE_CDSPDIF; 1452 OUTL(devc, 1453 HCFG_AUDIOENABLE | HCFG_AUTOMUTE | 1454 HCFG_JOYENABLE | A_HCFG_VMUTE | 1455 A_HCFG_AUTOMUTE | mode, devc->regs + HCFG); 1456 1457 OUTL(devc, INL(devc, devc->regs + 0x18) | 1458 0x0004, devc->regs + 0x18); /* GPIO (S/PDIF enable) */ 1459 1460 1461 /* enable IR port */ 1462 tmp = INL(devc, devc->regs + 0x18); 1463 OUTL(devc, tmp | A_IOCFG_GPOUT2, devc->regs + 0x18); 1464 drv_usecwait(500); 1465 OUTL(devc, tmp | A_IOCFG_GPOUT1 | A_IOCFG_GPOUT2, 1466 devc->regs + 0x18); 1467 drv_usecwait(100); 1468 OUTL(devc, tmp, devc->regs + 0x18); 1469 } else { 1470 OUTL(devc, 1471 HCFG_AUDIOENABLE | HCFG_LOCKTANKCACHE_MASK | 1472 HCFG_AUTOMUTE | HCFG_JOYENABLE, devc->regs + HCFG); 1473 } 1474 1475 1476 /* enable IR port */ 1477 tmp = INL(devc, devc->regs + HCFG); 1478 OUTL(devc, tmp | HCFG_GPOUT2, devc->regs + HCFG); 1479 drv_usecwait(500); 1480 OUTL(devc, tmp | HCFG_GPOUT1 | HCFG_GPOUT2, devc->regs + HCFG); 1481 drv_usecwait(100); 1482 OUTL(devc, tmp, devc->regs + HCFG); 1483 1484 1485 /* 1486 * Start by configuring for analog mode. 1487 */ 1488 if (devc->feature_mask & (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL)) { 1489 reg = INL(devc, devc->regs + 0x18) & ~A_IOCFG_GPOUT0; 1490 reg |= ((devc->feature_mask & SB_INVSP) ? 0x4 : 0); 1491 OUTL(devc, reg, devc->regs + 0x18); 1492 } 1493 if (devc->feature_mask & SB_LIVE) { /* SBLIVE */ 1494 reg = INL(devc, devc->regs + HCFG) & ~HCFG_GPOUT0; 1495 reg |= ((devc->feature_mask & SB_INVSP) ? HCFG_GPOUT0 : 0); 1496 OUTL(devc, reg, devc->regs + HCFG); 1497 } 1498 1499 if (devc->feature_mask & SB_AUDIGY2VAL) { 1500 OUTL(devc, INL(devc, devc->regs + 0x18) | 0x0060, 1501 devc->regs + 0x18); 1502 } else if (devc->feature_mask & SB_AUDIGY2) { 1503 OUTL(devc, INL(devc, devc->regs + 0x18) | 0x0040, 1504 devc->regs + 0x18); 1505 } else if (devc->feature_mask & SB_AUDIGY) { 1506 OUTL(devc, INL(devc, devc->regs + 0x18) | 0x0080, 1507 devc->regs + 0x18); 1508 } 1509 1510 emu10k_init_effects(devc); 1511 1512 return (DDI_SUCCESS); 1513 } 1514 1515 static const int db2lin_101[101] = { 1516 0x00000000, 1517 0x0024B53A, 0x002750CA, 0x002A1BC6, 0x002D198D, 0x00304DBA, 0x0033BC2A, 1518 0x00376901, 0x003B58AF, 0x003F8FF1, 0x004413DF, 0x0048E9EA, 0x004E17E9, 1519 0x0053A419, 0x0059952C, 0x005FF24E, 0x0066C32A, 0x006E0FFB, 0x0075E18D, 1520 0x007E414F, 0x0087395B, 0x0090D482, 0x009B1E5B, 0x00A6234F, 0x00B1F0A7, 1521 0x00BE94A1, 0x00CC1E7C, 0x00DA9E8D, 0x00EA2650, 0x00FAC881, 0x010C9931, 1522 0x011FADDC, 0x01341D87, 0x014A00D8, 0x01617235, 0x017A8DE6, 0x01957233, 1523 0x01B23F8D, 0x01D118B1, 0x01F222D4, 0x021585D1, 0x023B6C57, 0x0264041D, 1524 0x028F7E19, 0x02BE0EBD, 0x02EFEE33, 0x032558A2, 0x035E8E7A, 0x039BD4BC, 1525 0x03DD7551, 0x0423BF61, 0x046F07B5, 0x04BFA91B, 0x051604D5, 0x0572830D, 1526 0x05D59354, 0x063FAD27, 0x06B15080, 0x072B0673, 0x07AD61CD, 0x0838FFCA, 1527 0x08CE88D3, 0x096EB147, 0x0A1A3A53, 0x0AD1F2E0, 0x0B96B889, 0x0C6978A5, 1528 0x0D4B316A, 0x0E3CF31B, 0x0F3FE155, 0x10553469, 0x117E3AD9, 0x12BC5AEA, 1529 0x14111457, 0x157E0219, 0x1704DC5E, 0x18A77A97, 0x1A67D5B6, 0x1C480A87, 1530 0x1E4A5C45, 0x2071374D, 0x22BF3412, 0x25371A37, 0x27DBE3EF, 0x2AB0C18F, 1531 0x2DB91D6F, 0x30F89FFD, 0x34733433, 0x382D0C46, 0x3C2AA6BD, 0x4070D3D9, 1532 0x4504BB66, 0x49EBE2F1, 0x4F2C346F, 0x54CC0565, 0x5AD21E86, 0x6145C3E7, 1533 0x682EBDBD, 0x6F9561C4, 0x77829D4D, 1534 0x7fffffff 1535 }; 1536 1537 static int 1538 emu10k_convert_fixpoint(int val) 1539 { 1540 if (val < 0) 1541 val = 0; 1542 if (val > 100) 1543 val = 100; 1544 return (db2lin_101[val]); 1545 } 1546 1547 static void 1548 emu10k_write_gpr(emu10k_devc_t *devc, int gpr, uint32_t value) 1549 { 1550 ASSERT(gpr < MAX_GPR); 1551 devc->gpr_shadow[gpr].valid = B_TRUE; 1552 devc->gpr_shadow[gpr].value = value; 1553 if (!devc->suspended) { 1554 emu10k_write_reg(devc, gpr + GPR0, 0, value); 1555 } 1556 } 1557 1558 static int 1559 emu10k_set_stereo(void *arg, uint64_t val) 1560 { 1561 emu10k_ctrl_t *ec = arg; 1562 emu10k_devc_t *devc = ec->devc; 1563 uint32_t left, right; 1564 1565 left = (val >> 8) & 0xff; 1566 right = val & 0xff; 1567 if ((left > 100) || (right > 100) || (val & ~(0xffff))) 1568 return (EINVAL); 1569 1570 left = emu10k_convert_fixpoint(left); 1571 right = emu10k_convert_fixpoint(right); 1572 1573 mutex_enter(&devc->mutex); 1574 ec->val = val; 1575 1576 emu10k_write_gpr(devc, ec->gpr_num, left); 1577 emu10k_write_gpr(devc, ec->gpr_num + 1, right); 1578 1579 mutex_exit(&devc->mutex); 1580 return (0); 1581 } 1582 1583 static int 1584 emu10k_set_mono(void *arg, uint64_t val) 1585 { 1586 emu10k_ctrl_t *ec = arg; 1587 emu10k_devc_t *devc = ec->devc; 1588 uint32_t v; 1589 1590 if (val > 100) 1591 return (EINVAL); 1592 1593 v = emu10k_convert_fixpoint(val & 0xff); 1594 1595 mutex_enter(&devc->mutex); 1596 ec->val = val; 1597 emu10k_write_gpr(devc, ec->gpr_num, v); 1598 mutex_exit(&devc->mutex); 1599 return (0); 1600 } 1601 1602 static int 1603 emu10k_get_control(void *arg, uint64_t *val) 1604 { 1605 emu10k_ctrl_t *ec = arg; 1606 emu10k_devc_t *devc = ec->devc; 1607 1608 mutex_enter(&devc->mutex); 1609 *val = ec->val; 1610 mutex_exit(&devc->mutex); 1611 return (0); 1612 } 1613 1614 #define PLAYCTL (AUDIO_CTRL_FLAG_RW | AUDIO_CTRL_FLAG_PLAY) 1615 #define RECCTL (AUDIO_CTRL_FLAG_RW | AUDIO_CTRL_FLAG_REC) 1616 #define MONCTL (AUDIO_CTRL_FLAG_RW | AUDIO_CTRL_FLAG_MONITOR) 1617 #define MAINVOL (PLAYCTL | AUDIO_CTRL_FLAG_MAINVOL) 1618 #define PCMVOL (PLAYCTL | AUDIO_CTRL_FLAG_PCMVOL) 1619 #define RECVOL (RECCTL | AUDIO_CTRL_FLAG_RECVOL) 1620 #define MONVOL (MONCTL | AUDIO_CTRL_FLAG_MONVOL) 1621 1622 static int 1623 emu10k_get_ac97src(void *arg, uint64_t *valp) 1624 { 1625 ac97_ctrl_t *ctrl = arg; 1626 1627 return (ac97_control_get(ctrl, valp)); 1628 } 1629 1630 static int 1631 emu10k_set_ac97src(void *arg, uint64_t value) 1632 { 1633 ac97_ctrl_t *ctrl = arg; 1634 1635 return (ac97_control_set(ctrl, value)); 1636 } 1637 1638 static int 1639 emu10k_set_jack3(void *arg, uint64_t value) 1640 { 1641 emu10k_ctrl_t *ec = arg; 1642 emu10k_devc_t *devc = ec->devc; 1643 uint32_t set_val; 1644 uint32_t val; 1645 1646 set_val = ddi_ffs(value & 0xffffffffU); 1647 set_val--; 1648 mutex_enter(&devc->mutex); 1649 switch (set_val) { 1650 case 0: 1651 case 1: 1652 break; 1653 default: 1654 mutex_exit(&devc->mutex); 1655 return (EINVAL); 1656 } 1657 ec->val = value; 1658 /* center/lfe */ 1659 if (devc->feature_mask & SB_INVSP) { 1660 set_val = !set_val; 1661 } 1662 if (!devc->suspended) { 1663 if (devc->feature_mask & (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL)) { 1664 val = INL(devc, devc->regs + 0x18); 1665 val &= ~A_IOCFG_GPOUT0; 1666 val |= set_val ? 0x44 : 0x40; 1667 OUTL(devc, val, devc->regs + 0x18); 1668 1669 } else if (devc->feature_mask & SB_LIVE) { 1670 val = INL(devc, devc->regs + HCFG); 1671 val &= ~HCFG_GPOUT0; 1672 val |= set_val ? HCFG_GPOUT0 : 0; 1673 OUTL(devc, val, devc->regs + HCFG); 1674 } 1675 } 1676 mutex_exit(&devc->mutex); 1677 return (0); 1678 } 1679 1680 static int 1681 emu10k_set_recsrc(void *arg, uint64_t value) 1682 { 1683 emu10k_ctrl_t *ec = arg; 1684 emu10k_devc_t *devc = ec->devc; 1685 uint32_t set_val; 1686 1687 set_val = ddi_ffs(value & 0xffffffffU); 1688 set_val--; 1689 1690 /* 1691 * We start assuming well set up AC'97 for stereomix recording. 1692 */ 1693 switch (set_val) { 1694 case INPUT_AC97: 1695 case INPUT_SPD1: 1696 case INPUT_SPD2: 1697 case INPUT_DIGCD: 1698 case INPUT_AUX2: 1699 case INPUT_LINE2: 1700 case INPUT_STEREOMIX: 1701 break; 1702 default: 1703 return (EINVAL); 1704 } 1705 1706 mutex_enter(&devc->mutex); 1707 ec->val = value; 1708 1709 emu10k_write_gpr(devc, GPR_REC_AC97, (set_val == INPUT_AC97)); 1710 emu10k_write_gpr(devc, GPR_REC_SPDIF1, (set_val == INPUT_SPD1)); 1711 emu10k_write_gpr(devc, GPR_REC_SPDIF2, (set_val == INPUT_SPD2)); 1712 emu10k_write_gpr(devc, GPR_REC_DIGCD, (set_val == INPUT_DIGCD)); 1713 emu10k_write_gpr(devc, GPR_REC_AUX2, (set_val == INPUT_AUX2)); 1714 emu10k_write_gpr(devc, GPR_REC_LINE2, (set_val == INPUT_LINE2)); 1715 emu10k_write_gpr(devc, GPR_REC_PCM, (set_val == INPUT_STEREOMIX)); 1716 1717 mutex_exit(&devc->mutex); 1718 1719 return (0); 1720 } 1721 1722 static void 1723 emu10k_create_stereo(emu10k_devc_t *devc, int ctl, int gpr, 1724 const char *id, int flags, int defval) 1725 { 1726 emu10k_ctrl_t *ec; 1727 audio_ctrl_desc_t desc; 1728 1729 bzero(&desc, sizeof (desc)); 1730 1731 ec = &devc->ctrls[ctl]; 1732 ec->devc = devc; 1733 ec->gpr_num = gpr; 1734 1735 desc.acd_name = id; 1736 desc.acd_type = AUDIO_CTRL_TYPE_STEREO; 1737 desc.acd_minvalue = 0; 1738 desc.acd_maxvalue = 100; 1739 desc.acd_flags = flags; 1740 1741 ec->val = (defval << 8) | defval; 1742 ec->ctrl = audio_dev_add_control(devc->adev, &desc, 1743 emu10k_get_control, emu10k_set_stereo, ec); 1744 1745 mutex_enter(&devc->mutex); 1746 emu10k_write_gpr(devc, gpr, emu10k_convert_fixpoint(defval)); 1747 emu10k_write_gpr(devc, gpr + 1, emu10k_convert_fixpoint(defval)); 1748 mutex_exit(&devc->mutex); 1749 } 1750 1751 static void 1752 emu10k_create_mono(emu10k_devc_t *devc, int ctl, int gpr, 1753 const char *id, int flags, int defval) 1754 { 1755 emu10k_ctrl_t *ec; 1756 audio_ctrl_desc_t desc; 1757 1758 bzero(&desc, sizeof (desc)); 1759 1760 ec = &devc->ctrls[ctl]; 1761 ec->devc = devc; 1762 ec->gpr_num = gpr; 1763 1764 desc.acd_name = id; 1765 desc.acd_type = AUDIO_CTRL_TYPE_MONO; 1766 desc.acd_minvalue = 0; 1767 desc.acd_maxvalue = 100; 1768 desc.acd_flags = flags; 1769 1770 ec->val = defval; 1771 ec->ctrl = audio_dev_add_control(devc->adev, &desc, 1772 emu10k_get_control, emu10k_set_mono, ec); 1773 1774 mutex_enter(&devc->mutex); 1775 emu10k_write_gpr(devc, gpr, emu10k_convert_fixpoint(defval)); 1776 mutex_exit(&devc->mutex); 1777 } 1778 1779 /* 1780 * AC'97 source. The AC'97 PCM record channel is routed to our 1781 * mixer. While we could support the direct monitoring capability of 1782 * the AC'97 part itself, this would not work correctly with outputs 1783 * that are not routed via AC'97 (such as the Live Drive headphones 1784 * or digital outputs.) So we just offer the ability to select one 1785 * AC'97 source, and then offer independent ability to either monitor 1786 * or record from the AC'97 mixer's PCM record channel. 1787 */ 1788 static void 1789 emu10k_create_ac97src(emu10k_devc_t *devc) 1790 { 1791 emu10k_ctrl_t *ec; 1792 audio_ctrl_desc_t desc; 1793 ac97_ctrl_t *ac; 1794 const audio_ctrl_desc_t *acd; 1795 1796 bzero(&desc, sizeof (desc)); 1797 1798 ec = &devc->ctrls[CTL_AC97SRC]; 1799 desc.acd_name = "ac97-source"; 1800 desc.acd_type = AUDIO_CTRL_TYPE_ENUM; 1801 desc.acd_flags = RECCTL; 1802 ec->devc = devc; 1803 ac = ac97_control_find(devc->ac97, AUDIO_CTRL_ID_RECSRC); 1804 if (ac == NULL) { 1805 return; 1806 } 1807 1808 acd = ac97_control_desc(ac); 1809 1810 for (int i = 0; i < 64; i++) { 1811 const char *n; 1812 if (((acd->acd_minvalue & (1ULL << i)) == 0) || 1813 ((n = acd->acd_enum[i]) == NULL)) { 1814 continue; 1815 } 1816 desc.acd_enum[i] = acd->acd_enum[i]; 1817 /* we suppress some port options */ 1818 if ((strcmp(n, AUDIO_PORT_STEREOMIX) == 0) || 1819 (strcmp(n, AUDIO_PORT_MONOMIX) == 0) || 1820 (strcmp(n, AUDIO_PORT_VIDEO) == 0)) { 1821 continue; 1822 } 1823 desc.acd_minvalue |= (1ULL << i); 1824 desc.acd_maxvalue |= (1ULL << i); 1825 } 1826 1827 ec->ctrl = audio_dev_add_control(devc->adev, &desc, 1828 emu10k_get_ac97src, emu10k_set_ac97src, ac); 1829 } 1830 1831 /* 1832 * Record source... this one is tricky. While the chip will 1833 * conceivably let us *mix* some of the audio streams for recording, 1834 * the AC'97 inputs don't have this capability. Offering it to users 1835 * is likely to be confusing, so we offer a single record source 1836 * selection option. Its not ideal, but it ought to be good enough 1837 * for the vast majority of users. 1838 */ 1839 static void 1840 emu10k_create_recsrc(emu10k_devc_t *devc) 1841 { 1842 emu10k_ctrl_t *ec; 1843 audio_ctrl_desc_t desc; 1844 ac97_ctrl_t *ac; 1845 1846 bzero(&desc, sizeof (desc)); 1847 1848 ec = &devc->ctrls[CTL_RECSRC]; 1849 desc.acd_name = AUDIO_CTRL_ID_RECSRC; 1850 desc.acd_type = AUDIO_CTRL_TYPE_ENUM; 1851 desc.acd_flags = RECCTL; 1852 desc.acd_minvalue = 0; 1853 desc.acd_maxvalue = 0; 1854 bzero(desc.acd_enum, sizeof (desc.acd_enum)); 1855 ec->devc = devc; 1856 ac = ac97_control_find(devc->ac97, AUDIO_CTRL_ID_RECSRC); 1857 1858 /* only low order bits set by AC'97 */ 1859 ASSERT(desc.acd_minvalue == desc.acd_maxvalue); 1860 ASSERT((desc.acd_minvalue & ~0xffff) == 0); 1861 1862 /* 1863 * It would be really cool if we could detect whether these 1864 * options are all sensible on a given configuration. Units 1865 * without live-drive support, and units without a physical 1866 * live-drive, simply can't do all these. 1867 */ 1868 if (ac != NULL) { 1869 desc.acd_minvalue |= (1 << INPUT_AC97); 1870 desc.acd_maxvalue |= (1 << INPUT_AC97); 1871 desc.acd_enum[INPUT_AC97] = "ac97"; 1872 ec->val = (1 << INPUT_AC97); 1873 } else { 1874 /* next best guess */ 1875 ec->val = (1 << INPUT_LINE2); 1876 } 1877 1878 desc.acd_minvalue |= (1 << INPUT_SPD1); 1879 desc.acd_maxvalue |= (1 << INPUT_SPD1); 1880 desc.acd_enum[INPUT_SPD1] = AUDIO_PORT_SPDIFIN; 1881 1882 desc.acd_minvalue |= (1 << INPUT_SPD2); 1883 desc.acd_maxvalue |= (1 << INPUT_SPD2); 1884 desc.acd_enum[INPUT_SPD2] = "spdif2-in"; 1885 1886 desc.acd_minvalue |= (1 << INPUT_DIGCD); 1887 desc.acd_maxvalue |= (1 << INPUT_DIGCD); 1888 desc.acd_enum[INPUT_DIGCD] = "digital-cd"; 1889 1890 desc.acd_minvalue |= (1 << INPUT_AUX2); 1891 desc.acd_maxvalue |= (1 << INPUT_AUX2); 1892 desc.acd_enum[INPUT_AUX2] = AUDIO_PORT_AUX2IN; 1893 1894 desc.acd_minvalue |= (1 << INPUT_LINE2); 1895 desc.acd_maxvalue |= (1 << INPUT_LINE2); 1896 desc.acd_enum[INPUT_LINE2] = "line2-in"; 1897 1898 desc.acd_minvalue |= (1 << INPUT_STEREOMIX); 1899 desc.acd_maxvalue |= (1 << INPUT_STEREOMIX); 1900 desc.acd_enum[INPUT_STEREOMIX] = AUDIO_PORT_STEREOMIX; 1901 1902 emu10k_write_gpr(devc, GPR_REC_SPDIF1, 0); 1903 emu10k_write_gpr(devc, GPR_REC_SPDIF2, 0); 1904 emu10k_write_gpr(devc, GPR_REC_DIGCD, 0); 1905 emu10k_write_gpr(devc, GPR_REC_AUX2, 0); 1906 emu10k_write_gpr(devc, GPR_REC_LINE2, 0); 1907 emu10k_write_gpr(devc, GPR_REC_PCM, 0); 1908 emu10k_write_gpr(devc, GPR_REC_AC97, 1); 1909 1910 ec->ctrl = audio_dev_add_control(devc->adev, &desc, 1911 emu10k_get_control, emu10k_set_recsrc, ec); 1912 } 1913 1914 static void 1915 emu10k_create_jack3(emu10k_devc_t *devc) 1916 { 1917 emu10k_ctrl_t *ec; 1918 audio_ctrl_desc_t desc; 1919 1920 bzero(&desc, sizeof (desc)); 1921 1922 ec = &devc->ctrls[CTL_JACK3]; 1923 desc.acd_name = AUDIO_CTRL_ID_JACK3; 1924 desc.acd_type = AUDIO_CTRL_TYPE_ENUM; 1925 desc.acd_flags = AUDIO_CTRL_FLAG_RW; 1926 desc.acd_minvalue = 0x3; 1927 desc.acd_maxvalue = 0x3; 1928 bzero(desc.acd_enum, sizeof (desc.acd_enum)); 1929 ec->devc = devc; 1930 ec->val = 0x1; 1931 1932 desc.acd_enum[0] = AUDIO_PORT_CENLFE; 1933 desc.acd_enum[1] = AUDIO_PORT_SPDIFOUT; 1934 1935 ec->ctrl = audio_dev_add_control(devc->adev, &desc, 1936 emu10k_get_control, emu10k_set_jack3, ec); 1937 } 1938 1939 1940 static void 1941 emu10k_create_controls(emu10k_devc_t *devc) 1942 { 1943 ac97_t *ac97; 1944 ac97_ctrl_t *ac; 1945 1946 emu10k_create_mono(devc, CTL_VOLUME, GPR_VOL_PCM, 1947 AUDIO_CTRL_ID_VOLUME, PCMVOL, 75); 1948 1949 emu10k_create_stereo(devc, CTL_FRONT, GPR_VOL_FRONT, 1950 AUDIO_CTRL_ID_FRONT, MAINVOL, 100); 1951 emu10k_create_stereo(devc, CTL_SURROUND, GPR_VOL_SURR, 1952 AUDIO_CTRL_ID_SURROUND, MAINVOL, 100); 1953 if (devc->feature_mask & (SB_51 | SB_71)) { 1954 emu10k_create_mono(devc, CTL_CENTER, GPR_VOL_CEN, 1955 AUDIO_CTRL_ID_CENTER, MAINVOL, 100); 1956 emu10k_create_mono(devc, CTL_LFE, GPR_VOL_LFE, 1957 AUDIO_CTRL_ID_LFE, MAINVOL, 100); 1958 } 1959 if (devc->feature_mask & SB_71) { 1960 emu10k_create_stereo(devc, CTL_SIDE, GPR_VOL_SIDE, 1961 "side", MAINVOL, 100); 1962 } 1963 1964 emu10k_create_stereo(devc, CTL_RECGAIN, GPR_VOL_REC, 1965 AUDIO_CTRL_ID_RECGAIN, RECVOL, 50); 1966 1967 emu10k_create_ac97src(devc); 1968 emu10k_create_recsrc(devc); 1969 /* 1970 * 5.1 devices have versa jack. Note that from what we can 1971 * tell, none of the 7.1 devices have or need this versa jack, 1972 * as they all seem to have a dedicated digital I/O port. 1973 */ 1974 if ((devc->feature_mask & SB_51) && 1975 !(devc->feature_mask & SB_AUDIGY2VAL)) { 1976 emu10k_create_jack3(devc); 1977 } 1978 1979 /* these ones AC'97 can manage directly */ 1980 ac97 = devc->ac97; 1981 1982 if ((ac = ac97_control_find(ac97, AUDIO_CTRL_ID_MICBOOST)) != NULL) 1983 ac97_control_register(ac); 1984 if ((ac = ac97_control_find(ac97, AUDIO_CTRL_ID_MICGAIN)) != NULL) 1985 ac97_control_register(ac); 1986 1987 /* set any AC'97 analog outputs to full volume (no attenuation) */ 1988 if ((ac = ac97_control_find(ac97, AUDIO_CTRL_ID_FRONT)) != NULL) 1989 (void) ac97_control_set(ac, (100 << 8) | 100); 1990 if ((ac = ac97_control_find(ac97, AUDIO_CTRL_ID_LINEOUT)) != NULL) 1991 (void) ac97_control_set(ac, (100 << 8) | 100); 1992 if ((ac = ac97_control_find(ac97, AUDIO_CTRL_ID_SURROUND)) != NULL) 1993 (void) ac97_control_set(ac, (100 << 8) | 100); 1994 if ((ac = ac97_control_find(ac97, AUDIO_CTRL_ID_CENTER)) != NULL) 1995 (void) ac97_control_set(ac, 100); 1996 if ((ac = ac97_control_find(ac97, AUDIO_CTRL_ID_LFE)) != NULL) 1997 (void) ac97_control_set(ac, 100); 1998 1999 /* Monitor sources */ 2000 emu10k_create_stereo(devc, CTL_AC97, GPR_MON_AC97, 2001 "ac97-monitor", MONVOL, 0); 2002 emu10k_create_stereo(devc, CTL_SPD1, GPR_MON_SPDIF1, 2003 AUDIO_PORT_SPDIFIN, MONVOL, 0); 2004 emu10k_create_stereo(devc, CTL_DIGCD, GPR_MON_DIGCD, 2005 "digital-cd", MONVOL, 0); 2006 emu10k_create_stereo(devc, CTL_SPD1, GPR_MON_SPDIF1, 2007 AUDIO_PORT_SPDIFIN, MONVOL, 0); 2008 2009 if ((devc->feature_mask & SB_NOEXP) == 0) { 2010 /* 2011 * These ports are only available via an external 2012 * expansion box. Don't expose them for cards that 2013 * don't have support for it. 2014 */ 2015 emu10k_create_stereo(devc, CTL_HEADPH, GPR_VOL_HEADPH, 2016 AUDIO_CTRL_ID_HEADPHONE, MAINVOL, 100); 2017 emu10k_create_stereo(devc, CTL_SPD2, GPR_MON_SPDIF2, 2018 "spdif2-in", MONVOL, 0); 2019 emu10k_create_stereo(devc, CTL_LINE2, GPR_MON_LINE2, 2020 "line2-in", MONVOL, 0); 2021 emu10k_create_stereo(devc, CTL_AUX2, GPR_MON_AUX2, 2022 AUDIO_PORT_AUX2IN, MONVOL, 0); 2023 } 2024 } 2025 2026 static void 2027 emu10k_load_dsp(emu10k_devc_t *devc, uint32_t *code, int ncode, 2028 uint32_t *init, int ninit) 2029 { 2030 int i; 2031 2032 if (ncode > 1024) { 2033 audio_dev_warn(devc->adev, "DSP file size too big"); 2034 return; 2035 } 2036 if (ninit > MAX_GPR) { 2037 audio_dev_warn(devc->adev, "Too many inits"); 2038 return; 2039 } 2040 2041 /* Upload our DSP code */ 2042 for (i = 0; i < ncode; i++) { 2043 emu10k_write_efx(devc, UC0 + i, code[i]); 2044 } 2045 2046 /* Upload the initialization settings */ 2047 for (i = 0; i < ninit; i += 2) { 2048 emu10k_write_reg(devc, init[i] + GPR0, 0, init[i + 1]); 2049 } 2050 } 2051 2052 #define LIVE_NOP() \ 2053 emu10k_write_efx(devc, UC0 + (pc * 2), 0x10040); \ 2054 emu10k_write_efx(devc, UC0 + (pc * 2 + 1), 0x610040); \ 2055 pc++ 2056 #define LIVE_ACC3(r, a, x, y) /* z=w+x+y */ \ 2057 emu10k_write_efx(devc, UC0 + (pc * 2), (x << 10) | y); \ 2058 emu10k_write_efx(devc, UC0 + (pc * 2 + 1), (6 << 20) | (r << 10) | a); \ 2059 pc++ 2060 2061 #define AUDIGY_ACC3(r, a, x, y) /* z=w+x+y */ \ 2062 emu10k_write_efx(devc, UC0 + (pc * 2), (x << 12) | y); \ 2063 emu10k_write_efx(devc, UC0 + (pc * 2+1), (6 << 24) | (r << 12) | a); \ 2064 pc++ 2065 #define AUDIGY_NOP() AUDIGY_ACC3(0xc0, 0xc0, 0xc0, 0xc0) 2066 2067 static void 2068 emu10k_init_effects(emu10k_devc_t *devc) 2069 { 2070 int i; 2071 unsigned short pc; 2072 2073 ASSERT(mutex_owned(&devc->mutex)); 2074 2075 if (devc->feature_mask & (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL)) { 2076 pc = 0; 2077 for (i = 0; i < 512; i++) { 2078 AUDIGY_NOP(); 2079 } 2080 2081 for (i = 0; i < 256; i++) 2082 emu10k_write_efx(devc, GPR0 + i, 0); 2083 emu10k_write_reg(devc, AUDIGY_DBG, 0, 0); 2084 emu10k_load_dsp(devc, 2085 emu10k2_code, 2086 sizeof (emu10k2_code) / sizeof (emu10k2_code[0]), 2087 emu10k2_init, 2088 sizeof (emu10k2_init) / sizeof (emu10k2_init[0])); 2089 2090 } else { 2091 pc = 0; 2092 for (i = 0; i < 512; i++) { 2093 LIVE_NOP(); 2094 } 2095 2096 for (i = 0; i < 256; i++) 2097 emu10k_write_efx(devc, GPR0 + i, 0); 2098 emu10k_write_reg(devc, DBG, 0, 0); 2099 emu10k_load_dsp(devc, 2100 emu10k1_code, 2101 sizeof (emu10k1_code) / sizeof (emu10k1_code[0]), 2102 emu10k1_init, 2103 sizeof (emu10k1_init) / sizeof (emu10k1_init[0])); 2104 } 2105 } 2106 2107 /* mixer */ 2108 2109 static struct { 2110 uint16_t devid; 2111 uint16_t subid; 2112 const char *model; 2113 const char *prod; 2114 unsigned feature_mask; 2115 } emu10k_cards[] = { 2116 { 0x2, 0x0020, "CT4670", "Live! Value", SB_LIVE | SB_NOEXP }, 2117 { 0x2, 0x0021, "CT4621", "Live!", SB_LIVE }, 2118 { 0x2, 0x100a, "SB0220", "Live! 5.1 Digital", 2119 SB_LIVE | SB_51 | SB_NOEXP }, 2120 { 0x2, 0x8022, "CT4780", "Live! Value", SB_LIVE }, 2121 { 0x2, 0x8023, "CT4790", "PCI512", SB_LIVE | SB_NOEXP }, 2122 { 0x2, 0x8026, "CT4830", "Live! Value", SB_LIVE }, 2123 { 0x2, 0x8028, "CT4870", "Live! Value", SB_LIVE }, 2124 { 0x2, 0x8031, "CT4831", "Live! Value", SB_LIVE }, 2125 { 0x2, 0x8040, "CT4760", "Live!", SB_LIVE }, 2126 { 0x2, 0x8051, "CT4850", "Live! Value", SB_LIVE }, 2127 { 0x2, 0x8061, "SB0060", "Live! 5.1", SB_LIVE | SB_51 }, 2128 { 0x2, 0x8064, "SB0100", "Live! 5.1", SB_LIVE | SB_51 }, 2129 { 0x2, 0x8065, "SB0220", "Live! 5.1", SB_LIVE | SB_51 }, 2130 { 0x2, 0x8066, "SB0228", "Live! 5.1", SB_LIVE | SB_51 }, 2131 { 0x4, 0x0051, "SB0090", "Audigy", SB_AUDIGY | SB_51 }, 2132 { 0x4, 0x0052, "SB0160", "Audigy ES", SB_AUDIGY | SB_51 }, 2133 { 0x4, 0x0053, "SB0092", "Audigy", SB_AUDIGY | SB_51 }, 2134 { 0x4, 0x1002, "SB0240P", "Audigy 2 Platinum", 2135 SB_AUDIGY2 | SB_71 | SB_INVSP }, 2136 { 0x4, 0x1003, "SB0353", "Audigy 2 ZS", SB_AUDIGY2 | SB_71 | SB_INVSP }, 2137 { 0x4, 0x1005, "SB0280", "Audigy 2 Platinum EX", SB_AUDIGY2 | SB_71 }, 2138 { 0x4, 0x1007, "SB0240", "Audigy 2", SB_AUDIGY2 | SB_71 }, 2139 { 0x4, 0x2001, "SB0360", "Audigy 2 ZS", SB_AUDIGY2 | SB_71 | SB_INVSP }, 2140 { 0x4, 0x2002, "SB0350", "Audigy 2 ZS", SB_AUDIGY2 | SB_71 | SB_INVSP }, 2141 { 0x4, 0x2006, "SB0350", "Audigy 2", SB_AUDIGY2 | SB_71 | SB_INVSP }, 2142 { 0x4, 0x2007, "SB0380", "Audigy 4 Pro", SB_AUDIGY2 | SB_71 }, 2143 { 0x8, 0x1001, "SB0400", "Audigy 2 Value", 2144 SB_AUDIGY2VAL | SB_71 | SB_NOEXP }, 2145 { 0x8, 0x1021, "SB0610", "Audigy 4", 2146 SB_AUDIGY2VAL | SB_71 | SB_NOEXP }, 2147 { 0x8, 0x2001, "SB0530", "Audigy 2 ZS Notebook", 2148 SB_AUDIGY2VAL | SB_71 }, 2149 { 0, 0, NULL, NULL, 0 }, 2150 }; 2151 2152 int 2153 emu10k_attach(dev_info_t *dip) 2154 { 2155 uint16_t pci_command; 2156 uint16_t subid; 2157 uint16_t devid; 2158 emu10k_devc_t *devc; 2159 ddi_acc_handle_t pcih; 2160 ddi_dma_cookie_t cookie; 2161 uint_t count; 2162 ulong_t len; 2163 int i; 2164 const char *name; 2165 const char *model; 2166 char namebuf[64]; 2167 int feature_mask; 2168 2169 devc = kmem_zalloc(sizeof (*devc), KM_SLEEP); 2170 devc->dip = dip; 2171 ddi_set_driver_private(dip, devc); 2172 2173 if ((devc->adev = audio_dev_alloc(dip, 0)) == NULL) { 2174 cmn_err(CE_WARN, "audio_dev_alloc failed"); 2175 goto error; 2176 } 2177 2178 if (pci_config_setup(dip, &pcih) != DDI_SUCCESS) { 2179 audio_dev_warn(devc->adev, "pci_config_setup failed"); 2180 goto error; 2181 } 2182 devc->pcih = pcih; 2183 2184 devid = pci_config_get16(pcih, PCI_CONF_DEVID); 2185 subid = pci_config_get16(pcih, PCI_CONF_SUBSYSID); 2186 2187 pci_command = pci_config_get16(pcih, PCI_CONF_COMM); 2188 pci_command |= PCI_COMM_ME | PCI_COMM_IO; 2189 pci_config_put16(pcih, PCI_CONF_COMM, pci_command); 2190 2191 if ((ddi_regs_map_setup(dip, 1, &devc->regs, 0, 0, &dev_attr, 2192 &devc->regsh)) != DDI_SUCCESS) { 2193 audio_dev_warn(devc->adev, "failed to map registers"); 2194 goto error; 2195 } 2196 2197 switch (devid) { 2198 case PCI_DEVICE_ID_SBLIVE: 2199 name = "Live!"; 2200 model = "CT????"; 2201 feature_mask = SB_LIVE; 2202 break; 2203 2204 case PCI_DEVICE_ID_AUDIGYVALUE: 2205 name = "Audigy 2 Value"; 2206 model = "SB????"; 2207 feature_mask = SB_AUDIGY2VAL; 2208 break; 2209 2210 case PCI_DEVICE_ID_AUDIGY: 2211 if (subid >= 0x1002 && subid <= 0x2005) { 2212 name = "Audigy 2"; 2213 model = "SB????"; 2214 feature_mask = SB_AUDIGY2; 2215 } else { 2216 name = "Audigy"; 2217 model = "SB????"; 2218 feature_mask = SB_AUDIGY; 2219 } 2220 break; 2221 2222 default: 2223 audio_dev_warn(devc->adev, "Unrecognized device"); 2224 goto error; 2225 } 2226 2227 for (i = 0; emu10k_cards[i].prod; i++) { 2228 if ((devid == emu10k_cards[i].devid) && 2229 (subid == emu10k_cards[i].subid)) { 2230 name = emu10k_cards[i].prod; 2231 model = emu10k_cards[i].model; 2232 feature_mask = emu10k_cards[i].feature_mask; 2233 break; 2234 } 2235 } 2236 devc->feature_mask = feature_mask; 2237 2238 (void) snprintf(namebuf, sizeof (namebuf), "Sound Blaster %s", name); 2239 2240 audio_dev_set_description(devc->adev, namebuf); 2241 audio_dev_set_version(devc->adev, model); 2242 2243 if (emu10k_setup_intrs(devc) != DDI_SUCCESS) 2244 goto error; 2245 2246 /* allocate static page table memory */ 2247 2248 devc->max_mem = AUDIO_MEMSIZE; 2249 2250 /* SB Live/Audigy supports at most 32M of memory) */ 2251 if (devc->max_mem > 32 * 1024 * 1024) 2252 devc->max_mem = 32 * 1024 * 1024; 2253 2254 devc->max_pages = devc->max_mem / 4096; 2255 if (devc->max_pages < 1024) 2256 devc->max_pages = 1024; 2257 2258 /* Allocate page table */ 2259 if (ddi_dma_alloc_handle(devc->dip, &dma_attr_buf, DDI_DMA_SLEEP, NULL, 2260 &devc->pt_dmah) != DDI_SUCCESS) { 2261 audio_dev_warn(devc->adev, 2262 "failed to allocate page table handle"); 2263 return (DDI_FAILURE); 2264 } 2265 2266 if (ddi_dma_mem_alloc(devc->pt_dmah, devc->max_pages * 4, 2267 &dev_attr, DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, 2268 &devc->pt_kaddr, &len, &devc->pt_acch) != 2269 DDI_SUCCESS) { 2270 audio_dev_warn(devc->adev, 2271 "failed to allocate memory for page table"); 2272 return (DDI_FAILURE); 2273 } 2274 2275 if (ddi_dma_addr_bind_handle(devc->pt_dmah, NULL, 2276 devc->pt_kaddr, len, DDI_DMA_CONSISTENT | DDI_DMA_WRITE, 2277 DDI_DMA_SLEEP, NULL, &cookie, &count) != DDI_SUCCESS) { 2278 audio_dev_warn(devc->adev, 2279 "failed binding page table DMA handle"); 2280 return (DDI_FAILURE); 2281 } 2282 2283 devc->page_map = (void *)devc->pt_kaddr; 2284 devc->pt_paddr = cookie.dmac_address; 2285 bzero(devc->pt_kaddr, devc->max_pages * 4); 2286 2287 /* Allocate silent page */ 2288 if (ddi_dma_alloc_handle(devc->dip, &dma_attr_buf, DDI_DMA_SLEEP, NULL, 2289 &devc->silence_dmah) != DDI_SUCCESS) { 2290 audio_dev_warn(devc->adev, 2291 "failed to allocate silent page handle"); 2292 return (DDI_FAILURE); 2293 } 2294 2295 if (ddi_dma_mem_alloc(devc->silence_dmah, 4096, 2296 &buf_attr, DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, 2297 &devc->silence_kaddr, &len, 2298 &devc->silence_acch) != DDI_SUCCESS) { 2299 audio_dev_warn(devc->adev, 2300 "failed to allocate silent page memory"); 2301 return (DDI_FAILURE); 2302 } 2303 2304 (void) ddi_dma_sync(devc->silence_dmah, 0, 0, DDI_DMA_SYNC_FORDEV); 2305 2306 if (ddi_dma_addr_bind_handle(devc->silence_dmah, NULL, 2307 devc->silence_kaddr, len, DDI_DMA_CONSISTENT | DDI_DMA_WRITE, 2308 DDI_DMA_SLEEP, NULL, &cookie, &count) != DDI_SUCCESS) { 2309 audio_dev_warn(devc->adev, 2310 "failed binding silent page DMA handle"); 2311 return (DDI_FAILURE); 2312 } 2313 2314 devc->silence_paddr = cookie.dmac_address; 2315 bzero(devc->silence_kaddr, 4096); 2316 devc->audio_memptr = 4096; /* Skip the silence page */ 2317 2318 for (i = 0; i < devc->max_pages; i++) 2319 FILL_PAGE_MAP_ENTRY(i, devc->silence_paddr); 2320 2321 (void) ddi_dma_sync(devc->pt_dmah, 0, 0, DDI_DMA_SYNC_FORDEV); 2322 2323 devc->ac97 = ac97_allocate(devc->adev, dip, 2324 emu10k_read_ac97, emu10k_write_ac97, devc); 2325 if (devc->ac97 == NULL) { 2326 audio_dev_warn(devc->adev, "failed to allocate ac97 handle"); 2327 goto error; 2328 } 2329 2330 ac97_probe_controls(devc->ac97); 2331 2332 /* allocate voice 0 for play */ 2333 if (emu10k_alloc_port(devc, EMU10K_REC) != DDI_SUCCESS) 2334 goto error; 2335 2336 if (emu10k_alloc_port(devc, EMU10K_PLAY) != DDI_SUCCESS) 2337 goto error; 2338 2339 /* now initialize the hardware */ 2340 mutex_enter(&devc->mutex); 2341 if (emu10k_hwinit(devc) != DDI_SUCCESS) { 2342 mutex_exit(&devc->mutex); 2343 goto error; 2344 } 2345 mutex_exit(&devc->mutex); 2346 2347 emu10k_create_controls(devc); 2348 2349 /* set up kernel statistics */ 2350 if ((devc->ksp = kstat_create(EMU10K_NAME, ddi_get_instance(dip), 2351 EMU10K_NAME, "controller", KSTAT_TYPE_INTR, 2352 1, KSTAT_FLAG_PERSISTENT)) != NULL) { 2353 kstat_install(devc->ksp); 2354 } 2355 2356 if (audio_dev_register(devc->adev) != DDI_SUCCESS) { 2357 audio_dev_warn(devc->adev, "unable to register audio device"); 2358 goto error; 2359 } 2360 2361 (void) ddi_intr_enable(devc->ih); 2362 ddi_report_dev(dip); 2363 2364 return (DDI_SUCCESS); 2365 2366 error: 2367 emu10k_destroy(devc); 2368 return (DDI_FAILURE); 2369 } 2370 2371 int 2372 emu10k_resume(dev_info_t *dip) 2373 { 2374 emu10k_devc_t *devc; 2375 emu10k_portc_t *portc; 2376 2377 devc = ddi_get_driver_private(dip); 2378 2379 for (int i = 0; i < EMU10K_NUM_PORTC; i++) { 2380 portc = devc->portc[i]; 2381 audio_engine_reset(portc->engine); 2382 } 2383 2384 mutex_enter(&devc->mutex); 2385 if (emu10k_hwinit(devc) != DDI_SUCCESS) { 2386 mutex_exit(&devc->mutex); 2387 /* 2388 * In case of failure, we leave the chip suspended, 2389 * but don't panic. Audio service is not normally a a 2390 * critical service. 2391 */ 2392 audio_dev_warn(devc->adev, "FAILED to RESUME device"); 2393 return (DDI_SUCCESS); 2394 } 2395 2396 emu10k_refresh_mixer(devc); 2397 2398 devc->suspended = B_FALSE; 2399 2400 for (int i = 0; i < EMU10K_NUM_PORTC; i++) { 2401 2402 portc = devc->portc[i]; 2403 2404 portc->stop_port(portc); 2405 2406 portc->dopos = 1; 2407 if (portc->started) { 2408 portc->reset_port(portc); 2409 portc->start_port(portc); 2410 } 2411 } 2412 2413 mutex_exit(&devc->mutex); 2414 2415 /* resume ac97 */ 2416 ac97_resume(devc->ac97); 2417 2418 return (DDI_SUCCESS); 2419 } 2420 2421 int 2422 emu10k_detach(emu10k_devc_t *devc) 2423 { 2424 if (audio_dev_unregister(devc->adev) != DDI_SUCCESS) 2425 return (DDI_FAILURE); 2426 2427 emu10k_destroy(devc); 2428 return (DDI_SUCCESS); 2429 } 2430 2431 int 2432 emu10k_suspend(emu10k_devc_t *devc) 2433 { 2434 ac97_suspend(devc->ac97); 2435 2436 mutex_enter(&devc->mutex); 2437 2438 devc->suspended = B_TRUE; 2439 2440 emu10k_write_reg(devc, CLIEL, 0, 0); 2441 emu10k_write_reg(devc, CLIEH, 0, 0); 2442 if (!(devc->feature_mask & SB_LIVE)) { 2443 emu10k_write_reg(devc, HLIEL, 0, 0x0); 2444 emu10k_write_reg(devc, HLIEH, 0, 0x0); 2445 } 2446 OUTL(devc, 0, devc->regs + IE); /* Intr enable (all off) */ 2447 2448 for (int i = 0; i < EMU10K_NUM_PORTC; i++) { 2449 emu10k_portc_t *portc = devc->portc[i]; 2450 portc->stop_port(portc); 2451 } 2452 2453 /* stop all voices */ 2454 for (int i = 0; i < 64; i++) { 2455 emu10k_write_reg(devc, VEDS, i, 0); 2456 } 2457 for (int i = 0; i < 64; i++) { 2458 emu10k_write_reg(devc, VTFT, i, 0); 2459 emu10k_write_reg(devc, CVCF, i, 0); 2460 emu10k_write_reg(devc, PTAB, i, 0); 2461 emu10k_write_reg(devc, CPF, i, 0); 2462 } 2463 /* 2464 * Turn off the hardware 2465 */ 2466 OUTL(devc, 2467 HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK | 2468 HCFG_MUTEBUTTONENABLE, devc->regs + HCFG); 2469 2470 /* stop ADC recording */ 2471 emu10k_write_reg(devc, ADCSR, 0, 0x0); 2472 emu10k_write_reg(devc, ADCBA, 0, 0x0); 2473 emu10k_write_reg(devc, ADCBA, 0, 0x0); 2474 2475 emu10k_write_reg(devc, PTBA, 0, 0); 2476 2477 mutex_exit(&devc->mutex); 2478 2479 return (DDI_SUCCESS); 2480 } 2481 2482 static int emu10k_ddi_attach(dev_info_t *, ddi_attach_cmd_t); 2483 static int emu10k_ddi_detach(dev_info_t *, ddi_detach_cmd_t); 2484 static int emu10k_ddi_quiesce(dev_info_t *); 2485 2486 static struct dev_ops emu10k_dev_ops = { 2487 DEVO_REV, /* rev */ 2488 0, /* refcnt */ 2489 NULL, /* getinfo */ 2490 nulldev, /* identify */ 2491 nulldev, /* probe */ 2492 emu10k_ddi_attach, /* attach */ 2493 emu10k_ddi_detach, /* detach */ 2494 nodev, /* reset */ 2495 NULL, /* cb_ops */ 2496 NULL, /* bus_ops */ 2497 NULL, /* power */ 2498 emu10k_ddi_quiesce, /* quiesce */ 2499 }; 2500 2501 static struct modldrv emu10k_modldrv = { 2502 &mod_driverops, /* drv_modops */ 2503 "Creative EMU10K Audio", /* linkinfo */ 2504 &emu10k_dev_ops, /* dev_ops */ 2505 }; 2506 2507 static struct modlinkage modlinkage = { 2508 MODREV_1, 2509 { &emu10k_modldrv, NULL } 2510 }; 2511 2512 int 2513 _init(void) 2514 { 2515 int rv; 2516 2517 audio_init_ops(&emu10k_dev_ops, EMU10K_NAME); 2518 if ((rv = mod_install(&modlinkage)) != 0) { 2519 audio_fini_ops(&emu10k_dev_ops); 2520 } 2521 return (rv); 2522 } 2523 2524 int 2525 _fini(void) 2526 { 2527 int rv; 2528 2529 if ((rv = mod_remove(&modlinkage)) == 0) { 2530 audio_fini_ops(&emu10k_dev_ops); 2531 } 2532 return (rv); 2533 } 2534 2535 int 2536 _info(struct modinfo *modinfop) 2537 { 2538 return (mod_info(&modlinkage, modinfop)); 2539 } 2540 2541 int 2542 emu10k_ddi_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 2543 { 2544 switch (cmd) { 2545 case DDI_ATTACH: 2546 return (emu10k_attach(dip)); 2547 2548 case DDI_RESUME: 2549 return (emu10k_resume(dip)); 2550 2551 default: 2552 return (DDI_FAILURE); 2553 } 2554 } 2555 2556 int 2557 emu10k_ddi_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 2558 { 2559 emu10k_devc_t *devc; 2560 2561 devc = ddi_get_driver_private(dip); 2562 2563 switch (cmd) { 2564 case DDI_DETACH: 2565 return (emu10k_detach(devc)); 2566 2567 case DDI_SUSPEND: 2568 return (emu10k_suspend(devc)); 2569 2570 default: 2571 return (DDI_FAILURE); 2572 } 2573 } 2574 2575 int 2576 emu10k_ddi_quiesce(dev_info_t *dip) 2577 { 2578 emu10k_devc_t *devc; 2579 2580 devc = ddi_get_driver_private(dip); 2581 2582 /* stop all voices */ 2583 for (int i = 0; i < 64; i++) { 2584 emu10k_write_reg(devc, VEDS, i, 0); 2585 } 2586 for (int i = 0; i < 64; i++) { 2587 emu10k_write_reg(devc, VTFT, i, 0); 2588 emu10k_write_reg(devc, CVCF, i, 0); 2589 emu10k_write_reg(devc, PTAB, i, 0); 2590 emu10k_write_reg(devc, CPF, i, 0); 2591 } 2592 2593 /* 2594 * Turn off the hardware 2595 */ 2596 OUTL(devc, 0, devc->regs + IE); /* Intr enable (all off) */ 2597 OUTL(devc, 2598 HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK | 2599 HCFG_MUTEBUTTONENABLE, devc->regs + HCFG); 2600 2601 /* stop ADC recording */ 2602 emu10k_write_reg(devc, ADCSR, 0, 0x0); 2603 emu10k_write_reg(devc, ADCBA, 0, 0x0); 2604 emu10k_write_reg(devc, ADCBA, 0, 0x0); 2605 2606 emu10k_write_reg(devc, PTBA, 0, 0); 2607 2608 return (DDI_SUCCESS); 2609 } 2610