1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2022 Oxide Computer Company 14 */ 15 16 /* 17 * Go through and test the different versions of NPS hashing. Unlike with the 18 * COD hash, we also need to take into account socket interleaving. In addition 19 * to the basic ones, we also do a 5-channel and 6-channel variant to get 20 * various parts of the non-power of 2 forms tested. 21 */ 22 23 #include "zen_umc_test.h" 24 25 /* 26 * Start with the heavy hitter, the 2 socket, 8 channel (8/socket) configuration 27 * that does both socket interleaving and the hashing. Because this is a DFv4 28 * variant, we opt to set up the channels for DDR5. 29 */ 30 static const zen_umc_t zen_umc_nps8_2p = { 31 .umc_tom = 4ULL * 1024ULL * 1024ULL * 1024ULL, 32 .umc_tom2 = 256ULL * 1024ULL * 1024ULL * 1024ULL, 33 .umc_df_rev = DF_REV_4, 34 .umc_decomp = { 35 .dfd_sock_mask = 0x01, 36 .dfd_die_mask = 0x00, 37 .dfd_node_mask = 0x20, 38 .dfd_comp_mask = 0x1f, 39 .dfd_sock_shift = 0, 40 .dfd_die_shift = 0, 41 .dfd_node_shift = 5, 42 .dfd_comp_shift = 0 43 }, 44 .umc_ndfs = 2, 45 .umc_dfs = { { 46 .zud_dfno = 0, 47 .zud_dram_nrules = 1, 48 .zud_nchan = 8, 49 .zud_cs_nremap = 0, 50 .zud_hole_base = 0, 51 .zud_rules = { { 52 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_HASH_16_18 | 53 DF_DRAM_F_HASH_21_23 | DF_DRAM_F_HASH_30_32, 54 .ddr_base = 0, 55 .ddr_limit = 256ULL * 1024ULL * 1024ULL * 1024ULL, 56 .ddr_dest_fabid = 0, 57 .ddr_sock_ileave_bits = 1, 58 .ddr_die_ileave_bits = 0, 59 .ddr_addr_start = 9, 60 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS1_8CH 61 } }, 62 .zud_chan = { { 63 .chan_flags = UMC_CHAN_F_ECC_EN, 64 .chan_fabid = 0, 65 .chan_instid = 0, 66 .chan_logid = 0, 67 .chan_nrules = 1, 68 .chan_rules = { { 69 .ddr_flags = DF_DRAM_F_VALID | 70 DF_DRAM_F_HASH_16_18 | 71 DF_DRAM_F_HASH_21_23 | 72 DF_DRAM_F_HASH_30_32, 73 .ddr_base = 0, 74 .ddr_limit = 256ULL * 1024ULL * 1024ULL * 75 1024ULL, 76 .ddr_dest_fabid = 0, 77 .ddr_sock_ileave_bits = 1, 78 .ddr_die_ileave_bits = 0, 79 .ddr_addr_start = 9, 80 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS1_8CH 81 } }, 82 .chan_dimms = { { 83 .ud_flags = UMC_DIMM_F_VALID, 84 .ud_width = UMC_DIMM_W_X4, 85 .ud_type = UMC_DIMM_T_DDR5, 86 .ud_kind = UMC_DIMM_K_RDIMM, 87 .ud_dimmno = 0, 88 .ud_cs = { { 89 .ucs_base = { 90 .udb_base = 0, 91 .udb_valid = B_TRUE 92 }, 93 .ucs_base_mask = 0x3ffffffff, 94 .ucs_nbanks = 0x5, 95 .ucs_ncol = 0xa, 96 .ucs_nrow_lo = 0x10, 97 .ucs_nbank_groups = 0x3, 98 .ucs_row_low_bit = 0x12, 99 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 100 0xe }, 101 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 102 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 103 .ucs_subchan = 0x6 104 } } 105 } }, 106 }, { 107 .chan_flags = UMC_CHAN_F_ECC_EN, 108 .chan_fabid = 1, 109 .chan_instid = 1, 110 .chan_logid = 1, 111 .chan_nrules = 1, 112 .chan_rules = { { 113 .ddr_flags = DF_DRAM_F_VALID | 114 DF_DRAM_F_HASH_16_18 | 115 DF_DRAM_F_HASH_21_23 | 116 DF_DRAM_F_HASH_30_32, 117 .ddr_base = 0, 118 .ddr_limit = 256ULL * 1024ULL * 1024ULL * 119 1024ULL, 120 .ddr_dest_fabid = 0, 121 .ddr_sock_ileave_bits = 1, 122 .ddr_die_ileave_bits = 0, 123 .ddr_addr_start = 9, 124 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS1_8CH 125 } }, 126 .chan_dimms = { { 127 .ud_flags = UMC_DIMM_F_VALID, 128 .ud_width = UMC_DIMM_W_X4, 129 .ud_type = UMC_DIMM_T_DDR5, 130 .ud_kind = UMC_DIMM_K_RDIMM, 131 .ud_dimmno = 0, 132 .ud_cs = { { 133 .ucs_base = { 134 .udb_base = 0, 135 .udb_valid = B_TRUE 136 }, 137 .ucs_base_mask = 0x3ffffffff, 138 .ucs_nbanks = 0x5, 139 .ucs_ncol = 0xa, 140 .ucs_nrow_lo = 0x10, 141 .ucs_nbank_groups = 0x3, 142 .ucs_row_low_bit = 0x12, 143 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 144 0xe }, 145 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 146 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 147 .ucs_subchan = 0x6 148 } } 149 } }, 150 }, { 151 .chan_flags = UMC_CHAN_F_ECC_EN, 152 .chan_fabid = 2, 153 .chan_instid = 2, 154 .chan_logid = 2, 155 .chan_nrules = 1, 156 .chan_rules = { { 157 .ddr_flags = DF_DRAM_F_VALID | 158 DF_DRAM_F_HASH_16_18 | 159 DF_DRAM_F_HASH_21_23 | 160 DF_DRAM_F_HASH_30_32, 161 .ddr_base = 0, 162 .ddr_limit = 256ULL * 1024ULL * 1024ULL * 163 1024ULL, 164 .ddr_dest_fabid = 0, 165 .ddr_sock_ileave_bits = 1, 166 .ddr_die_ileave_bits = 0, 167 .ddr_addr_start = 9, 168 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS1_8CH 169 } }, 170 .chan_dimms = { { 171 .ud_flags = UMC_DIMM_F_VALID, 172 .ud_width = UMC_DIMM_W_X4, 173 .ud_type = UMC_DIMM_T_DDR5, 174 .ud_kind = UMC_DIMM_K_RDIMM, 175 .ud_dimmno = 0, 176 .ud_cs = { { 177 .ucs_base = { 178 .udb_base = 0, 179 .udb_valid = B_TRUE 180 }, 181 .ucs_base_mask = 0x3ffffffff, 182 .ucs_nbanks = 0x5, 183 .ucs_ncol = 0xa, 184 .ucs_nrow_lo = 0x10, 185 .ucs_nbank_groups = 0x3, 186 .ucs_row_low_bit = 0x12, 187 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 188 0xe }, 189 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 190 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 191 .ucs_subchan = 0x6 192 } } 193 } }, 194 }, { 195 .chan_flags = UMC_CHAN_F_ECC_EN, 196 .chan_fabid = 3, 197 .chan_instid = 3, 198 .chan_logid = 3, 199 .chan_nrules = 1, 200 .chan_rules = { { 201 .ddr_flags = DF_DRAM_F_VALID | 202 DF_DRAM_F_HASH_16_18 | 203 DF_DRAM_F_HASH_21_23 | 204 DF_DRAM_F_HASH_30_32, 205 .ddr_base = 0, 206 .ddr_limit = 256ULL * 1024ULL * 1024ULL * 207 1024ULL, 208 .ddr_dest_fabid = 0, 209 .ddr_sock_ileave_bits = 1, 210 .ddr_die_ileave_bits = 0, 211 .ddr_addr_start = 9, 212 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS1_8CH 213 } }, 214 .chan_dimms = { { 215 .ud_flags = UMC_DIMM_F_VALID, 216 .ud_width = UMC_DIMM_W_X4, 217 .ud_type = UMC_DIMM_T_DDR5, 218 .ud_kind = UMC_DIMM_K_RDIMM, 219 .ud_dimmno = 0, 220 .ud_cs = { { 221 .ucs_base = { 222 .udb_base = 0, 223 .udb_valid = B_TRUE 224 }, 225 .ucs_base_mask = 0x3ffffffff, 226 .ucs_nbanks = 0x5, 227 .ucs_ncol = 0xa, 228 .ucs_nrow_lo = 0x10, 229 .ucs_nbank_groups = 0x3, 230 .ucs_row_low_bit = 0x12, 231 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 232 0xe }, 233 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 234 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 235 .ucs_subchan = 0x6 236 } } 237 } }, 238 }, { 239 .chan_flags = UMC_CHAN_F_ECC_EN, 240 .chan_fabid = 4, 241 .chan_instid = 4, 242 .chan_logid = 4, 243 .chan_nrules = 1, 244 .chan_rules = { { 245 .ddr_flags = DF_DRAM_F_VALID | 246 DF_DRAM_F_HASH_16_18 | 247 DF_DRAM_F_HASH_21_23 | 248 DF_DRAM_F_HASH_30_32, 249 .ddr_base = 0, 250 .ddr_limit = 256ULL * 1024ULL * 1024ULL * 251 1024ULL, 252 .ddr_dest_fabid = 0, 253 .ddr_sock_ileave_bits = 1, 254 .ddr_die_ileave_bits = 0, 255 .ddr_addr_start = 9, 256 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS1_8CH 257 } }, 258 .chan_dimms = { { 259 .ud_flags = UMC_DIMM_F_VALID, 260 .ud_width = UMC_DIMM_W_X4, 261 .ud_type = UMC_DIMM_T_DDR5, 262 .ud_kind = UMC_DIMM_K_RDIMM, 263 .ud_dimmno = 0, 264 .ud_cs = { { 265 .ucs_base = { 266 .udb_base = 0, 267 .udb_valid = B_TRUE 268 }, 269 .ucs_base_mask = 0x3ffffffff, 270 .ucs_nbanks = 0x5, 271 .ucs_ncol = 0xa, 272 .ucs_nrow_lo = 0x10, 273 .ucs_nbank_groups = 0x3, 274 .ucs_row_low_bit = 0x12, 275 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 276 0xe }, 277 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 278 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 279 .ucs_subchan = 0x6 280 } } 281 } }, 282 }, { 283 .chan_flags = UMC_CHAN_F_ECC_EN, 284 .chan_fabid = 5, 285 .chan_instid = 5, 286 .chan_logid = 5, 287 .chan_nrules = 1, 288 .chan_rules = { { 289 .ddr_flags = DF_DRAM_F_VALID | 290 DF_DRAM_F_HASH_16_18 | 291 DF_DRAM_F_HASH_21_23 | 292 DF_DRAM_F_HASH_30_32, 293 .ddr_base = 0, 294 .ddr_limit = 256ULL * 1024ULL * 1024ULL * 295 1024ULL, 296 .ddr_dest_fabid = 0, 297 .ddr_sock_ileave_bits = 1, 298 .ddr_die_ileave_bits = 0, 299 .ddr_addr_start = 9, 300 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS1_8CH 301 } }, 302 .chan_dimms = { { 303 .ud_flags = UMC_DIMM_F_VALID, 304 .ud_width = UMC_DIMM_W_X4, 305 .ud_type = UMC_DIMM_T_DDR5, 306 .ud_kind = UMC_DIMM_K_RDIMM, 307 .ud_dimmno = 0, 308 .ud_cs = { { 309 .ucs_base = { 310 .udb_base = 0, 311 .udb_valid = B_TRUE 312 }, 313 .ucs_base_mask = 0x3ffffffff, 314 .ucs_nbanks = 0x5, 315 .ucs_ncol = 0xa, 316 .ucs_nrow_lo = 0x10, 317 .ucs_nbank_groups = 0x3, 318 .ucs_row_low_bit = 0x12, 319 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 320 0xe }, 321 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 322 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 323 .ucs_subchan = 0x6 324 } } 325 } }, 326 }, { 327 .chan_flags = UMC_CHAN_F_ECC_EN, 328 .chan_fabid = 6, 329 .chan_instid = 6, 330 .chan_logid = 6, 331 .chan_nrules = 1, 332 .chan_rules = { { 333 .ddr_flags = DF_DRAM_F_VALID | 334 DF_DRAM_F_HASH_16_18 | 335 DF_DRAM_F_HASH_21_23 | 336 DF_DRAM_F_HASH_30_32, 337 .ddr_base = 0, 338 .ddr_limit = 256ULL * 1024ULL * 1024ULL * 339 1024ULL, 340 .ddr_dest_fabid = 0, 341 .ddr_sock_ileave_bits = 1, 342 .ddr_die_ileave_bits = 0, 343 .ddr_addr_start = 9, 344 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS1_8CH 345 } }, 346 .chan_dimms = { { 347 .ud_flags = UMC_DIMM_F_VALID, 348 .ud_width = UMC_DIMM_W_X4, 349 .ud_type = UMC_DIMM_T_DDR5, 350 .ud_kind = UMC_DIMM_K_RDIMM, 351 .ud_dimmno = 0, 352 .ud_cs = { { 353 .ucs_base = { 354 .udb_base = 0, 355 .udb_valid = B_TRUE 356 }, 357 .ucs_base_mask = 0x3ffffffff, 358 .ucs_nbanks = 0x5, 359 .ucs_ncol = 0xa, 360 .ucs_nrow_lo = 0x10, 361 .ucs_nbank_groups = 0x3, 362 .ucs_row_low_bit = 0x12, 363 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 364 0xe }, 365 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 366 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 367 .ucs_subchan = 0x6 368 } } 369 } }, 370 }, { 371 .chan_flags = UMC_CHAN_F_ECC_EN, 372 .chan_fabid = 7, 373 .chan_instid = 7, 374 .chan_logid = 7, 375 .chan_nrules = 1, 376 .chan_rules = { { 377 .ddr_flags = DF_DRAM_F_VALID | 378 DF_DRAM_F_HASH_16_18 | 379 DF_DRAM_F_HASH_21_23 | 380 DF_DRAM_F_HASH_30_32, 381 .ddr_base = 0, 382 .ddr_limit = 256ULL * 1024ULL * 1024ULL * 383 1024ULL, 384 .ddr_dest_fabid = 0, 385 .ddr_sock_ileave_bits = 1, 386 .ddr_die_ileave_bits = 0, 387 .ddr_addr_start = 9, 388 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS1_8CH 389 } }, 390 .chan_dimms = { { 391 .ud_flags = UMC_DIMM_F_VALID, 392 .ud_width = UMC_DIMM_W_X4, 393 .ud_type = UMC_DIMM_T_DDR5, 394 .ud_kind = UMC_DIMM_K_RDIMM, 395 .ud_dimmno = 0, 396 .ud_cs = { { 397 .ucs_base = { 398 .udb_base = 0, 399 .udb_valid = B_TRUE 400 }, 401 .ucs_base_mask = 0x3ffffffff, 402 .ucs_nbanks = 0x5, 403 .ucs_ncol = 0xa, 404 .ucs_nrow_lo = 0x10, 405 .ucs_nbank_groups = 0x3, 406 .ucs_row_low_bit = 0x12, 407 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 408 0xe }, 409 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 410 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 411 .ucs_subchan = 0x6 412 } } 413 } }, 414 } } 415 }, { 416 .zud_dfno = 1, 417 .zud_dram_nrules = 2, 418 .zud_nchan = 8, 419 .zud_cs_nremap = 0, 420 .zud_hole_base = 0, 421 .zud_rules = { { 422 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_HASH_16_18 | 423 DF_DRAM_F_HASH_21_23 | DF_DRAM_F_HASH_30_32, 424 .ddr_base = 0, 425 .ddr_limit = 256ULL * 1024ULL * 1024ULL * 1024ULL, 426 .ddr_dest_fabid = 0, 427 .ddr_sock_ileave_bits = 1, 428 .ddr_die_ileave_bits = 0, 429 .ddr_addr_start = 9, 430 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS1_8CH 431 } }, 432 .zud_chan = { { 433 .chan_flags = UMC_CHAN_F_ECC_EN, 434 .chan_fabid = 0x20, 435 .chan_instid = 0, 436 .chan_logid = 0, 437 .chan_nrules = 1, 438 .chan_rules = { { 439 .ddr_flags = DF_DRAM_F_VALID | 440 DF_DRAM_F_HASH_16_18 | 441 DF_DRAM_F_HASH_21_23 | 442 DF_DRAM_F_HASH_30_32, 443 .ddr_base = 0, 444 .ddr_limit = 256ULL * 1024ULL * 1024ULL * 445 1024ULL, 446 .ddr_dest_fabid = 0, 447 .ddr_sock_ileave_bits = 1, 448 .ddr_die_ileave_bits = 0, 449 .ddr_addr_start = 9, 450 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS1_8CH 451 } }, 452 .chan_dimms = { { 453 .ud_flags = UMC_DIMM_F_VALID, 454 .ud_width = UMC_DIMM_W_X4, 455 .ud_type = UMC_DIMM_T_DDR5, 456 .ud_kind = UMC_DIMM_K_RDIMM, 457 .ud_dimmno = 0, 458 .ud_cs = { { 459 .ucs_base = { 460 .udb_base = 0, 461 .udb_valid = B_TRUE 462 }, 463 .ucs_base_mask = 0x3ffffffff, 464 .ucs_nbanks = 0x5, 465 .ucs_ncol = 0xa, 466 .ucs_nrow_lo = 0x10, 467 .ucs_nbank_groups = 0x3, 468 .ucs_row_low_bit = 0x12, 469 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 470 0xe }, 471 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 472 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 473 .ucs_subchan = 0x6 474 } } 475 } }, 476 }, { 477 .chan_flags = UMC_CHAN_F_ECC_EN, 478 .chan_fabid = 0x21, 479 .chan_instid = 1, 480 .chan_logid = 1, 481 .chan_nrules = 1, 482 .chan_rules = { { 483 .ddr_flags = DF_DRAM_F_VALID | 484 DF_DRAM_F_HASH_16_18 | 485 DF_DRAM_F_HASH_21_23 | 486 DF_DRAM_F_HASH_30_32, 487 .ddr_base = 0, 488 .ddr_limit = 256ULL * 1024ULL * 1024ULL * 489 1024ULL, 490 .ddr_dest_fabid = 0, 491 .ddr_sock_ileave_bits = 1, 492 .ddr_die_ileave_bits = 0, 493 .ddr_addr_start = 9, 494 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS1_8CH 495 } }, 496 .chan_dimms = { { 497 .ud_flags = UMC_DIMM_F_VALID, 498 .ud_width = UMC_DIMM_W_X4, 499 .ud_type = UMC_DIMM_T_DDR5, 500 .ud_kind = UMC_DIMM_K_RDIMM, 501 .ud_dimmno = 0, 502 .ud_cs = { { 503 .ucs_base = { 504 .udb_base = 0, 505 .udb_valid = B_TRUE 506 }, 507 .ucs_base_mask = 0x3ffffffff, 508 .ucs_nbanks = 0x5, 509 .ucs_ncol = 0xa, 510 .ucs_nrow_lo = 0x10, 511 .ucs_nbank_groups = 0x3, 512 .ucs_row_low_bit = 0x12, 513 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 514 0xe }, 515 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 516 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 517 .ucs_subchan = 0x6 518 } } 519 } }, 520 }, { 521 .chan_flags = UMC_CHAN_F_ECC_EN, 522 .chan_fabid = 0x22, 523 .chan_instid = 2, 524 .chan_logid = 2, 525 .chan_nrules = 1, 526 .chan_rules = { { 527 .ddr_flags = DF_DRAM_F_VALID | 528 DF_DRAM_F_HASH_16_18 | 529 DF_DRAM_F_HASH_21_23 | 530 DF_DRAM_F_HASH_30_32, 531 .ddr_base = 0, 532 .ddr_limit = 256ULL * 1024ULL * 1024ULL * 533 1024ULL, 534 .ddr_dest_fabid = 0, 535 .ddr_sock_ileave_bits = 1, 536 .ddr_die_ileave_bits = 0, 537 .ddr_addr_start = 9, 538 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS1_8CH 539 } }, 540 .chan_dimms = { { 541 .ud_flags = UMC_DIMM_F_VALID, 542 .ud_width = UMC_DIMM_W_X4, 543 .ud_type = UMC_DIMM_T_DDR5, 544 .ud_kind = UMC_DIMM_K_RDIMM, 545 .ud_dimmno = 0, 546 .ud_cs = { { 547 .ucs_base = { 548 .udb_base = 0, 549 .udb_valid = B_TRUE 550 }, 551 .ucs_base_mask = 0x3ffffffff, 552 .ucs_nbanks = 0x5, 553 .ucs_ncol = 0xa, 554 .ucs_nrow_lo = 0x10, 555 .ucs_nbank_groups = 0x3, 556 .ucs_row_low_bit = 0x12, 557 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 558 0xe }, 559 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 560 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 561 .ucs_subchan = 0x6 562 } } 563 } }, 564 }, { 565 .chan_flags = UMC_CHAN_F_ECC_EN, 566 .chan_fabid = 0x23, 567 .chan_instid = 3, 568 .chan_logid = 3, 569 .chan_nrules = 1, 570 .chan_rules = { { 571 .ddr_flags = DF_DRAM_F_VALID | 572 DF_DRAM_F_HASH_16_18 | 573 DF_DRAM_F_HASH_21_23 | 574 DF_DRAM_F_HASH_30_32, 575 .ddr_base = 0, 576 .ddr_limit = 256ULL * 1024ULL * 1024ULL * 577 1024ULL, 578 .ddr_dest_fabid = 0, 579 .ddr_sock_ileave_bits = 1, 580 .ddr_die_ileave_bits = 0, 581 .ddr_addr_start = 9, 582 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS1_8CH 583 } }, 584 .chan_dimms = { { 585 .ud_flags = UMC_DIMM_F_VALID, 586 .ud_width = UMC_DIMM_W_X4, 587 .ud_type = UMC_DIMM_T_DDR5, 588 .ud_kind = UMC_DIMM_K_RDIMM, 589 .ud_dimmno = 0, 590 .ud_cs = { { 591 .ucs_base = { 592 .udb_base = 0, 593 .udb_valid = B_TRUE 594 }, 595 .ucs_base_mask = 0x3ffffffff, 596 .ucs_nbanks = 0x5, 597 .ucs_ncol = 0xa, 598 .ucs_nrow_lo = 0x10, 599 .ucs_nbank_groups = 0x3, 600 .ucs_row_low_bit = 0x12, 601 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 602 0xe }, 603 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 604 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 605 .ucs_subchan = 0x6 606 } } 607 } }, 608 }, { 609 .chan_flags = UMC_CHAN_F_ECC_EN, 610 .chan_fabid = 0x24, 611 .chan_instid = 4, 612 .chan_logid = 4, 613 .chan_nrules = 1, 614 .chan_rules = { { 615 .ddr_flags = DF_DRAM_F_VALID | 616 DF_DRAM_F_HASH_16_18 | 617 DF_DRAM_F_HASH_21_23 | 618 DF_DRAM_F_HASH_30_32, 619 .ddr_base = 0, 620 .ddr_limit = 256ULL * 1024ULL * 1024ULL * 621 1024ULL, 622 .ddr_dest_fabid = 0, 623 .ddr_sock_ileave_bits = 1, 624 .ddr_die_ileave_bits = 0, 625 .ddr_addr_start = 9, 626 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS1_8CH 627 } }, 628 .chan_dimms = { { 629 .ud_flags = UMC_DIMM_F_VALID, 630 .ud_width = UMC_DIMM_W_X4, 631 .ud_type = UMC_DIMM_T_DDR5, 632 .ud_kind = UMC_DIMM_K_RDIMM, 633 .ud_dimmno = 0, 634 .ud_cs = { { 635 .ucs_base = { 636 .udb_base = 0, 637 .udb_valid = B_TRUE 638 }, 639 .ucs_base_mask = 0x3ffffffff, 640 .ucs_nbanks = 0x5, 641 .ucs_ncol = 0xa, 642 .ucs_nrow_lo = 0x10, 643 .ucs_nbank_groups = 0x3, 644 .ucs_row_low_bit = 0x12, 645 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 646 0xe }, 647 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 648 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 649 .ucs_subchan = 0x6 650 } } 651 } }, 652 }, { 653 .chan_flags = UMC_CHAN_F_ECC_EN, 654 .chan_fabid = 0x25, 655 .chan_instid = 5, 656 .chan_logid = 5, 657 .chan_nrules = 1, 658 .chan_rules = { { 659 .ddr_flags = DF_DRAM_F_VALID | 660 DF_DRAM_F_HASH_16_18 | 661 DF_DRAM_F_HASH_21_23 | 662 DF_DRAM_F_HASH_30_32, 663 .ddr_base = 0, 664 .ddr_limit = 256ULL * 1024ULL * 1024ULL * 665 1024ULL, 666 .ddr_dest_fabid = 0, 667 .ddr_sock_ileave_bits = 1, 668 .ddr_die_ileave_bits = 0, 669 .ddr_addr_start = 9, 670 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS1_8CH 671 } }, 672 .chan_dimms = { { 673 .ud_flags = UMC_DIMM_F_VALID, 674 .ud_width = UMC_DIMM_W_X4, 675 .ud_type = UMC_DIMM_T_DDR5, 676 .ud_kind = UMC_DIMM_K_RDIMM, 677 .ud_dimmno = 0, 678 .ud_cs = { { 679 .ucs_base = { 680 .udb_base = 0, 681 .udb_valid = B_TRUE 682 }, 683 .ucs_base_mask = 0x3ffffffff, 684 .ucs_nbanks = 0x5, 685 .ucs_ncol = 0xa, 686 .ucs_nrow_lo = 0x10, 687 .ucs_nbank_groups = 0x3, 688 .ucs_row_low_bit = 0x12, 689 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 690 0xe }, 691 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 692 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 693 .ucs_subchan = 0x6 694 } } 695 } }, 696 }, { 697 .chan_flags = UMC_CHAN_F_ECC_EN, 698 .chan_fabid = 0x26, 699 .chan_instid = 6, 700 .chan_logid = 6, 701 .chan_nrules = 1, 702 .chan_rules = { { 703 .ddr_flags = DF_DRAM_F_VALID | 704 DF_DRAM_F_HASH_16_18 | 705 DF_DRAM_F_HASH_21_23 | 706 DF_DRAM_F_HASH_30_32, 707 .ddr_base = 0, 708 .ddr_limit = 256ULL * 1024ULL * 1024ULL * 709 1024ULL, 710 .ddr_dest_fabid = 0, 711 .ddr_sock_ileave_bits = 1, 712 .ddr_die_ileave_bits = 0, 713 .ddr_addr_start = 9, 714 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS1_8CH 715 } }, 716 .chan_dimms = { { 717 .ud_flags = UMC_DIMM_F_VALID, 718 .ud_width = UMC_DIMM_W_X4, 719 .ud_type = UMC_DIMM_T_DDR5, 720 .ud_kind = UMC_DIMM_K_RDIMM, 721 .ud_dimmno = 0, 722 .ud_cs = { { 723 .ucs_base = { 724 .udb_base = 0, 725 .udb_valid = B_TRUE 726 }, 727 .ucs_base_mask = 0x3ffffffff, 728 .ucs_nbanks = 0x5, 729 .ucs_ncol = 0xa, 730 .ucs_nrow_lo = 0x10, 731 .ucs_nbank_groups = 0x3, 732 .ucs_row_low_bit = 0x12, 733 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 734 0xe }, 735 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 736 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 737 .ucs_subchan = 0x6 738 } } 739 } }, 740 }, { 741 .chan_flags = UMC_CHAN_F_ECC_EN, 742 .chan_fabid = 0x27, 743 .chan_instid = 7, 744 .chan_logid = 7, 745 .chan_nrules = 1, 746 .chan_rules = { { 747 .ddr_flags = DF_DRAM_F_VALID | 748 DF_DRAM_F_HASH_16_18 | 749 DF_DRAM_F_HASH_21_23 | 750 DF_DRAM_F_HASH_30_32, 751 .ddr_base = 0, 752 .ddr_limit = 256ULL * 1024ULL * 1024ULL * 753 1024ULL, 754 .ddr_dest_fabid = 0, 755 .ddr_sock_ileave_bits = 1, 756 .ddr_die_ileave_bits = 0, 757 .ddr_addr_start = 9, 758 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS1_8CH 759 } }, 760 .chan_dimms = { { 761 .ud_flags = UMC_DIMM_F_VALID, 762 .ud_width = UMC_DIMM_W_X4, 763 .ud_type = UMC_DIMM_T_DDR5, 764 .ud_kind = UMC_DIMM_K_RDIMM, 765 .ud_dimmno = 0, 766 .ud_cs = { { 767 .ucs_base = { 768 .udb_base = 0, 769 .udb_valid = B_TRUE 770 }, 771 .ucs_base_mask = 0x3ffffffff, 772 .ucs_nbanks = 0x5, 773 .ucs_ncol = 0xa, 774 .ucs_nrow_lo = 0x10, 775 .ucs_nbank_groups = 0x3, 776 .ucs_row_low_bit = 0x12, 777 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 778 0xe }, 779 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 780 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 781 .ucs_subchan = 0x6 782 } } 783 } }, 784 } } 785 } } 786 }; 787 788 /* 789 * Here we switch back to a 1P 2-channel configuration so we can test how things 790 * change with the extra bit that is now included since we're not hashing the 791 * socket. 792 */ 793 static const zen_umc_t zen_umc_nps2_1p = { 794 .umc_tom = 4ULL * 1024ULL * 1024ULL * 1024ULL, 795 .umc_tom2 = 32ULL * 1024ULL * 1024ULL * 1024ULL, 796 .umc_df_rev = DF_REV_4, 797 .umc_decomp = { 798 .dfd_sock_mask = 0x01, 799 .dfd_die_mask = 0x00, 800 .dfd_node_mask = 0x20, 801 .dfd_comp_mask = 0x1f, 802 .dfd_sock_shift = 0, 803 .dfd_die_shift = 0, 804 .dfd_node_shift = 5, 805 .dfd_comp_shift = 0 806 }, 807 .umc_ndfs = 1, 808 .umc_dfs = { { 809 .zud_dfno = 0, 810 .zud_dram_nrules = 1, 811 .zud_nchan = 2, 812 .zud_cs_nremap = 0, 813 .zud_hole_base = 0, 814 .zud_rules = { { 815 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_HASH_16_18 | 816 DF_DRAM_F_HASH_21_23 | DF_DRAM_F_HASH_30_32, 817 .ddr_base = 0, 818 .ddr_limit = 32ULL * 1024ULL * 1024ULL * 1024ULL, 819 .ddr_dest_fabid = 0, 820 .ddr_sock_ileave_bits = 0, 821 .ddr_die_ileave_bits = 0, 822 .ddr_addr_start = 9, 823 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS4_2CH 824 } }, 825 .zud_chan = { { 826 .chan_flags = UMC_CHAN_F_ECC_EN, 827 .chan_fabid = 0, 828 .chan_instid = 0, 829 .chan_logid = 0, 830 .chan_nrules = 1, 831 .chan_rules = { { 832 .ddr_flags = DF_DRAM_F_VALID | 833 DF_DRAM_F_HASH_16_18 | 834 DF_DRAM_F_HASH_21_23 | 835 DF_DRAM_F_HASH_30_32, 836 .ddr_base = 0, 837 .ddr_limit = 32ULL * 1024ULL * 1024ULL * 838 1024ULL, 839 .ddr_dest_fabid = 0, 840 .ddr_sock_ileave_bits = 0, 841 .ddr_die_ileave_bits = 0, 842 .ddr_addr_start = 9, 843 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS4_2CH 844 } }, 845 .chan_dimms = { { 846 .ud_flags = UMC_DIMM_F_VALID, 847 .ud_width = UMC_DIMM_W_X4, 848 .ud_type = UMC_DIMM_T_DDR5, 849 .ud_kind = UMC_DIMM_K_RDIMM, 850 .ud_dimmno = 0, 851 .ud_cs = { { 852 .ucs_base = { 853 .udb_base = 0, 854 .udb_valid = B_TRUE 855 }, 856 .ucs_base_mask = 0x3ffffffff, 857 .ucs_nbanks = 0x5, 858 .ucs_ncol = 0xa, 859 .ucs_nrow_lo = 0x10, 860 .ucs_nbank_groups = 0x3, 861 .ucs_row_low_bit = 0x12, 862 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 863 0xe }, 864 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 865 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 866 .ucs_subchan = 0x6 867 } } 868 } }, 869 }, { 870 .chan_flags = UMC_CHAN_F_ECC_EN, 871 .chan_fabid = 1, 872 .chan_instid = 1, 873 .chan_logid = 1, 874 .chan_nrules = 1, 875 .chan_rules = { { 876 .ddr_flags = DF_DRAM_F_VALID | 877 DF_DRAM_F_HASH_16_18 | 878 DF_DRAM_F_HASH_21_23 | 879 DF_DRAM_F_HASH_30_32, 880 .ddr_base = 0, 881 .ddr_limit = 32ULL * 1024ULL * 1024ULL * 882 1024ULL, 883 .ddr_dest_fabid = 0, 884 .ddr_sock_ileave_bits = 0, 885 .ddr_die_ileave_bits = 0, 886 .ddr_addr_start = 9, 887 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS4_2CH 888 } }, 889 .chan_dimms = { { 890 .ud_flags = UMC_DIMM_F_VALID, 891 .ud_width = UMC_DIMM_W_X4, 892 .ud_type = UMC_DIMM_T_DDR5, 893 .ud_kind = UMC_DIMM_K_RDIMM, 894 .ud_dimmno = 0, 895 .ud_cs = { { 896 .ucs_base = { 897 .udb_base = 0, 898 .udb_valid = B_TRUE 899 }, 900 .ucs_base_mask = 0x3ffffffff, 901 .ucs_nbanks = 0x5, 902 .ucs_ncol = 0xa, 903 .ucs_nrow_lo = 0x10, 904 .ucs_nbank_groups = 0x3, 905 .ucs_row_low_bit = 0x12, 906 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 907 0xe }, 908 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 909 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 910 .ucs_subchan = 0x6 911 } } 912 } }, 913 } } 914 } } 915 }; 916 917 /* 918 * This here is a five-channel version, giving us some of our favorite non-power 919 * of 2 cases. 920 */ 921 static const zen_umc_t zen_umc_nps5_1p = { 922 .umc_tom = 4ULL * 1024ULL * 1024ULL * 1024ULL, 923 .umc_tom2 = 80ULL * 1024ULL * 1024ULL * 1024ULL, 924 .umc_df_rev = DF_REV_4, 925 .umc_decomp = { 926 .dfd_sock_mask = 0x01, 927 .dfd_die_mask = 0x00, 928 .dfd_node_mask = 0x20, 929 .dfd_comp_mask = 0x1f, 930 .dfd_sock_shift = 0, 931 .dfd_die_shift = 0, 932 .dfd_node_shift = 5, 933 .dfd_comp_shift = 0 934 }, 935 .umc_ndfs = 1, 936 .umc_dfs = { { 937 .zud_dfno = 0, 938 .zud_dram_nrules = 1, 939 .zud_nchan = 5, 940 .zud_cs_nremap = 0, 941 .zud_hole_base = 0, 942 .zud_rules = { { 943 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_HASH_16_18 | 944 DF_DRAM_F_HASH_21_23 | DF_DRAM_F_HASH_30_32, 945 .ddr_base = 0, 946 .ddr_limit = 80ULL * 1024ULL * 1024ULL * 1024ULL, 947 .ddr_dest_fabid = 0, 948 .ddr_sock_ileave_bits = 0, 949 .ddr_die_ileave_bits = 0, 950 .ddr_addr_start = 8, 951 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS2_5CH 952 } }, 953 .zud_chan = { { 954 .chan_flags = UMC_CHAN_F_ECC_EN, 955 .chan_fabid = 0, 956 .chan_instid = 0, 957 .chan_logid = 0, 958 .chan_nrules = 1, 959 .chan_rules = { { 960 .ddr_flags = DF_DRAM_F_VALID | 961 DF_DRAM_F_HASH_16_18 | 962 DF_DRAM_F_HASH_21_23 | 963 DF_DRAM_F_HASH_30_32, 964 .ddr_base = 0, 965 .ddr_limit = 80ULL * 1024ULL * 1024ULL * 966 1024ULL, 967 .ddr_dest_fabid = 0, 968 .ddr_sock_ileave_bits = 0, 969 .ddr_die_ileave_bits = 0, 970 .ddr_addr_start = 8, 971 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS2_5CH 972 } }, 973 .chan_dimms = { { 974 .ud_flags = UMC_DIMM_F_VALID, 975 .ud_width = UMC_DIMM_W_X4, 976 .ud_type = UMC_DIMM_T_DDR5, 977 .ud_kind = UMC_DIMM_K_RDIMM, 978 .ud_dimmno = 0, 979 .ud_cs = { { 980 .ucs_base = { 981 .udb_base = 0, 982 .udb_valid = B_TRUE 983 }, 984 .ucs_base_mask = 0x3ffffffff, 985 .ucs_nbanks = 0x5, 986 .ucs_ncol = 0xa, 987 .ucs_nrow_lo = 0x10, 988 .ucs_nbank_groups = 0x3, 989 .ucs_row_low_bit = 0x12, 990 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 991 0xe }, 992 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 993 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 994 .ucs_subchan = 0x6 995 } } 996 } }, 997 }, { 998 .chan_flags = UMC_CHAN_F_ECC_EN, 999 .chan_fabid = 1, 1000 .chan_instid = 1, 1001 .chan_logid = 1, 1002 .chan_nrules = 1, 1003 .chan_rules = { { 1004 .ddr_flags = DF_DRAM_F_VALID | 1005 DF_DRAM_F_HASH_16_18 | 1006 DF_DRAM_F_HASH_21_23 | 1007 DF_DRAM_F_HASH_30_32, 1008 .ddr_base = 0, 1009 .ddr_limit = 80ULL * 1024ULL * 1024ULL * 1010 1024ULL, 1011 .ddr_dest_fabid = 0, 1012 .ddr_sock_ileave_bits = 0, 1013 .ddr_die_ileave_bits = 0, 1014 .ddr_addr_start = 8, 1015 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS2_5CH 1016 } }, 1017 .chan_dimms = { { 1018 .ud_flags = UMC_DIMM_F_VALID, 1019 .ud_width = UMC_DIMM_W_X4, 1020 .ud_type = UMC_DIMM_T_DDR5, 1021 .ud_kind = UMC_DIMM_K_RDIMM, 1022 .ud_dimmno = 0, 1023 .ud_cs = { { 1024 .ucs_base = { 1025 .udb_base = 0, 1026 .udb_valid = B_TRUE 1027 }, 1028 .ucs_base_mask = 0x3ffffffff, 1029 .ucs_nbanks = 0x5, 1030 .ucs_ncol = 0xa, 1031 .ucs_nrow_lo = 0x10, 1032 .ucs_nbank_groups = 0x3, 1033 .ucs_row_low_bit = 0x12, 1034 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 1035 0xe }, 1036 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 1037 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 1038 .ucs_subchan = 0x6 1039 } } 1040 } }, 1041 }, { 1042 .chan_flags = UMC_CHAN_F_ECC_EN, 1043 .chan_fabid = 2, 1044 .chan_instid = 2, 1045 .chan_logid = 2, 1046 .chan_nrules = 1, 1047 .chan_rules = { { 1048 .ddr_flags = DF_DRAM_F_VALID | 1049 DF_DRAM_F_HASH_16_18 | 1050 DF_DRAM_F_HASH_21_23 | 1051 DF_DRAM_F_HASH_30_32, 1052 .ddr_base = 0, 1053 .ddr_limit = 80ULL * 1024ULL * 1024ULL * 1054 1024ULL, 1055 .ddr_dest_fabid = 0, 1056 .ddr_sock_ileave_bits = 0, 1057 .ddr_die_ileave_bits = 0, 1058 .ddr_addr_start = 8, 1059 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS2_5CH 1060 } }, 1061 .chan_dimms = { { 1062 .ud_flags = UMC_DIMM_F_VALID, 1063 .ud_width = UMC_DIMM_W_X4, 1064 .ud_type = UMC_DIMM_T_DDR5, 1065 .ud_kind = UMC_DIMM_K_RDIMM, 1066 .ud_dimmno = 0, 1067 .ud_cs = { { 1068 .ucs_base = { 1069 .udb_base = 0, 1070 .udb_valid = B_TRUE 1071 }, 1072 .ucs_base_mask = 0x3ffffffff, 1073 .ucs_nbanks = 0x5, 1074 .ucs_ncol = 0xa, 1075 .ucs_nrow_lo = 0x10, 1076 .ucs_nbank_groups = 0x3, 1077 .ucs_row_low_bit = 0x12, 1078 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 1079 0xe }, 1080 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 1081 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 1082 .ucs_subchan = 0x6 1083 } } 1084 } }, 1085 }, { 1086 .chan_flags = UMC_CHAN_F_ECC_EN, 1087 .chan_fabid = 3, 1088 .chan_instid = 3, 1089 .chan_logid = 3, 1090 .chan_nrules = 1, 1091 .chan_rules = { { 1092 .ddr_flags = DF_DRAM_F_VALID | 1093 DF_DRAM_F_HASH_16_18 | 1094 DF_DRAM_F_HASH_21_23 | 1095 DF_DRAM_F_HASH_30_32, 1096 .ddr_base = 0, 1097 .ddr_limit = 80ULL * 1024ULL * 1024ULL * 1098 1024ULL, 1099 .ddr_dest_fabid = 0, 1100 .ddr_sock_ileave_bits = 0, 1101 .ddr_die_ileave_bits = 0, 1102 .ddr_addr_start = 8, 1103 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS2_5CH 1104 } }, 1105 .chan_dimms = { { 1106 .ud_flags = UMC_DIMM_F_VALID, 1107 .ud_width = UMC_DIMM_W_X4, 1108 .ud_type = UMC_DIMM_T_DDR5, 1109 .ud_kind = UMC_DIMM_K_RDIMM, 1110 .ud_dimmno = 0, 1111 .ud_cs = { { 1112 .ucs_base = { 1113 .udb_base = 0, 1114 .udb_valid = B_TRUE 1115 }, 1116 .ucs_base_mask = 0x3ffffffff, 1117 .ucs_nbanks = 0x5, 1118 .ucs_ncol = 0xa, 1119 .ucs_nrow_lo = 0x10, 1120 .ucs_nbank_groups = 0x3, 1121 .ucs_row_low_bit = 0x12, 1122 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 1123 0xe }, 1124 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 1125 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 1126 .ucs_subchan = 0x6 1127 } } 1128 } }, 1129 }, { 1130 .chan_flags = UMC_CHAN_F_ECC_EN, 1131 .chan_fabid = 4, 1132 .chan_instid = 4, 1133 .chan_logid = 4, 1134 .chan_nrules = 1, 1135 .chan_rules = { { 1136 .ddr_flags = DF_DRAM_F_VALID | 1137 DF_DRAM_F_HASH_16_18 | 1138 DF_DRAM_F_HASH_21_23 | 1139 DF_DRAM_F_HASH_30_32, 1140 .ddr_base = 0, 1141 .ddr_limit = 80ULL * 1024ULL * 1024ULL * 1142 1024ULL, 1143 .ddr_dest_fabid = 0, 1144 .ddr_sock_ileave_bits = 0, 1145 .ddr_die_ileave_bits = 0, 1146 .ddr_addr_start = 8, 1147 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS2_5CH 1148 } }, 1149 .chan_dimms = { { 1150 .ud_flags = UMC_DIMM_F_VALID, 1151 .ud_width = UMC_DIMM_W_X4, 1152 .ud_type = UMC_DIMM_T_DDR5, 1153 .ud_kind = UMC_DIMM_K_RDIMM, 1154 .ud_dimmno = 0, 1155 .ud_cs = { { 1156 .ucs_base = { 1157 .udb_base = 0, 1158 .udb_valid = B_TRUE 1159 }, 1160 .ucs_base_mask = 0x3ffffffff, 1161 .ucs_nbanks = 0x5, 1162 .ucs_ncol = 0xa, 1163 .ucs_nrow_lo = 0x10, 1164 .ucs_nbank_groups = 0x3, 1165 .ucs_row_low_bit = 0x12, 1166 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 1167 0xe }, 1168 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 1169 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 1170 .ucs_subchan = 0x6 1171 } } 1172 } }, 1173 } } 1174 } } 1175 }; 1176 1177 /* 1178 * And now in 6-channels so we can get the spiciness of the new normalization 1179 * scheme. We've also turned off several of the hash bits on this so we can 1180 * verify that using those middle bits doesn't do anything here. 1181 */ 1182 static const zen_umc_t zen_umc_nps6_1p = { 1183 .umc_tom = 4ULL * 1024ULL * 1024ULL * 1024ULL, 1184 .umc_tom2 = 96ULL * 1024ULL * 1024ULL * 1024ULL, 1185 .umc_df_rev = DF_REV_4, 1186 .umc_decomp = { 1187 .dfd_sock_mask = 0x01, 1188 .dfd_die_mask = 0x00, 1189 .dfd_node_mask = 0x20, 1190 .dfd_comp_mask = 0x1f, 1191 .dfd_sock_shift = 0, 1192 .dfd_die_shift = 0, 1193 .dfd_node_shift = 5, 1194 .dfd_comp_shift = 0 1195 }, 1196 .umc_ndfs = 1, 1197 .umc_dfs = { { 1198 .zud_dfno = 0, 1199 .zud_dram_nrules = 1, 1200 .zud_nchan = 6, 1201 .zud_cs_nremap = 0, 1202 .zud_hole_base = 0, 1203 .zud_rules = { { 1204 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_HASH_30_32, 1205 .ddr_base = 0, 1206 .ddr_limit = 96ULL * 1024ULL * 1024ULL * 1024ULL, 1207 .ddr_dest_fabid = 0, 1208 .ddr_sock_ileave_bits = 0, 1209 .ddr_die_ileave_bits = 0, 1210 .ddr_addr_start = 8, 1211 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS2_6CH 1212 } }, 1213 .zud_chan = { { 1214 .chan_flags = UMC_CHAN_F_ECC_EN, 1215 .chan_fabid = 0, 1216 .chan_instid = 0, 1217 .chan_logid = 0, 1218 .chan_nrules = 1, 1219 .chan_rules = { { 1220 .ddr_flags = DF_DRAM_F_VALID | 1221 DF_DRAM_F_HASH_30_32, 1222 .ddr_base = 0, 1223 .ddr_limit = 96ULL * 1024ULL * 1024ULL * 1224 1024ULL, 1225 .ddr_dest_fabid = 0, 1226 .ddr_sock_ileave_bits = 0, 1227 .ddr_die_ileave_bits = 0, 1228 .ddr_addr_start = 8, 1229 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS2_6CH 1230 } }, 1231 .chan_dimms = { { 1232 .ud_flags = UMC_DIMM_F_VALID, 1233 .ud_width = UMC_DIMM_W_X4, 1234 .ud_type = UMC_DIMM_T_DDR5, 1235 .ud_kind = UMC_DIMM_K_RDIMM, 1236 .ud_dimmno = 0, 1237 .ud_cs = { { 1238 .ucs_base = { 1239 .udb_base = 0, 1240 .udb_valid = B_TRUE 1241 }, 1242 .ucs_base_mask = 0x3ffffffff, 1243 .ucs_nbanks = 0x5, 1244 .ucs_ncol = 0xa, 1245 .ucs_nrow_lo = 0x10, 1246 .ucs_nbank_groups = 0x3, 1247 .ucs_row_low_bit = 0x12, 1248 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 1249 0xe }, 1250 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 1251 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 1252 .ucs_subchan = 0x6 1253 } } 1254 } }, 1255 }, { 1256 .chan_flags = UMC_CHAN_F_ECC_EN, 1257 .chan_fabid = 1, 1258 .chan_instid = 1, 1259 .chan_logid = 1, 1260 .chan_nrules = 1, 1261 .chan_rules = { { 1262 .ddr_flags = DF_DRAM_F_VALID | 1263 DF_DRAM_F_HASH_30_32, 1264 .ddr_base = 0, 1265 .ddr_limit = 96ULL * 1024ULL * 1024ULL * 1266 1024ULL, 1267 .ddr_dest_fabid = 0, 1268 .ddr_sock_ileave_bits = 0, 1269 .ddr_die_ileave_bits = 0, 1270 .ddr_addr_start = 8, 1271 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS2_6CH 1272 } }, 1273 .chan_dimms = { { 1274 .ud_flags = UMC_DIMM_F_VALID, 1275 .ud_width = UMC_DIMM_W_X4, 1276 .ud_type = UMC_DIMM_T_DDR5, 1277 .ud_kind = UMC_DIMM_K_RDIMM, 1278 .ud_dimmno = 0, 1279 .ud_cs = { { 1280 .ucs_base = { 1281 .udb_base = 0, 1282 .udb_valid = B_TRUE 1283 }, 1284 .ucs_base_mask = 0x3ffffffff, 1285 .ucs_nbanks = 0x5, 1286 .ucs_ncol = 0xa, 1287 .ucs_nrow_lo = 0x10, 1288 .ucs_nbank_groups = 0x3, 1289 .ucs_row_low_bit = 0x12, 1290 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 1291 0xe }, 1292 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 1293 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 1294 .ucs_subchan = 0x6 1295 } } 1296 } }, 1297 }, { 1298 .chan_flags = UMC_CHAN_F_ECC_EN, 1299 .chan_fabid = 2, 1300 .chan_instid = 2, 1301 .chan_logid = 2, 1302 .chan_nrules = 1, 1303 .chan_rules = { { 1304 .ddr_flags = DF_DRAM_F_VALID | 1305 DF_DRAM_F_HASH_30_32, 1306 .ddr_base = 0, 1307 .ddr_limit = 96ULL * 1024ULL * 1024ULL * 1308 1024ULL, 1309 .ddr_dest_fabid = 0, 1310 .ddr_sock_ileave_bits = 0, 1311 .ddr_die_ileave_bits = 0, 1312 .ddr_addr_start = 8, 1313 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS2_6CH 1314 } }, 1315 .chan_dimms = { { 1316 .ud_flags = UMC_DIMM_F_VALID, 1317 .ud_width = UMC_DIMM_W_X4, 1318 .ud_type = UMC_DIMM_T_DDR5, 1319 .ud_kind = UMC_DIMM_K_RDIMM, 1320 .ud_dimmno = 0, 1321 .ud_cs = { { 1322 .ucs_base = { 1323 .udb_base = 0, 1324 .udb_valid = B_TRUE 1325 }, 1326 .ucs_base_mask = 0x3ffffffff, 1327 .ucs_nbanks = 0x5, 1328 .ucs_ncol = 0xa, 1329 .ucs_nrow_lo = 0x10, 1330 .ucs_nbank_groups = 0x3, 1331 .ucs_row_low_bit = 0x12, 1332 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 1333 0xe }, 1334 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 1335 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 1336 .ucs_subchan = 0x6 1337 } } 1338 } }, 1339 }, { 1340 .chan_flags = UMC_CHAN_F_ECC_EN, 1341 .chan_fabid = 3, 1342 .chan_instid = 3, 1343 .chan_logid = 3, 1344 .chan_nrules = 1, 1345 .chan_rules = { { 1346 .ddr_flags = DF_DRAM_F_VALID | 1347 DF_DRAM_F_HASH_30_32, 1348 .ddr_base = 0, 1349 .ddr_limit = 96ULL * 1024ULL * 1024ULL * 1350 1024ULL, 1351 .ddr_dest_fabid = 0, 1352 .ddr_sock_ileave_bits = 0, 1353 .ddr_die_ileave_bits = 0, 1354 .ddr_addr_start = 8, 1355 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS2_6CH 1356 } }, 1357 .chan_dimms = { { 1358 .ud_flags = UMC_DIMM_F_VALID, 1359 .ud_width = UMC_DIMM_W_X4, 1360 .ud_type = UMC_DIMM_T_DDR5, 1361 .ud_kind = UMC_DIMM_K_RDIMM, 1362 .ud_dimmno = 0, 1363 .ud_cs = { { 1364 .ucs_base = { 1365 .udb_base = 0, 1366 .udb_valid = B_TRUE 1367 }, 1368 .ucs_base_mask = 0x3ffffffff, 1369 .ucs_nbanks = 0x5, 1370 .ucs_ncol = 0xa, 1371 .ucs_nrow_lo = 0x10, 1372 .ucs_nbank_groups = 0x3, 1373 .ucs_row_low_bit = 0x12, 1374 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 1375 0xe }, 1376 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 1377 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 1378 .ucs_subchan = 0x6 1379 } } 1380 } }, 1381 }, { 1382 .chan_flags = UMC_CHAN_F_ECC_EN, 1383 .chan_fabid = 4, 1384 .chan_instid = 4, 1385 .chan_logid = 4, 1386 .chan_nrules = 1, 1387 .chan_rules = { { 1388 .ddr_flags = DF_DRAM_F_VALID | 1389 DF_DRAM_F_HASH_30_32, 1390 .ddr_base = 0, 1391 .ddr_limit = 96ULL * 1024ULL * 1024ULL * 1392 1024ULL, 1393 .ddr_dest_fabid = 0, 1394 .ddr_sock_ileave_bits = 0, 1395 .ddr_die_ileave_bits = 0, 1396 .ddr_addr_start = 8, 1397 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS2_6CH 1398 } }, 1399 .chan_dimms = { { 1400 .ud_flags = UMC_DIMM_F_VALID, 1401 .ud_width = UMC_DIMM_W_X4, 1402 .ud_type = UMC_DIMM_T_DDR5, 1403 .ud_kind = UMC_DIMM_K_RDIMM, 1404 .ud_dimmno = 0, 1405 .ud_cs = { { 1406 .ucs_base = { 1407 .udb_base = 0, 1408 .udb_valid = B_TRUE 1409 }, 1410 .ucs_base_mask = 0x3ffffffff, 1411 .ucs_nbanks = 0x5, 1412 .ucs_ncol = 0xa, 1413 .ucs_nrow_lo = 0x10, 1414 .ucs_nbank_groups = 0x3, 1415 .ucs_row_low_bit = 0x12, 1416 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 1417 0xe }, 1418 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 1419 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 1420 .ucs_subchan = 0x6 1421 } } 1422 } }, 1423 }, { 1424 .chan_flags = UMC_CHAN_F_ECC_EN, 1425 .chan_fabid = 5, 1426 .chan_instid = 5, 1427 .chan_logid = 5, 1428 .chan_nrules = 1, 1429 .chan_rules = { { 1430 .ddr_flags = DF_DRAM_F_VALID | 1431 DF_DRAM_F_HASH_30_32, 1432 .ddr_base = 0, 1433 .ddr_limit = 96ULL * 1024ULL * 1024ULL * 1434 1024ULL, 1435 .ddr_dest_fabid = 0, 1436 .ddr_sock_ileave_bits = 0, 1437 .ddr_die_ileave_bits = 0, 1438 .ddr_addr_start = 8, 1439 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS2_6CH 1440 } }, 1441 .chan_dimms = { { 1442 .ud_flags = UMC_DIMM_F_VALID, 1443 .ud_width = UMC_DIMM_W_X4, 1444 .ud_type = UMC_DIMM_T_DDR5, 1445 .ud_kind = UMC_DIMM_K_RDIMM, 1446 .ud_dimmno = 0, 1447 .ud_cs = { { 1448 .ucs_base = { 1449 .udb_base = 0, 1450 .udb_valid = B_TRUE 1451 }, 1452 .ucs_base_mask = 0x3ffffffff, 1453 .ucs_nbanks = 0x5, 1454 .ucs_ncol = 0xa, 1455 .ucs_nrow_lo = 0x10, 1456 .ucs_nbank_groups = 0x3, 1457 .ucs_row_low_bit = 0x12, 1458 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 1459 0xe }, 1460 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 1461 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 1462 .ucs_subchan = 0x6 1463 } } 1464 } }, 1465 } } 1466 } } 1467 }; 1468 1469 /* 1470 * Finally our last bit here is a 3-channel 2P system. This is used to test that 1471 * the variant of the normalization with socket interleaving works correctly. 1472 */ 1473 static const zen_umc_t zen_umc_nps3_2p = { 1474 .umc_tom = 4ULL * 1024ULL * 1024ULL * 1024ULL, 1475 .umc_tom2 = 96ULL * 1024ULL * 1024ULL * 1024ULL, 1476 .umc_df_rev = DF_REV_4, 1477 .umc_decomp = { 1478 .dfd_sock_mask = 0x01, 1479 .dfd_die_mask = 0x00, 1480 .dfd_node_mask = 0x20, 1481 .dfd_comp_mask = 0x1f, 1482 .dfd_sock_shift = 0, 1483 .dfd_die_shift = 0, 1484 .dfd_node_shift = 5, 1485 .dfd_comp_shift = 0 1486 }, 1487 .umc_ndfs = 2, 1488 .umc_dfs = { { 1489 .zud_dfno = 0, 1490 .zud_dram_nrules = 1, 1491 .zud_nchan = 3, 1492 .zud_cs_nremap = 0, 1493 .zud_hole_base = 0, 1494 .zud_rules = { { 1495 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_HASH_21_23, 1496 .ddr_base = 0, 1497 .ddr_limit = 96ULL * 1024ULL * 1024ULL * 1024ULL, 1498 .ddr_dest_fabid = 0, 1499 .ddr_sock_ileave_bits = 1, 1500 .ddr_die_ileave_bits = 0, 1501 .ddr_addr_start = 8, 1502 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS4_3CH 1503 } }, 1504 .zud_chan = { { 1505 .chan_flags = UMC_CHAN_F_ECC_EN, 1506 .chan_fabid = 0, 1507 .chan_instid = 0, 1508 .chan_logid = 0, 1509 .chan_nrules = 1, 1510 .chan_rules = { { 1511 .ddr_flags = DF_DRAM_F_VALID | 1512 DF_DRAM_F_HASH_21_23, 1513 .ddr_base = 0, 1514 .ddr_limit = 96ULL * 1024ULL * 1024ULL * 1515 1024ULL, 1516 .ddr_dest_fabid = 0, 1517 .ddr_sock_ileave_bits = 1, 1518 .ddr_die_ileave_bits = 0, 1519 .ddr_addr_start = 8, 1520 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS4_3CH 1521 } }, 1522 .chan_dimms = { { 1523 .ud_flags = UMC_DIMM_F_VALID, 1524 .ud_width = UMC_DIMM_W_X4, 1525 .ud_type = UMC_DIMM_T_DDR5, 1526 .ud_kind = UMC_DIMM_K_RDIMM, 1527 .ud_dimmno = 0, 1528 .ud_cs = { { 1529 .ucs_base = { 1530 .udb_base = 0, 1531 .udb_valid = B_TRUE 1532 }, 1533 .ucs_base_mask = 0x3ffffffff, 1534 .ucs_nbanks = 0x5, 1535 .ucs_ncol = 0xa, 1536 .ucs_nrow_lo = 0x10, 1537 .ucs_nbank_groups = 0x3, 1538 .ucs_row_low_bit = 0x12, 1539 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 1540 0xe }, 1541 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 1542 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 1543 .ucs_subchan = 0x6 1544 } } 1545 } }, 1546 }, { 1547 .chan_flags = UMC_CHAN_F_ECC_EN, 1548 .chan_fabid = 1, 1549 .chan_instid = 1, 1550 .chan_logid = 1, 1551 .chan_nrules = 1, 1552 .chan_rules = { { 1553 .ddr_flags = DF_DRAM_F_VALID | 1554 DF_DRAM_F_HASH_21_23, 1555 .ddr_base = 0, 1556 .ddr_limit = 96ULL * 1024ULL * 1024ULL * 1557 1024ULL, 1558 .ddr_dest_fabid = 0, 1559 .ddr_sock_ileave_bits = 1, 1560 .ddr_die_ileave_bits = 0, 1561 .ddr_addr_start = 8, 1562 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS4_3CH 1563 } }, 1564 .chan_dimms = { { 1565 .ud_flags = UMC_DIMM_F_VALID, 1566 .ud_width = UMC_DIMM_W_X4, 1567 .ud_type = UMC_DIMM_T_DDR5, 1568 .ud_kind = UMC_DIMM_K_RDIMM, 1569 .ud_dimmno = 0, 1570 .ud_cs = { { 1571 .ucs_base = { 1572 .udb_base = 0, 1573 .udb_valid = B_TRUE 1574 }, 1575 .ucs_base_mask = 0x3ffffffff, 1576 .ucs_nbanks = 0x5, 1577 .ucs_ncol = 0xa, 1578 .ucs_nrow_lo = 0x10, 1579 .ucs_nbank_groups = 0x3, 1580 .ucs_row_low_bit = 0x12, 1581 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 1582 0xe }, 1583 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 1584 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 1585 .ucs_subchan = 0x6 1586 } } 1587 } }, 1588 }, { 1589 .chan_flags = UMC_CHAN_F_ECC_EN, 1590 .chan_fabid = 2, 1591 .chan_instid = 2, 1592 .chan_logid = 2, 1593 .chan_nrules = 1, 1594 .chan_rules = { { 1595 .ddr_flags = DF_DRAM_F_VALID | 1596 DF_DRAM_F_HASH_21_23, 1597 .ddr_base = 0, 1598 .ddr_limit = 96ULL * 1024ULL * 1024ULL * 1599 1024ULL, 1600 .ddr_dest_fabid = 0, 1601 .ddr_sock_ileave_bits = 1, 1602 .ddr_die_ileave_bits = 0, 1603 .ddr_addr_start = 8, 1604 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS4_3CH 1605 } }, 1606 .chan_dimms = { { 1607 .ud_flags = UMC_DIMM_F_VALID, 1608 .ud_width = UMC_DIMM_W_X4, 1609 .ud_type = UMC_DIMM_T_DDR5, 1610 .ud_kind = UMC_DIMM_K_RDIMM, 1611 .ud_dimmno = 0, 1612 .ud_cs = { { 1613 .ucs_base = { 1614 .udb_base = 0, 1615 .udb_valid = B_TRUE 1616 }, 1617 .ucs_base_mask = 0x3ffffffff, 1618 .ucs_nbanks = 0x5, 1619 .ucs_ncol = 0xa, 1620 .ucs_nrow_lo = 0x10, 1621 .ucs_nbank_groups = 0x3, 1622 .ucs_row_low_bit = 0x12, 1623 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 1624 0xe }, 1625 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 1626 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 1627 .ucs_subchan = 0x6 1628 } } 1629 } } 1630 } } 1631 }, { 1632 .zud_dfno = 1, 1633 .zud_dram_nrules = 1, 1634 .zud_nchan = 3, 1635 .zud_cs_nremap = 0, 1636 .zud_hole_base = 0, 1637 .zud_rules = { { 1638 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_HASH_21_23, 1639 .ddr_base = 0, 1640 .ddr_limit = 96ULL * 1024ULL * 1024ULL * 1024ULL, 1641 .ddr_dest_fabid = 0, 1642 .ddr_sock_ileave_bits = 1, 1643 .ddr_die_ileave_bits = 0, 1644 .ddr_addr_start = 8, 1645 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS4_3CH 1646 } }, 1647 .zud_chan = { { 1648 .chan_flags = UMC_CHAN_F_ECC_EN, 1649 .chan_fabid = 0x20, 1650 .chan_instid = 0, 1651 .chan_logid = 0, 1652 .chan_nrules = 1, 1653 .chan_rules = { { 1654 .ddr_flags = DF_DRAM_F_VALID | 1655 DF_DRAM_F_HASH_21_23, 1656 .ddr_base = 0, 1657 .ddr_limit = 96ULL * 1024ULL * 1024ULL * 1658 1024ULL, 1659 .ddr_dest_fabid = 0, 1660 .ddr_sock_ileave_bits = 1, 1661 .ddr_die_ileave_bits = 0, 1662 .ddr_addr_start = 8, 1663 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS4_3CH 1664 } }, 1665 .chan_dimms = { { 1666 .ud_flags = UMC_DIMM_F_VALID, 1667 .ud_width = UMC_DIMM_W_X4, 1668 .ud_type = UMC_DIMM_T_DDR5, 1669 .ud_kind = UMC_DIMM_K_RDIMM, 1670 .ud_dimmno = 0, 1671 .ud_cs = { { 1672 .ucs_base = { 1673 .udb_base = 0, 1674 .udb_valid = B_TRUE 1675 }, 1676 .ucs_base_mask = 0x3ffffffff, 1677 .ucs_nbanks = 0x5, 1678 .ucs_ncol = 0xa, 1679 .ucs_nrow_lo = 0x10, 1680 .ucs_nbank_groups = 0x3, 1681 .ucs_row_low_bit = 0x12, 1682 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 1683 0xe }, 1684 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 1685 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 1686 .ucs_subchan = 0x6 1687 } } 1688 } }, 1689 }, { 1690 .chan_flags = UMC_CHAN_F_ECC_EN, 1691 .chan_fabid = 0x21, 1692 .chan_instid = 1, 1693 .chan_logid = 1, 1694 .chan_nrules = 1, 1695 .chan_rules = { { 1696 .ddr_flags = DF_DRAM_F_VALID | 1697 DF_DRAM_F_HASH_21_23, 1698 .ddr_base = 0, 1699 .ddr_limit = 96ULL * 1024ULL * 1024ULL * 1700 1024ULL, 1701 .ddr_dest_fabid = 0, 1702 .ddr_sock_ileave_bits = 1, 1703 .ddr_die_ileave_bits = 0, 1704 .ddr_addr_start = 8, 1705 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS4_3CH 1706 } }, 1707 .chan_dimms = { { 1708 .ud_flags = UMC_DIMM_F_VALID, 1709 .ud_width = UMC_DIMM_W_X4, 1710 .ud_type = UMC_DIMM_T_DDR5, 1711 .ud_kind = UMC_DIMM_K_RDIMM, 1712 .ud_dimmno = 0, 1713 .ud_cs = { { 1714 .ucs_base = { 1715 .udb_base = 0, 1716 .udb_valid = B_TRUE 1717 }, 1718 .ucs_base_mask = 0x3ffffffff, 1719 .ucs_nbanks = 0x5, 1720 .ucs_ncol = 0xa, 1721 .ucs_nrow_lo = 0x10, 1722 .ucs_nbank_groups = 0x3, 1723 .ucs_row_low_bit = 0x12, 1724 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 1725 0xe }, 1726 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 1727 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 1728 .ucs_subchan = 0x6 1729 } } 1730 } }, 1731 }, { 1732 .chan_flags = UMC_CHAN_F_ECC_EN, 1733 .chan_fabid = 0x22, 1734 .chan_instid = 2, 1735 .chan_logid = 2, 1736 .chan_nrules = 1, 1737 .chan_rules = { { 1738 .ddr_flags = DF_DRAM_F_VALID | 1739 DF_DRAM_F_HASH_21_23, 1740 .ddr_base = 0, 1741 .ddr_limit = 96ULL * 1024ULL * 1024ULL * 1742 1024ULL, 1743 .ddr_dest_fabid = 0, 1744 .ddr_sock_ileave_bits = 1, 1745 .ddr_die_ileave_bits = 0, 1746 .ddr_addr_start = 8, 1747 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS4_3CH 1748 } }, 1749 .chan_dimms = { { 1750 .ud_flags = UMC_DIMM_F_VALID, 1751 .ud_width = UMC_DIMM_W_X4, 1752 .ud_type = UMC_DIMM_T_DDR5, 1753 .ud_kind = UMC_DIMM_K_RDIMM, 1754 .ud_dimmno = 0, 1755 .ud_cs = { { 1756 .ucs_base = { 1757 .udb_base = 0, 1758 .udb_valid = B_TRUE 1759 }, 1760 .ucs_base_mask = 0x3ffffffff, 1761 .ucs_nbanks = 0x5, 1762 .ucs_ncol = 0xa, 1763 .ucs_nrow_lo = 0x10, 1764 .ucs_nbank_groups = 0x3, 1765 .ucs_row_low_bit = 0x12, 1766 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 1767 0xe }, 1768 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 1769 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 1770 .ucs_subchan = 0x6 1771 } } 1772 } } 1773 } } 1774 } } 1775 }; 1776 1777 const umc_decode_test_t zen_umc_test_nps[] = { { 1778 .udt_desc = "NPS 8ch, 2P ilv (0)", 1779 .udt_umc = &zen_umc_nps8_2p, 1780 .udt_pa = 0x123, 1781 .udt_pass = B_TRUE, 1782 .udt_norm_addr = 0x123, 1783 .udt_sock = 0, 1784 .udt_die = 0, 1785 .udt_comp = 0, 1786 .udt_dimm_no = 0, 1787 .udt_dimm_col = 0x28, 1788 .udt_dimm_row = 0, 1789 .udt_dimm_bank = 0, 1790 .udt_dimm_bank_group = 0, 1791 .udt_dimm_subchan = 0, 1792 .udt_dimm_rm = 0, 1793 .udt_dimm_cs = 0 1794 }, { 1795 .udt_desc = "NPS 8ch, 2P ilv (1)", 1796 .udt_umc = &zen_umc_nps8_2p, 1797 .udt_pa = 0x323, 1798 .udt_pass = B_TRUE, 1799 .udt_norm_addr = 0x123, 1800 .udt_sock = 1, 1801 .udt_die = 0, 1802 .udt_comp = 0, 1803 .udt_dimm_no = 0, 1804 .udt_dimm_col = 0x28, 1805 .udt_dimm_row = 0, 1806 .udt_dimm_bank = 0, 1807 .udt_dimm_bank_group = 0, 1808 .udt_dimm_subchan = 0, 1809 .udt_dimm_rm = 0, 1810 .udt_dimm_cs = 0 1811 }, { 1812 .udt_desc = "NPS 8ch, 2P ilv (2)", 1813 .udt_umc = &zen_umc_nps8_2p, 1814 .udt_pa = 0x1123, 1815 .udt_pass = B_TRUE, 1816 .udt_norm_addr = 0x123, 1817 .udt_sock = 0, 1818 .udt_die = 0, 1819 .udt_comp = 1, 1820 .udt_dimm_no = 0, 1821 .udt_dimm_col = 0x28, 1822 .udt_dimm_row = 0, 1823 .udt_dimm_bank = 0, 1824 .udt_dimm_bank_group = 0, 1825 .udt_dimm_subchan = 0, 1826 .udt_dimm_rm = 0, 1827 .udt_dimm_cs = 0 1828 }, { 1829 .udt_desc = "NPS 8ch, 2P ilv (3)", 1830 .udt_umc = &zen_umc_nps8_2p, 1831 .udt_pa = 0x1323, 1832 .udt_pass = B_TRUE, 1833 .udt_norm_addr = 0x123, 1834 .udt_sock = 1, 1835 .udt_die = 0, 1836 .udt_comp = 1, 1837 .udt_dimm_no = 0, 1838 .udt_dimm_col = 0x28, 1839 .udt_dimm_row = 0, 1840 .udt_dimm_bank = 0, 1841 .udt_dimm_bank_group = 0, 1842 .udt_dimm_subchan = 0, 1843 .udt_dimm_rm = 0, 1844 .udt_dimm_cs = 0 1845 }, { 1846 .udt_desc = "NPS 8ch, 2P ilv (4)", 1847 .udt_umc = &zen_umc_nps8_2p, 1848 .udt_pa = 0x2123, 1849 .udt_pass = B_TRUE, 1850 .udt_norm_addr = 0x123, 1851 .udt_sock = 0, 1852 .udt_die = 0, 1853 .udt_comp = 2, 1854 .udt_dimm_no = 0, 1855 .udt_dimm_col = 0x28, 1856 .udt_dimm_row = 0, 1857 .udt_dimm_bank = 0, 1858 .udt_dimm_bank_group = 0, 1859 .udt_dimm_subchan = 0, 1860 .udt_dimm_rm = 0, 1861 .udt_dimm_cs = 0 1862 }, { 1863 .udt_desc = "NPS 8ch, 2P ilv (5)", 1864 .udt_umc = &zen_umc_nps8_2p, 1865 .udt_pa = 0x2323, 1866 .udt_pass = B_TRUE, 1867 .udt_norm_addr = 0x123, 1868 .udt_sock = 1, 1869 .udt_die = 0, 1870 .udt_comp = 2, 1871 .udt_dimm_no = 0, 1872 .udt_dimm_col = 0x28, 1873 .udt_dimm_row = 0, 1874 .udt_dimm_bank = 0, 1875 .udt_dimm_bank_group = 0, 1876 .udt_dimm_subchan = 0, 1877 .udt_dimm_rm = 0, 1878 .udt_dimm_cs = 0 1879 }, { 1880 .udt_desc = "NPS 8ch, 2P ilv (6)", 1881 .udt_umc = &zen_umc_nps8_2p, 1882 .udt_pa = 0x3123, 1883 .udt_pass = B_TRUE, 1884 .udt_norm_addr = 0x123, 1885 .udt_sock = 0, 1886 .udt_die = 0, 1887 .udt_comp = 3, 1888 .udt_dimm_no = 0, 1889 .udt_dimm_col = 0x28, 1890 .udt_dimm_row = 0, 1891 .udt_dimm_bank = 0, 1892 .udt_dimm_bank_group = 0, 1893 .udt_dimm_subchan = 0, 1894 .udt_dimm_rm = 0, 1895 .udt_dimm_cs = 0 1896 }, { 1897 .udt_desc = "NPS 8ch, 2P ilv (7)", 1898 .udt_umc = &zen_umc_nps8_2p, 1899 .udt_pa = 0x3323, 1900 .udt_pass = B_TRUE, 1901 .udt_norm_addr = 0x123, 1902 .udt_sock = 1, 1903 .udt_die = 0, 1904 .udt_comp = 3, 1905 .udt_dimm_no = 0, 1906 .udt_dimm_col = 0x28, 1907 .udt_dimm_row = 0, 1908 .udt_dimm_bank = 0, 1909 .udt_dimm_bank_group = 0, 1910 .udt_dimm_subchan = 0, 1911 .udt_dimm_rm = 0, 1912 .udt_dimm_cs = 0 1913 }, { 1914 .udt_desc = "NPS 8ch, 2P ilv (8)", 1915 .udt_umc = &zen_umc_nps8_2p, 1916 .udt_pa = 0x4123, 1917 .udt_pass = B_TRUE, 1918 .udt_norm_addr = 0x123, 1919 .udt_sock = 0, 1920 .udt_die = 0, 1921 .udt_comp = 4, 1922 .udt_dimm_no = 0, 1923 .udt_dimm_col = 0x28, 1924 .udt_dimm_row = 0, 1925 .udt_dimm_bank = 0, 1926 .udt_dimm_bank_group = 0, 1927 .udt_dimm_subchan = 0, 1928 .udt_dimm_rm = 0, 1929 .udt_dimm_cs = 0 1930 }, { 1931 .udt_desc = "NPS 8ch, 2P ilv (9)", 1932 .udt_umc = &zen_umc_nps8_2p, 1933 .udt_pa = 0x4323, 1934 .udt_pass = B_TRUE, 1935 .udt_norm_addr = 0x123, 1936 .udt_sock = 1, 1937 .udt_die = 0, 1938 .udt_comp = 4, 1939 .udt_dimm_no = 0, 1940 .udt_dimm_col = 0x28, 1941 .udt_dimm_row = 0, 1942 .udt_dimm_bank = 0, 1943 .udt_dimm_bank_group = 0, 1944 .udt_dimm_subchan = 0, 1945 .udt_dimm_rm = 0, 1946 .udt_dimm_cs = 0 1947 }, { 1948 .udt_desc = "NPS 8ch, 2P ilv (10)", 1949 .udt_umc = &zen_umc_nps8_2p, 1950 .udt_pa = 0x5123, 1951 .udt_pass = B_TRUE, 1952 .udt_norm_addr = 0x123, 1953 .udt_sock = 0, 1954 .udt_die = 0, 1955 .udt_comp = 5, 1956 .udt_dimm_no = 0, 1957 .udt_dimm_col = 0x28, 1958 .udt_dimm_row = 0, 1959 .udt_dimm_bank = 0, 1960 .udt_dimm_bank_group = 0, 1961 .udt_dimm_subchan = 0, 1962 .udt_dimm_rm = 0, 1963 .udt_dimm_cs = 0 1964 }, { 1965 .udt_desc = "NPS 8ch, 2P ilv (11)", 1966 .udt_umc = &zen_umc_nps8_2p, 1967 .udt_pa = 0x5323, 1968 .udt_pass = B_TRUE, 1969 .udt_norm_addr = 0x123, 1970 .udt_sock = 1, 1971 .udt_die = 0, 1972 .udt_comp = 5, 1973 .udt_dimm_no = 0, 1974 .udt_dimm_col = 0x28, 1975 .udt_dimm_row = 0, 1976 .udt_dimm_bank = 0, 1977 .udt_dimm_bank_group = 0, 1978 .udt_dimm_subchan = 0, 1979 .udt_dimm_rm = 0, 1980 .udt_dimm_cs = 0 1981 }, { 1982 .udt_desc = "NPS 8ch, 2P ilv (12)", 1983 .udt_umc = &zen_umc_nps8_2p, 1984 .udt_pa = 0x6123, 1985 .udt_pass = B_TRUE, 1986 .udt_norm_addr = 0x123, 1987 .udt_sock = 0, 1988 .udt_die = 0, 1989 .udt_comp = 6, 1990 .udt_dimm_no = 0, 1991 .udt_dimm_col = 0x28, 1992 .udt_dimm_row = 0, 1993 .udt_dimm_bank = 0, 1994 .udt_dimm_bank_group = 0, 1995 .udt_dimm_subchan = 0, 1996 .udt_dimm_rm = 0, 1997 .udt_dimm_cs = 0 1998 }, { 1999 .udt_desc = "NPS 8ch, 2P ilv (13)", 2000 .udt_umc = &zen_umc_nps8_2p, 2001 .udt_pa = 0x6323, 2002 .udt_pass = B_TRUE, 2003 .udt_norm_addr = 0x123, 2004 .udt_sock = 1, 2005 .udt_die = 0, 2006 .udt_comp = 6, 2007 .udt_dimm_no = 0, 2008 .udt_dimm_col = 0x28, 2009 .udt_dimm_row = 0, 2010 .udt_dimm_bank = 0, 2011 .udt_dimm_bank_group = 0, 2012 .udt_dimm_subchan = 0, 2013 .udt_dimm_rm = 0, 2014 .udt_dimm_cs = 0 2015 }, { 2016 .udt_desc = "NPS 8ch, 2P ilv (14)", 2017 .udt_umc = &zen_umc_nps8_2p, 2018 .udt_pa = 0x7123, 2019 .udt_pass = B_TRUE, 2020 .udt_norm_addr = 0x123, 2021 .udt_sock = 0, 2022 .udt_die = 0, 2023 .udt_comp = 7, 2024 .udt_dimm_no = 0, 2025 .udt_dimm_col = 0x28, 2026 .udt_dimm_row = 0, 2027 .udt_dimm_bank = 0, 2028 .udt_dimm_bank_group = 0, 2029 .udt_dimm_subchan = 0, 2030 .udt_dimm_rm = 0, 2031 .udt_dimm_cs = 0 2032 }, { 2033 .udt_desc = "NPS 8ch, 2P ilv (15)", 2034 .udt_umc = &zen_umc_nps8_2p, 2035 .udt_pa = 0x7323, 2036 .udt_pass = B_TRUE, 2037 .udt_norm_addr = 0x123, 2038 .udt_sock = 1, 2039 .udt_die = 0, 2040 .udt_comp = 7, 2041 .udt_dimm_no = 0, 2042 .udt_dimm_col = 0x28, 2043 .udt_dimm_row = 0, 2044 .udt_dimm_bank = 0, 2045 .udt_dimm_bank_group = 0, 2046 .udt_dimm_subchan = 0, 2047 .udt_dimm_rm = 0, 2048 .udt_dimm_cs = 0 2049 }, { 2050 .udt_desc = "NPS 8ch, 2P ilv (16)", 2051 .udt_umc = &zen_umc_nps8_2p, 2052 .udt_pa = 0x17323, 2053 .udt_pass = B_TRUE, 2054 .udt_norm_addr = 0x1123, 2055 .udt_sock = 0, 2056 .udt_die = 0, 2057 .udt_comp = 7, 2058 .udt_dimm_no = 0, 2059 .udt_dimm_col = 0x228, 2060 .udt_dimm_row = 0, 2061 .udt_dimm_bank = 0, 2062 .udt_dimm_bank_group = 0, 2063 .udt_dimm_subchan = 0, 2064 .udt_dimm_rm = 0, 2065 .udt_dimm_cs = 0 2066 }, { 2067 .udt_desc = "NPS 8ch, 2P ilv (17)", 2068 .udt_umc = &zen_umc_nps8_2p, 2069 .udt_pa = 0x217323, 2070 .udt_pass = B_TRUE, 2071 .udt_norm_addr = 0x21123, 2072 .udt_sock = 1, 2073 .udt_die = 0, 2074 .udt_comp = 7, 2075 .udt_dimm_no = 0, 2076 .udt_dimm_col = 0x228, 2077 .udt_dimm_row = 0, 2078 .udt_dimm_bank = 0, 2079 .udt_dimm_bank_group = 0x4, 2080 .udt_dimm_subchan = 0, 2081 .udt_dimm_rm = 0, 2082 .udt_dimm_cs = 0 2083 }, { 2084 .udt_desc = "NPS 8ch, 2P ilv (18)", 2085 .udt_umc = &zen_umc_nps8_2p, 2086 .udt_pa = 0x40217323, 2087 .udt_pass = B_TRUE, 2088 .udt_norm_addr = 0x4021123, 2089 .udt_sock = 0, 2090 .udt_die = 0, 2091 .udt_comp = 7, 2092 .udt_dimm_no = 0, 2093 .udt_dimm_col = 0x228, 2094 .udt_dimm_row = 0x100, 2095 .udt_dimm_bank = 0, 2096 .udt_dimm_bank_group = 0x4, 2097 .udt_dimm_subchan = 0, 2098 .udt_dimm_rm = 0, 2099 .udt_dimm_cs = 0 2100 }, { 2101 .udt_desc = "NPS 8ch, 2P ilv (19)", 2102 .udt_umc = &zen_umc_nps8_2p, 2103 .udt_pa = 0x240217323, 2104 .udt_pass = B_TRUE, 2105 .udt_norm_addr = 0x24021123, 2106 .udt_sock = 0, 2107 .udt_die = 0, 2108 .udt_comp = 3, 2109 .udt_dimm_no = 0, 2110 .udt_dimm_col = 0x228, 2111 .udt_dimm_row = 0x900, 2112 .udt_dimm_bank = 0, 2113 .udt_dimm_bank_group = 0x4, 2114 .udt_dimm_subchan = 0, 2115 .udt_dimm_rm = 0, 2116 .udt_dimm_cs = 0 2117 }, { 2118 .udt_desc = "NPS 8ch, 2P ilv (20)", 2119 .udt_umc = &zen_umc_nps8_2p, 2120 .udt_pa = 0x240617323, 2121 .udt_pass = B_TRUE, 2122 .udt_norm_addr = 0x24061123, 2123 .udt_sock = 0, 2124 .udt_die = 0, 2125 .udt_comp = 2, 2126 .udt_dimm_no = 0, 2127 .udt_dimm_col = 0x228, 2128 .udt_dimm_row = 0x901, 2129 .udt_dimm_bank = 0, 2130 .udt_dimm_bank_group = 0x4, 2131 .udt_dimm_subchan = 0, 2132 .udt_dimm_rm = 0, 2133 .udt_dimm_cs = 0 2134 }, { 2135 .udt_desc = "NPS 8ch, 2P ilv (21)", 2136 .udt_umc = &zen_umc_nps8_2p, 2137 .udt_pa = 0x240617323, 2138 .udt_pass = B_TRUE, 2139 .udt_norm_addr = 0x24061123, 2140 .udt_sock = 0, 2141 .udt_die = 0, 2142 .udt_comp = 2, 2143 .udt_dimm_no = 0, 2144 .udt_dimm_col = 0x228, 2145 .udt_dimm_row = 0x901, 2146 .udt_dimm_bank = 0, 2147 .udt_dimm_bank_group = 0x4, 2148 .udt_dimm_subchan = 0, 2149 .udt_dimm_rm = 0, 2150 .udt_dimm_cs = 0 2151 }, { 2152 .udt_desc = "NPS 8ch, 2P ilv (22)", 2153 .udt_umc = &zen_umc_nps8_2p, 2154 .udt_pa = 0x240687323, 2155 .udt_pass = B_TRUE, 2156 .udt_norm_addr = 0x24068123, 2157 .udt_sock = 1, 2158 .udt_die = 0, 2159 .udt_comp = 6, 2160 .udt_dimm_no = 0, 2161 .udt_dimm_col = 0x28, 2162 .udt_dimm_row = 0x901, 2163 .udt_dimm_bank = 0, 2164 .udt_dimm_bank_group = 0x5, 2165 .udt_dimm_subchan = 0, 2166 .udt_dimm_rm = 0, 2167 .udt_dimm_cs = 0 2168 }, { 2169 .udt_desc = "NPS 8ch, 2P ilv (23)", 2170 .udt_umc = &zen_umc_nps8_2p, 2171 .udt_pa = 0x2c0687323, 2172 .udt_pass = B_TRUE, 2173 .udt_norm_addr = 0x2c068123, 2174 .udt_sock = 1, 2175 .udt_die = 0, 2176 .udt_comp = 7, 2177 .udt_dimm_no = 0, 2178 .udt_dimm_col = 0x28, 2179 .udt_dimm_row = 0xb01, 2180 .udt_dimm_bank = 0, 2181 .udt_dimm_bank_group = 0x5, 2182 .udt_dimm_subchan = 0, 2183 .udt_dimm_rm = 0, 2184 .udt_dimm_cs = 0 2185 }, { 2186 .udt_desc = "NPS 2ch, 1P (0)", 2187 .udt_umc = &zen_umc_nps2_1p, 2188 .udt_pa = 0x167, 2189 .udt_pass = B_TRUE, 2190 .udt_norm_addr = 0x167, 2191 .udt_sock = 0, 2192 .udt_die = 0, 2193 .udt_comp = 0, 2194 .udt_dimm_no = 0, 2195 .udt_dimm_col = 0x29, 2196 .udt_dimm_row = 0x0, 2197 .udt_dimm_bank = 0, 2198 .udt_dimm_bank_group = 0x0, 2199 .udt_dimm_subchan = 1, 2200 .udt_dimm_rm = 0, 2201 .udt_dimm_cs = 0 2202 }, { 2203 .udt_desc = "NPS 2ch, 1P (1)", 2204 .udt_umc = &zen_umc_nps2_1p, 2205 .udt_pa = 0x367, 2206 .udt_pass = B_TRUE, 2207 .udt_norm_addr = 0x167, 2208 .udt_sock = 0, 2209 .udt_die = 0, 2210 .udt_comp = 1, 2211 .udt_dimm_no = 0, 2212 .udt_dimm_col = 0x29, 2213 .udt_dimm_row = 0x0, 2214 .udt_dimm_bank = 0, 2215 .udt_dimm_bank_group = 0x0, 2216 .udt_dimm_subchan = 1, 2217 .udt_dimm_rm = 0, 2218 .udt_dimm_cs = 0 2219 }, { 2220 .udt_desc = "NPS 2ch, 1P (2)", 2221 .udt_umc = &zen_umc_nps2_1p, 2222 .udt_pa = 0x4167, 2223 .udt_pass = B_TRUE, 2224 .udt_norm_addr = 0x2167, 2225 .udt_sock = 0, 2226 .udt_die = 0, 2227 .udt_comp = 1, 2228 .udt_dimm_no = 0, 2229 .udt_dimm_col = 0x29, 2230 .udt_dimm_row = 0x0, 2231 .udt_dimm_bank = 1, 2232 .udt_dimm_bank_group = 0x0, 2233 .udt_dimm_subchan = 1, 2234 .udt_dimm_rm = 0, 2235 .udt_dimm_cs = 0 2236 }, { 2237 .udt_desc = "NPS 2ch, 1P (3)", 2238 .udt_umc = &zen_umc_nps2_1p, 2239 .udt_pa = 0x14167, 2240 .udt_pass = B_TRUE, 2241 .udt_norm_addr = 0xa167, 2242 .udt_sock = 0, 2243 .udt_die = 0, 2244 .udt_comp = 0, 2245 .udt_dimm_no = 0, 2246 .udt_dimm_col = 0x29, 2247 .udt_dimm_row = 0x0, 2248 .udt_dimm_bank = 1, 2249 .udt_dimm_bank_group = 0x1, 2250 .udt_dimm_subchan = 1, 2251 .udt_dimm_rm = 0, 2252 .udt_dimm_cs = 0 2253 }, { 2254 .udt_desc = "NPS 2ch, 1P (4)", 2255 .udt_umc = &zen_umc_nps2_1p, 2256 .udt_pa = 0x40014167, 2257 .udt_pass = B_TRUE, 2258 .udt_norm_addr = 0x2000a167, 2259 .udt_sock = 0, 2260 .udt_die = 0, 2261 .udt_comp = 1, 2262 .udt_dimm_no = 0, 2263 .udt_dimm_col = 0x29, 2264 .udt_dimm_row = 0x800, 2265 .udt_dimm_bank = 1, 2266 .udt_dimm_bank_group = 0x1, 2267 .udt_dimm_subchan = 1, 2268 .udt_dimm_rm = 0, 2269 .udt_dimm_cs = 0 2270 }, { 2271 .udt_desc = "NPS 2ch, 1P (5)", 2272 .udt_umc = &zen_umc_nps2_1p, 2273 .udt_pa = 0x214167, 2274 .udt_pass = B_TRUE, 2275 .udt_norm_addr = 0x10a167, 2276 .udt_sock = 0, 2277 .udt_die = 0, 2278 .udt_comp = 1, 2279 .udt_dimm_no = 0, 2280 .udt_dimm_col = 0x29, 2281 .udt_dimm_row = 0x4, 2282 .udt_dimm_bank = 1, 2283 .udt_dimm_bank_group = 0x1, 2284 .udt_dimm_subchan = 1, 2285 .udt_dimm_rm = 0, 2286 .udt_dimm_cs = 0 2287 }, { 2288 .udt_desc = "NPS 2ch, 1P (6)", 2289 .udt_umc = &zen_umc_nps2_1p, 2290 .udt_pa = 0x40214167, 2291 .udt_pass = B_TRUE, 2292 .udt_norm_addr = 0x2010a167, 2293 .udt_sock = 0, 2294 .udt_die = 0, 2295 .udt_comp = 0, 2296 .udt_dimm_no = 0, 2297 .udt_dimm_col = 0x29, 2298 .udt_dimm_row = 0x804, 2299 .udt_dimm_bank = 1, 2300 .udt_dimm_bank_group = 0x1, 2301 .udt_dimm_subchan = 1, 2302 .udt_dimm_rm = 0, 2303 .udt_dimm_cs = 0 2304 }, { 2305 .udt_desc = "NPS 5ch, 1P (0)", 2306 .udt_umc = &zen_umc_nps5_1p, 2307 .udt_pa = 0xcd, 2308 .udt_pass = B_TRUE, 2309 .udt_norm_addr = 0xcd, 2310 .udt_sock = 0, 2311 .udt_die = 0, 2312 .udt_comp = 0, 2313 .udt_dimm_no = 0, 2314 .udt_dimm_col = 0x13, 2315 .udt_dimm_row = 0x0, 2316 .udt_dimm_bank = 0, 2317 .udt_dimm_bank_group = 0x0, 2318 .udt_dimm_subchan = 1, 2319 .udt_dimm_rm = 0, 2320 .udt_dimm_cs = 0 2321 }, { 2322 .udt_desc = "NPS 5ch, 1P (1)", 2323 .udt_umc = &zen_umc_nps5_1p, 2324 .udt_pa = 0x1cd, 2325 .udt_pass = B_TRUE, 2326 .udt_norm_addr = 0x20cd, 2327 .udt_sock = 0, 2328 .udt_die = 0, 2329 .udt_comp = 1, 2330 .udt_dimm_no = 0, 2331 .udt_dimm_col = 0x13, 2332 .udt_dimm_row = 0x0, 2333 .udt_dimm_bank = 1, 2334 .udt_dimm_bank_group = 0x0, 2335 .udt_dimm_subchan = 1, 2336 .udt_dimm_rm = 0, 2337 .udt_dimm_cs = 0 2338 }, { 2339 .udt_desc = "NPS 5ch, 1P (2)", 2340 .udt_umc = &zen_umc_nps5_1p, 2341 .udt_pa = 0x2cd, 2342 .udt_pass = B_TRUE, 2343 .udt_norm_addr = 0x1cd, 2344 .udt_sock = 0, 2345 .udt_die = 0, 2346 .udt_comp = 0, 2347 .udt_dimm_no = 0, 2348 .udt_dimm_col = 0x33, 2349 .udt_dimm_row = 0x0, 2350 .udt_dimm_bank = 0, 2351 .udt_dimm_bank_group = 0x0, 2352 .udt_dimm_subchan = 1, 2353 .udt_dimm_rm = 0, 2354 .udt_dimm_cs = 0 2355 }, { 2356 .udt_desc = "NPS 5ch, 1P (3)", 2357 .udt_umc = &zen_umc_nps5_1p, 2358 .udt_pa = 0x3cd, 2359 .udt_pass = B_TRUE, 2360 .udt_norm_addr = 0x21cd, 2361 .udt_sock = 0, 2362 .udt_die = 0, 2363 .udt_comp = 1, 2364 .udt_dimm_no = 0, 2365 .udt_dimm_col = 0x33, 2366 .udt_dimm_row = 0x0, 2367 .udt_dimm_bank = 1, 2368 .udt_dimm_bank_group = 0x0, 2369 .udt_dimm_subchan = 1, 2370 .udt_dimm_rm = 0, 2371 .udt_dimm_cs = 0 2372 }, { 2373 .udt_desc = "NPS 5ch, 1P (4)", 2374 .udt_umc = &zen_umc_nps5_1p, 2375 .udt_pa = 0x4cd, 2376 .udt_pass = B_TRUE, 2377 .udt_norm_addr = 0x2cd, 2378 .udt_sock = 0, 2379 .udt_die = 0, 2380 .udt_comp = 0, 2381 .udt_dimm_no = 0, 2382 .udt_dimm_col = 0x53, 2383 .udt_dimm_row = 0x0, 2384 .udt_dimm_bank = 0, 2385 .udt_dimm_bank_group = 0x0, 2386 .udt_dimm_subchan = 1, 2387 .udt_dimm_rm = 0, 2388 .udt_dimm_cs = 0 2389 }, { 2390 .udt_desc = "NPS 5ch, 1P (5)", 2391 .udt_umc = &zen_umc_nps5_1p, 2392 .udt_pa = 0x5cd, 2393 .udt_pass = B_TRUE, 2394 .udt_norm_addr = 0x22cd, 2395 .udt_sock = 0, 2396 .udt_die = 0, 2397 .udt_comp = 1, 2398 .udt_dimm_no = 0, 2399 .udt_dimm_col = 0x53, 2400 .udt_dimm_row = 0x0, 2401 .udt_dimm_bank = 1, 2402 .udt_dimm_bank_group = 0x0, 2403 .udt_dimm_subchan = 1, 2404 .udt_dimm_rm = 0, 2405 .udt_dimm_cs = 0 2406 }, { 2407 .udt_desc = "NPS 5ch, 1P (6)", 2408 .udt_umc = &zen_umc_nps5_1p, 2409 .udt_pa = 0x6cd, 2410 .udt_pass = B_TRUE, 2411 .udt_norm_addr = 0x3cd, 2412 .udt_sock = 0, 2413 .udt_die = 0, 2414 .udt_comp = 0, 2415 .udt_dimm_no = 0, 2416 .udt_dimm_col = 0x73, 2417 .udt_dimm_row = 0x0, 2418 .udt_dimm_bank = 0, 2419 .udt_dimm_bank_group = 0x0, 2420 .udt_dimm_subchan = 1, 2421 .udt_dimm_rm = 0, 2422 .udt_dimm_cs = 0 2423 }, { 2424 .udt_desc = "NPS 5ch, 1P (7)", 2425 .udt_umc = &zen_umc_nps5_1p, 2426 .udt_pa = 0x3ecd, 2427 .udt_pass = B_TRUE, 2428 .udt_norm_addr = 0x1fcd, 2429 .udt_sock = 0, 2430 .udt_die = 0, 2431 .udt_comp = 0, 2432 .udt_dimm_no = 0, 2433 .udt_dimm_col = 0x3f3, 2434 .udt_dimm_row = 0x0, 2435 .udt_dimm_bank = 0, 2436 .udt_dimm_bank_group = 0x0, 2437 .udt_dimm_subchan = 1, 2438 .udt_dimm_rm = 0, 2439 .udt_dimm_cs = 0 2440 }, { 2441 .udt_desc = "NPS 5ch, 1P (8)", 2442 .udt_umc = &zen_umc_nps5_1p, 2443 .udt_pa = 0x3fcd, 2444 .udt_pass = B_TRUE, 2445 .udt_norm_addr = 0x3fcd, 2446 .udt_sock = 0, 2447 .udt_die = 0, 2448 .udt_comp = 1, 2449 .udt_dimm_no = 0, 2450 .udt_dimm_col = 0x3f3, 2451 .udt_dimm_row = 0x0, 2452 .udt_dimm_bank = 1, 2453 .udt_dimm_bank_group = 0x0, 2454 .udt_dimm_subchan = 1, 2455 .udt_dimm_rm = 0, 2456 .udt_dimm_cs = 0 2457 }, { 2458 .udt_desc = "NPS 5ch, 1P (9)", 2459 .udt_umc = &zen_umc_nps5_1p, 2460 .udt_pa = 0x40cd, 2461 .udt_pass = B_TRUE, 2462 .udt_norm_addr = 0x20cd, 2463 .udt_sock = 0, 2464 .udt_die = 0, 2465 .udt_comp = 2, 2466 .udt_dimm_no = 0, 2467 .udt_dimm_col = 0x13, 2468 .udt_dimm_row = 0x0, 2469 .udt_dimm_bank = 1, 2470 .udt_dimm_bank_group = 0x0, 2471 .udt_dimm_subchan = 1, 2472 .udt_dimm_rm = 0, 2473 .udt_dimm_cs = 0 2474 }, { 2475 .udt_desc = "NPS 5ch, 1P (10)", 2476 .udt_umc = &zen_umc_nps5_1p, 2477 .udt_pa = 0x41cd, 2478 .udt_pass = B_TRUE, 2479 .udt_norm_addr = 0xcd, 2480 .udt_sock = 0, 2481 .udt_die = 0, 2482 .udt_comp = 1, 2483 .udt_dimm_no = 0, 2484 .udt_dimm_col = 0x13, 2485 .udt_dimm_row = 0x0, 2486 .udt_dimm_bank = 0, 2487 .udt_dimm_bank_group = 0x0, 2488 .udt_dimm_subchan = 1, 2489 .udt_dimm_rm = 0, 2490 .udt_dimm_cs = 0 2491 }, { 2492 .udt_desc = "NPS 5ch, 1P (11)", 2493 .udt_umc = &zen_umc_nps5_1p, 2494 .udt_pa = 0x80cd, 2495 .udt_pass = B_TRUE, 2496 .udt_norm_addr = 0xcd, 2497 .udt_sock = 0, 2498 .udt_die = 0, 2499 .udt_comp = 2, 2500 .udt_dimm_no = 0, 2501 .udt_dimm_col = 0x13, 2502 .udt_dimm_row = 0x0, 2503 .udt_dimm_bank = 0, 2504 .udt_dimm_bank_group = 0x0, 2505 .udt_dimm_subchan = 1, 2506 .udt_dimm_rm = 0, 2507 .udt_dimm_cs = 0 2508 }, { 2509 .udt_desc = "NPS 5ch, 1P (12)", 2510 .udt_umc = &zen_umc_nps5_1p, 2511 .udt_pa = 0x81cd, 2512 .udt_pass = B_TRUE, 2513 .udt_norm_addr = 0x20cd, 2514 .udt_sock = 0, 2515 .udt_die = 0, 2516 .udt_comp = 3, 2517 .udt_dimm_no = 0, 2518 .udt_dimm_col = 0x13, 2519 .udt_dimm_row = 0x0, 2520 .udt_dimm_bank = 1, 2521 .udt_dimm_bank_group = 0x0, 2522 .udt_dimm_subchan = 1, 2523 .udt_dimm_rm = 0, 2524 .udt_dimm_cs = 0 2525 }, { 2526 .udt_desc = "NPS 5ch, 1P (13)", 2527 .udt_umc = &zen_umc_nps5_1p, 2528 .udt_pa = 0xc0cd, 2529 .udt_pass = B_TRUE, 2530 .udt_norm_addr = 0x20cd, 2531 .udt_sock = 0, 2532 .udt_die = 0, 2533 .udt_comp = 4, 2534 .udt_dimm_no = 0, 2535 .udt_dimm_col = 0x13, 2536 .udt_dimm_row = 0x0, 2537 .udt_dimm_bank = 1, 2538 .udt_dimm_bank_group = 0x0, 2539 .udt_dimm_subchan = 1, 2540 .udt_dimm_rm = 0, 2541 .udt_dimm_cs = 0 2542 }, { 2543 .udt_desc = "NPS 5ch, 1P (14)", 2544 .udt_umc = &zen_umc_nps5_1p, 2545 .udt_pa = 0xc1cd, 2546 .udt_pass = B_TRUE, 2547 .udt_norm_addr = 0xcd, 2548 .udt_sock = 0, 2549 .udt_die = 0, 2550 .udt_comp = 3, 2551 .udt_dimm_no = 0, 2552 .udt_dimm_col = 0x13, 2553 .udt_dimm_row = 0x0, 2554 .udt_dimm_bank = 0, 2555 .udt_dimm_bank_group = 0x0, 2556 .udt_dimm_subchan = 1, 2557 .udt_dimm_rm = 0, 2558 .udt_dimm_cs = 0 2559 }, { 2560 .udt_desc = "NPS 5ch, 1P (15)", 2561 .udt_umc = &zen_umc_nps5_1p, 2562 .udt_pa = 0x100cd, 2563 .udt_pass = B_TRUE, 2564 .udt_norm_addr = 0x20cd, 2565 .udt_sock = 0, 2566 .udt_die = 0, 2567 .udt_comp = 0, 2568 .udt_dimm_no = 0, 2569 .udt_dimm_col = 0x13, 2570 .udt_dimm_row = 0x0, 2571 .udt_dimm_bank = 1, 2572 .udt_dimm_bank_group = 0x0, 2573 .udt_dimm_subchan = 1, 2574 .udt_dimm_rm = 0, 2575 .udt_dimm_cs = 0 2576 }, { 2577 .udt_desc = "NPS 5ch, 1P (16)", 2578 .udt_umc = &zen_umc_nps5_1p, 2579 .udt_pa = 0x101cd, 2580 .udt_pass = B_TRUE, 2581 .udt_norm_addr = 0xcd, 2582 .udt_sock = 0, 2583 .udt_die = 0, 2584 .udt_comp = 4, 2585 .udt_dimm_no = 0, 2586 .udt_dimm_col = 0x13, 2587 .udt_dimm_row = 0x0, 2588 .udt_dimm_bank = 0, 2589 .udt_dimm_bank_group = 0x0, 2590 .udt_dimm_subchan = 1, 2591 .udt_dimm_rm = 0, 2592 .udt_dimm_cs = 0 2593 }, { 2594 .udt_desc = "NPS 5ch, 1P (17)", 2595 .udt_umc = &zen_umc_nps5_1p, 2596 .udt_pa = 0x140cd, 2597 .udt_pass = B_TRUE, 2598 .udt_norm_addr = 0x40cd, 2599 .udt_sock = 0, 2600 .udt_die = 0, 2601 .udt_comp = 0, 2602 .udt_dimm_no = 0, 2603 .udt_dimm_col = 0x13, 2604 .udt_dimm_row = 0x0, 2605 .udt_dimm_bank = 2, 2606 .udt_dimm_bank_group = 0x0, 2607 .udt_dimm_subchan = 1, 2608 .udt_dimm_rm = 0, 2609 .udt_dimm_cs = 0 2610 }, { 2611 .udt_desc = "NPS 5ch, 1P (18)", 2612 .udt_umc = &zen_umc_nps5_1p, 2613 .udt_pa = 0x141cd, 2614 .udt_pass = B_TRUE, 2615 .udt_norm_addr = 0x60cd, 2616 .udt_sock = 0, 2617 .udt_die = 0, 2618 .udt_comp = 1, 2619 .udt_dimm_no = 0, 2620 .udt_dimm_col = 0x13, 2621 .udt_dimm_row = 0x0, 2622 .udt_dimm_bank = 3, 2623 .udt_dimm_bank_group = 0x0, 2624 .udt_dimm_subchan = 1, 2625 .udt_dimm_rm = 0, 2626 .udt_dimm_cs = 0 2627 }, { 2628 .udt_desc = "NPS 6ch, 1P (0)", 2629 .udt_umc = &zen_umc_nps6_1p, 2630 .udt_pa = 0xbc, 2631 .udt_pass = B_TRUE, 2632 .udt_norm_addr = 0xbc, 2633 .udt_sock = 0, 2634 .udt_die = 0, 2635 .udt_comp = 0, 2636 .udt_dimm_no = 0, 2637 .udt_dimm_col = 0x1f, 2638 .udt_dimm_row = 0x0, 2639 .udt_dimm_bank = 0, 2640 .udt_dimm_bank_group = 0x0, 2641 .udt_dimm_subchan = 0, 2642 .udt_dimm_rm = 0, 2643 .udt_dimm_cs = 0 2644 }, { 2645 .udt_desc = "NPS 6ch, 1P (1)", 2646 .udt_umc = &zen_umc_nps6_1p, 2647 .udt_pa = 0x1bc, 2648 .udt_pass = B_TRUE, 2649 .udt_norm_addr = 0x10bc, 2650 .udt_sock = 0, 2651 .udt_die = 0, 2652 .udt_comp = 1, 2653 .udt_dimm_no = 0, 2654 .udt_dimm_col = 0x21f, 2655 .udt_dimm_row = 0x0, 2656 .udt_dimm_bank = 0, 2657 .udt_dimm_bank_group = 0x0, 2658 .udt_dimm_subchan = 0, 2659 .udt_dimm_rm = 0, 2660 .udt_dimm_cs = 0 2661 }, { 2662 .udt_desc = "NPS 6ch, 1P (2)", 2663 .udt_umc = &zen_umc_nps6_1p, 2664 .udt_pa = 0x20bc, 2665 .udt_pass = B_TRUE, 2666 .udt_norm_addr = 0xbc, 2667 .udt_sock = 0, 2668 .udt_die = 0, 2669 .udt_comp = 3, 2670 .udt_dimm_no = 0, 2671 .udt_dimm_col = 0x1f, 2672 .udt_dimm_row = 0x0, 2673 .udt_dimm_bank = 0, 2674 .udt_dimm_bank_group = 0x0, 2675 .udt_dimm_subchan = 0, 2676 .udt_dimm_rm = 0, 2677 .udt_dimm_cs = 0 2678 }, { 2679 .udt_desc = "NPS 6ch, 1P (3)", 2680 .udt_umc = &zen_umc_nps6_1p, 2681 .udt_pa = 0x21bc, 2682 .udt_pass = B_TRUE, 2683 .udt_norm_addr = 0x10bc, 2684 .udt_sock = 0, 2685 .udt_die = 0, 2686 .udt_comp = 4, 2687 .udt_dimm_no = 0, 2688 .udt_dimm_col = 0x21f, 2689 .udt_dimm_row = 0x0, 2690 .udt_dimm_bank = 0, 2691 .udt_dimm_bank_group = 0x0, 2692 .udt_dimm_subchan = 0, 2693 .udt_dimm_rm = 0, 2694 .udt_dimm_cs = 0 2695 }, { 2696 .udt_desc = "NPS 6ch, 1P (4)", 2697 .udt_umc = &zen_umc_nps6_1p, 2698 .udt_pa = 0x40bc, 2699 .udt_pass = B_TRUE, 2700 .udt_norm_addr = 0x10bc, 2701 .udt_sock = 0, 2702 .udt_die = 0, 2703 .udt_comp = 2, 2704 .udt_dimm_no = 0, 2705 .udt_dimm_col = 0x21f, 2706 .udt_dimm_row = 0x0, 2707 .udt_dimm_bank = 0, 2708 .udt_dimm_bank_group = 0x0, 2709 .udt_dimm_subchan = 0, 2710 .udt_dimm_rm = 0, 2711 .udt_dimm_cs = 0 2712 }, { 2713 .udt_desc = "NPS 6ch, 1P (5)", 2714 .udt_umc = &zen_umc_nps6_1p, 2715 .udt_pa = 0x41bc, 2716 .udt_pass = B_TRUE, 2717 .udt_norm_addr = 0xbc, 2718 .udt_sock = 0, 2719 .udt_die = 0, 2720 .udt_comp = 1, 2721 .udt_dimm_no = 0, 2722 .udt_dimm_col = 0x1f, 2723 .udt_dimm_row = 0x0, 2724 .udt_dimm_bank = 0, 2725 .udt_dimm_bank_group = 0x0, 2726 .udt_dimm_subchan = 0, 2727 .udt_dimm_rm = 0, 2728 .udt_dimm_cs = 0 2729 }, { 2730 .udt_desc = "NPS 6ch, 1P (6)", 2731 .udt_umc = &zen_umc_nps6_1p, 2732 .udt_pa = 0x60bc, 2733 .udt_pass = B_TRUE, 2734 .udt_norm_addr = 0x10bc, 2735 .udt_sock = 0, 2736 .udt_die = 0, 2737 .udt_comp = 5, 2738 .udt_dimm_no = 0, 2739 .udt_dimm_col = 0x21f, 2740 .udt_dimm_row = 0x0, 2741 .udt_dimm_bank = 0, 2742 .udt_dimm_bank_group = 0x0, 2743 .udt_dimm_subchan = 0, 2744 .udt_dimm_rm = 0, 2745 .udt_dimm_cs = 0 2746 }, { 2747 .udt_desc = "NPS 6ch, 1P (7)", 2748 .udt_umc = &zen_umc_nps6_1p, 2749 .udt_pa = 0x61bc, 2750 .udt_pass = B_TRUE, 2751 .udt_norm_addr = 0xbc, 2752 .udt_sock = 0, 2753 .udt_die = 0, 2754 .udt_comp = 4, 2755 .udt_dimm_no = 0, 2756 .udt_dimm_col = 0x1f, 2757 .udt_dimm_row = 0x0, 2758 .udt_dimm_bank = 0, 2759 .udt_dimm_bank_group = 0x0, 2760 .udt_dimm_subchan = 0, 2761 .udt_dimm_rm = 0, 2762 .udt_dimm_cs = 0 2763 }, { 2764 .udt_desc = "NPS 6ch, 1P (8)", 2765 .udt_umc = &zen_umc_nps6_1p, 2766 .udt_pa = 0x80bc, 2767 .udt_pass = B_TRUE, 2768 .udt_norm_addr = 0xbc, 2769 .udt_sock = 0, 2770 .udt_die = 0, 2771 .udt_comp = 2, 2772 .udt_dimm_no = 0, 2773 .udt_dimm_col = 0x1f, 2774 .udt_dimm_row = 0x0, 2775 .udt_dimm_bank = 0, 2776 .udt_dimm_bank_group = 0x0, 2777 .udt_dimm_subchan = 0, 2778 .udt_dimm_rm = 0, 2779 .udt_dimm_cs = 0 2780 }, { 2781 .udt_desc = "NPS 6ch, 1P (9)", 2782 .udt_umc = &zen_umc_nps6_1p, 2783 .udt_pa = 0x81bc, 2784 .udt_pass = B_TRUE, 2785 .udt_norm_addr = 0x10bc, 2786 .udt_sock = 0, 2787 .udt_die = 0, 2788 .udt_comp = 0, 2789 .udt_dimm_no = 0, 2790 .udt_dimm_col = 0x21f, 2791 .udt_dimm_row = 0x0, 2792 .udt_dimm_bank = 0, 2793 .udt_dimm_bank_group = 0x0, 2794 .udt_dimm_subchan = 0, 2795 .udt_dimm_rm = 0, 2796 .udt_dimm_cs = 0 2797 }, { 2798 .udt_desc = "NPS 6ch, 1P (10)", 2799 .udt_umc = &zen_umc_nps6_1p, 2800 .udt_pa = 0xa0bc, 2801 .udt_pass = B_TRUE, 2802 .udt_norm_addr = 0xbc, 2803 .udt_sock = 0, 2804 .udt_die = 0, 2805 .udt_comp = 5, 2806 .udt_dimm_no = 0, 2807 .udt_dimm_col = 0x1f, 2808 .udt_dimm_row = 0x0, 2809 .udt_dimm_bank = 0, 2810 .udt_dimm_bank_group = 0x0, 2811 .udt_dimm_subchan = 0, 2812 .udt_dimm_rm = 0, 2813 .udt_dimm_cs = 0 2814 }, { 2815 .udt_desc = "NPS 6ch, 1P (11)", 2816 .udt_umc = &zen_umc_nps6_1p, 2817 .udt_pa = 0xa1bc, 2818 .udt_pass = B_TRUE, 2819 .udt_norm_addr = 0x10bc, 2820 .udt_sock = 0, 2821 .udt_die = 0, 2822 .udt_comp = 3, 2823 .udt_dimm_no = 0, 2824 .udt_dimm_col = 0x21f, 2825 .udt_dimm_row = 0x0, 2826 .udt_dimm_bank = 0, 2827 .udt_dimm_bank_group = 0x0, 2828 .udt_dimm_subchan = 0, 2829 .udt_dimm_rm = 0, 2830 .udt_dimm_cs = 0 2831 }, 2832 /* 2833 * We don't use hashing on the 64 KiB range, but walking through it should still 2834 * change the component IDs because of how the scheme works, but it should be 2835 * more contiguous. 2836 */ 2837 { 2838 .udt_desc = "NPS 6ch, 1P (12)", 2839 .udt_umc = &zen_umc_nps6_1p, 2840 .udt_pa = 0x120bc, 2841 .udt_pass = B_TRUE, 2842 .udt_norm_addr = 0x20bc, 2843 .udt_sock = 0, 2844 .udt_die = 0, 2845 .udt_comp = 4, 2846 .udt_dimm_no = 0, 2847 .udt_dimm_col = 0x1f, 2848 .udt_dimm_row = 0x0, 2849 .udt_dimm_bank = 1, 2850 .udt_dimm_bank_group = 0x0, 2851 .udt_dimm_subchan = 0, 2852 .udt_dimm_rm = 0, 2853 .udt_dimm_cs = 0 2854 }, { 2855 .udt_desc = "NPS 6ch, 1P (13)", 2856 .udt_umc = &zen_umc_nps6_1p, 2857 .udt_pa = 0x220bc, 2858 .udt_pass = B_TRUE, 2859 .udt_norm_addr = 0x40bc, 2860 .udt_sock = 0, 2861 .udt_die = 0, 2862 .udt_comp = 5, 2863 .udt_dimm_no = 0, 2864 .udt_dimm_col = 0x1f, 2865 .udt_dimm_row = 0x0, 2866 .udt_dimm_bank = 0x2, 2867 .udt_dimm_bank_group = 0x0, 2868 .udt_dimm_subchan = 0, 2869 .udt_dimm_rm = 0, 2870 .udt_dimm_cs = 0 2871 }, { 2872 .udt_desc = "NPS 6ch, 1P (14)", 2873 .udt_umc = &zen_umc_nps6_1p, 2874 .udt_pa = 0x320bc, 2875 .udt_pass = B_TRUE, 2876 .udt_norm_addr = 0x80bc, 2877 .udt_sock = 0, 2878 .udt_die = 0, 2879 .udt_comp = 3, 2880 .udt_dimm_no = 0, 2881 .udt_dimm_col = 0x1f, 2882 .udt_dimm_row = 0x0, 2883 .udt_dimm_bank = 0x0, 2884 .udt_dimm_bank_group = 0x1, 2885 .udt_dimm_subchan = 0, 2886 .udt_dimm_rm = 0, 2887 .udt_dimm_cs = 0 2888 }, { 2889 .udt_desc = "NPS 6ch, 1P (15)", 2890 .udt_umc = &zen_umc_nps6_1p, 2891 .udt_pa = 0x420bc, 2892 .udt_pass = B_TRUE, 2893 .udt_norm_addr = 0xa0bc, 2894 .udt_sock = 0, 2895 .udt_die = 0, 2896 .udt_comp = 4, 2897 .udt_dimm_no = 0, 2898 .udt_dimm_col = 0x1f, 2899 .udt_dimm_row = 0x0, 2900 .udt_dimm_bank = 0x1, 2901 .udt_dimm_bank_group = 0x1, 2902 .udt_dimm_subchan = 0, 2903 .udt_dimm_rm = 0, 2904 .udt_dimm_cs = 0 2905 }, { 2906 .udt_desc = "NPS 6ch, 1P (16)", 2907 .udt_umc = &zen_umc_nps6_1p, 2908 .udt_pa = 0x720bc, 2909 .udt_pass = B_TRUE, 2910 .udt_norm_addr = 0x120bc, 2911 .udt_sock = 0, 2912 .udt_die = 0, 2913 .udt_comp = 4, 2914 .udt_dimm_no = 0, 2915 .udt_dimm_col = 0x1f, 2916 .udt_dimm_row = 0x0, 2917 .udt_dimm_bank = 0x1, 2918 .udt_dimm_bank_group = 0x2, 2919 .udt_dimm_subchan = 0, 2920 .udt_dimm_rm = 0, 2921 .udt_dimm_cs = 0 2922 }, { 2923 .udt_desc = "NPS 6ch, 1P (17)", 2924 .udt_umc = &zen_umc_nps6_1p, 2925 .udt_pa = 0x1000020bc, 2926 .udt_pass = B_TRUE, 2927 .udt_norm_addr = 0x2aaaa0bc, 2928 .udt_sock = 0, 2929 .udt_die = 0, 2930 .udt_comp = 1, 2931 .udt_dimm_no = 0, 2932 .udt_dimm_col = 0x1f, 2933 .udt_dimm_row = 0xaaa, 2934 .udt_dimm_bank = 0x1, 2935 .udt_dimm_bank_group = 0x5, 2936 .udt_dimm_subchan = 0, 2937 .udt_dimm_rm = 0, 2938 .udt_dimm_cs = 0 2939 }, { 2940 .udt_desc = "NPS 6ch, 1P (18)", 2941 .udt_umc = &zen_umc_nps6_1p, 2942 .udt_pa = 0x1800020bc, 2943 .udt_pass = B_TRUE, 2944 .udt_norm_addr = 0x400000bc, 2945 .udt_sock = 0, 2946 .udt_die = 0, 2947 .udt_comp = 0, 2948 .udt_dimm_no = 0, 2949 .udt_dimm_col = 0x1f, 2950 .udt_dimm_row = 0x1000, 2951 .udt_dimm_bank = 0x0, 2952 .udt_dimm_bank_group = 0x0, 2953 .udt_dimm_subchan = 0, 2954 .udt_dimm_rm = 0, 2955 .udt_dimm_cs = 0 2956 }, { 2957 .udt_desc = "NPS 6ch, 1P (19)", 2958 .udt_umc = &zen_umc_nps6_1p, 2959 .udt_pa = 0x1c00020bc, 2960 .udt_pass = B_TRUE, 2961 .udt_norm_addr = 0x4aaab0bc, 2962 .udt_sock = 0, 2963 .udt_die = 0, 2964 .udt_comp = 2, 2965 .udt_dimm_no = 0, 2966 .udt_dimm_col = 0x21f, 2967 .udt_dimm_row = 0x12aa, 2968 .udt_dimm_bank = 0x1, 2969 .udt_dimm_bank_group = 0x5, 2970 .udt_dimm_subchan = 0, 2971 .udt_dimm_rm = 0, 2972 .udt_dimm_cs = 0 2973 }, { 2974 .udt_desc = "NPS 6ch, 1P (20)", 2975 .udt_umc = &zen_umc_nps6_1p, 2976 .udt_pa = 0x1c00060bc, 2977 .udt_pass = B_TRUE, 2978 .udt_norm_addr = 0x4aaaa0bc, 2979 .udt_sock = 0, 2980 .udt_die = 0, 2981 .udt_comp = 2, 2982 .udt_dimm_no = 0, 2983 .udt_dimm_col = 0x1f, 2984 .udt_dimm_row = 0x12aa, 2985 .udt_dimm_bank = 0x1, 2986 .udt_dimm_bank_group = 0x5, 2987 .udt_dimm_subchan = 0, 2988 .udt_dimm_rm = 0, 2989 .udt_dimm_cs = 0 2990 }, { 2991 .udt_desc = "NPS 6ch, 1P (21)", 2992 .udt_umc = &zen_umc_nps6_1p, 2993 .udt_pa = 0x1c00040bc, 2994 .udt_pass = B_TRUE, 2995 .udt_norm_addr = 0x4aaaa0bc, 2996 .udt_sock = 0, 2997 .udt_die = 0, 2998 .udt_comp = 5, 2999 .udt_dimm_no = 0, 3000 .udt_dimm_col = 0x1f, 3001 .udt_dimm_row = 0x12aa, 3002 .udt_dimm_bank = 0x1, 3003 .udt_dimm_bank_group = 0x5, 3004 .udt_dimm_subchan = 0, 3005 .udt_dimm_rm = 0, 3006 .udt_dimm_cs = 0 3007 }, { 3008 .udt_desc = "NPS 6ch, 1P (22)", 3009 .udt_umc = &zen_umc_nps6_1p, 3010 .udt_pa = 0x1c00041bc, 3011 .udt_pass = B_TRUE, 3012 .udt_norm_addr = 0x4aaab0bc, 3013 .udt_sock = 0, 3014 .udt_die = 0, 3015 .udt_comp = 3, 3016 .udt_dimm_no = 0, 3017 .udt_dimm_col = 0x21f, 3018 .udt_dimm_row = 0x12aa, 3019 .udt_dimm_bank = 0x1, 3020 .udt_dimm_bank_group = 0x5, 3021 .udt_dimm_subchan = 0, 3022 .udt_dimm_rm = 0, 3023 .udt_dimm_cs = 0 3024 }, { 3025 .udt_desc = "NPS 6ch, 1P (23)", 3026 .udt_umc = &zen_umc_nps6_1p, 3027 .udt_pa = 0x1c00061bc, 3028 .udt_pass = B_TRUE, 3029 .udt_norm_addr = 0x4aaab0bc, 3030 .udt_sock = 0, 3031 .udt_die = 0, 3032 .udt_comp = 0, 3033 .udt_dimm_no = 0, 3034 .udt_dimm_col = 0x21f, 3035 .udt_dimm_row = 0x12aa, 3036 .udt_dimm_bank = 0x1, 3037 .udt_dimm_bank_group = 0x5, 3038 .udt_dimm_subchan = 0, 3039 .udt_dimm_rm = 0, 3040 .udt_dimm_cs = 0 3041 }, { 3042 .udt_desc = "NPS 3ch, 2P (0)", 3043 .udt_umc = &zen_umc_nps3_2p, 3044 .udt_pa = 0xad, 3045 .udt_pass = B_TRUE, 3046 .udt_norm_addr = 0xad, 3047 .udt_sock = 0, 3048 .udt_die = 0, 3049 .udt_comp = 0, 3050 .udt_dimm_no = 0, 3051 .udt_dimm_col = 0x1b, 3052 .udt_dimm_row = 0x0, 3053 .udt_dimm_bank = 0x0, 3054 .udt_dimm_bank_group = 0x0, 3055 .udt_dimm_subchan = 0, 3056 .udt_dimm_rm = 0, 3057 .udt_dimm_cs = 0 3058 }, { 3059 .udt_desc = "NPS 3ch, 2P (1)", 3060 .udt_umc = &zen_umc_nps3_2p, 3061 .udt_pa = 0x1ad, 3062 .udt_pass = B_TRUE, 3063 .udt_norm_addr = 0xad, 3064 .udt_sock = 1, 3065 .udt_die = 0, 3066 .udt_comp = 1, 3067 .udt_dimm_no = 0, 3068 .udt_dimm_col = 0x1b, 3069 .udt_dimm_row = 0x0, 3070 .udt_dimm_bank = 0x0, 3071 .udt_dimm_bank_group = 0x0, 3072 .udt_dimm_subchan = 0, 3073 .udt_dimm_rm = 0, 3074 .udt_dimm_cs = 0 3075 }, { 3076 .udt_desc = "NPS 3ch, 2P (2)", 3077 .udt_umc = &zen_umc_nps3_2p, 3078 .udt_pa = 0x40ad, 3079 .udt_pass = B_TRUE, 3080 .udt_norm_addr = 0xad, 3081 .udt_sock = 1, 3082 .udt_die = 0, 3083 .udt_comp = 2, 3084 .udt_dimm_no = 0, 3085 .udt_dimm_col = 0x1b, 3086 .udt_dimm_row = 0x0, 3087 .udt_dimm_bank = 0x0, 3088 .udt_dimm_bank_group = 0x0, 3089 .udt_dimm_subchan = 0, 3090 .udt_dimm_rm = 0, 3091 .udt_dimm_cs = 0 3092 }, { 3093 .udt_desc = "NPS 3ch, 2P (3)", 3094 .udt_umc = &zen_umc_nps3_2p, 3095 .udt_pa = 0x41ad, 3096 .udt_pass = B_TRUE, 3097 .udt_norm_addr = 0xad, 3098 .udt_sock = 0, 3099 .udt_die = 0, 3100 .udt_comp = 1, 3101 .udt_dimm_no = 0, 3102 .udt_dimm_col = 0x1b, 3103 .udt_dimm_row = 0x0, 3104 .udt_dimm_bank = 0x0, 3105 .udt_dimm_bank_group = 0x0, 3106 .udt_dimm_subchan = 0, 3107 .udt_dimm_rm = 0, 3108 .udt_dimm_cs = 0 3109 }, { 3110 .udt_desc = "NPS 3ch, 2P (4)", 3111 .udt_umc = &zen_umc_nps3_2p, 3112 .udt_pa = 0x80ad, 3113 .udt_pass = B_TRUE, 3114 .udt_norm_addr = 0xad, 3115 .udt_sock = 0, 3116 .udt_die = 0, 3117 .udt_comp = 2, 3118 .udt_dimm_no = 0, 3119 .udt_dimm_col = 0x1b, 3120 .udt_dimm_row = 0x0, 3121 .udt_dimm_bank = 0x0, 3122 .udt_dimm_bank_group = 0x0, 3123 .udt_dimm_subchan = 0, 3124 .udt_dimm_rm = 0, 3125 .udt_dimm_cs = 0 3126 }, { 3127 .udt_desc = "NPS 3ch, 2P (5)", 3128 .udt_umc = &zen_umc_nps3_2p, 3129 .udt_pa = 0x81ad, 3130 .udt_pass = B_TRUE, 3131 .udt_norm_addr = 0xad, 3132 .udt_sock = 1, 3133 .udt_die = 0, 3134 .udt_comp = 0, 3135 .udt_dimm_no = 0, 3136 .udt_dimm_col = 0x1b, 3137 .udt_dimm_row = 0x0, 3138 .udt_dimm_bank = 0x0, 3139 .udt_dimm_bank_group = 0x0, 3140 .udt_dimm_subchan = 0, 3141 .udt_dimm_rm = 0, 3142 .udt_dimm_cs = 0 3143 }, { 3144 .udt_desc = "NPS 3ch, 2P (6)", 3145 .udt_umc = &zen_umc_nps3_2p, 3146 .udt_pa = 0x1fc0ad, 3147 .udt_pass = B_TRUE, 3148 .udt_norm_addr = 0x540ad, 3149 .udt_sock = 1, 3150 .udt_die = 0, 3151 .udt_comp = 2, 3152 .udt_dimm_no = 0, 3153 .udt_dimm_col = 0x1b, 3154 .udt_dimm_row = 0x1, 3155 .udt_dimm_bank = 0x2, 3156 .udt_dimm_bank_group = 0x2, 3157 .udt_dimm_subchan = 0, 3158 .udt_dimm_rm = 0, 3159 .udt_dimm_cs = 0 3160 }, { 3161 .udt_desc = "NPS 3ch, 2P (7)", 3162 .udt_umc = &zen_umc_nps3_2p, 3163 .udt_pa = 0x1fc1ad, 3164 .udt_pass = B_TRUE, 3165 .udt_norm_addr = 0x540ad, 3166 .udt_sock = 0, 3167 .udt_die = 0, 3168 .udt_comp = 1, 3169 .udt_dimm_no = 0, 3170 .udt_dimm_col = 0x1b, 3171 .udt_dimm_row = 0x1, 3172 .udt_dimm_bank = 0x2, 3173 .udt_dimm_bank_group = 0x2, 3174 .udt_dimm_subchan = 0, 3175 .udt_dimm_rm = 0, 3176 .udt_dimm_cs = 0 3177 }, { 3178 .udt_desc = "NPS 3ch, 2P (8)", 3179 .udt_umc = &zen_umc_nps3_2p, 3180 .udt_pa = 0x2000ad, 3181 .udt_pass = B_TRUE, 3182 .udt_norm_addr = 0x540ad, 3183 .udt_sock = 1, 3184 .udt_die = 0, 3185 .udt_comp = 0, 3186 .udt_dimm_no = 0, 3187 .udt_dimm_col = 0x1b, 3188 .udt_dimm_row = 0x1, 3189 .udt_dimm_bank = 0x2, 3190 .udt_dimm_bank_group = 0x2, 3191 .udt_dimm_subchan = 0, 3192 .udt_dimm_rm = 0, 3193 .udt_dimm_cs = 0 3194 }, { 3195 .udt_desc = "NPS 3ch, 2P (9)", 3196 .udt_umc = &zen_umc_nps3_2p, 3197 .udt_pa = 0x2001ad, 3198 .udt_pass = B_TRUE, 3199 .udt_norm_addr = 0x540ad, 3200 .udt_sock = 0, 3201 .udt_die = 0, 3202 .udt_comp = 2, 3203 .udt_dimm_no = 0, 3204 .udt_dimm_col = 0x1b, 3205 .udt_dimm_row = 0x1, 3206 .udt_dimm_bank = 0x2, 3207 .udt_dimm_bank_group = 0x2, 3208 .udt_dimm_subchan = 0, 3209 .udt_dimm_rm = 0, 3210 .udt_dimm_cs = 0 3211 }, { 3212 .udt_desc = "NPS 3ch, 2P (10)", 3213 .udt_umc = &zen_umc_nps3_2p, 3214 .udt_pa = 0x2040ad, 3215 .udt_pass = B_TRUE, 3216 .udt_norm_addr = 0x560ad, 3217 .udt_sock = 0, 3218 .udt_die = 0, 3219 .udt_comp = 0, 3220 .udt_dimm_no = 0, 3221 .udt_dimm_col = 0x1b, 3222 .udt_dimm_row = 0x1, 3223 .udt_dimm_bank = 0x3, 3224 .udt_dimm_bank_group = 0x2, 3225 .udt_dimm_subchan = 0, 3226 .udt_dimm_rm = 0, 3227 .udt_dimm_cs = 0 3228 }, { 3229 .udt_desc = "NPS 3ch, 2P (11)", 3230 .udt_umc = &zen_umc_nps3_2p, 3231 .udt_pa = 0x2041ad, 3232 .udt_pass = B_TRUE, 3233 .udt_norm_addr = 0x560ad, 3234 .udt_sock = 1, 3235 .udt_die = 0, 3236 .udt_comp = 1, 3237 .udt_dimm_no = 0, 3238 .udt_dimm_col = 0x1b, 3239 .udt_dimm_row = 0x1, 3240 .udt_dimm_bank = 0x3, 3241 .udt_dimm_bank_group = 0x2, 3242 .udt_dimm_subchan = 0, 3243 .udt_dimm_rm = 0, 3244 .udt_dimm_cs = 0 3245 }, { 3246 .udt_desc = "NPS 3ch, 2P (12)", 3247 .udt_umc = &zen_umc_nps3_2p, 3248 .udt_pa = 0x2080ad, 3249 .udt_pass = B_TRUE, 3250 .udt_norm_addr = 0x560ad, 3251 .udt_sock = 1, 3252 .udt_die = 0, 3253 .udt_comp = 2, 3254 .udt_dimm_no = 0, 3255 .udt_dimm_col = 0x1b, 3256 .udt_dimm_row = 0x1, 3257 .udt_dimm_bank = 0x3, 3258 .udt_dimm_bank_group = 0x2, 3259 .udt_dimm_subchan = 0, 3260 .udt_dimm_rm = 0, 3261 .udt_dimm_cs = 0 3262 }, { 3263 .udt_desc = "NPS 3ch, 2P (13)", 3264 .udt_umc = &zen_umc_nps3_2p, 3265 .udt_pa = 0x2081ad, 3266 .udt_pass = B_TRUE, 3267 .udt_norm_addr = 0x560ad, 3268 .udt_sock = 0, 3269 .udt_die = 0, 3270 .udt_comp = 1, 3271 .udt_dimm_no = 0, 3272 .udt_dimm_col = 0x1b, 3273 .udt_dimm_row = 0x1, 3274 .udt_dimm_bank = 0x3, 3275 .udt_dimm_bank_group = 0x2, 3276 .udt_dimm_subchan = 0, 3277 .udt_dimm_rm = 0, 3278 .udt_dimm_cs = 0 3279 }, { 3280 .udt_desc = "NPS 3ch, 2P (14)", 3281 .udt_umc = &zen_umc_nps3_2p, 3282 .udt_pa = 0x20c0ad, 3283 .udt_pass = B_TRUE, 3284 .udt_norm_addr = 0x560ad, 3285 .udt_sock = 0, 3286 .udt_die = 0, 3287 .udt_comp = 2, 3288 .udt_dimm_no = 0, 3289 .udt_dimm_col = 0x1b, 3290 .udt_dimm_row = 0x1, 3291 .udt_dimm_bank = 0x3, 3292 .udt_dimm_bank_group = 0x2, 3293 .udt_dimm_subchan = 0, 3294 .udt_dimm_rm = 0, 3295 .udt_dimm_cs = 0 3296 }, { 3297 .udt_desc = "NPS 3ch, 2P (15)", 3298 .udt_umc = &zen_umc_nps3_2p, 3299 .udt_pa = 0x20c1ad, 3300 .udt_pass = B_TRUE, 3301 .udt_norm_addr = 0x560ad, 3302 .udt_sock = 1, 3303 .udt_die = 0, 3304 .udt_comp = 0, 3305 .udt_dimm_no = 0, 3306 .udt_dimm_col = 0x1b, 3307 .udt_dimm_row = 0x1, 3308 .udt_dimm_bank = 0x3, 3309 .udt_dimm_bank_group = 0x2, 3310 .udt_dimm_subchan = 0, 3311 .udt_dimm_rm = 0, 3312 .udt_dimm_cs = 0 3313 }, { 3314 .udt_desc = "NPS 3ch, 2P (16)", 3315 .udt_umc = &zen_umc_nps3_2p, 3316 .udt_pa = 0x10020c0ad, 3317 .udt_pass = B_TRUE, 3318 .udt_norm_addr = 0x2ab020ad, 3319 .udt_sock = 0, 3320 .udt_die = 0, 3321 .udt_comp = 0, 3322 .udt_dimm_no = 0, 3323 .udt_dimm_col = 0x1b, 3324 .udt_dimm_row = 0xaac, 3325 .udt_dimm_bank = 0x1, 3326 .udt_dimm_bank_group = 0x0, 3327 .udt_dimm_subchan = 0, 3328 .udt_dimm_rm = 0, 3329 .udt_dimm_cs = 0 3330 }, { 3331 .udt_desc = "NPS 3ch, 2P (17)", 3332 .udt_umc = &zen_umc_nps3_2p, 3333 .udt_pa = 0x10020c1ad, 3334 .udt_pass = B_TRUE, 3335 .udt_norm_addr = 0x2ab020ad, 3336 .udt_sock = 1, 3337 .udt_die = 0, 3338 .udt_comp = 1, 3339 .udt_dimm_no = 0, 3340 .udt_dimm_col = 0x1b, 3341 .udt_dimm_row = 0xaac, 3342 .udt_dimm_bank = 0x1, 3343 .udt_dimm_bank_group = 0x0, 3344 .udt_dimm_subchan = 0, 3345 .udt_dimm_rm = 0, 3346 .udt_dimm_cs = 0 3347 }, { 3348 .udt_desc = NULL 3349 } }; 3350