1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2022 Oxide Computer Company 14 */ 15 16 /* 17 * Here we construct a more realistic DF situation where we have multiple rules. 18 * In particular, we use a DFv3 style configuration with a single die and 19 * socket. To make sense of the channel offset logic, we construct a system with 20 * two channels, one with 64 GiB and one one 8 GiB DIMMs. We basically 21 * interleave with the 16 GiB channel over the last 16 GiB of the 128 GiB 22 * channel. This requires us to therefore use the channel offset for the first 23 * channel to get it in a reasonable spot for the second rule. This also allows 24 * us to test what happens with multiple rules and ensure that we select the 25 * right one and when two rules map to one channel. 26 * 27 * Here, the hole is sized to 1.75 GiB. This is based on a system we saw that 28 * was set up this way. 29 */ 30 31 #include "zen_umc_test.h" 32 33 static const zen_umc_t zen_umc_multi = { 34 .umc_tom = 0x90000000, 35 .umc_tom2 = 0x2470000000, 36 .umc_df_rev = DF_REV_3, 37 .umc_decomp = { 38 .dfd_sock_mask = 0x01, 39 .dfd_die_mask = 0x00, 40 .dfd_node_mask = 0x20, 41 .dfd_comp_mask = 0x1f, 42 .dfd_sock_shift = 0, 43 .dfd_die_shift = 0, 44 .dfd_node_shift = 5, 45 .dfd_comp_shift = 0 46 }, 47 .umc_ndfs = 1, 48 .umc_dfs = { { 49 .zud_flags = ZEN_UMC_DF_F_HOLE_VALID, 50 .zud_dfno = 0, 51 .zud_dram_nrules = 2, 52 .zud_nchan = 4, 53 .zud_cs_nremap = 0, 54 .zud_hole_base = 0x90000000, 55 .zud_rules = { { 56 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_HOLE, 57 .ddr_base = 0, 58 .ddr_limit = 0x1c70000000, 59 .ddr_dest_fabid = 0, 60 .ddr_sock_ileave_bits = 0, 61 .ddr_die_ileave_bits = 0, 62 .ddr_addr_start = 8, 63 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 64 }, { 65 .ddr_flags = DF_DRAM_F_VALID, 66 .ddr_base = 0x1c70000000, 67 .ddr_limit = 0x2470000000, 68 .ddr_dest_fabid = 0, 69 .ddr_sock_ileave_bits = 0, 70 .ddr_die_ileave_bits = 0, 71 .ddr_addr_start = 8, 72 .ddr_chan_ileave = DF_CHAN_ILEAVE_2CH 73 } }, 74 .zud_chan = { { 75 .chan_flags = UMC_CHAN_F_ECC_EN, 76 .chan_fabid = 0, 77 .chan_instid = 0, 78 .chan_logid = 0, 79 .chan_nrules = 2, 80 .chan_rules = { { 81 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_HOLE, 82 .ddr_base = 0, 83 .ddr_limit = 0x1c70000000, 84 .ddr_dest_fabid = 0, 85 .ddr_sock_ileave_bits = 0, 86 .ddr_die_ileave_bits = 0, 87 .ddr_addr_start = 8, 88 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 89 }, { 90 .ddr_flags = DF_DRAM_F_VALID, 91 .ddr_base = 0x1c70000000, 92 .ddr_limit = 0x2470000000, 93 .ddr_dest_fabid = 0, 94 .ddr_sock_ileave_bits = 0, 95 .ddr_die_ileave_bits = 0, 96 .ddr_addr_start = 8, 97 .ddr_chan_ileave = DF_CHAN_ILEAVE_2CH 98 } }, 99 .chan_offsets = { { 100 .cho_valid = B_TRUE, 101 .cho_offset = 0x1c00000000, 102 } }, 103 .chan_dimms = { { 104 .ud_flags = UMC_DIMM_F_VALID, 105 .ud_width = UMC_DIMM_W_X4, 106 .ud_type = UMC_DIMM_T_DDR4, 107 .ud_kind = UMC_DIMM_K_RDIMM, 108 .ud_dimmno = 0, 109 .ud_cs = { { 110 .ucs_base = { 111 .udb_base = 0, 112 .udb_valid = B_TRUE 113 }, 114 .ucs_base_mask = 0x7ffffffff, 115 .ucs_nbanks = 0x4, 116 .ucs_ncol = 0xa, 117 .ucs_nrow_lo = 0x12, 118 .ucs_nbank_groups = 0x2, 119 .ucs_row_hi_bit = 0x18, 120 .ucs_row_low_bit = 0x11, 121 .ucs_bank_bits = { 0xf, 0x10, 0xd, 122 0xe }, 123 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 124 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 125 }, { 126 .ucs_base = { 127 .udb_base = 0x800000000, 128 .udb_valid = B_TRUE 129 }, 130 .ucs_base_mask = 0x7ffffffff, 131 .ucs_nbanks = 0x4, 132 .ucs_ncol = 0xa, 133 .ucs_nrow_lo = 0x12, 134 .ucs_nbank_groups = 0x2, 135 .ucs_row_hi_bit = 0x18, 136 .ucs_row_low_bit = 0x11, 137 .ucs_bank_bits = { 0xf, 0x10, 0xd, 138 0xe }, 139 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 140 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 141 } } 142 }, { 143 .ud_flags = UMC_DIMM_F_VALID, 144 .ud_width = UMC_DIMM_W_X4, 145 .ud_type = UMC_DIMM_T_DDR4, 146 .ud_kind = UMC_DIMM_K_RDIMM, 147 .ud_dimmno = 1, 148 .ud_cs = { { 149 .ucs_base = { 150 .udb_base = 0x1000000000, 151 .udb_valid = B_TRUE 152 }, 153 .ucs_base_mask = 0x7ffffffff, 154 .ucs_nbanks = 0x4, 155 .ucs_ncol = 0xa, 156 .ucs_nrow_lo = 0x12, 157 .ucs_nbank_groups = 0x2, 158 .ucs_row_hi_bit = 0x18, 159 .ucs_row_low_bit = 0x11, 160 .ucs_bank_bits = { 0xf, 0x10, 0xd, 161 0xe }, 162 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 163 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 164 }, { 165 .ucs_base = { 166 .udb_base = 0x1800000000, 167 .udb_valid = B_TRUE 168 }, 169 .ucs_base_mask = 0x7ffffffff, 170 .ucs_nbanks = 0x4, 171 .ucs_ncol = 0xa, 172 .ucs_nrow_lo = 0x12, 173 .ucs_nbank_groups = 0x2, 174 .ucs_row_hi_bit = 0x18, 175 .ucs_row_low_bit = 0x11, 176 .ucs_bank_bits = { 0xf, 0x10, 0xd, 177 0xe }, 178 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 179 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 180 } } 181 } } 182 }, { 183 .chan_flags = UMC_CHAN_F_ECC_EN, 184 .chan_fabid = 1, 185 .chan_instid = 1, 186 .chan_logid = 1, 187 .chan_nrules = 1, 188 .chan_rules = { { 189 .ddr_flags = DF_DRAM_F_VALID, 190 .ddr_base = 0x1c70000000, 191 .ddr_limit = 0x2470000000, 192 .ddr_dest_fabid = 0, 193 .ddr_sock_ileave_bits = 0, 194 .ddr_die_ileave_bits = 0, 195 .ddr_addr_start = 8, 196 .ddr_chan_ileave = DF_CHAN_ILEAVE_2CH 197 } }, 198 .chan_dimms = { { 199 .ud_flags = UMC_DIMM_F_VALID, 200 .ud_width = UMC_DIMM_W_X8, 201 .ud_type = UMC_DIMM_T_DDR4, 202 .ud_kind = UMC_DIMM_K_RDIMM, 203 .ud_dimmno = 0, 204 .ud_cs = { { 205 .ucs_base = { 206 .udb_base = 0, 207 .udb_valid = B_TRUE 208 }, 209 .ucs_base_mask = 0x3fffdffff, 210 .ucs_nbanks = 0x4, 211 .ucs_ncol = 0xa, 212 .ucs_nrow_lo = 0x10, 213 .ucs_nbank_groups = 0x2, 214 .ucs_row_hi_bit = 0x18, 215 .ucs_row_low_bit = 0x11, 216 .ucs_bank_bits = { 0xf, 0x10, 0xd, 217 0xe }, 218 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 219 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 220 } } 221 }, { 222 .ud_flags = UMC_DIMM_F_VALID, 223 .ud_width = UMC_DIMM_W_X8, 224 .ud_type = UMC_DIMM_T_DDR4, 225 .ud_kind = UMC_DIMM_K_RDIMM, 226 .ud_dimmno = 0, 227 .ud_cs = { { 228 .ucs_base = { 229 .udb_base = 0x20000, 230 .udb_valid = B_TRUE 231 }, 232 .ucs_base_mask = 0x3fffdffff, 233 .ucs_nbanks = 0x4, 234 .ucs_ncol = 0xa, 235 .ucs_nrow_lo = 0x10, 236 .ucs_nbank_groups = 0x2, 237 .ucs_row_hi_bit = 0x18, 238 .ucs_row_low_bit = 0x11, 239 .ucs_bank_bits = { 0xf, 0x10, 0xd, 240 0xe }, 241 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 242 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 243 } } 244 } }, 245 } } 246 } } 247 }; 248 249 const umc_decode_test_t zen_umc_test_multi[] = { { 250 .udt_desc = "Multi-rule (0)", 251 .udt_umc = &zen_umc_multi, 252 .udt_pa = 0x12345603, 253 .udt_pass = B_TRUE, 254 .udt_norm_addr = 0x12345603, 255 .udt_sock = 0, 256 .udt_die = 0, 257 .udt_comp = 0, 258 .udt_dimm_no = 0, 259 .udt_dimm_col = 0x2c0, 260 .udt_dimm_row = 0x91a, 261 .udt_dimm_bank = 2, 262 .udt_dimm_bank_group = 0, 263 .udt_dimm_subchan = UINT8_MAX, 264 .udt_dimm_rm = 0, 265 .udt_dimm_cs = 0 266 267 }, { 268 .udt_desc = "Multi-rule (1)", 269 .udt_umc = &zen_umc_multi, 270 .udt_pa = 0x12345703, 271 .udt_pass = B_TRUE, 272 .udt_norm_addr = 0x12345703, 273 .udt_sock = 0, 274 .udt_die = 0, 275 .udt_comp = 0, 276 .udt_dimm_no = 0, 277 .udt_dimm_col = 0x2e0, 278 .udt_dimm_row = 0x91a, 279 .udt_dimm_bank = 2, 280 .udt_dimm_bank_group = 0, 281 .udt_dimm_subchan = UINT8_MAX, 282 .udt_dimm_rm = 0, 283 .udt_dimm_cs = 0 284 285 }, { 286 .udt_desc = "Multi-rule (2)", 287 .udt_umc = &zen_umc_multi, 288 .udt_pa = 0x1ba9876543, 289 .udt_pass = B_TRUE, 290 .udt_norm_addr = 0x1b39876543, 291 .udt_sock = 0, 292 .udt_die = 0, 293 .udt_comp = 0, 294 .udt_dimm_no = 1, 295 .udt_dimm_col = 0xa8, 296 .udt_dimm_row = 0x19cc3, 297 .udt_dimm_bank = 3, 298 .udt_dimm_bank_group = 2, 299 .udt_dimm_subchan = UINT8_MAX, 300 .udt_dimm_rm = 0, 301 .udt_dimm_cs = 1 302 303 }, { 304 .udt_desc = "Multi-rule (3)", 305 .udt_umc = &zen_umc_multi, 306 .udt_pa = 0x1ba9876643, 307 .udt_pass = B_TRUE, 308 .udt_norm_addr = 0x1b39876643, 309 .udt_sock = 0, 310 .udt_die = 0, 311 .udt_comp = 0, 312 .udt_dimm_no = 1, 313 .udt_dimm_col = 0xc8, 314 .udt_dimm_row = 0x19cc3, 315 .udt_dimm_bank = 3, 316 .udt_dimm_bank_group = 2, 317 .udt_dimm_subchan = UINT8_MAX, 318 .udt_dimm_rm = 0, 319 .udt_dimm_cs = 1 320 }, 321 /* 322 * All of the accesses below should now hit our second rule. When normalizing we 323 * subtract the base and add the channel offset. So that is why the normalized 324 * address will look totally different depending on which DIMM we go to. 325 */ 326 { 327 .udt_desc = "Multi-rule (4)", 328 .udt_umc = &zen_umc_multi, 329 .udt_pa = 0x1c70000000, 330 .udt_pass = B_TRUE, 331 .udt_norm_addr = 0x1c00000000, 332 .udt_sock = 0, 333 .udt_die = 0, 334 .udt_comp = 0, 335 .udt_dimm_no = 1, 336 .udt_dimm_col = 0, 337 .udt_dimm_row = 0x20000, 338 .udt_dimm_bank = 0, 339 .udt_dimm_bank_group = 0, 340 .udt_dimm_subchan = UINT8_MAX, 341 .udt_dimm_rm = 0, 342 .udt_dimm_cs = 1 343 }, { 344 .udt_desc = "Multi-rule (5)", 345 .udt_umc = &zen_umc_multi, 346 .udt_pa = 0x1c70000100, 347 .udt_pass = B_TRUE, 348 .udt_norm_addr = 0x0, 349 .udt_sock = 0, 350 .udt_die = 0, 351 .udt_comp = 1, 352 .udt_dimm_no = 0, 353 .udt_dimm_col = 0, 354 .udt_dimm_row = 0, 355 .udt_dimm_bank = 0, 356 .udt_dimm_bank_group = 0, 357 .udt_dimm_subchan = UINT8_MAX, 358 .udt_dimm_rm = 0, 359 .udt_dimm_cs = 0 360 }, { 361 .udt_desc = "Multi-rule (6)", 362 .udt_umc = &zen_umc_multi, 363 .udt_pa = 0x23456789ab, 364 .udt_pass = B_TRUE, 365 .udt_norm_addr = 0x36ab3c4ab, 366 .udt_sock = 0, 367 .udt_die = 0, 368 .udt_comp = 1, 369 .udt_dimm_no = 1, 370 .udt_dimm_col = 0x95, 371 .udt_dimm_row = 0xb559, 372 .udt_dimm_bank = 2, 373 .udt_dimm_bank_group = 3, 374 .udt_dimm_subchan = UINT8_MAX, 375 .udt_dimm_rm = 0, 376 .udt_dimm_cs = 0 377 }, { 378 .udt_desc = "Multi-rule (7)", 379 .udt_umc = &zen_umc_multi, 380 .udt_pa = 0x2345678aab, 381 .udt_pass = B_TRUE, 382 .udt_norm_addr = 0x1f6ab3c5ab, 383 .udt_sock = 0, 384 .udt_die = 0, 385 .udt_comp = 0, 386 .udt_dimm_no = 1, 387 .udt_dimm_col = 0xb5, 388 .udt_dimm_row = 0x3b559, 389 .udt_dimm_bank = 2, 390 .udt_dimm_bank_group = 3, 391 .udt_dimm_subchan = UINT8_MAX, 392 .udt_dimm_rm = 0, 393 .udt_dimm_cs = 1 394 }, { 395 .udt_desc = NULL 396 } }; 397