1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2022 Oxide Computer Company 14 */ 15 16 /* 17 * This provides a simple case with one DIMM, one channel, one socket, and no 18 * interleaving, and no DRAM hole. This sends everything to exactly one DIMM. In 19 * particular we have configurations with the following DIMM sizes: 20 * 21 * o 16 GiB RDIMM (1 rank) 22 * o 64 GiB RDIMM (2 rank) 23 * 24 * There is no hashing going on in the channel in any way here (e.g. no CS 25 * interleaving). This is basically simple linear mappings. 26 */ 27 28 #include "zen_umc_test.h" 29 30 static const zen_umc_t zen_umc_basic_1p1c1d = { 31 .umc_tom = 4ULL * 1024ULL * 1024ULL * 1024ULL, 32 .umc_tom2 = 16ULL * 1024ULL * 1024ULL * 1024ULL, 33 .umc_df_rev = DF_REV_3, 34 /* Per milan_decomp */ 35 .umc_decomp = { 36 .dfd_sock_mask = 0x01, 37 .dfd_die_mask = 0x00, 38 .dfd_node_mask = 0x20, 39 .dfd_comp_mask = 0x1f, 40 .dfd_sock_shift = 0, 41 .dfd_die_shift = 0, 42 .dfd_node_shift = 5, 43 .dfd_comp_shift = 0 44 }, 45 .umc_ndfs = 1, 46 .umc_dfs = { { 47 .zud_dfno = 0, 48 .zud_ccm_inst = 0, 49 .zud_dram_nrules = 1, 50 .zud_nchan = 1, 51 .zud_cs_nremap = 0, 52 .zud_hole_base = 0, 53 .zud_rules = { { 54 .ddr_flags = DF_DRAM_F_VALID, 55 .ddr_base = 0, 56 .ddr_limit = 16ULL * 1024ULL * 1024ULL * 1024ULL, 57 .ddr_dest_fabid = 1, 58 .ddr_sock_ileave_bits = 0, 59 .ddr_die_ileave_bits = 0, 60 .ddr_addr_start = 9, 61 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 62 } }, 63 .zud_chan = { { 64 .chan_flags = UMC_CHAN_F_ECC_EN, 65 .chan_fabid = 1, 66 .chan_instid = 1, 67 .chan_logid = 0, 68 .chan_nrules = 1, 69 .chan_rules = { { 70 .ddr_flags = DF_DRAM_F_VALID, 71 .ddr_base = 0, 72 .ddr_limit = 16ULL * 1024ULL * 1024ULL * 73 1024ULL, 74 .ddr_dest_fabid = 1, 75 .ddr_sock_ileave_bits = 0, 76 .ddr_die_ileave_bits = 0, 77 .ddr_addr_start = 9, 78 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 79 } }, 80 .chan_dimms = { { 81 .ud_flags = UMC_DIMM_F_VALID, 82 .ud_width = UMC_DIMM_W_X4, 83 .ud_type = UMC_DIMM_T_DDR4, 84 .ud_kind = UMC_DIMM_K_RDIMM, 85 .ud_dimmno = 0, 86 .ud_cs = { { 87 .ucs_base = { 88 .udb_base = 0, 89 .udb_valid = B_TRUE 90 }, 91 .ucs_base_mask = 0x3ffffffff, 92 .ucs_nbanks = 0x4, 93 .ucs_ncol = 0xa, 94 .ucs_nrow_lo = 0x11, 95 .ucs_nbank_groups = 0x2, 96 .ucs_row_hi_bit = 0x18, 97 .ucs_row_low_bit = 0x11, 98 .ucs_bank_bits = { 0xf, 0x10, 0xd, 99 0xe }, 100 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 101 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 102 } } 103 } }, 104 } } 105 } } 106 }; 107 108 static const zen_umc_t zen_umc_basic_1p1c1d_64g = { 109 .umc_tom = 4ULL * 1024ULL * 1024ULL * 1024ULL, 110 .umc_tom2 = 64ULL * 1024ULL * 1024ULL * 1024ULL, 111 .umc_df_rev = DF_REV_3, 112 /* Per milan_decomp */ 113 .umc_decomp = { 114 .dfd_sock_mask = 0x01, 115 .dfd_die_mask = 0x00, 116 .dfd_node_mask = 0x20, 117 .dfd_comp_mask = 0x1f, 118 .dfd_sock_shift = 0, 119 .dfd_die_shift = 0, 120 .dfd_node_shift = 5, 121 .dfd_comp_shift = 0 122 }, 123 .umc_ndfs = 1, 124 .umc_dfs = { { 125 .zud_dfno = 0, 126 .zud_ccm_inst = 0, 127 .zud_dram_nrules = 1, 128 .zud_nchan = 1, 129 .zud_cs_nremap = 0, 130 .zud_hole_base = 0, 131 .zud_rules = { { 132 .ddr_flags = DF_DRAM_F_VALID, 133 .ddr_base = 0, 134 .ddr_limit = 64ULL * 1024ULL * 1024ULL * 1024ULL, 135 .ddr_dest_fabid = 1, 136 .ddr_sock_ileave_bits = 0, 137 .ddr_die_ileave_bits = 0, 138 .ddr_addr_start = 9, 139 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 140 } }, 141 .zud_chan = { { 142 .chan_flags = UMC_CHAN_F_ECC_EN, 143 .chan_fabid = 1, 144 .chan_instid = 1, 145 .chan_logid = 0, 146 .chan_nrules = 1, 147 .chan_rules = { { 148 .ddr_flags = DF_DRAM_F_VALID, 149 .ddr_base = 0, 150 .ddr_limit = 64ULL * 1024ULL * 1024ULL * 151 1024ULL, 152 .ddr_dest_fabid = 1, 153 .ddr_sock_ileave_bits = 0, 154 .ddr_die_ileave_bits = 0, 155 .ddr_addr_start = 9, 156 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 157 } }, 158 .chan_dimms = { { 159 .ud_flags = UMC_DIMM_F_VALID, 160 .ud_width = UMC_DIMM_W_X4, 161 .ud_type = UMC_DIMM_T_DDR4, 162 .ud_kind = UMC_DIMM_K_RDIMM, 163 .ud_dimmno = 0, 164 .ud_cs = { { 165 .ucs_base = { 166 .udb_base = 0, 167 .udb_valid = B_TRUE 168 }, 169 .ucs_base_mask = 0x7ffffffff, 170 .ucs_nbanks = 0x4, 171 .ucs_ncol = 0xa, 172 .ucs_nrow_lo = 0x12, 173 .ucs_nbank_groups = 0x2, 174 .ucs_row_hi_bit = 0x18, 175 .ucs_row_low_bit = 0x11, 176 .ucs_bank_bits = { 0xf, 0x10, 0xd, 177 0xe }, 178 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 179 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 180 }, { 181 .ucs_base = { 182 .udb_base = 0x800000000, 183 .udb_valid = B_TRUE 184 }, 185 .ucs_base_mask = 0x7ffffffff, 186 .ucs_nbanks = 0x4, 187 .ucs_ncol = 0xa, 188 .ucs_nrow_lo = 0x12, 189 .ucs_nbank_groups = 0x2, 190 .ucs_row_hi_bit = 0x18, 191 .ucs_row_low_bit = 0x11, 192 .ucs_bank_bits = { 0xf, 0x10, 0xd, 193 0xe }, 194 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 195 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 196 } } 197 } }, 198 } } 199 } } 200 }; 201 202 const umc_decode_test_t zen_umc_test_basics[] = { { 203 .udt_desc = "decode basic single socket/channel/DIMM DDR4 (0)", 204 .udt_umc = &zen_umc_basic_1p1c1d, 205 .udt_pa = 0, 206 .udt_pass = B_TRUE, 207 .udt_norm_addr = 0, 208 .udt_sock = 0, 209 .udt_die = 0, 210 .udt_comp = 1, 211 .udt_dimm_no = 0, 212 .udt_dimm_col = 0, 213 .udt_dimm_row = 0, 214 .udt_dimm_bank = 0, 215 .udt_dimm_bank_group = 0, 216 .udt_dimm_subchan = 0, 217 .udt_dimm_rm = 0, 218 .udt_dimm_cs = 0 219 }, { 220 .udt_desc = "decode basic single socket/channel/DIMM DDR4 (1)", 221 .udt_umc = &zen_umc_basic_1p1c1d, 222 .udt_pa = 0x123, 223 .udt_pass = B_TRUE, 224 .udt_norm_addr = 0x123, 225 .udt_sock = 0, 226 .udt_die = 0, 227 .udt_comp = 1, 228 .udt_dimm_no = 0, 229 .udt_dimm_col = 0x24, 230 .udt_dimm_row = 0, 231 .udt_dimm_bank = 0, 232 .udt_dimm_bank_group = 0, 233 .udt_dimm_subchan = UINT8_MAX, 234 .udt_dimm_rm = 0, 235 .udt_dimm_cs = 0 236 }, { 237 .udt_desc = "decode basic single socket/channel/DIMM DDR4 (2)", 238 .udt_umc = &zen_umc_basic_1p1c1d, 239 .udt_pa = 0x5000, 240 .udt_pass = B_TRUE, 241 .udt_norm_addr = 0x5000, 242 .udt_sock = 0, 243 .udt_die = 0, 244 .udt_comp = 1, 245 .udt_dimm_no = 0, 246 .udt_dimm_col = 0x200, 247 .udt_dimm_row = 0, 248 .udt_dimm_bank = 0x2, 249 .udt_dimm_bank_group = 0, 250 .udt_dimm_subchan = UINT8_MAX, 251 .udt_dimm_rm = 0, 252 .udt_dimm_cs = 0 253 }, { 254 .udt_desc = "decode basic single socket/channel/DIMM DDR4 (3)", 255 .udt_umc = &zen_umc_basic_1p1c1d, 256 .udt_pa = 0x345678901, 257 .udt_pass = B_TRUE, 258 .udt_norm_addr = 0x345678901, 259 .udt_sock = 0, 260 .udt_die = 0, 261 .udt_comp = 1, 262 .udt_dimm_no = 0, 263 .udt_dimm_col = 0x120, 264 .udt_dimm_row = 0x1a2b3, 265 .udt_dimm_bank = 0, 266 .udt_dimm_bank_group = 0x3, 267 .udt_dimm_subchan = UINT8_MAX, 268 .udt_dimm_rm = 0, 269 .udt_dimm_cs = 0 270 }, { 271 .udt_desc = "decode basic single socket/channel/DIMM DDR4 (4)", 272 .udt_umc = &zen_umc_basic_1p1c1d, 273 .udt_pa = 0x3ffffffff, 274 .udt_pass = B_TRUE, 275 .udt_norm_addr = 0x3ffffffff, 276 .udt_sock = 0, 277 .udt_die = 0, 278 .udt_comp = 1, 279 .udt_dimm_no = 0, 280 .udt_dimm_col = 0x3ff, 281 .udt_dimm_row = 0x1ffff, 282 .udt_dimm_bank = 0x3, 283 .udt_dimm_bank_group = 0x3, 284 .udt_dimm_subchan = UINT8_MAX, 285 .udt_dimm_rm = 0, 286 .udt_dimm_cs = 0 287 }, { 288 .udt_desc = "single socket/channel/DIMM 2R DDR4 (0)", 289 .udt_umc = &zen_umc_basic_1p1c1d_64g, 290 .udt_pa = 0, 291 .udt_pass = B_TRUE, 292 .udt_norm_addr = 0, 293 .udt_sock = 0, 294 .udt_die = 0, 295 .udt_comp = 1, 296 .udt_dimm_no = 0, 297 .udt_dimm_col = 0, 298 .udt_dimm_row = 0, 299 .udt_dimm_bank = 0, 300 .udt_dimm_bank_group = 0, 301 .udt_dimm_subchan = 0, 302 .udt_dimm_rm = 0, 303 .udt_dimm_cs = 0 304 }, { 305 .udt_desc = "single socket/channel/DIMM 2R DDR4 (1)", 306 .udt_umc = &zen_umc_basic_1p1c1d_64g, 307 .udt_pa = 0x800000000, 308 .udt_pass = B_TRUE, 309 .udt_norm_addr = 0x800000000, 310 .udt_sock = 0, 311 .udt_die = 0, 312 .udt_comp = 1, 313 .udt_dimm_no = 0, 314 .udt_dimm_col = 0, 315 .udt_dimm_row = 0, 316 .udt_dimm_bank = 0, 317 .udt_dimm_bank_group = 0, 318 .udt_dimm_subchan = 0, 319 .udt_dimm_rm = 0, 320 .udt_dimm_cs = 1 321 }, { 322 .udt_desc = "single socket/channel/DIMM 2R DDR4 (2)", 323 .udt_umc = &zen_umc_basic_1p1c1d_64g, 324 .udt_pa = 0x876543210, 325 .udt_pass = B_TRUE, 326 .udt_norm_addr = 0x876543210, 327 .udt_sock = 0, 328 .udt_die = 0, 329 .udt_comp = 1, 330 .udt_dimm_no = 0, 331 .udt_dimm_col = 0x242, 332 .udt_dimm_row = 0x3b2a, 333 .udt_dimm_bank = 1, 334 .udt_dimm_bank_group = 0, 335 .udt_dimm_subchan = 0, 336 .udt_dimm_rm = 0, 337 .udt_dimm_cs = 1 338 }, { 339 .udt_desc = "single socket/channel/DIMM 2R DDR4 (3)", 340 .udt_umc = &zen_umc_basic_1p1c1d_64g, 341 .udt_pa = 0x076543210, 342 .udt_pass = B_TRUE, 343 .udt_norm_addr = 0x076543210, 344 .udt_sock = 0, 345 .udt_die = 0, 346 .udt_comp = 1, 347 .udt_dimm_no = 0, 348 .udt_dimm_col = 0x242, 349 .udt_dimm_row = 0x3b2a, 350 .udt_dimm_bank = 1, 351 .udt_dimm_bank_group = 0, 352 .udt_dimm_subchan = 0, 353 .udt_dimm_rm = 0, 354 .udt_dimm_cs = 0 355 }, { 356 .udt_desc = NULL 357 } }; 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