1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (C) 2012-2013 Intel Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 * 30 * Copyright 2019 Joyent, Inc. 31 */ 32 33 #ifndef __NVME_H__ 34 #define __NVME_H__ 35 36 #ifdef _KERNEL 37 #include <sys/types.h> 38 #endif 39 40 #include <sys/param.h> 41 #include <sys/endian.h> 42 43 #define NVME_PASSTHROUGH_CMD _IOWR('n', 0, struct nvme_pt_command) 44 #define NVME_RESET_CONTROLLER _IO('n', 1) 45 46 #define NVME_IO_TEST _IOWR('n', 100, struct nvme_io_test) 47 #define NVME_BIO_TEST _IOWR('n', 101, struct nvme_io_test) 48 49 /* 50 * Macros to deal with NVME revisions, as defined VS register 51 */ 52 #define NVME_REV(x, y) (((x) << 16) | ((y) << 8)) 53 #define NVME_MAJOR(r) (((r) >> 16) & 0xffff) 54 #define NVME_MINOR(r) (((r) >> 8) & 0xff) 55 56 /* 57 * Use to mark a command to apply to all namespaces, or to retrieve global 58 * log pages. 59 */ 60 #define NVME_GLOBAL_NAMESPACE_TAG ((uint32_t)0xFFFFFFFF) 61 62 /* Cap nvme to 1MB transfers driver explodes with larger sizes */ 63 #define NVME_MAX_XFER_SIZE (MAXPHYS < (1<<20) ? MAXPHYS : (1<<20)) 64 65 /* Register field definitions */ 66 #define NVME_CAP_LO_REG_MQES_SHIFT (0) 67 #define NVME_CAP_LO_REG_MQES_MASK (0xFFFF) 68 #define NVME_CAP_LO_REG_CQR_SHIFT (16) 69 #define NVME_CAP_LO_REG_CQR_MASK (0x1) 70 #define NVME_CAP_LO_REG_AMS_SHIFT (17) 71 #define NVME_CAP_LO_REG_AMS_MASK (0x3) 72 #define NVME_CAP_LO_REG_TO_SHIFT (24) 73 #define NVME_CAP_LO_REG_TO_MASK (0xFF) 74 75 #define NVME_CAP_HI_REG_DSTRD_SHIFT (0) 76 #define NVME_CAP_HI_REG_DSTRD_MASK (0xF) 77 #define NVME_CAP_HI_REG_CSS_NVM_SHIFT (5) 78 #define NVME_CAP_HI_REG_CSS_NVM_MASK (0x1) 79 #define NVME_CAP_HI_REG_MPSMIN_SHIFT (16) 80 #define NVME_CAP_HI_REG_MPSMIN_MASK (0xF) 81 #define NVME_CAP_HI_REG_MPSMAX_SHIFT (20) 82 #define NVME_CAP_HI_REG_MPSMAX_MASK (0xF) 83 84 #define NVME_CC_REG_EN_SHIFT (0) 85 #define NVME_CC_REG_EN_MASK (0x1) 86 #define NVME_CC_REG_CSS_SHIFT (4) 87 #define NVME_CC_REG_CSS_MASK (0x7) 88 #define NVME_CC_REG_MPS_SHIFT (7) 89 #define NVME_CC_REG_MPS_MASK (0xF) 90 #define NVME_CC_REG_AMS_SHIFT (11) 91 #define NVME_CC_REG_AMS_MASK (0x7) 92 #define NVME_CC_REG_SHN_SHIFT (14) 93 #define NVME_CC_REG_SHN_MASK (0x3) 94 #define NVME_CC_REG_IOSQES_SHIFT (16) 95 #define NVME_CC_REG_IOSQES_MASK (0xF) 96 #define NVME_CC_REG_IOCQES_SHIFT (20) 97 #define NVME_CC_REG_IOCQES_MASK (0xF) 98 99 #define NVME_CSTS_REG_RDY_SHIFT (0) 100 #define NVME_CSTS_REG_RDY_MASK (0x1) 101 #define NVME_CSTS_REG_CFS_SHIFT (1) 102 #define NVME_CSTS_REG_CFS_MASK (0x1) 103 #define NVME_CSTS_REG_SHST_SHIFT (2) 104 #define NVME_CSTS_REG_SHST_MASK (0x3) 105 106 #define NVME_CSTS_GET_SHST(csts) (((csts) >> NVME_CSTS_REG_SHST_SHIFT) & NVME_CSTS_REG_SHST_MASK) 107 108 #define NVME_AQA_REG_ASQS_SHIFT (0) 109 #define NVME_AQA_REG_ASQS_MASK (0xFFF) 110 #define NVME_AQA_REG_ACQS_SHIFT (16) 111 #define NVME_AQA_REG_ACQS_MASK (0xFFF) 112 113 /* Command field definitions */ 114 115 #define NVME_CMD_FUSE_SHIFT (8) 116 #define NVME_CMD_FUSE_MASK (0x3) 117 118 #define NVME_STATUS_P_SHIFT (0) 119 #define NVME_STATUS_P_MASK (0x1) 120 #define NVME_STATUS_SC_SHIFT (1) 121 #define NVME_STATUS_SC_MASK (0xFF) 122 #define NVME_STATUS_SCT_SHIFT (9) 123 #define NVME_STATUS_SCT_MASK (0x7) 124 #define NVME_STATUS_M_SHIFT (14) 125 #define NVME_STATUS_M_MASK (0x1) 126 #define NVME_STATUS_DNR_SHIFT (15) 127 #define NVME_STATUS_DNR_MASK (0x1) 128 129 #define NVME_STATUS_GET_P(st) (((st) >> NVME_STATUS_P_SHIFT) & NVME_STATUS_P_MASK) 130 #define NVME_STATUS_GET_SC(st) (((st) >> NVME_STATUS_SC_SHIFT) & NVME_STATUS_SC_MASK) 131 #define NVME_STATUS_GET_SCT(st) (((st) >> NVME_STATUS_SCT_SHIFT) & NVME_STATUS_SCT_MASK) 132 #define NVME_STATUS_GET_M(st) (((st) >> NVME_STATUS_M_SHIFT) & NVME_STATUS_M_MASK) 133 #define NVME_STATUS_GET_DNR(st) (((st) >> NVME_STATUS_DNR_SHIFT) & NVME_STATUS_DNR_MASK) 134 135 #define NVME_PWR_ST_MPS_SHIFT (0) 136 #define NVME_PWR_ST_MPS_MASK (0x1) 137 #define NVME_PWR_ST_NOPS_SHIFT (1) 138 #define NVME_PWR_ST_NOPS_MASK (0x1) 139 #define NVME_PWR_ST_RRT_SHIFT (0) 140 #define NVME_PWR_ST_RRT_MASK (0x1F) 141 #define NVME_PWR_ST_RRL_SHIFT (0) 142 #define NVME_PWR_ST_RRL_MASK (0x1F) 143 #define NVME_PWR_ST_RWT_SHIFT (0) 144 #define NVME_PWR_ST_RWT_MASK (0x1F) 145 #define NVME_PWR_ST_RWL_SHIFT (0) 146 #define NVME_PWR_ST_RWL_MASK (0x1F) 147 #define NVME_PWR_ST_IPS_SHIFT (6) 148 #define NVME_PWR_ST_IPS_MASK (0x3) 149 #define NVME_PWR_ST_APW_SHIFT (0) 150 #define NVME_PWR_ST_APW_MASK (0x7) 151 #define NVME_PWR_ST_APS_SHIFT (6) 152 #define NVME_PWR_ST_APS_MASK (0x3) 153 154 /** Controller Multi-path I/O and Namespace Sharing Capabilities */ 155 /* More then one port */ 156 #define NVME_CTRLR_DATA_MIC_MPORTS_SHIFT (0) 157 #define NVME_CTRLR_DATA_MIC_MPORTS_MASK (0x1) 158 /* More then one controller */ 159 #define NVME_CTRLR_DATA_MIC_MCTRLRS_SHIFT (1) 160 #define NVME_CTRLR_DATA_MIC_MCTRLRS_MASK (0x1) 161 /* SR-IOV Virtual Function */ 162 #define NVME_CTRLR_DATA_MIC_SRIOVVF_SHIFT (2) 163 #define NVME_CTRLR_DATA_MIC_SRIOVVF_MASK (0x1) 164 165 /** OACS - optional admin command support */ 166 /* supports security send/receive commands */ 167 #define NVME_CTRLR_DATA_OACS_SECURITY_SHIFT (0) 168 #define NVME_CTRLR_DATA_OACS_SECURITY_MASK (0x1) 169 /* supports format nvm command */ 170 #define NVME_CTRLR_DATA_OACS_FORMAT_SHIFT (1) 171 #define NVME_CTRLR_DATA_OACS_FORMAT_MASK (0x1) 172 /* supports firmware activate/download commands */ 173 #define NVME_CTRLR_DATA_OACS_FIRMWARE_SHIFT (2) 174 #define NVME_CTRLR_DATA_OACS_FIRMWARE_MASK (0x1) 175 /* supports namespace management commands */ 176 #define NVME_CTRLR_DATA_OACS_NSMGMT_SHIFT (3) 177 #define NVME_CTRLR_DATA_OACS_NSMGMT_MASK (0x1) 178 /* supports Device Self-test command */ 179 #define NVME_CTRLR_DATA_OACS_SELFTEST_SHIFT (4) 180 #define NVME_CTRLR_DATA_OACS_SELFTEST_MASK (0x1) 181 /* supports Directives */ 182 #define NVME_CTRLR_DATA_OACS_DIRECTIVES_SHIFT (5) 183 #define NVME_CTRLR_DATA_OACS_DIRECTIVES_MASK (0x1) 184 /* supports NVMe-MI Send/Receive */ 185 #define NVME_CTRLR_DATA_OACS_NVMEMI_SHIFT (6) 186 #define NVME_CTRLR_DATA_OACS_NVMEMI_MASK (0x1) 187 /* supports Virtualization Management */ 188 #define NVME_CTRLR_DATA_OACS_VM_SHIFT (7) 189 #define NVME_CTRLR_DATA_OACS_VM_MASK (0x1) 190 /* supports Doorbell Buffer Config */ 191 #define NVME_CTRLR_DATA_OACS_DBBUFFER_SHIFT (8) 192 #define NVME_CTRLR_DATA_OACS_DBBUFFER_MASK (0x1) 193 194 /** firmware updates */ 195 /* first slot is read-only */ 196 #define NVME_CTRLR_DATA_FRMW_SLOT1_RO_SHIFT (0) 197 #define NVME_CTRLR_DATA_FRMW_SLOT1_RO_MASK (0x1) 198 /* number of firmware slots */ 199 #define NVME_CTRLR_DATA_FRMW_NUM_SLOTS_SHIFT (1) 200 #define NVME_CTRLR_DATA_FRMW_NUM_SLOTS_MASK (0x7) 201 202 /** log page attributes */ 203 /* per namespace smart/health log page */ 204 #define NVME_CTRLR_DATA_LPA_NS_SMART_SHIFT (0) 205 #define NVME_CTRLR_DATA_LPA_NS_SMART_MASK (0x1) 206 207 /** AVSCC - admin vendor specific command configuration */ 208 /* admin vendor specific commands use spec format */ 209 #define NVME_CTRLR_DATA_AVSCC_SPEC_FORMAT_SHIFT (0) 210 #define NVME_CTRLR_DATA_AVSCC_SPEC_FORMAT_MASK (0x1) 211 212 /** Autonomous Power State Transition Attributes */ 213 /* Autonomous Power State Transitions supported */ 214 #define NVME_CTRLR_DATA_APSTA_APST_SUPP_SHIFT (0) 215 #define NVME_CTRLR_DATA_APSTA_APST_SUPP_MASK (0x1) 216 217 /** submission queue entry size */ 218 #define NVME_CTRLR_DATA_SQES_MIN_SHIFT (0) 219 #define NVME_CTRLR_DATA_SQES_MIN_MASK (0xF) 220 #define NVME_CTRLR_DATA_SQES_MAX_SHIFT (4) 221 #define NVME_CTRLR_DATA_SQES_MAX_MASK (0xF) 222 223 /** completion queue entry size */ 224 #define NVME_CTRLR_DATA_CQES_MIN_SHIFT (0) 225 #define NVME_CTRLR_DATA_CQES_MIN_MASK (0xF) 226 #define NVME_CTRLR_DATA_CQES_MAX_SHIFT (4) 227 #define NVME_CTRLR_DATA_CQES_MAX_MASK (0xF) 228 229 /** optional nvm command support */ 230 #define NVME_CTRLR_DATA_ONCS_COMPARE_SHIFT (0) 231 #define NVME_CTRLR_DATA_ONCS_COMPARE_MASK (0x1) 232 #define NVME_CTRLR_DATA_ONCS_WRITE_UNC_SHIFT (1) 233 #define NVME_CTRLR_DATA_ONCS_WRITE_UNC_MASK (0x1) 234 #define NVME_CTRLR_DATA_ONCS_DSM_SHIFT (2) 235 #define NVME_CTRLR_DATA_ONCS_DSM_MASK (0x1) 236 #define NVME_CTRLR_DATA_ONCS_WRZERO_SHIFT (3) 237 #define NVME_CTRLR_DATA_ONCS_WRZERO_MASK (0x1) 238 #define NVME_CTRLR_DATA_ONCS_SAVEFEAT_SHIFT (4) 239 #define NVME_CTRLR_DATA_ONCS_SAVEFEAT_MASK (0x1) 240 #define NVME_CTRLR_DATA_ONCS_RESERV_SHIFT (5) 241 #define NVME_CTRLR_DATA_ONCS_RESERV_MASK (0x1) 242 #define NVME_CTRLR_DATA_ONCS_TIMESTAMP_SHIFT (6) 243 #define NVME_CTRLR_DATA_ONCS_TIMESTAMP_MASK (0x1) 244 245 /** Fused Operation Support */ 246 #define NVME_CTRLR_DATA_FUSES_CNW_SHIFT (0) 247 #define NVME_CTRLR_DATA_FUSES_CNW_MASK (0x1) 248 249 /** Format NVM Attributes */ 250 #define NVME_CTRLR_DATA_FNA_FORMAT_ALL_SHIFT (0) 251 #define NVME_CTRLR_DATA_FNA_FORMAT_ALL_MASK (0x1) 252 #define NVME_CTRLR_DATA_FNA_ERASE_ALL_SHIFT (1) 253 #define NVME_CTRLR_DATA_FNA_ERASE_ALL_MASK (0x1) 254 #define NVME_CTRLR_DATA_FNA_CRYPTO_ERASE_SHIFT (2) 255 #define NVME_CTRLR_DATA_FNA_CRYPTO_ERASE_MASK (0x1) 256 257 /** volatile write cache */ 258 #define NVME_CTRLR_DATA_VWC_PRESENT_SHIFT (0) 259 #define NVME_CTRLR_DATA_VWC_PRESENT_MASK (0x1) 260 261 /** namespace features */ 262 /* thin provisioning */ 263 #define NVME_NS_DATA_NSFEAT_THIN_PROV_SHIFT (0) 264 #define NVME_NS_DATA_NSFEAT_THIN_PROV_MASK (0x1) 265 /* NAWUN, NAWUPF, and NACWU fields are valid */ 266 #define NVME_NS_DATA_NSFEAT_NA_FIELDS_SHIFT (1) 267 #define NVME_NS_DATA_NSFEAT_NA_FIELDS_MASK (0x1) 268 /* Deallocated or Unwritten Logical Block errors supported */ 269 #define NVME_NS_DATA_NSFEAT_DEALLOC_SHIFT (2) 270 #define NVME_NS_DATA_NSFEAT_DEALLOC_MASK (0x1) 271 /* NGUID and EUI64 fields are not reusable */ 272 #define NVME_NS_DATA_NSFEAT_NO_ID_REUSE_SHIFT (3) 273 #define NVME_NS_DATA_NSFEAT_NO_ID_REUSE_MASK (0x1) 274 275 /** formatted lba size */ 276 #define NVME_NS_DATA_FLBAS_FORMAT_SHIFT (0) 277 #define NVME_NS_DATA_FLBAS_FORMAT_MASK (0xF) 278 #define NVME_NS_DATA_FLBAS_EXTENDED_SHIFT (4) 279 #define NVME_NS_DATA_FLBAS_EXTENDED_MASK (0x1) 280 281 /** metadata capabilities */ 282 /* metadata can be transferred as part of data prp list */ 283 #define NVME_NS_DATA_MC_EXTENDED_SHIFT (0) 284 #define NVME_NS_DATA_MC_EXTENDED_MASK (0x1) 285 /* metadata can be transferred with separate metadata pointer */ 286 #define NVME_NS_DATA_MC_POINTER_SHIFT (1) 287 #define NVME_NS_DATA_MC_POINTER_MASK (0x1) 288 289 /** end-to-end data protection capabilities */ 290 /* protection information type 1 */ 291 #define NVME_NS_DATA_DPC_PIT1_SHIFT (0) 292 #define NVME_NS_DATA_DPC_PIT1_MASK (0x1) 293 /* protection information type 2 */ 294 #define NVME_NS_DATA_DPC_PIT2_SHIFT (1) 295 #define NVME_NS_DATA_DPC_PIT2_MASK (0x1) 296 /* protection information type 3 */ 297 #define NVME_NS_DATA_DPC_PIT3_SHIFT (2) 298 #define NVME_NS_DATA_DPC_PIT3_MASK (0x1) 299 /* first eight bytes of metadata */ 300 #define NVME_NS_DATA_DPC_MD_START_SHIFT (3) 301 #define NVME_NS_DATA_DPC_MD_START_MASK (0x1) 302 /* last eight bytes of metadata */ 303 #define NVME_NS_DATA_DPC_MD_END_SHIFT (4) 304 #define NVME_NS_DATA_DPC_MD_END_MASK (0x1) 305 306 /** end-to-end data protection type settings */ 307 /* protection information type */ 308 #define NVME_NS_DATA_DPS_PIT_SHIFT (0) 309 #define NVME_NS_DATA_DPS_PIT_MASK (0x7) 310 /* 1 == protection info transferred at start of metadata */ 311 /* 0 == protection info transferred at end of metadata */ 312 #define NVME_NS_DATA_DPS_MD_START_SHIFT (3) 313 #define NVME_NS_DATA_DPS_MD_START_MASK (0x1) 314 315 /** Namespace Multi-path I/O and Namespace Sharing Capabilities */ 316 /* the namespace may be attached to two or more controllers */ 317 #define NVME_NS_DATA_NMIC_MAY_BE_SHARED_SHIFT (0) 318 #define NVME_NS_DATA_NMIC_MAY_BE_SHARED_MASK (0x1) 319 320 /** Reservation Capabilities */ 321 /* Persist Through Power Loss */ 322 #define NVME_NS_DATA_RESCAP_PTPL_SHIFT (0) 323 #define NVME_NS_DATA_RESCAP_PTPL_MASK (0x1) 324 /* supports the Write Exclusive */ 325 #define NVME_NS_DATA_RESCAP_WR_EX_SHIFT (1) 326 #define NVME_NS_DATA_RESCAP_WR_EX_MASK (0x1) 327 /* supports the Exclusive Access */ 328 #define NVME_NS_DATA_RESCAP_EX_AC_SHIFT (2) 329 #define NVME_NS_DATA_RESCAP_EX_AC_MASK (0x1) 330 /* supports the Write Exclusive – Registrants Only */ 331 #define NVME_NS_DATA_RESCAP_WR_EX_RO_SHIFT (3) 332 #define NVME_NS_DATA_RESCAP_WR_EX_RO_MASK (0x1) 333 /* supports the Exclusive Access - Registrants Only */ 334 #define NVME_NS_DATA_RESCAP_EX_AC_RO_SHIFT (4) 335 #define NVME_NS_DATA_RESCAP_EX_AC_RO_MASK (0x1) 336 /* supports the Write Exclusive – All Registrants */ 337 #define NVME_NS_DATA_RESCAP_WR_EX_AR_SHIFT (5) 338 #define NVME_NS_DATA_RESCAP_WR_EX_AR_MASK (0x1) 339 /* supports the Exclusive Access - All Registrants */ 340 #define NVME_NS_DATA_RESCAP_EX_AC_AR_SHIFT (6) 341 #define NVME_NS_DATA_RESCAP_EX_AC_AR_MASK (0x1) 342 /* Ignore Existing Key is used as defined in revision 1.3 or later */ 343 #define NVME_NS_DATA_RESCAP_IEKEY13_SHIFT (7) 344 #define NVME_NS_DATA_RESCAP_IEKEY13_MASK (0x1) 345 346 /** Format Progress Indicator */ 347 /* percentage of the Format NVM command that remains to be completed */ 348 #define NVME_NS_DATA_FPI_PERC_SHIFT (0) 349 #define NVME_NS_DATA_FPI_PERC_MASK (0x7f) 350 /* namespace supports the Format Progress Indicator */ 351 #define NVME_NS_DATA_FPI_SUPP_SHIFT (7) 352 #define NVME_NS_DATA_FPI_SUPP_MASK (0x1) 353 354 /** lba format support */ 355 /* metadata size */ 356 #define NVME_NS_DATA_LBAF_MS_SHIFT (0) 357 #define NVME_NS_DATA_LBAF_MS_MASK (0xFFFF) 358 /* lba data size */ 359 #define NVME_NS_DATA_LBAF_LBADS_SHIFT (16) 360 #define NVME_NS_DATA_LBAF_LBADS_MASK (0xFF) 361 /* relative performance */ 362 #define NVME_NS_DATA_LBAF_RP_SHIFT (24) 363 #define NVME_NS_DATA_LBAF_RP_MASK (0x3) 364 365 enum nvme_critical_warning_state { 366 NVME_CRIT_WARN_ST_AVAILABLE_SPARE = 0x1, 367 NVME_CRIT_WARN_ST_TEMPERATURE = 0x2, 368 NVME_CRIT_WARN_ST_DEVICE_RELIABILITY = 0x4, 369 NVME_CRIT_WARN_ST_READ_ONLY = 0x8, 370 NVME_CRIT_WARN_ST_VOLATILE_MEMORY_BACKUP = 0x10, 371 }; 372 #define NVME_CRIT_WARN_ST_RESERVED_MASK (0xE0) 373 374 /* slot for current FW */ 375 #define NVME_FIRMWARE_PAGE_AFI_SLOT_SHIFT (0) 376 #define NVME_FIRMWARE_PAGE_AFI_SLOT_MASK (0x7) 377 378 /* CC register SHN field values */ 379 enum shn_value { 380 NVME_SHN_NORMAL = 0x1, 381 NVME_SHN_ABRUPT = 0x2, 382 }; 383 384 /* CSTS register SHST field values */ 385 enum shst_value { 386 NVME_SHST_NORMAL = 0x0, 387 NVME_SHST_OCCURRING = 0x1, 388 NVME_SHST_COMPLETE = 0x2, 389 }; 390 391 struct nvme_registers 392 { 393 /** controller capabilities */ 394 uint32_t cap_lo; 395 uint32_t cap_hi; 396 397 uint32_t vs; /* version */ 398 uint32_t intms; /* interrupt mask set */ 399 uint32_t intmc; /* interrupt mask clear */ 400 401 /** controller configuration */ 402 uint32_t cc; 403 404 uint32_t reserved1; 405 406 /** controller status */ 407 uint32_t csts; 408 409 uint32_t reserved2; 410 411 /** admin queue attributes */ 412 uint32_t aqa; 413 414 uint64_t asq; /* admin submission queue base addr */ 415 uint64_t acq; /* admin completion queue base addr */ 416 uint32_t reserved3[0x3f2]; 417 418 struct { 419 uint32_t sq_tdbl; /* submission queue tail doorbell */ 420 uint32_t cq_hdbl; /* completion queue head doorbell */ 421 } doorbell[1] __packed; 422 } __packed; 423 424 _Static_assert(sizeof(struct nvme_registers) == 0x1008, "bad size for nvme_registers"); 425 426 struct nvme_command 427 { 428 /* dword 0 */ 429 uint8_t opc; /* opcode */ 430 uint8_t fuse; /* fused operation */ 431 uint16_t cid; /* command identifier */ 432 433 /* dword 1 */ 434 uint32_t nsid; /* namespace identifier */ 435 436 /* dword 2-3 */ 437 uint32_t rsvd2; 438 uint32_t rsvd3; 439 440 /* dword 4-5 */ 441 uint64_t mptr; /* metadata pointer */ 442 443 /* dword 6-7 */ 444 uint64_t prp1; /* prp entry 1 */ 445 446 /* dword 8-9 */ 447 uint64_t prp2; /* prp entry 2 */ 448 449 /* dword 10-15 */ 450 uint32_t cdw10; /* command-specific */ 451 uint32_t cdw11; /* command-specific */ 452 uint32_t cdw12; /* command-specific */ 453 uint32_t cdw13; /* command-specific */ 454 uint32_t cdw14; /* command-specific */ 455 uint32_t cdw15; /* command-specific */ 456 } __packed; 457 458 _Static_assert(sizeof(struct nvme_command) == 16 * 4, "bad size for nvme_command"); 459 460 struct nvme_completion { 461 462 /* dword 0 */ 463 uint32_t cdw0; /* command-specific */ 464 465 /* dword 1 */ 466 uint32_t rsvd1; 467 468 /* dword 2 */ 469 uint16_t sqhd; /* submission queue head pointer */ 470 uint16_t sqid; /* submission queue identifier */ 471 472 /* dword 3 */ 473 uint16_t cid; /* command identifier */ 474 uint16_t status; 475 } __packed; 476 477 _Static_assert(sizeof(struct nvme_completion) == 4 * 4, "bad size for nvme_completion"); 478 479 struct nvme_dsm_range { 480 uint32_t attributes; 481 uint32_t length; 482 uint64_t starting_lba; 483 } __packed; 484 485 /* Largest DSM Trim that can be done */ 486 #define NVME_MAX_DSM_TRIM 4096 487 488 _Static_assert(sizeof(struct nvme_dsm_range) == 16, "bad size for nvme_dsm_ranage"); 489 490 /* status code types */ 491 enum nvme_status_code_type { 492 NVME_SCT_GENERIC = 0x0, 493 NVME_SCT_COMMAND_SPECIFIC = 0x1, 494 NVME_SCT_MEDIA_ERROR = 0x2, 495 /* 0x3-0x6 - reserved */ 496 NVME_SCT_VENDOR_SPECIFIC = 0x7, 497 }; 498 499 /* generic command status codes */ 500 enum nvme_generic_command_status_code { 501 NVME_SC_SUCCESS = 0x00, 502 NVME_SC_INVALID_OPCODE = 0x01, 503 NVME_SC_INVALID_FIELD = 0x02, 504 NVME_SC_COMMAND_ID_CONFLICT = 0x03, 505 NVME_SC_DATA_TRANSFER_ERROR = 0x04, 506 NVME_SC_ABORTED_POWER_LOSS = 0x05, 507 NVME_SC_INTERNAL_DEVICE_ERROR = 0x06, 508 NVME_SC_ABORTED_BY_REQUEST = 0x07, 509 NVME_SC_ABORTED_SQ_DELETION = 0x08, 510 NVME_SC_ABORTED_FAILED_FUSED = 0x09, 511 NVME_SC_ABORTED_MISSING_FUSED = 0x0a, 512 NVME_SC_INVALID_NAMESPACE_OR_FORMAT = 0x0b, 513 NVME_SC_COMMAND_SEQUENCE_ERROR = 0x0c, 514 NVME_SC_INVALID_SGL_SEGMENT_DESCR = 0x0d, 515 NVME_SC_INVALID_NUMBER_OF_SGL_DESCR = 0x0e, 516 NVME_SC_DATA_SGL_LENGTH_INVALID = 0x0f, 517 NVME_SC_METADATA_SGL_LENGTH_INVALID = 0x10, 518 NVME_SC_SGL_DESCRIPTOR_TYPE_INVALID = 0x11, 519 NVME_SC_INVALID_USE_OF_CMB = 0x12, 520 NVME_SC_PRP_OFFET_INVALID = 0x13, 521 NVME_SC_ATOMIC_WRITE_UNIT_EXCEEDED = 0x14, 522 NVME_SC_OPERATION_DENIED = 0x15, 523 NVME_SC_SGL_OFFSET_INVALID = 0x16, 524 /* 0x17 - reserved */ 525 NVME_SC_HOST_ID_INCONSISTENT_FORMAT = 0x18, 526 NVME_SC_KEEP_ALIVE_TIMEOUT_EXPIRED = 0x19, 527 NVME_SC_KEEP_ALIVE_TIMEOUT_INVALID = 0x1a, 528 NVME_SC_ABORTED_DUE_TO_PREEMPT = 0x1b, 529 NVME_SC_SANITIZE_FAILED = 0x1c, 530 NVME_SC_SANITIZE_IN_PROGRESS = 0x1d, 531 NVME_SC_SGL_DATA_BLOCK_GRAN_INVALID = 0x1e, 532 NVME_SC_NOT_SUPPORTED_IN_CMB = 0x1f, 533 534 NVME_SC_LBA_OUT_OF_RANGE = 0x80, 535 NVME_SC_CAPACITY_EXCEEDED = 0x81, 536 NVME_SC_NAMESPACE_NOT_READY = 0x82, 537 NVME_SC_RESERVATION_CONFLICT = 0x83, 538 NVME_SC_FORMAT_IN_PROGRESS = 0x84, 539 }; 540 541 /* command specific status codes */ 542 enum nvme_command_specific_status_code { 543 NVME_SC_COMPLETION_QUEUE_INVALID = 0x00, 544 NVME_SC_INVALID_QUEUE_IDENTIFIER = 0x01, 545 NVME_SC_MAXIMUM_QUEUE_SIZE_EXCEEDED = 0x02, 546 NVME_SC_ABORT_COMMAND_LIMIT_EXCEEDED = 0x03, 547 /* 0x04 - reserved */ 548 NVME_SC_ASYNC_EVENT_REQUEST_LIMIT_EXCEEDED = 0x05, 549 NVME_SC_INVALID_FIRMWARE_SLOT = 0x06, 550 NVME_SC_INVALID_FIRMWARE_IMAGE = 0x07, 551 NVME_SC_INVALID_INTERRUPT_VECTOR = 0x08, 552 NVME_SC_INVALID_LOG_PAGE = 0x09, 553 NVME_SC_INVALID_FORMAT = 0x0a, 554 NVME_SC_FIRMWARE_REQUIRES_RESET = 0x0b, 555 NVME_SC_INVALID_QUEUE_DELETION = 0x0c, 556 NVME_SC_FEATURE_NOT_SAVEABLE = 0x0d, 557 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x0e, 558 NVME_SC_FEATURE_NOT_NS_SPECIFIC = 0x0f, 559 NVME_SC_FW_ACT_REQUIRES_NVMS_RESET = 0x10, 560 NVME_SC_FW_ACT_REQUIRES_RESET = 0x11, 561 NVME_SC_FW_ACT_REQUIRES_TIME = 0x12, 562 NVME_SC_FW_ACT_PROHIBITED = 0x13, 563 NVME_SC_OVERLAPPING_RANGE = 0x14, 564 NVME_SC_NS_INSUFFICIENT_CAPACITY = 0x15, 565 NVME_SC_NS_ID_UNAVAILABLE = 0x16, 566 /* 0x17 - reserved */ 567 NVME_SC_NS_ALREADY_ATTACHED = 0x18, 568 NVME_SC_NS_IS_PRIVATE = 0x19, 569 NVME_SC_NS_NOT_ATTACHED = 0x1a, 570 NVME_SC_THIN_PROV_NOT_SUPPORTED = 0x1b, 571 NVME_SC_CTRLR_LIST_INVALID = 0x1c, 572 NVME_SC_SELT_TEST_IN_PROGRESS = 0x1d, 573 NVME_SC_BOOT_PART_WRITE_PROHIB = 0x1e, 574 NVME_SC_INVALID_CTRLR_ID = 0x1f, 575 NVME_SC_INVALID_SEC_CTRLR_STATE = 0x20, 576 NVME_SC_INVALID_NUM_OF_CTRLR_RESRC = 0x21, 577 NVME_SC_INVALID_RESOURCE_ID = 0x22, 578 579 NVME_SC_CONFLICTING_ATTRIBUTES = 0x80, 580 NVME_SC_INVALID_PROTECTION_INFO = 0x81, 581 NVME_SC_ATTEMPTED_WRITE_TO_RO_PAGE = 0x82, 582 }; 583 584 /* media error status codes */ 585 enum nvme_media_error_status_code { 586 NVME_SC_WRITE_FAULTS = 0x80, 587 NVME_SC_UNRECOVERED_READ_ERROR = 0x81, 588 NVME_SC_GUARD_CHECK_ERROR = 0x82, 589 NVME_SC_APPLICATION_TAG_CHECK_ERROR = 0x83, 590 NVME_SC_REFERENCE_TAG_CHECK_ERROR = 0x84, 591 NVME_SC_COMPARE_FAILURE = 0x85, 592 NVME_SC_ACCESS_DENIED = 0x86, 593 NVME_SC_DEALLOCATED_OR_UNWRITTEN = 0x87, 594 }; 595 596 /* admin opcodes */ 597 enum nvme_admin_opcode { 598 NVME_OPC_DELETE_IO_SQ = 0x00, 599 NVME_OPC_CREATE_IO_SQ = 0x01, 600 NVME_OPC_GET_LOG_PAGE = 0x02, 601 /* 0x03 - reserved */ 602 NVME_OPC_DELETE_IO_CQ = 0x04, 603 NVME_OPC_CREATE_IO_CQ = 0x05, 604 NVME_OPC_IDENTIFY = 0x06, 605 /* 0x07 - reserved */ 606 NVME_OPC_ABORT = 0x08, 607 NVME_OPC_SET_FEATURES = 0x09, 608 NVME_OPC_GET_FEATURES = 0x0a, 609 /* 0x0b - reserved */ 610 NVME_OPC_ASYNC_EVENT_REQUEST = 0x0c, 611 NVME_OPC_NAMESPACE_MANAGEMENT = 0x0d, 612 /* 0x0e-0x0f - reserved */ 613 NVME_OPC_FIRMWARE_ACTIVATE = 0x10, 614 NVME_OPC_FIRMWARE_IMAGE_DOWNLOAD = 0x11, 615 NVME_OPC_DEVICE_SELF_TEST = 0x14, 616 NVME_OPC_NAMESPACE_ATTACHMENT = 0x15, 617 NVME_OPC_KEEP_ALIVE = 0x18, 618 NVME_OPC_DIRECTIVE_SEND = 0x19, 619 NVME_OPC_DIRECTIVE_RECEIVE = 0x1a, 620 NVME_OPC_VIRTUALIZATION_MANAGEMENT = 0x1c, 621 NVME_OPC_NVME_MI_SEND = 0x1d, 622 NVME_OPC_NVME_MI_RECEIVE = 0x1e, 623 NVME_OPC_DOORBELL_BUFFER_CONFIG = 0x7c, 624 625 NVME_OPC_FORMAT_NVM = 0x80, 626 NVME_OPC_SECURITY_SEND = 0x81, 627 NVME_OPC_SECURITY_RECEIVE = 0x82, 628 NVME_OPC_SANITIZE = 0x84, 629 }; 630 631 /* nvme nvm opcodes */ 632 enum nvme_nvm_opcode { 633 NVME_OPC_FLUSH = 0x00, 634 NVME_OPC_WRITE = 0x01, 635 NVME_OPC_READ = 0x02, 636 /* 0x03 - reserved */ 637 NVME_OPC_WRITE_UNCORRECTABLE = 0x04, 638 NVME_OPC_COMPARE = 0x05, 639 /* 0x06 - reserved */ 640 NVME_OPC_WRITE_ZEROES = 0x08, 641 /* 0x07 - reserved */ 642 NVME_OPC_DATASET_MANAGEMENT = 0x09, 643 /* 0x0a-0x0c - reserved */ 644 NVME_OPC_RESERVATION_REGISTER = 0x0d, 645 NVME_OPC_RESERVATION_REPORT = 0x0e, 646 /* 0x0f-0x10 - reserved */ 647 NVME_OPC_RESERVATION_ACQUIRE = 0x11, 648 /* 0x12-0x14 - reserved */ 649 NVME_OPC_RESERVATION_RELEASE = 0x15, 650 }; 651 652 enum nvme_feature { 653 /* 0x00 - reserved */ 654 NVME_FEAT_ARBITRATION = 0x01, 655 NVME_FEAT_POWER_MANAGEMENT = 0x02, 656 NVME_FEAT_LBA_RANGE_TYPE = 0x03, 657 NVME_FEAT_TEMPERATURE_THRESHOLD = 0x04, 658 NVME_FEAT_ERROR_RECOVERY = 0x05, 659 NVME_FEAT_VOLATILE_WRITE_CACHE = 0x06, 660 NVME_FEAT_NUMBER_OF_QUEUES = 0x07, 661 NVME_FEAT_INTERRUPT_COALESCING = 0x08, 662 NVME_FEAT_INTERRUPT_VECTOR_CONFIGURATION = 0x09, 663 NVME_FEAT_WRITE_ATOMICITY = 0x0A, 664 NVME_FEAT_ASYNC_EVENT_CONFIGURATION = 0x0B, 665 NVME_FEAT_AUTONOMOUS_POWER_STATE_TRANSITION = 0x0C, 666 NVME_FEAT_HOST_MEMORY_BUFFER = 0x0D, 667 NVME_FEAT_TIMESTAMP = 0x0E, 668 NVME_FEAT_KEEP_ALIVE_TIMER = 0x0F, 669 NVME_FEAT_HOST_CONTROLLED_THERMAL_MGMT = 0x10, 670 NVME_FEAT_NON_OP_POWER_STATE_CONFIG = 0x11, 671 /* 0x12-0x77 - reserved */ 672 /* 0x78-0x7f - NVMe Management Interface */ 673 NVME_FEAT_SOFTWARE_PROGRESS_MARKER = 0x80, 674 /* 0x81-0xBF - command set specific (reserved) */ 675 /* 0xC0-0xFF - vendor specific */ 676 }; 677 678 enum nvme_dsm_attribute { 679 NVME_DSM_ATTR_INTEGRAL_READ = 0x1, 680 NVME_DSM_ATTR_INTEGRAL_WRITE = 0x2, 681 NVME_DSM_ATTR_DEALLOCATE = 0x4, 682 }; 683 684 enum nvme_activate_action { 685 NVME_AA_REPLACE_NO_ACTIVATE = 0x0, 686 NVME_AA_REPLACE_ACTIVATE = 0x1, 687 NVME_AA_ACTIVATE = 0x2, 688 }; 689 690 struct nvme_power_state { 691 /** Maximum Power */ 692 uint16_t mp; /* Maximum Power */ 693 uint8_t ps_rsvd1; 694 uint8_t mps_nops; /* Max Power Scale, Non-Operational State */ 695 696 uint32_t enlat; /* Entry Latency */ 697 uint32_t exlat; /* Exit Latency */ 698 699 uint8_t rrt; /* Relative Read Throughput */ 700 uint8_t rrl; /* Relative Read Latency */ 701 uint8_t rwt; /* Relative Write Throughput */ 702 uint8_t rwl; /* Relative Write Latency */ 703 704 uint16_t idlp; /* Idle Power */ 705 uint8_t ips; /* Idle Power Scale */ 706 uint8_t ps_rsvd8; 707 708 uint16_t actp; /* Active Power */ 709 uint8_t apw_aps; /* Active Power Workload, Active Power Scale */ 710 uint8_t ps_rsvd10[9]; 711 } __packed; 712 713 _Static_assert(sizeof(struct nvme_power_state) == 32, "bad size for nvme_power_state"); 714 715 #define NVME_SERIAL_NUMBER_LENGTH 20 716 #define NVME_MODEL_NUMBER_LENGTH 40 717 #define NVME_FIRMWARE_REVISION_LENGTH 8 718 719 struct nvme_controller_data { 720 721 /* bytes 0-255: controller capabilities and features */ 722 723 /** pci vendor id */ 724 uint16_t vid; 725 726 /** pci subsystem vendor id */ 727 uint16_t ssvid; 728 729 /** serial number */ 730 uint8_t sn[NVME_SERIAL_NUMBER_LENGTH]; 731 732 /** model number */ 733 uint8_t mn[NVME_MODEL_NUMBER_LENGTH]; 734 735 /** firmware revision */ 736 uint8_t fr[NVME_FIRMWARE_REVISION_LENGTH]; 737 738 /** recommended arbitration burst */ 739 uint8_t rab; 740 741 /** ieee oui identifier */ 742 uint8_t ieee[3]; 743 744 /** multi-interface capabilities */ 745 uint8_t mic; 746 747 /** maximum data transfer size */ 748 uint8_t mdts; 749 750 /** Controller ID */ 751 uint16_t ctrlr_id; 752 753 /** Version */ 754 uint32_t ver; 755 756 /** RTD3 Resume Latency */ 757 uint32_t rtd3r; 758 759 /** RTD3 Enter Latency */ 760 uint32_t rtd3e; 761 762 /** Optional Asynchronous Events Supported */ 763 uint32_t oaes; /* bitfield really */ 764 765 /** Controller Attributes */ 766 uint32_t ctratt; /* bitfield really */ 767 768 uint8_t reserved1[12]; 769 770 /** FRU Globally Unique Identifier */ 771 uint8_t fguid[16]; 772 773 uint8_t reserved2[128]; 774 775 /* bytes 256-511: admin command set attributes */ 776 777 /** optional admin command support */ 778 uint16_t oacs; 779 780 /** abort command limit */ 781 uint8_t acl; 782 783 /** asynchronous event request limit */ 784 uint8_t aerl; 785 786 /** firmware updates */ 787 uint8_t frmw; 788 789 /** log page attributes */ 790 uint8_t lpa; 791 792 /** error log page entries */ 793 uint8_t elpe; 794 795 /** number of power states supported */ 796 uint8_t npss; 797 798 /** admin vendor specific command configuration */ 799 uint8_t avscc; 800 801 /** Autonomous Power State Transition Attributes */ 802 uint8_t apsta; 803 804 /** Warning Composite Temperature Threshold */ 805 uint16_t wctemp; 806 807 /** Critical Composite Temperature Threshold */ 808 uint16_t cctemp; 809 810 /** Maximum Time for Firmware Activation */ 811 uint16_t mtfa; 812 813 /** Host Memory Buffer Preferred Size */ 814 uint32_t hmpre; 815 816 /** Host Memory Buffer Minimum Size */ 817 uint32_t hmmin; 818 819 /** Name space capabilities */ 820 struct { 821 /* if nsmgmt, report tnvmcap and unvmcap */ 822 uint8_t tnvmcap[16]; 823 uint8_t unvmcap[16]; 824 } __packed untncap; 825 826 /** Replay Protected Memory Block Support */ 827 uint32_t rpmbs; /* Really a bitfield */ 828 829 /** Extended Device Self-test Time */ 830 uint16_t edstt; 831 832 /** Device Self-test Options */ 833 uint8_t dsto; /* Really a bitfield */ 834 835 /** Firmware Update Granularity */ 836 uint8_t fwug; 837 838 /** Keep Alive Support */ 839 uint16_t kas; 840 841 /** Host Controlled Thermal Management Attributes */ 842 uint16_t hctma; /* Really a bitfield */ 843 844 /** Minimum Thermal Management Temperature */ 845 uint16_t mntmt; 846 847 /** Maximum Thermal Management Temperature */ 848 uint16_t mxtmt; 849 850 /** Sanitize Capabilities */ 851 uint32_t sanicap; /* Really a bitfield */ 852 853 uint8_t reserved3[180]; 854 /* bytes 512-703: nvm command set attributes */ 855 856 /** submission queue entry size */ 857 uint8_t sqes; 858 859 /** completion queue entry size */ 860 uint8_t cqes; 861 862 /** Maximum Outstanding Commands */ 863 uint16_t maxcmd; 864 865 /** number of namespaces */ 866 uint32_t nn; 867 868 /** optional nvm command support */ 869 uint16_t oncs; 870 871 /** fused operation support */ 872 uint16_t fuses; 873 874 /** format nvm attributes */ 875 uint8_t fna; 876 877 /** volatile write cache */ 878 uint8_t vwc; 879 880 /** Atomic Write Unit Normal */ 881 uint16_t awun; 882 883 /** Atomic Write Unit Power Fail */ 884 uint16_t awupf; 885 886 /** NVM Vendor Specific Command Configuration */ 887 uint8_t nvscc; 888 uint8_t reserved5; 889 890 /** Atomic Compare & Write Unit */ 891 uint16_t acwu; 892 uint16_t reserved6; 893 894 /** SGL Support */ 895 uint32_t sgls; 896 897 /* bytes 540-767: Reserved */ 898 uint8_t reserved7[228]; 899 900 /** NVM Subsystem NVMe Qualified Name */ 901 uint8_t subnqn[256]; 902 903 /* bytes 1024-1791: Reserved */ 904 uint8_t reserved8[768]; 905 906 /* bytes 1792-2047: NVMe over Fabrics specification */ 907 uint8_t reserved9[256]; 908 909 /* bytes 2048-3071: power state descriptors */ 910 struct nvme_power_state power_state[32]; 911 912 /* bytes 3072-4095: vendor specific */ 913 uint8_t vs[1024]; 914 } __packed __aligned(4); 915 916 _Static_assert(sizeof(struct nvme_controller_data) == 4096, "bad size for nvme_controller_data"); 917 918 struct nvme_namespace_data { 919 920 /** namespace size */ 921 uint64_t nsze; 922 923 /** namespace capacity */ 924 uint64_t ncap; 925 926 /** namespace utilization */ 927 uint64_t nuse; 928 929 /** namespace features */ 930 uint8_t nsfeat; 931 932 /** number of lba formats */ 933 uint8_t nlbaf; 934 935 /** formatted lba size */ 936 uint8_t flbas; 937 938 /** metadata capabilities */ 939 uint8_t mc; 940 941 /** end-to-end data protection capabilities */ 942 uint8_t dpc; 943 944 /** end-to-end data protection type settings */ 945 uint8_t dps; 946 947 /** Namespace Multi-path I/O and Namespace Sharing Capabilities */ 948 uint8_t nmic; 949 950 /** Reservation Capabilities */ 951 uint8_t rescap; 952 953 /** Format Progress Indicator */ 954 uint8_t fpi; 955 956 /** Deallocate Logical Block Features */ 957 uint8_t dlfeat; 958 959 /** Namespace Atomic Write Unit Normal */ 960 uint16_t nawun; 961 962 /** Namespace Atomic Write Unit Power Fail */ 963 uint16_t nawupf; 964 965 /** Namespace Atomic Compare & Write Unit */ 966 uint16_t nacwu; 967 968 /** Namespace Atomic Boundary Size Normal */ 969 uint16_t nabsn; 970 971 /** Namespace Atomic Boundary Offset */ 972 uint16_t nabo; 973 974 /** Namespace Atomic Boundary Size Power Fail */ 975 uint16_t nabspf; 976 977 /** Namespace Optimal IO Boundary */ 978 uint16_t noiob; 979 980 /** NVM Capacity */ 981 uint8_t nvmcap[16]; 982 983 /* bytes 64-103: Reserved */ 984 uint8_t reserved5[40]; 985 986 /** Namespace Globally Unique Identifier */ 987 uint8_t nguid[16]; 988 989 /** IEEE Extended Unique Identifier */ 990 uint8_t eui64[8]; 991 992 /** lba format support */ 993 uint32_t lbaf[16]; 994 995 uint8_t reserved6[192]; 996 997 uint8_t vendor_specific[3712]; 998 } __packed __aligned(4); 999 1000 _Static_assert(sizeof(struct nvme_namespace_data) == 4096, "bad size for nvme_namepsace_data"); 1001 1002 enum nvme_log_page { 1003 1004 /* 0x00 - reserved */ 1005 NVME_LOG_ERROR = 0x01, 1006 NVME_LOG_HEALTH_INFORMATION = 0x02, 1007 NVME_LOG_FIRMWARE_SLOT = 0x03, 1008 NVME_LOG_CHANGED_NAMESPACE = 0x04, 1009 NVME_LOG_COMMAND_EFFECT = 0x05, 1010 /* 0x06-0x7F - reserved */ 1011 /* 0x80-0xBF - I/O command set specific */ 1012 NVME_LOG_RES_NOTIFICATION = 0x80, 1013 /* 0xC0-0xFF - vendor specific */ 1014 1015 /* 1016 * The following are Intel Specific log pages, but they seem 1017 * to be widely implemented. 1018 */ 1019 INTEL_LOG_READ_LAT_LOG = 0xc1, 1020 INTEL_LOG_WRITE_LAT_LOG = 0xc2, 1021 INTEL_LOG_TEMP_STATS = 0xc5, 1022 INTEL_LOG_ADD_SMART = 0xca, 1023 INTEL_LOG_DRIVE_MKT_NAME = 0xdd, 1024 1025 /* 1026 * HGST log page, with lots ofs sub pages. 1027 */ 1028 HGST_INFO_LOG = 0xc1, 1029 }; 1030 1031 struct nvme_error_information_entry { 1032 1033 uint64_t error_count; 1034 uint16_t sqid; 1035 uint16_t cid; 1036 uint16_t status; 1037 uint16_t error_location; 1038 uint64_t lba; 1039 uint32_t nsid; 1040 uint8_t vendor_specific; 1041 uint8_t reserved[35]; 1042 } __packed __aligned(4); 1043 1044 _Static_assert(sizeof(struct nvme_error_information_entry) == 64, "bad size for nvme_error_information_entry"); 1045 1046 struct nvme_health_information_page { 1047 1048 uint8_t critical_warning; 1049 uint16_t temperature; 1050 uint8_t available_spare; 1051 uint8_t available_spare_threshold; 1052 uint8_t percentage_used; 1053 1054 uint8_t reserved[26]; 1055 1056 /* 1057 * Note that the following are 128-bit values, but are 1058 * defined as an array of 2 64-bit values. 1059 */ 1060 /* Data Units Read is always in 512-byte units. */ 1061 uint64_t data_units_read[2]; 1062 /* Data Units Written is always in 512-byte units. */ 1063 uint64_t data_units_written[2]; 1064 /* For NVM command set, this includes Compare commands. */ 1065 uint64_t host_read_commands[2]; 1066 uint64_t host_write_commands[2]; 1067 /* Controller Busy Time is reported in minutes. */ 1068 uint64_t controller_busy_time[2]; 1069 uint64_t power_cycles[2]; 1070 uint64_t power_on_hours[2]; 1071 uint64_t unsafe_shutdowns[2]; 1072 uint64_t media_errors[2]; 1073 uint64_t num_error_info_log_entries[2]; 1074 uint32_t warning_temp_time; 1075 uint32_t error_temp_time; 1076 uint16_t temp_sensor[8]; 1077 1078 uint8_t reserved2[296]; 1079 } __packed __aligned(4); 1080 1081 /* Currently sparse/smatch incorrectly packs this struct in some situations. */ 1082 #ifndef __CHECKER__ 1083 _Static_assert(sizeof(struct nvme_health_information_page) == 512, "bad size for nvme_health_information_page"); 1084 #endif 1085 1086 struct nvme_firmware_page { 1087 1088 uint8_t afi; 1089 uint8_t reserved[7]; 1090 uint64_t revision[7]; /* revisions for 7 slots */ 1091 uint8_t reserved2[448]; 1092 } __packed __aligned(4); 1093 1094 _Static_assert(sizeof(struct nvme_firmware_page) == 512, "bad size for nvme_firmware_page"); 1095 1096 struct nvme_ns_list { 1097 uint32_t ns[1024]; 1098 } __packed __aligned(4); 1099 1100 _Static_assert(sizeof(struct nvme_ns_list) == 4096, "bad size for nvme_ns_list"); 1101 1102 struct intel_log_temp_stats 1103 { 1104 uint64_t current; 1105 uint64_t overtemp_flag_last; 1106 uint64_t overtemp_flag_life; 1107 uint64_t max_temp; 1108 uint64_t min_temp; 1109 uint64_t _rsvd[5]; 1110 uint64_t max_oper_temp; 1111 uint64_t min_oper_temp; 1112 uint64_t est_offset; 1113 } __packed __aligned(4); 1114 1115 _Static_assert(sizeof(struct intel_log_temp_stats) == 13 * 8, "bad size for intel_log_temp_stats"); 1116 1117 #define NVME_TEST_MAX_THREADS 128 1118 1119 struct nvme_io_test { 1120 1121 enum nvme_nvm_opcode opc; 1122 uint32_t size; 1123 uint32_t time; /* in seconds */ 1124 uint32_t num_threads; 1125 uint32_t flags; 1126 uint64_t io_completed[NVME_TEST_MAX_THREADS]; 1127 }; 1128 1129 enum nvme_io_test_flags { 1130 1131 /* 1132 * Specifies whether dev_refthread/dev_relthread should be 1133 * called during NVME_BIO_TEST. Ignored for other test 1134 * types. 1135 */ 1136 NVME_TEST_FLAG_REFTHREAD = 0x1, 1137 }; 1138 1139 struct nvme_pt_command { 1140 1141 /* 1142 * cmd is used to specify a passthrough command to a controller or 1143 * namespace. 1144 * 1145 * The following fields from cmd may be specified by the caller: 1146 * * opc (opcode) 1147 * * nsid (namespace id) - for admin commands only 1148 * * cdw10-cdw15 1149 * 1150 * Remaining fields must be set to 0 by the caller. 1151 */ 1152 struct nvme_command cmd; 1153 1154 /* 1155 * cpl returns completion status for the passthrough command 1156 * specified by cmd. 1157 * 1158 * The following fields will be filled out by the driver, for 1159 * consumption by the caller: 1160 * * cdw0 1161 * * status (except for phase) 1162 * 1163 * Remaining fields will be set to 0 by the driver. 1164 */ 1165 struct nvme_completion cpl; 1166 1167 /* buf is the data buffer associated with this passthrough command. */ 1168 void * buf; 1169 1170 /* 1171 * len is the length of the data buffer associated with this 1172 * passthrough command. 1173 */ 1174 uint32_t len; 1175 1176 /* 1177 * is_read = 1 if the passthrough command will read data into the 1178 * supplied buffer from the controller. 1179 * 1180 * is_read = 0 if the passthrough command will write data from the 1181 * supplied buffer to the controller. 1182 */ 1183 uint32_t is_read; 1184 1185 /* 1186 * driver_lock is used by the driver only. It must be set to 0 1187 * by the caller. 1188 */ 1189 struct mtx * driver_lock; 1190 }; 1191 1192 #define nvme_completion_is_error(cpl) \ 1193 (NVME_STATUS_GET_SC((cpl)->status) != 0 || NVME_STATUS_GET_SCT((cpl)->status) != 0) 1194 1195 void nvme_strvis(uint8_t *dst, const uint8_t *src, int dstlen, int srclen); 1196 1197 #ifdef _KERNEL 1198 1199 struct bio; 1200 1201 struct nvme_namespace; 1202 struct nvme_controller; 1203 struct nvme_consumer; 1204 1205 typedef void (*nvme_cb_fn_t)(void *, const struct nvme_completion *); 1206 1207 typedef void *(*nvme_cons_ns_fn_t)(struct nvme_namespace *, void *); 1208 typedef void *(*nvme_cons_ctrlr_fn_t)(struct nvme_controller *); 1209 typedef void (*nvme_cons_async_fn_t)(void *, const struct nvme_completion *, 1210 uint32_t, void *, uint32_t); 1211 typedef void (*nvme_cons_fail_fn_t)(void *); 1212 1213 enum nvme_namespace_flags { 1214 NVME_NS_DEALLOCATE_SUPPORTED = 0x1, 1215 NVME_NS_FLUSH_SUPPORTED = 0x2, 1216 }; 1217 1218 int nvme_ctrlr_passthrough_cmd(struct nvme_controller *ctrlr, 1219 struct nvme_pt_command *pt, 1220 uint32_t nsid, int is_user_buffer, 1221 int is_admin_cmd); 1222 1223 /* Admin functions */ 1224 void nvme_ctrlr_cmd_set_feature(struct nvme_controller *ctrlr, 1225 uint8_t feature, uint32_t cdw11, 1226 void *payload, uint32_t payload_size, 1227 nvme_cb_fn_t cb_fn, void *cb_arg); 1228 void nvme_ctrlr_cmd_get_feature(struct nvme_controller *ctrlr, 1229 uint8_t feature, uint32_t cdw11, 1230 void *payload, uint32_t payload_size, 1231 nvme_cb_fn_t cb_fn, void *cb_arg); 1232 void nvme_ctrlr_cmd_get_log_page(struct nvme_controller *ctrlr, 1233 uint8_t log_page, uint32_t nsid, 1234 void *payload, uint32_t payload_size, 1235 nvme_cb_fn_t cb_fn, void *cb_arg); 1236 1237 /* NVM I/O functions */ 1238 int nvme_ns_cmd_write(struct nvme_namespace *ns, void *payload, 1239 uint64_t lba, uint32_t lba_count, nvme_cb_fn_t cb_fn, 1240 void *cb_arg); 1241 int nvme_ns_cmd_write_bio(struct nvme_namespace *ns, struct bio *bp, 1242 nvme_cb_fn_t cb_fn, void *cb_arg); 1243 int nvme_ns_cmd_read(struct nvme_namespace *ns, void *payload, 1244 uint64_t lba, uint32_t lba_count, nvme_cb_fn_t cb_fn, 1245 void *cb_arg); 1246 int nvme_ns_cmd_read_bio(struct nvme_namespace *ns, struct bio *bp, 1247 nvme_cb_fn_t cb_fn, void *cb_arg); 1248 int nvme_ns_cmd_deallocate(struct nvme_namespace *ns, void *payload, 1249 uint8_t num_ranges, nvme_cb_fn_t cb_fn, 1250 void *cb_arg); 1251 int nvme_ns_cmd_flush(struct nvme_namespace *ns, nvme_cb_fn_t cb_fn, 1252 void *cb_arg); 1253 int nvme_ns_dump(struct nvme_namespace *ns, void *virt, off_t offset, 1254 size_t len); 1255 1256 /* Registration functions */ 1257 struct nvme_consumer * nvme_register_consumer(nvme_cons_ns_fn_t ns_fn, 1258 nvme_cons_ctrlr_fn_t ctrlr_fn, 1259 nvme_cons_async_fn_t async_fn, 1260 nvme_cons_fail_fn_t fail_fn); 1261 void nvme_unregister_consumer(struct nvme_consumer *consumer); 1262 1263 /* Controller helper functions */ 1264 device_t nvme_ctrlr_get_device(struct nvme_controller *ctrlr); 1265 const struct nvme_controller_data * 1266 nvme_ctrlr_get_data(struct nvme_controller *ctrlr); 1267 1268 /* Namespace helper functions */ 1269 uint32_t nvme_ns_get_max_io_xfer_size(struct nvme_namespace *ns); 1270 uint32_t nvme_ns_get_sector_size(struct nvme_namespace *ns); 1271 uint64_t nvme_ns_get_num_sectors(struct nvme_namespace *ns); 1272 uint64_t nvme_ns_get_size(struct nvme_namespace *ns); 1273 uint32_t nvme_ns_get_flags(struct nvme_namespace *ns); 1274 const char * nvme_ns_get_serial_number(struct nvme_namespace *ns); 1275 const char * nvme_ns_get_model_number(struct nvme_namespace *ns); 1276 const struct nvme_namespace_data * 1277 nvme_ns_get_data(struct nvme_namespace *ns); 1278 uint32_t nvme_ns_get_stripesize(struct nvme_namespace *ns); 1279 1280 int nvme_ns_bio_process(struct nvme_namespace *ns, struct bio *bp, 1281 nvme_cb_fn_t cb_fn); 1282 1283 /* 1284 * Command building helper functions -- shared with CAM 1285 * These functions assume allocator zeros out cmd structure 1286 * CAM's xpt_get_ccb and the request allocator for nvme both 1287 * do zero'd allocations. 1288 */ 1289 static inline 1290 void nvme_ns_flush_cmd(struct nvme_command *cmd, uint32_t nsid) 1291 { 1292 1293 cmd->opc = NVME_OPC_FLUSH; 1294 cmd->nsid = htole32(nsid); 1295 } 1296 1297 static inline 1298 void nvme_ns_rw_cmd(struct nvme_command *cmd, uint32_t rwcmd, uint32_t nsid, 1299 uint64_t lba, uint32_t count) 1300 { 1301 cmd->opc = rwcmd; 1302 cmd->nsid = htole32(nsid); 1303 cmd->cdw10 = htole32(lba & 0xffffffffu); 1304 cmd->cdw11 = htole32(lba >> 32); 1305 cmd->cdw12 = htole32(count-1); 1306 } 1307 1308 static inline 1309 void nvme_ns_write_cmd(struct nvme_command *cmd, uint32_t nsid, 1310 uint64_t lba, uint32_t count) 1311 { 1312 nvme_ns_rw_cmd(cmd, NVME_OPC_WRITE, nsid, lba, count); 1313 } 1314 1315 static inline 1316 void nvme_ns_read_cmd(struct nvme_command *cmd, uint32_t nsid, 1317 uint64_t lba, uint32_t count) 1318 { 1319 nvme_ns_rw_cmd(cmd, NVME_OPC_READ, nsid, lba, count); 1320 } 1321 1322 static inline 1323 void nvme_ns_trim_cmd(struct nvme_command *cmd, uint32_t nsid, 1324 uint32_t num_ranges) 1325 { 1326 cmd->opc = NVME_OPC_DATASET_MANAGEMENT; 1327 cmd->nsid = htole32(nsid); 1328 cmd->cdw10 = htole32(num_ranges - 1); 1329 cmd->cdw11 = htole32(NVME_DSM_ATTR_DEALLOCATE); 1330 } 1331 1332 extern int nvme_use_nvd; 1333 1334 #endif /* _KERNEL */ 1335 1336 /* Endianess conversion functions for NVMe structs */ 1337 static inline 1338 void nvme_completion_swapbytes(struct nvme_completion *s) 1339 { 1340 1341 s->cdw0 = le32toh(s->cdw0); 1342 /* omit rsvd1 */ 1343 s->sqhd = le16toh(s->sqhd); 1344 s->sqid = le16toh(s->sqid); 1345 /* omit cid */ 1346 s->status = le16toh(s->status); 1347 } 1348 1349 static inline 1350 void nvme_power_state_swapbytes(struct nvme_power_state *s) 1351 { 1352 1353 s->mp = le16toh(s->mp); 1354 s->enlat = le32toh(s->enlat); 1355 s->exlat = le32toh(s->exlat); 1356 s->idlp = le16toh(s->idlp); 1357 s->actp = le16toh(s->actp); 1358 } 1359 1360 static inline 1361 void nvme_controller_data_swapbytes(struct nvme_controller_data *s) 1362 { 1363 int i; 1364 1365 s->vid = le16toh(s->vid); 1366 s->ssvid = le16toh(s->ssvid); 1367 s->ctrlr_id = le16toh(s->ctrlr_id); 1368 s->ver = le32toh(s->ver); 1369 s->rtd3r = le32toh(s->rtd3r); 1370 s->rtd3e = le32toh(s->rtd3e); 1371 s->oaes = le32toh(s->oaes); 1372 s->ctratt = le32toh(s->ctratt); 1373 s->oacs = le16toh(s->oacs); 1374 s->wctemp = le16toh(s->wctemp); 1375 s->cctemp = le16toh(s->cctemp); 1376 s->mtfa = le16toh(s->mtfa); 1377 s->hmpre = le32toh(s->hmpre); 1378 s->hmmin = le32toh(s->hmmin); 1379 s->rpmbs = le32toh(s->rpmbs); 1380 s->edstt = le16toh(s->edstt); 1381 s->kas = le16toh(s->kas); 1382 s->hctma = le16toh(s->hctma); 1383 s->mntmt = le16toh(s->mntmt); 1384 s->mxtmt = le16toh(s->mxtmt); 1385 s->sanicap = le32toh(s->sanicap); 1386 s->maxcmd = le16toh(s->maxcmd); 1387 s->nn = le32toh(s->nn); 1388 s->oncs = le16toh(s->oncs); 1389 s->fuses = le16toh(s->fuses); 1390 s->awun = le16toh(s->awun); 1391 s->awupf = le16toh(s->awupf); 1392 s->acwu = le16toh(s->acwu); 1393 s->sgls = le32toh(s->sgls); 1394 for (i = 0; i < 32; i++) 1395 nvme_power_state_swapbytes(&s->power_state[i]); 1396 } 1397 1398 static inline 1399 void nvme_namespace_data_swapbytes(struct nvme_namespace_data *s) 1400 { 1401 int i; 1402 1403 s->nsze = le64toh(s->nsze); 1404 s->ncap = le64toh(s->ncap); 1405 s->nuse = le64toh(s->nuse); 1406 s->nawun = le16toh(s->nawun); 1407 s->nawupf = le16toh(s->nawupf); 1408 s->nacwu = le16toh(s->nacwu); 1409 s->nabsn = le16toh(s->nabsn); 1410 s->nabo = le16toh(s->nabo); 1411 s->nabspf = le16toh(s->nabspf); 1412 s->noiob = le16toh(s->noiob); 1413 for (i = 0; i < 16; i++) 1414 s->lbaf[i] = le32toh(s->lbaf[i]); 1415 } 1416 1417 static inline 1418 void nvme_error_information_entry_swapbytes(struct nvme_error_information_entry *s) 1419 { 1420 1421 s->error_count = le64toh(s->error_count); 1422 s->sqid = le16toh(s->sqid); 1423 s->cid = le16toh(s->cid); 1424 s->status = le16toh(s->status); 1425 s->error_location = le16toh(s->error_location); 1426 s->lba = le64toh(s->lba); 1427 s->nsid = le32toh(s->nsid); 1428 } 1429 1430 static inline 1431 void nvme_le128toh(void *p) 1432 { 1433 /* 1434 * Upstream, this uses the following comparison: 1435 * #if _BYTE_ORDER != _LITTLE_ENDIAN 1436 * 1437 * Rather than keep this file in compat with only that little bit 1438 * changed, we'll just float a little patch here for now. 1439 */ 1440 #ifndef _LITTLE_ENDIAN 1441 /* Swap 16 bytes in place */ 1442 char *tmp = (char*)p; 1443 char b; 1444 int i; 1445 for (i = 0; i < 8; i++) { 1446 b = tmp[i]; 1447 tmp[i] = tmp[15-i]; 1448 tmp[15-i] = b; 1449 } 1450 #else 1451 (void)p; 1452 #endif 1453 } 1454 1455 static inline 1456 void nvme_health_information_page_swapbytes(struct nvme_health_information_page *s) 1457 { 1458 int i; 1459 1460 s->temperature = le16toh(s->temperature); 1461 nvme_le128toh((void *)s->data_units_read); 1462 nvme_le128toh((void *)s->data_units_written); 1463 nvme_le128toh((void *)s->host_read_commands); 1464 nvme_le128toh((void *)s->host_write_commands); 1465 nvme_le128toh((void *)s->controller_busy_time); 1466 nvme_le128toh((void *)s->power_cycles); 1467 nvme_le128toh((void *)s->power_on_hours); 1468 nvme_le128toh((void *)s->unsafe_shutdowns); 1469 nvme_le128toh((void *)s->media_errors); 1470 nvme_le128toh((void *)s->num_error_info_log_entries); 1471 s->warning_temp_time = le32toh(s->warning_temp_time); 1472 s->error_temp_time = le32toh(s->error_temp_time); 1473 for (i = 0; i < 8; i++) 1474 s->temp_sensor[i] = le16toh(s->temp_sensor[i]); 1475 } 1476 1477 1478 static inline 1479 void nvme_firmware_page_swapbytes(struct nvme_firmware_page *s) 1480 { 1481 int i; 1482 1483 for (i = 0; i < 7; i++) 1484 s->revision[i] = le64toh(s->revision[i]); 1485 } 1486 1487 static inline 1488 void nvme_ns_list_swapbytes(struct nvme_ns_list *s) 1489 { 1490 int i; 1491 1492 for (i = 0; i < 1024; i++) 1493 s->ns[i] = le32toh(s->ns[i]); 1494 } 1495 1496 static inline 1497 void intel_log_temp_stats_swapbytes(struct intel_log_temp_stats *s) 1498 { 1499 1500 s->current = le64toh(s->current); 1501 s->overtemp_flag_last = le64toh(s->overtemp_flag_last); 1502 s->overtemp_flag_life = le64toh(s->overtemp_flag_life); 1503 s->max_temp = le64toh(s->max_temp); 1504 s->min_temp = le64toh(s->min_temp); 1505 /* omit _rsvd[] */ 1506 s->max_oper_temp = le64toh(s->max_oper_temp); 1507 s->min_oper_temp = le64toh(s->min_oper_temp); 1508 s->est_offset = le64toh(s->est_offset); 1509 } 1510 1511 #endif /* __NVME_H__ */ 1512