xref: /illumos-gate/usr/src/contrib/bhyve/dev/nvme/nvme.h (revision 4f3f3e9a1dee62c031fa67cfe64e11d6dd3fab1b)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3  *
4  * Copyright (C) 2012-2013 Intel Corporation
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  *
28  * $FreeBSD$
29  *
30  * Copyright 2019 Joyent, Inc.
31  */
32 
33 /*
34  * illumos port notes:
35  *
36  * The upstream version of this file uses conditionals of the form
37  *	#if _BYTE_ORDER != _LITTLE_ENDIAN
38  * Rather than keep this file in compat with only that little bit changed,
39  * this is locally patched below.
40  *
41  * There is also a static assertion which has been commented out due to a
42  * problem with smatch.
43  */
44 
45 #ifndef __NVME_H__
46 #define __NVME_H__
47 
48 #ifdef _KERNEL
49 #include <sys/types.h>
50 #endif
51 
52 #include <sys/param.h>
53 #include <sys/endian.h>
54 
55 #define	NVME_PASSTHROUGH_CMD		_IOWR('n', 0, struct nvme_pt_command)
56 #define	NVME_RESET_CONTROLLER		_IO('n', 1)
57 #define	NVME_GET_NSID			_IOR('n', 2, struct nvme_get_nsid)
58 #define	NVME_GET_MAX_XFER_SIZE		_IOR('n', 3, uint64_t)
59 
60 #define	NVME_IO_TEST			_IOWR('n', 100, struct nvme_io_test)
61 #define	NVME_BIO_TEST			_IOWR('n', 101, struct nvme_io_test)
62 
63 /*
64  * Macros to deal with NVME revisions, as defined VS register
65  */
66 #define NVME_REV(x, y)			(((x) << 16) | ((y) << 8))
67 #define NVME_MAJOR(r)			(((r) >> 16) & 0xffff)
68 #define NVME_MINOR(r)			(((r) >> 8) & 0xff)
69 
70 /*
71  * Use to mark a command to apply to all namespaces, or to retrieve global
72  *  log pages.
73  */
74 #define NVME_GLOBAL_NAMESPACE_TAG	((uint32_t)0xFFFFFFFF)
75 
76 /* Host memory buffer sizes are always in 4096 byte chunks */
77 #define	NVME_HMB_UNITS			4096
78 
79 /* Many items are expressed in terms of power of two times MPS */
80 #define NVME_MPS_SHIFT			12
81 
82 /* Register field definitions */
83 #define NVME_CAP_LO_REG_MQES_SHIFT			(0)
84 #define NVME_CAP_LO_REG_MQES_MASK			(0xFFFF)
85 #define NVME_CAP_LO_REG_CQR_SHIFT			(16)
86 #define NVME_CAP_LO_REG_CQR_MASK			(0x1)
87 #define NVME_CAP_LO_REG_AMS_SHIFT			(17)
88 #define NVME_CAP_LO_REG_AMS_MASK			(0x3)
89 #define NVME_CAP_LO_REG_TO_SHIFT			(24)
90 #define NVME_CAP_LO_REG_TO_MASK				(0xFF)
91 #define NVME_CAP_LO_MQES(x) \
92 	(((x) >> NVME_CAP_LO_REG_MQES_SHIFT) & NVME_CAP_LO_REG_MQES_MASK)
93 #define NVME_CAP_LO_CQR(x) \
94 	(((x) >> NVME_CAP_LO_REG_CQR_SHIFT) & NVME_CAP_LO_REG_CQR_MASK)
95 #define NVME_CAP_LO_AMS(x) \
96 	(((x) >> NVME_CAP_LO_REG_AMS_SHIFT) & NVME_CAP_LO_REG_AMS_MASK)
97 #define NVME_CAP_LO_TO(x) \
98 	(((x) >> NVME_CAP_LO_REG_TO_SHIFT) & NVME_CAP_LO_REG_TO_MASK)
99 
100 #define NVME_CAP_HI_REG_DSTRD_SHIFT			(0)
101 #define NVME_CAP_HI_REG_DSTRD_MASK			(0xF)
102 #define NVME_CAP_HI_REG_NSSRS_SHIFT			(4)
103 #define NVME_CAP_HI_REG_NSSRS_MASK			(0x1)
104 #define NVME_CAP_HI_REG_CSS_SHIFT			(5)
105 #define NVME_CAP_HI_REG_CSS_MASK			(0xff)
106 #define NVME_CAP_HI_REG_CSS_NVM_SHIFT			(5)
107 #define NVME_CAP_HI_REG_CSS_NVM_MASK			(0x1)
108 #define NVME_CAP_HI_REG_BPS_SHIFT			(13)
109 #define NVME_CAP_HI_REG_BPS_MASK			(0x1)
110 #define NVME_CAP_HI_REG_MPSMIN_SHIFT			(16)
111 #define NVME_CAP_HI_REG_MPSMIN_MASK			(0xF)
112 #define NVME_CAP_HI_REG_MPSMAX_SHIFT			(20)
113 #define NVME_CAP_HI_REG_MPSMAX_MASK			(0xF)
114 #define NVME_CAP_HI_REG_PMRS_SHIFT			(24)
115 #define NVME_CAP_HI_REG_PMRS_MASK			(0x1)
116 #define NVME_CAP_HI_REG_CMBS_SHIFT			(25)
117 #define NVME_CAP_HI_REG_CMBS_MASK			(0x1)
118 #define NVME_CAP_HI_DSTRD(x) \
119 	(((x) >> NVME_CAP_HI_REG_DSTRD_SHIFT) & NVME_CAP_HI_REG_DSTRD_MASK)
120 #define NVME_CAP_HI_NSSRS(x) \
121 	(((x) >> NVME_CAP_HI_REG_NSSRS_SHIFT) & NVME_CAP_HI_REG_NSSRS_MASK)
122 #define NVME_CAP_HI_CSS(x) \
123 	(((x) >> NVME_CAP_HI_REG_CSS_SHIFT) & NVME_CAP_HI_REG_CSS_MASK)
124 #define NVME_CAP_HI_CSS_NVM(x) \
125 	(((x) >> NVME_CAP_HI_REG_CSS_NVM_SHIFT) & NVME_CAP_HI_REG_CSS_NVM_MASK)
126 #define NVME_CAP_HI_BPS(x) \
127 	(((x) >> NVME_CAP_HI_REG_BPS_SHIFT) & NVME_CAP_HI_REG_BPS_MASK)
128 #define NVME_CAP_HI_MPSMIN(x) \
129 	(((x) >> NVME_CAP_HI_REG_MPSMIN_SHIFT) & NVME_CAP_HI_REG_MPSMIN_MASK)
130 #define NVME_CAP_HI_MPSMAX(x) \
131 	(((x) >> NVME_CAP_HI_REG_MPSMAX_SHIFT) & NVME_CAP_HI_REG_MPSMAX_MASK)
132 #define NVME_CAP_HI_PMRS(x) \
133 	(((x) >> NVME_CAP_HI_REG_PMRS_SHIFT) & NVME_CAP_HI_REG_PMRS_MASK)
134 #define NVME_CAP_HI_CMBS(x) \
135 	(((x) >> NVME_CAP_HI_REG_CMBS_SHIFT) & NVME_CAP_HI_REG_CMBS_MASK)
136 
137 #define NVME_CC_REG_EN_SHIFT				(0)
138 #define NVME_CC_REG_EN_MASK				(0x1)
139 #define NVME_CC_REG_CSS_SHIFT				(4)
140 #define NVME_CC_REG_CSS_MASK				(0x7)
141 #define NVME_CC_REG_MPS_SHIFT				(7)
142 #define NVME_CC_REG_MPS_MASK				(0xF)
143 #define NVME_CC_REG_AMS_SHIFT				(11)
144 #define NVME_CC_REG_AMS_MASK				(0x7)
145 #define NVME_CC_REG_SHN_SHIFT				(14)
146 #define NVME_CC_REG_SHN_MASK				(0x3)
147 #define NVME_CC_REG_IOSQES_SHIFT			(16)
148 #define NVME_CC_REG_IOSQES_MASK				(0xF)
149 #define NVME_CC_REG_IOCQES_SHIFT			(20)
150 #define NVME_CC_REG_IOCQES_MASK				(0xF)
151 
152 #define NVME_CSTS_REG_RDY_SHIFT				(0)
153 #define NVME_CSTS_REG_RDY_MASK				(0x1)
154 #define NVME_CSTS_REG_CFS_SHIFT				(1)
155 #define NVME_CSTS_REG_CFS_MASK				(0x1)
156 #define NVME_CSTS_REG_SHST_SHIFT			(2)
157 #define NVME_CSTS_REG_SHST_MASK				(0x3)
158 #define NVME_CSTS_REG_NVSRO_SHIFT			(4)
159 #define NVME_CSTS_REG_NVSRO_MASK			(0x1)
160 #define NVME_CSTS_REG_PP_SHIFT				(5)
161 #define NVME_CSTS_REG_PP_MASK				(0x1)
162 
163 #define NVME_CSTS_GET_SHST(csts)			(((csts) >> NVME_CSTS_REG_SHST_SHIFT) & NVME_CSTS_REG_SHST_MASK)
164 
165 #define NVME_AQA_REG_ASQS_SHIFT				(0)
166 #define NVME_AQA_REG_ASQS_MASK				(0xFFF)
167 #define NVME_AQA_REG_ACQS_SHIFT				(16)
168 #define NVME_AQA_REG_ACQS_MASK				(0xFFF)
169 
170 #define NVME_PMRCAP_REG_RDS_SHIFT			(3)
171 #define NVME_PMRCAP_REG_RDS_MASK			(0x1)
172 #define NVME_PMRCAP_REG_WDS_SHIFT			(4)
173 #define NVME_PMRCAP_REG_WDS_MASK			(0x1)
174 #define NVME_PMRCAP_REG_BIR_SHIFT			(5)
175 #define NVME_PMRCAP_REG_BIR_MASK			(0x7)
176 #define NVME_PMRCAP_REG_PMRTU_SHIFT			(8)
177 #define NVME_PMRCAP_REG_PMRTU_MASK			(0x3)
178 #define NVME_PMRCAP_REG_PMRWBM_SHIFT			(10)
179 #define NVME_PMRCAP_REG_PMRWBM_MASK			(0xf)
180 #define NVME_PMRCAP_REG_PMRTO_SHIFT			(16)
181 #define NVME_PMRCAP_REG_PMRTO_MASK			(0xff)
182 #define NVME_PMRCAP_REG_CMSS_SHIFT			(24)
183 #define NVME_PMRCAP_REG_CMSS_MASK			(0x1)
184 
185 #define NVME_PMRCAP_RDS(x) \
186 	(((x) >> NVME_PMRCAP_REG_RDS_SHIFT) & NVME_PMRCAP_REG_RDS_MASK)
187 #define NVME_PMRCAP_WDS(x) \
188 	(((x) >> NVME_PMRCAP_REG_WDS_SHIFT) & NVME_PMRCAP_REG_WDS_MASK)
189 #define NVME_PMRCAP_BIR(x) \
190 	(((x) >> NVME_PMRCAP_REG_BIR_SHIFT) & NVME_PMRCAP_REG_BIR_MASK)
191 #define NVME_PMRCAP_PMRTU(x) \
192 	(((x) >> NVME_PMRCAP_REG_PMRTU_SHIFT) & NVME_PMRCAP_REG_PMRTU_MASK)
193 #define NVME_PMRCAP_PMRWBM(x) \
194 	(((x) >> NVME_PMRCAP_REG_PMRWBM_SHIFT) & NVME_PMRCAP_REG_PMRWBM_MASK)
195 #define NVME_PMRCAP_PMRTO(x) \
196 	(((x) >> NVME_PMRCAP_REG_PMRTO_SHIFT) & NVME_PMRCAP_REG_PMRTO_MASK)
197 #define NVME_PMRCAP_CMSS(x) \
198 	(((x) >> NVME_PMRCAP_REG_CMSS_SHIFT) & NVME_PMRCAP_REG_CMSS_MASK)
199 
200 /* Command field definitions */
201 
202 #define NVME_CMD_FUSE_SHIFT				(8)
203 #define NVME_CMD_FUSE_MASK				(0x3)
204 
205 #define NVME_STATUS_P_SHIFT				(0)
206 #define NVME_STATUS_P_MASK				(0x1)
207 #define NVME_STATUS_SC_SHIFT				(1)
208 #define NVME_STATUS_SC_MASK				(0xFF)
209 #define NVME_STATUS_SCT_SHIFT				(9)
210 #define NVME_STATUS_SCT_MASK				(0x7)
211 #define NVME_STATUS_CRD_SHIFT				(12)
212 #define NVME_STATUS_CRD_MASK				(0x3)
213 #define NVME_STATUS_M_SHIFT				(14)
214 #define NVME_STATUS_M_MASK				(0x1)
215 #define NVME_STATUS_DNR_SHIFT				(15)
216 #define NVME_STATUS_DNR_MASK				(0x1)
217 
218 #define NVME_STATUS_GET_P(st)				(((st) >> NVME_STATUS_P_SHIFT) & NVME_STATUS_P_MASK)
219 #define NVME_STATUS_GET_SC(st)				(((st) >> NVME_STATUS_SC_SHIFT) & NVME_STATUS_SC_MASK)
220 #define NVME_STATUS_GET_SCT(st)				(((st) >> NVME_STATUS_SCT_SHIFT) & NVME_STATUS_SCT_MASK)
221 #define NVME_STATUS_GET_CRD(st)				(((st) >> NVME_STATUS_CRD_SHIFT) & NVME_STATUS_CRD_MASK)
222 #define NVME_STATUS_GET_M(st)				(((st) >> NVME_STATUS_M_SHIFT) & NVME_STATUS_M_MASK)
223 #define NVME_STATUS_GET_DNR(st)				(((st) >> NVME_STATUS_DNR_SHIFT) & NVME_STATUS_DNR_MASK)
224 
225 #define NVME_PWR_ST_MPS_SHIFT				(0)
226 #define NVME_PWR_ST_MPS_MASK				(0x1)
227 #define NVME_PWR_ST_NOPS_SHIFT				(1)
228 #define NVME_PWR_ST_NOPS_MASK				(0x1)
229 #define NVME_PWR_ST_RRT_SHIFT				(0)
230 #define NVME_PWR_ST_RRT_MASK				(0x1F)
231 #define NVME_PWR_ST_RRL_SHIFT				(0)
232 #define NVME_PWR_ST_RRL_MASK				(0x1F)
233 #define NVME_PWR_ST_RWT_SHIFT				(0)
234 #define NVME_PWR_ST_RWT_MASK				(0x1F)
235 #define NVME_PWR_ST_RWL_SHIFT				(0)
236 #define NVME_PWR_ST_RWL_MASK				(0x1F)
237 #define NVME_PWR_ST_IPS_SHIFT				(6)
238 #define NVME_PWR_ST_IPS_MASK				(0x3)
239 #define NVME_PWR_ST_APW_SHIFT				(0)
240 #define NVME_PWR_ST_APW_MASK				(0x7)
241 #define NVME_PWR_ST_APS_SHIFT				(6)
242 #define NVME_PWR_ST_APS_MASK				(0x3)
243 
244 /** Controller Multi-path I/O and Namespace Sharing Capabilities */
245 /* More then one port */
246 #define NVME_CTRLR_DATA_MIC_MPORTS_SHIFT		(0)
247 #define NVME_CTRLR_DATA_MIC_MPORTS_MASK			(0x1)
248 /* More then one controller */
249 #define NVME_CTRLR_DATA_MIC_MCTRLRS_SHIFT		(1)
250 #define NVME_CTRLR_DATA_MIC_MCTRLRS_MASK		(0x1)
251 /* SR-IOV Virtual Function */
252 #define NVME_CTRLR_DATA_MIC_SRIOVVF_SHIFT		(2)
253 #define NVME_CTRLR_DATA_MIC_SRIOVVF_MASK		(0x1)
254 /* Asymmetric Namespace Access Reporting */
255 #define NVME_CTRLR_DATA_MIC_ANAR_SHIFT			(3)
256 #define NVME_CTRLR_DATA_MIC_ANAR_MASK			(0x1)
257 
258 /** OAES - Optional Asynchronous Events Supported */
259 /* supports Namespace Attribute Notices event */
260 #define NVME_CTRLR_DATA_OAES_NS_ATTR_SHIFT		(8)
261 #define NVME_CTRLR_DATA_OAES_NS_ATTR_MASK		(0x1)
262 /* supports Firmware Activation Notices event */
263 #define NVME_CTRLR_DATA_OAES_FW_ACTIVATE_SHIFT		(9)
264 #define NVME_CTRLR_DATA_OAES_FW_ACTIVATE_MASK		(0x1)
265 /* supports Asymmetric Namespace Access Change Notices event */
266 #define NVME_CTRLR_DATA_OAES_ASYM_NS_CHANGE_SHIFT	(11)
267 #define NVME_CTRLR_DATA_OAES_ASYM_NS_CHANGE_MASK	(0x1)
268 /* supports Predictable Latency Event Aggregate Log Change Notices event */
269 #define NVME_CTRLR_DATA_OAES_PREDICT_LATENCY_SHIFT	(12)
270 #define NVME_CTRLR_DATA_OAES_PREDICT_LATENCY_MASK	(0x1)
271 /* supports LBA Status Information Notices event */
272 #define NVME_CTRLR_DATA_OAES_LBA_STATUS_SHIFT		(13)
273 #define NVME_CTRLR_DATA_OAES_LBA_STATUS_MASK		(0x1)
274 /* supports Endurance Group Event Aggregate Log Page Changes Notices event */
275 #define NVME_CTRLR_DATA_OAES_ENDURANCE_GROUP_SHIFT	(14)
276 #define NVME_CTRLR_DATA_OAES_ENDURANCE_GROUP_MASK	(0x1)
277 /* supports Normal NVM Subsystem Shutdown event */
278 #define NVME_CTRLR_DATA_OAES_NORMAL_SHUTDOWN_SHIFT	(15)
279 #define NVME_CTRLR_DATA_OAES_NORMAL_SHUTDOWN_MASK	(0x1)
280 /* supports Zone Descriptor Changed Notices event */
281 #define NVME_CTRLR_DATA_OAES_ZONE_DESC_CHANGE_SHIFT	(27)
282 #define NVME_CTRLR_DATA_OAES_ZONE_DESC_CHANGE_MASK	(0x1)
283 /* supports Discovery Log Page Change Notification event */
284 #define NVME_CTRLR_DATA_OAES_LOG_PAGE_CHANGE_SHIFT	(31)
285 #define NVME_CTRLR_DATA_OAES_LOG_PAGE_CHANGE_MASK	(0x1)
286 
287 /** OACS - optional admin command support */
288 /* supports security send/receive commands */
289 #define NVME_CTRLR_DATA_OACS_SECURITY_SHIFT		(0)
290 #define NVME_CTRLR_DATA_OACS_SECURITY_MASK		(0x1)
291 /* supports format nvm command */
292 #define NVME_CTRLR_DATA_OACS_FORMAT_SHIFT		(1)
293 #define NVME_CTRLR_DATA_OACS_FORMAT_MASK		(0x1)
294 /* supports firmware activate/download commands */
295 #define NVME_CTRLR_DATA_OACS_FIRMWARE_SHIFT		(2)
296 #define NVME_CTRLR_DATA_OACS_FIRMWARE_MASK		(0x1)
297 /* supports namespace management commands */
298 #define NVME_CTRLR_DATA_OACS_NSMGMT_SHIFT		(3)
299 #define NVME_CTRLR_DATA_OACS_NSMGMT_MASK		(0x1)
300 /* supports Device Self-test command */
301 #define NVME_CTRLR_DATA_OACS_SELFTEST_SHIFT		(4)
302 #define NVME_CTRLR_DATA_OACS_SELFTEST_MASK		(0x1)
303 /* supports Directives */
304 #define NVME_CTRLR_DATA_OACS_DIRECTIVES_SHIFT		(5)
305 #define NVME_CTRLR_DATA_OACS_DIRECTIVES_MASK		(0x1)
306 /* supports NVMe-MI Send/Receive */
307 #define NVME_CTRLR_DATA_OACS_NVMEMI_SHIFT		(6)
308 #define NVME_CTRLR_DATA_OACS_NVMEMI_MASK		(0x1)
309 /* supports Virtualization Management */
310 #define NVME_CTRLR_DATA_OACS_VM_SHIFT			(7)
311 #define NVME_CTRLR_DATA_OACS_VM_MASK			(0x1)
312 /* supports Doorbell Buffer Config */
313 #define NVME_CTRLR_DATA_OACS_DBBUFFER_SHIFT		(8)
314 #define NVME_CTRLR_DATA_OACS_DBBUFFER_MASK		(0x1)
315 /* supports Get LBA Status */
316 #define NVME_CTRLR_DATA_OACS_GETLBA_SHIFT		(9)
317 #define NVME_CTRLR_DATA_OACS_GETLBA_MASK		(0x1)
318 
319 /** firmware updates */
320 /* first slot is read-only */
321 #define NVME_CTRLR_DATA_FRMW_SLOT1_RO_SHIFT		(0)
322 #define NVME_CTRLR_DATA_FRMW_SLOT1_RO_MASK		(0x1)
323 /* number of firmware slots */
324 #define NVME_CTRLR_DATA_FRMW_NUM_SLOTS_SHIFT		(1)
325 #define NVME_CTRLR_DATA_FRMW_NUM_SLOTS_MASK		(0x7)
326 /* firmware activation without reset */
327 #define NVME_CTRLR_DATA_FRMW_ACT_WO_RESET_SHIFT		(4)
328 #define NVME_CTRLR_DATA_FRMW_ACT_WO_RESET_MASK		(0x1)
329 
330 /** log page attributes */
331 /* per namespace smart/health log page */
332 #define NVME_CTRLR_DATA_LPA_NS_SMART_SHIFT		(0)
333 #define NVME_CTRLR_DATA_LPA_NS_SMART_MASK		(0x1)
334 
335 /** AVSCC - admin vendor specific command configuration */
336 /* admin vendor specific commands use spec format */
337 #define NVME_CTRLR_DATA_AVSCC_SPEC_FORMAT_SHIFT		(0)
338 #define NVME_CTRLR_DATA_AVSCC_SPEC_FORMAT_MASK		(0x1)
339 
340 /** Autonomous Power State Transition Attributes */
341 /* Autonomous Power State Transitions supported */
342 #define NVME_CTRLR_DATA_APSTA_APST_SUPP_SHIFT		(0)
343 #define NVME_CTRLR_DATA_APSTA_APST_SUPP_MASK		(0x1)
344 
345 /** Sanitize Capabilities */
346 /* Crypto Erase Support  */
347 #define NVME_CTRLR_DATA_SANICAP_CES_SHIFT		(0)
348 #define NVME_CTRLR_DATA_SANICAP_CES_MASK		(0x1)
349 /* Block Erase Support */
350 #define NVME_CTRLR_DATA_SANICAP_BES_SHIFT		(1)
351 #define NVME_CTRLR_DATA_SANICAP_BES_MASK		(0x1)
352 /* Overwrite Support */
353 #define NVME_CTRLR_DATA_SANICAP_OWS_SHIFT		(2)
354 #define NVME_CTRLR_DATA_SANICAP_OWS_MASK		(0x1)
355 /* No-Deallocate Inhibited  */
356 #define NVME_CTRLR_DATA_SANICAP_NDI_SHIFT		(29)
357 #define NVME_CTRLR_DATA_SANICAP_NDI_MASK		(0x1)
358 /* No-Deallocate Modifies Media After Sanitize */
359 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_SHIFT		(30)
360 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_MASK		(0x3)
361 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_UNDEF		(0)
362 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_NO		(1)
363 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_YES		(2)
364 
365 /** submission queue entry size */
366 #define NVME_CTRLR_DATA_SQES_MIN_SHIFT			(0)
367 #define NVME_CTRLR_DATA_SQES_MIN_MASK			(0xF)
368 #define NVME_CTRLR_DATA_SQES_MAX_SHIFT			(4)
369 #define NVME_CTRLR_DATA_SQES_MAX_MASK			(0xF)
370 
371 /** completion queue entry size */
372 #define NVME_CTRLR_DATA_CQES_MIN_SHIFT			(0)
373 #define NVME_CTRLR_DATA_CQES_MIN_MASK			(0xF)
374 #define NVME_CTRLR_DATA_CQES_MAX_SHIFT			(4)
375 #define NVME_CTRLR_DATA_CQES_MAX_MASK			(0xF)
376 
377 /** optional nvm command support */
378 #define NVME_CTRLR_DATA_ONCS_COMPARE_SHIFT		(0)
379 #define NVME_CTRLR_DATA_ONCS_COMPARE_MASK		(0x1)
380 #define NVME_CTRLR_DATA_ONCS_WRITE_UNC_SHIFT		(1)
381 #define NVME_CTRLR_DATA_ONCS_WRITE_UNC_MASK		(0x1)
382 #define NVME_CTRLR_DATA_ONCS_DSM_SHIFT			(2)
383 #define NVME_CTRLR_DATA_ONCS_DSM_MASK			(0x1)
384 #define NVME_CTRLR_DATA_ONCS_WRZERO_SHIFT		(3)
385 #define NVME_CTRLR_DATA_ONCS_WRZERO_MASK		(0x1)
386 #define NVME_CTRLR_DATA_ONCS_SAVEFEAT_SHIFT		(4)
387 #define NVME_CTRLR_DATA_ONCS_SAVEFEAT_MASK		(0x1)
388 #define NVME_CTRLR_DATA_ONCS_RESERV_SHIFT		(5)
389 #define NVME_CTRLR_DATA_ONCS_RESERV_MASK		(0x1)
390 #define NVME_CTRLR_DATA_ONCS_TIMESTAMP_SHIFT		(6)
391 #define NVME_CTRLR_DATA_ONCS_TIMESTAMP_MASK		(0x1)
392 #define NVME_CTRLR_DATA_ONCS_VERIFY_SHIFT		(7)
393 #define NVME_CTRLR_DATA_ONCS_VERIFY_MASK		(0x1)
394 
395 /** Fused Operation Support */
396 #define NVME_CTRLR_DATA_FUSES_CNW_SHIFT		(0)
397 #define NVME_CTRLR_DATA_FUSES_CNW_MASK		(0x1)
398 
399 /** Format NVM Attributes */
400 #define NVME_CTRLR_DATA_FNA_FORMAT_ALL_SHIFT		(0)
401 #define NVME_CTRLR_DATA_FNA_FORMAT_ALL_MASK		(0x1)
402 #define NVME_CTRLR_DATA_FNA_ERASE_ALL_SHIFT		(1)
403 #define NVME_CTRLR_DATA_FNA_ERASE_ALL_MASK		(0x1)
404 #define NVME_CTRLR_DATA_FNA_CRYPTO_ERASE_SHIFT		(2)
405 #define NVME_CTRLR_DATA_FNA_CRYPTO_ERASE_MASK		(0x1)
406 
407 /** volatile write cache */
408 /* volatile write cache present */
409 #define NVME_CTRLR_DATA_VWC_PRESENT_SHIFT		(0)
410 #define NVME_CTRLR_DATA_VWC_PRESENT_MASK		(0x1)
411 /* flush all namespaces supported */
412 #define NVME_CTRLR_DATA_VWC_ALL_SHIFT			(1)
413 #define NVME_CTRLR_DATA_VWC_ALL_MASK			(0x3)
414 #define NVME_CTRLR_DATA_VWC_ALL_UNKNOWN			(0)
415 #define NVME_CTRLR_DATA_VWC_ALL_NO			(2)
416 #define NVME_CTRLR_DATA_VWC_ALL_YES			(3)
417 
418 /** namespace features */
419 /* thin provisioning */
420 #define NVME_NS_DATA_NSFEAT_THIN_PROV_SHIFT		(0)
421 #define NVME_NS_DATA_NSFEAT_THIN_PROV_MASK		(0x1)
422 /* NAWUN, NAWUPF, and NACWU fields are valid */
423 #define NVME_NS_DATA_NSFEAT_NA_FIELDS_SHIFT		(1)
424 #define NVME_NS_DATA_NSFEAT_NA_FIELDS_MASK		(0x1)
425 /* Deallocated or Unwritten Logical Block errors supported */
426 #define NVME_NS_DATA_NSFEAT_DEALLOC_SHIFT		(2)
427 #define NVME_NS_DATA_NSFEAT_DEALLOC_MASK		(0x1)
428 /* NGUID and EUI64 fields are not reusable */
429 #define NVME_NS_DATA_NSFEAT_NO_ID_REUSE_SHIFT		(3)
430 #define NVME_NS_DATA_NSFEAT_NO_ID_REUSE_MASK		(0x1)
431 /* NPWG, NPWA, NPDG, NPDA, and NOWS are valid */
432 #define NVME_NS_DATA_NSFEAT_NPVALID_SHIFT		(4)
433 #define NVME_NS_DATA_NSFEAT_NPVALID_MASK		(0x1)
434 
435 /** formatted lba size */
436 #define NVME_NS_DATA_FLBAS_FORMAT_SHIFT			(0)
437 #define NVME_NS_DATA_FLBAS_FORMAT_MASK			(0xF)
438 #define NVME_NS_DATA_FLBAS_EXTENDED_SHIFT		(4)
439 #define NVME_NS_DATA_FLBAS_EXTENDED_MASK		(0x1)
440 
441 /** metadata capabilities */
442 /* metadata can be transferred as part of data prp list */
443 #define NVME_NS_DATA_MC_EXTENDED_SHIFT			(0)
444 #define NVME_NS_DATA_MC_EXTENDED_MASK			(0x1)
445 /* metadata can be transferred with separate metadata pointer */
446 #define NVME_NS_DATA_MC_POINTER_SHIFT			(1)
447 #define NVME_NS_DATA_MC_POINTER_MASK			(0x1)
448 
449 /** end-to-end data protection capabilities */
450 /* protection information type 1 */
451 #define NVME_NS_DATA_DPC_PIT1_SHIFT			(0)
452 #define NVME_NS_DATA_DPC_PIT1_MASK			(0x1)
453 /* protection information type 2 */
454 #define NVME_NS_DATA_DPC_PIT2_SHIFT			(1)
455 #define NVME_NS_DATA_DPC_PIT2_MASK			(0x1)
456 /* protection information type 3 */
457 #define NVME_NS_DATA_DPC_PIT3_SHIFT			(2)
458 #define NVME_NS_DATA_DPC_PIT3_MASK			(0x1)
459 /* first eight bytes of metadata */
460 #define NVME_NS_DATA_DPC_MD_START_SHIFT			(3)
461 #define NVME_NS_DATA_DPC_MD_START_MASK			(0x1)
462 /* last eight bytes of metadata */
463 #define NVME_NS_DATA_DPC_MD_END_SHIFT			(4)
464 #define NVME_NS_DATA_DPC_MD_END_MASK			(0x1)
465 
466 /** end-to-end data protection type settings */
467 /* protection information type */
468 #define NVME_NS_DATA_DPS_PIT_SHIFT			(0)
469 #define NVME_NS_DATA_DPS_PIT_MASK			(0x7)
470 /* 1 == protection info transferred at start of metadata */
471 /* 0 == protection info transferred at end of metadata */
472 #define NVME_NS_DATA_DPS_MD_START_SHIFT			(3)
473 #define NVME_NS_DATA_DPS_MD_START_MASK			(0x1)
474 
475 /** Namespace Multi-path I/O and Namespace Sharing Capabilities */
476 /* the namespace may be attached to two or more controllers */
477 #define NVME_NS_DATA_NMIC_MAY_BE_SHARED_SHIFT		(0)
478 #define NVME_NS_DATA_NMIC_MAY_BE_SHARED_MASK		(0x1)
479 
480 /** Reservation Capabilities */
481 /* Persist Through Power Loss */
482 #define NVME_NS_DATA_RESCAP_PTPL_SHIFT		(0)
483 #define NVME_NS_DATA_RESCAP_PTPL_MASK		(0x1)
484 /* supports the Write Exclusive */
485 #define NVME_NS_DATA_RESCAP_WR_EX_SHIFT		(1)
486 #define NVME_NS_DATA_RESCAP_WR_EX_MASK		(0x1)
487 /* supports the Exclusive Access */
488 #define NVME_NS_DATA_RESCAP_EX_AC_SHIFT		(2)
489 #define NVME_NS_DATA_RESCAP_EX_AC_MASK		(0x1)
490 /* supports the Write Exclusive – Registrants Only */
491 #define NVME_NS_DATA_RESCAP_WR_EX_RO_SHIFT	(3)
492 #define NVME_NS_DATA_RESCAP_WR_EX_RO_MASK	(0x1)
493 /* supports the Exclusive Access - Registrants Only */
494 #define NVME_NS_DATA_RESCAP_EX_AC_RO_SHIFT	(4)
495 #define NVME_NS_DATA_RESCAP_EX_AC_RO_MASK	(0x1)
496 /* supports the Write Exclusive – All Registrants */
497 #define NVME_NS_DATA_RESCAP_WR_EX_AR_SHIFT	(5)
498 #define NVME_NS_DATA_RESCAP_WR_EX_AR_MASK	(0x1)
499 /* supports the Exclusive Access - All Registrants */
500 #define NVME_NS_DATA_RESCAP_EX_AC_AR_SHIFT	(6)
501 #define NVME_NS_DATA_RESCAP_EX_AC_AR_MASK	(0x1)
502 /* Ignore Existing Key is used as defined in revision 1.3 or later */
503 #define NVME_NS_DATA_RESCAP_IEKEY13_SHIFT	(7)
504 #define NVME_NS_DATA_RESCAP_IEKEY13_MASK	(0x1)
505 
506 /** Format Progress Indicator */
507 /* percentage of the Format NVM command that remains to be completed */
508 #define NVME_NS_DATA_FPI_PERC_SHIFT		(0)
509 #define NVME_NS_DATA_FPI_PERC_MASK		(0x7f)
510 /* namespace supports the Format Progress Indicator */
511 #define NVME_NS_DATA_FPI_SUPP_SHIFT		(7)
512 #define NVME_NS_DATA_FPI_SUPP_MASK		(0x1)
513 
514 /** Deallocate Logical Block Features */
515 /* deallocated logical block read behavior */
516 #define NVME_NS_DATA_DLFEAT_READ_SHIFT		(0)
517 #define NVME_NS_DATA_DLFEAT_READ_MASK		(0x07)
518 #define NVME_NS_DATA_DLFEAT_READ_NR		(0x00)
519 #define NVME_NS_DATA_DLFEAT_READ_00		(0x01)
520 #define NVME_NS_DATA_DLFEAT_READ_FF		(0x02)
521 /* supports the Deallocate bit in the Write Zeroes */
522 #define NVME_NS_DATA_DLFEAT_DWZ_SHIFT		(3)
523 #define NVME_NS_DATA_DLFEAT_DWZ_MASK		(0x01)
524 /* Guard field for deallocated logical blocks is set to the CRC  */
525 #define NVME_NS_DATA_DLFEAT_GCRC_SHIFT		(4)
526 #define NVME_NS_DATA_DLFEAT_GCRC_MASK		(0x01)
527 
528 /** lba format support */
529 /* metadata size */
530 #define NVME_NS_DATA_LBAF_MS_SHIFT			(0)
531 #define NVME_NS_DATA_LBAF_MS_MASK			(0xFFFF)
532 /* lba data size */
533 #define NVME_NS_DATA_LBAF_LBADS_SHIFT			(16)
534 #define NVME_NS_DATA_LBAF_LBADS_MASK			(0xFF)
535 /* relative performance */
536 #define NVME_NS_DATA_LBAF_RP_SHIFT			(24)
537 #define NVME_NS_DATA_LBAF_RP_MASK			(0x3)
538 
539 enum nvme_critical_warning_state {
540 	NVME_CRIT_WARN_ST_AVAILABLE_SPARE		= 0x1,
541 	NVME_CRIT_WARN_ST_TEMPERATURE			= 0x2,
542 	NVME_CRIT_WARN_ST_DEVICE_RELIABILITY		= 0x4,
543 	NVME_CRIT_WARN_ST_READ_ONLY			= 0x8,
544 	NVME_CRIT_WARN_ST_VOLATILE_MEMORY_BACKUP	= 0x10,
545 };
546 #define NVME_CRIT_WARN_ST_RESERVED_MASK			(0xE0)
547 #define	NVME_ASYNC_EVENT_NS_ATTRIBUTE			(0x100)
548 #define	NVME_ASYNC_EVENT_FW_ACTIVATE			(0x200)
549 
550 /* slot for current FW */
551 #define NVME_FIRMWARE_PAGE_AFI_SLOT_SHIFT		(0)
552 #define NVME_FIRMWARE_PAGE_AFI_SLOT_MASK		(0x7)
553 
554 /* Commands Supported and Effects */
555 #define	NVME_CE_PAGE_CSUP_SHIFT				(0)
556 #define	NVME_CE_PAGE_CSUP_MASK				(0x1)
557 #define	NVME_CE_PAGE_LBCC_SHIFT				(1)
558 #define	NVME_CE_PAGE_LBCC_MASK				(0x1)
559 #define	NVME_CE_PAGE_NCC_SHIFT				(2)
560 #define	NVME_CE_PAGE_NCC_MASK				(0x1)
561 #define	NVME_CE_PAGE_NIC_SHIFT				(3)
562 #define	NVME_CE_PAGE_NIC_MASK				(0x1)
563 #define	NVME_CE_PAGE_CCC_SHIFT				(4)
564 #define	NVME_CE_PAGE_CCC_MASK				(0x1)
565 #define	NVME_CE_PAGE_CSE_SHIFT				(16)
566 #define	NVME_CE_PAGE_CSE_MASK				(0x7)
567 #define	NVME_CE_PAGE_UUID_SHIFT				(19)
568 #define	NVME_CE_PAGE_UUID_MASK				(0x1)
569 
570 /* Sanitize Status */
571 #define	NVME_SS_PAGE_SSTAT_STATUS_SHIFT			(0)
572 #define	NVME_SS_PAGE_SSTAT_STATUS_MASK			(0x7)
573 #define	NVME_SS_PAGE_SSTAT_STATUS_NEVER			(0)
574 #define	NVME_SS_PAGE_SSTAT_STATUS_COMPLETED		(1)
575 #define	NVME_SS_PAGE_SSTAT_STATUS_INPROG		(2)
576 #define	NVME_SS_PAGE_SSTAT_STATUS_FAILED		(3)
577 #define	NVME_SS_PAGE_SSTAT_STATUS_COMPLETEDWD		(4)
578 #define	NVME_SS_PAGE_SSTAT_PASSES_SHIFT			(3)
579 #define	NVME_SS_PAGE_SSTAT_PASSES_MASK			(0x1f)
580 #define	NVME_SS_PAGE_SSTAT_GDE_SHIFT			(8)
581 #define	NVME_SS_PAGE_SSTAT_GDE_MASK			(0x1)
582 
583 /* Helper macro to combine *_MASK and *_SHIFT defines */
584 #define NVMEB(name)	(name##_MASK << name##_SHIFT)
585 
586 /* CC register SHN field values */
587 enum shn_value {
588 	NVME_SHN_NORMAL		= 0x1,
589 	NVME_SHN_ABRUPT		= 0x2,
590 };
591 
592 /* CSTS register SHST field values */
593 enum shst_value {
594 	NVME_SHST_NORMAL	= 0x0,
595 	NVME_SHST_OCCURRING	= 0x1,
596 	NVME_SHST_COMPLETE	= 0x2,
597 };
598 
599 struct nvme_registers {
600 	uint32_t	cap_lo; /* controller capabilities */
601 	uint32_t	cap_hi;
602 	uint32_t	vs;	/* version */
603 	uint32_t	intms;	/* interrupt mask set */
604 	uint32_t	intmc;	/* interrupt mask clear */
605 	uint32_t	cc;	/* controller configuration */
606 	uint32_t	reserved1;
607 	uint32_t	csts;	/* controller status */
608 	uint32_t	nssr;	/* NVM Subsystem Reset */
609 	uint32_t	aqa;	/* admin queue attributes */
610 	uint64_t	asq;	/* admin submission queue base addr */
611 	uint64_t	acq;	/* admin completion queue base addr */
612 	uint32_t	cmbloc;	/* Controller Memory Buffer Location */
613 	uint32_t	cmbsz;	/* Controller Memory Buffer Size */
614 	uint32_t	bpinfo;	/* Boot Partition Information */
615 	uint32_t	bprsel;	/* Boot Partition Read Select */
616 	uint64_t	bpmbl;	/* Boot Partition Memory Buffer Location */
617 	uint64_t	cmbmsc;	/* Controller Memory Buffer Memory Space Control */
618 	uint32_t	cmbsts;	/* Controller Memory Buffer Status */
619 	uint8_t		reserved3[3492]; /* 5Ch - DFFh */
620 	uint32_t	pmrcap;	/* Persistent Memory Capabilities */
621 	uint32_t	pmrctl;	/* Persistent Memory Region Control */
622 	uint32_t	pmrsts;	/* Persistent Memory Region Status */
623 	uint32_t	pmrebs;	/* Persistent Memory Region Elasticity Buffer Size */
624 	uint32_t	pmrswtp; /* Persistent Memory Region Sustained Write Throughput */
625 	uint32_t	pmrmsc_lo; /* Persistent Memory Region Controller Memory Space Control */
626 	uint32_t	pmrmsc_hi;
627 	uint8_t		reserved4[484]; /* E1Ch - FFFh */
628 	struct {
629 	    uint32_t	sq_tdbl; /* submission queue tail doorbell */
630 	    uint32_t	cq_hdbl; /* completion queue head doorbell */
631 	} doorbell[1];
632 };
633 
634 _Static_assert(sizeof(struct nvme_registers) == 0x1008, "bad size for nvme_registers");
635 
636 struct nvme_command {
637 	/* dword 0 */
638 	uint8_t opc;		/* opcode */
639 	uint8_t fuse;		/* fused operation */
640 	uint16_t cid;		/* command identifier */
641 
642 	/* dword 1 */
643 	uint32_t nsid;		/* namespace identifier */
644 
645 	/* dword 2-3 */
646 	uint32_t rsvd2;
647 	uint32_t rsvd3;
648 
649 	/* dword 4-5 */
650 	uint64_t mptr;		/* metadata pointer */
651 
652 	/* dword 6-7 */
653 	uint64_t prp1;		/* prp entry 1 */
654 
655 	/* dword 8-9 */
656 	uint64_t prp2;		/* prp entry 2 */
657 
658 	/* dword 10-15 */
659 	uint32_t cdw10;		/* command-specific */
660 	uint32_t cdw11;		/* command-specific */
661 	uint32_t cdw12;		/* command-specific */
662 	uint32_t cdw13;		/* command-specific */
663 	uint32_t cdw14;		/* command-specific */
664 	uint32_t cdw15;		/* command-specific */
665 };
666 
667 _Static_assert(sizeof(struct nvme_command) == 16 * 4, "bad size for nvme_command");
668 
669 struct nvme_completion {
670 	/* dword 0 */
671 	uint32_t		cdw0;	/* command-specific */
672 
673 	/* dword 1 */
674 	uint32_t		rsvd1;
675 
676 	/* dword 2 */
677 	uint16_t		sqhd;	/* submission queue head pointer */
678 	uint16_t		sqid;	/* submission queue identifier */
679 
680 	/* dword 3 */
681 	uint16_t		cid;	/* command identifier */
682 	uint16_t		status;
683 } __aligned(8);	/* riscv: nvme_qpair_process_completions has better code gen */
684 
685 _Static_assert(sizeof(struct nvme_completion) == 4 * 4, "bad size for nvme_completion");
686 
687 struct nvme_dsm_range {
688 	uint32_t attributes;
689 	uint32_t length;
690 	uint64_t starting_lba;
691 };
692 
693 /* Largest DSM Trim that can be done */
694 #define NVME_MAX_DSM_TRIM		4096
695 
696 _Static_assert(sizeof(struct nvme_dsm_range) == 16, "bad size for nvme_dsm_ranage");
697 
698 /* status code types */
699 enum nvme_status_code_type {
700 	NVME_SCT_GENERIC		= 0x0,
701 	NVME_SCT_COMMAND_SPECIFIC	= 0x1,
702 	NVME_SCT_MEDIA_ERROR		= 0x2,
703 	NVME_SCT_PATH_RELATED		= 0x3,
704 	/* 0x3-0x6 - reserved */
705 	NVME_SCT_VENDOR_SPECIFIC	= 0x7,
706 };
707 
708 /* generic command status codes */
709 enum nvme_generic_command_status_code {
710 	NVME_SC_SUCCESS				= 0x00,
711 	NVME_SC_INVALID_OPCODE			= 0x01,
712 	NVME_SC_INVALID_FIELD			= 0x02,
713 	NVME_SC_COMMAND_ID_CONFLICT		= 0x03,
714 	NVME_SC_DATA_TRANSFER_ERROR		= 0x04,
715 	NVME_SC_ABORTED_POWER_LOSS		= 0x05,
716 	NVME_SC_INTERNAL_DEVICE_ERROR		= 0x06,
717 	NVME_SC_ABORTED_BY_REQUEST		= 0x07,
718 	NVME_SC_ABORTED_SQ_DELETION		= 0x08,
719 	NVME_SC_ABORTED_FAILED_FUSED		= 0x09,
720 	NVME_SC_ABORTED_MISSING_FUSED		= 0x0a,
721 	NVME_SC_INVALID_NAMESPACE_OR_FORMAT	= 0x0b,
722 	NVME_SC_COMMAND_SEQUENCE_ERROR		= 0x0c,
723 	NVME_SC_INVALID_SGL_SEGMENT_DESCR	= 0x0d,
724 	NVME_SC_INVALID_NUMBER_OF_SGL_DESCR	= 0x0e,
725 	NVME_SC_DATA_SGL_LENGTH_INVALID		= 0x0f,
726 	NVME_SC_METADATA_SGL_LENGTH_INVALID	= 0x10,
727 	NVME_SC_SGL_DESCRIPTOR_TYPE_INVALID	= 0x11,
728 	NVME_SC_INVALID_USE_OF_CMB		= 0x12,
729 	NVME_SC_PRP_OFFET_INVALID		= 0x13,
730 	NVME_SC_ATOMIC_WRITE_UNIT_EXCEEDED	= 0x14,
731 	NVME_SC_OPERATION_DENIED		= 0x15,
732 	NVME_SC_SGL_OFFSET_INVALID		= 0x16,
733 	/* 0x17 - reserved */
734 	NVME_SC_HOST_ID_INCONSISTENT_FORMAT	= 0x18,
735 	NVME_SC_KEEP_ALIVE_TIMEOUT_EXPIRED	= 0x19,
736 	NVME_SC_KEEP_ALIVE_TIMEOUT_INVALID	= 0x1a,
737 	NVME_SC_ABORTED_DUE_TO_PREEMPT		= 0x1b,
738 	NVME_SC_SANITIZE_FAILED			= 0x1c,
739 	NVME_SC_SANITIZE_IN_PROGRESS		= 0x1d,
740 	NVME_SC_SGL_DATA_BLOCK_GRAN_INVALID	= 0x1e,
741 	NVME_SC_NOT_SUPPORTED_IN_CMB		= 0x1f,
742 	NVME_SC_NAMESPACE_IS_WRITE_PROTECTED	= 0x20,
743 	NVME_SC_COMMAND_INTERRUPTED		= 0x21,
744 	NVME_SC_TRANSIENT_TRANSPORT_ERROR	= 0x22,
745 
746 	NVME_SC_LBA_OUT_OF_RANGE		= 0x80,
747 	NVME_SC_CAPACITY_EXCEEDED		= 0x81,
748 	NVME_SC_NAMESPACE_NOT_READY		= 0x82,
749 	NVME_SC_RESERVATION_CONFLICT		= 0x83,
750 	NVME_SC_FORMAT_IN_PROGRESS		= 0x84,
751 };
752 
753 /* command specific status codes */
754 enum nvme_command_specific_status_code {
755 	NVME_SC_COMPLETION_QUEUE_INVALID	= 0x00,
756 	NVME_SC_INVALID_QUEUE_IDENTIFIER	= 0x01,
757 	NVME_SC_MAXIMUM_QUEUE_SIZE_EXCEEDED	= 0x02,
758 	NVME_SC_ABORT_COMMAND_LIMIT_EXCEEDED	= 0x03,
759 	/* 0x04 - reserved */
760 	NVME_SC_ASYNC_EVENT_REQUEST_LIMIT_EXCEEDED = 0x05,
761 	NVME_SC_INVALID_FIRMWARE_SLOT		= 0x06,
762 	NVME_SC_INVALID_FIRMWARE_IMAGE		= 0x07,
763 	NVME_SC_INVALID_INTERRUPT_VECTOR	= 0x08,
764 	NVME_SC_INVALID_LOG_PAGE		= 0x09,
765 	NVME_SC_INVALID_FORMAT			= 0x0a,
766 	NVME_SC_FIRMWARE_REQUIRES_RESET		= 0x0b,
767 	NVME_SC_INVALID_QUEUE_DELETION		= 0x0c,
768 	NVME_SC_FEATURE_NOT_SAVEABLE		= 0x0d,
769 	NVME_SC_FEATURE_NOT_CHANGEABLE		= 0x0e,
770 	NVME_SC_FEATURE_NOT_NS_SPECIFIC		= 0x0f,
771 	NVME_SC_FW_ACT_REQUIRES_NVMS_RESET	= 0x10,
772 	NVME_SC_FW_ACT_REQUIRES_RESET		= 0x11,
773 	NVME_SC_FW_ACT_REQUIRES_TIME		= 0x12,
774 	NVME_SC_FW_ACT_PROHIBITED		= 0x13,
775 	NVME_SC_OVERLAPPING_RANGE		= 0x14,
776 	NVME_SC_NS_INSUFFICIENT_CAPACITY	= 0x15,
777 	NVME_SC_NS_ID_UNAVAILABLE		= 0x16,
778 	/* 0x17 - reserved */
779 	NVME_SC_NS_ALREADY_ATTACHED		= 0x18,
780 	NVME_SC_NS_IS_PRIVATE			= 0x19,
781 	NVME_SC_NS_NOT_ATTACHED			= 0x1a,
782 	NVME_SC_THIN_PROV_NOT_SUPPORTED		= 0x1b,
783 	NVME_SC_CTRLR_LIST_INVALID		= 0x1c,
784 	NVME_SC_SELF_TEST_IN_PROGRESS		= 0x1d,
785 	NVME_SC_BOOT_PART_WRITE_PROHIB		= 0x1e,
786 	NVME_SC_INVALID_CTRLR_ID		= 0x1f,
787 	NVME_SC_INVALID_SEC_CTRLR_STATE		= 0x20,
788 	NVME_SC_INVALID_NUM_OF_CTRLR_RESRC	= 0x21,
789 	NVME_SC_INVALID_RESOURCE_ID		= 0x22,
790 	NVME_SC_SANITIZE_PROHIBITED_WPMRE	= 0x23,
791 	NVME_SC_ANA_GROUP_ID_INVALID		= 0x24,
792 	NVME_SC_ANA_ATTACH_FAILED		= 0x25,
793 
794 	NVME_SC_CONFLICTING_ATTRIBUTES		= 0x80,
795 	NVME_SC_INVALID_PROTECTION_INFO		= 0x81,
796 	NVME_SC_ATTEMPTED_WRITE_TO_RO_PAGE	= 0x82,
797 };
798 
799 /* media error status codes */
800 enum nvme_media_error_status_code {
801 	NVME_SC_WRITE_FAULTS			= 0x80,
802 	NVME_SC_UNRECOVERED_READ_ERROR		= 0x81,
803 	NVME_SC_GUARD_CHECK_ERROR		= 0x82,
804 	NVME_SC_APPLICATION_TAG_CHECK_ERROR	= 0x83,
805 	NVME_SC_REFERENCE_TAG_CHECK_ERROR	= 0x84,
806 	NVME_SC_COMPARE_FAILURE			= 0x85,
807 	NVME_SC_ACCESS_DENIED			= 0x86,
808 	NVME_SC_DEALLOCATED_OR_UNWRITTEN	= 0x87,
809 };
810 
811 /* path related status codes */
812 enum nvme_path_related_status_code {
813 	NVME_SC_INTERNAL_PATH_ERROR		= 0x00,
814 	NVME_SC_ASYMMETRIC_ACCESS_PERSISTENT_LOSS = 0x01,
815 	NVME_SC_ASYMMETRIC_ACCESS_INACCESSIBLE	= 0x02,
816 	NVME_SC_ASYMMETRIC_ACCESS_TRANSITION	= 0x03,
817 	NVME_SC_CONTROLLER_PATHING_ERROR	= 0x60,
818 	NVME_SC_HOST_PATHING_ERROR		= 0x70,
819 	NVME_SC_COMMAND_ABOTHED_BY_HOST		= 0x71,
820 };
821 
822 /* admin opcodes */
823 enum nvme_admin_opcode {
824 	NVME_OPC_DELETE_IO_SQ			= 0x00,
825 	NVME_OPC_CREATE_IO_SQ			= 0x01,
826 	NVME_OPC_GET_LOG_PAGE			= 0x02,
827 	/* 0x03 - reserved */
828 	NVME_OPC_DELETE_IO_CQ			= 0x04,
829 	NVME_OPC_CREATE_IO_CQ			= 0x05,
830 	NVME_OPC_IDENTIFY			= 0x06,
831 	/* 0x07 - reserved */
832 	NVME_OPC_ABORT				= 0x08,
833 	NVME_OPC_SET_FEATURES			= 0x09,
834 	NVME_OPC_GET_FEATURES			= 0x0a,
835 	/* 0x0b - reserved */
836 	NVME_OPC_ASYNC_EVENT_REQUEST		= 0x0c,
837 	NVME_OPC_NAMESPACE_MANAGEMENT		= 0x0d,
838 	/* 0x0e-0x0f - reserved */
839 	NVME_OPC_FIRMWARE_ACTIVATE		= 0x10,
840 	NVME_OPC_FIRMWARE_IMAGE_DOWNLOAD	= 0x11,
841 	/* 0x12-0x13 - reserved */
842 	NVME_OPC_DEVICE_SELF_TEST		= 0x14,
843 	NVME_OPC_NAMESPACE_ATTACHMENT		= 0x15,
844 	/* 0x16-0x17 - reserved */
845 	NVME_OPC_KEEP_ALIVE			= 0x18,
846 	NVME_OPC_DIRECTIVE_SEND			= 0x19,
847 	NVME_OPC_DIRECTIVE_RECEIVE		= 0x1a,
848 	/* 0x1b - reserved */
849 	NVME_OPC_VIRTUALIZATION_MANAGEMENT	= 0x1c,
850 	NVME_OPC_NVME_MI_SEND			= 0x1d,
851 	NVME_OPC_NVME_MI_RECEIVE		= 0x1e,
852 	/* 0x1f-0x7b - reserved */
853 	NVME_OPC_DOORBELL_BUFFER_CONFIG		= 0x7c,
854 
855 	NVME_OPC_FORMAT_NVM			= 0x80,
856 	NVME_OPC_SECURITY_SEND			= 0x81,
857 	NVME_OPC_SECURITY_RECEIVE		= 0x82,
858 	/* 0x83 - reserved */
859 	NVME_OPC_SANITIZE			= 0x84,
860 	/* 0x85 - reserved */
861 	NVME_OPC_GET_LBA_STATUS			= 0x86,
862 };
863 
864 /* nvme nvm opcodes */
865 enum nvme_nvm_opcode {
866 	NVME_OPC_FLUSH				= 0x00,
867 	NVME_OPC_WRITE				= 0x01,
868 	NVME_OPC_READ				= 0x02,
869 	/* 0x03 - reserved */
870 	NVME_OPC_WRITE_UNCORRECTABLE		= 0x04,
871 	NVME_OPC_COMPARE			= 0x05,
872 	/* 0x06-0x07 - reserved */
873 	NVME_OPC_WRITE_ZEROES			= 0x08,
874 	NVME_OPC_DATASET_MANAGEMENT		= 0x09,
875 	/* 0x0a-0x0b - reserved */
876 	NVME_OPC_VERIFY				= 0x0c,
877 	NVME_OPC_RESERVATION_REGISTER		= 0x0d,
878 	NVME_OPC_RESERVATION_REPORT		= 0x0e,
879 	/* 0x0f-0x10 - reserved */
880 	NVME_OPC_RESERVATION_ACQUIRE		= 0x11,
881 	/* 0x12-0x14 - reserved */
882 	NVME_OPC_RESERVATION_RELEASE		= 0x15,
883 };
884 
885 enum nvme_feature {
886 	/* 0x00 - reserved */
887 	NVME_FEAT_ARBITRATION			= 0x01,
888 	NVME_FEAT_POWER_MANAGEMENT		= 0x02,
889 	NVME_FEAT_LBA_RANGE_TYPE		= 0x03,
890 	NVME_FEAT_TEMPERATURE_THRESHOLD		= 0x04,
891 	NVME_FEAT_ERROR_RECOVERY		= 0x05,
892 	NVME_FEAT_VOLATILE_WRITE_CACHE		= 0x06,
893 	NVME_FEAT_NUMBER_OF_QUEUES		= 0x07,
894 	NVME_FEAT_INTERRUPT_COALESCING		= 0x08,
895 	NVME_FEAT_INTERRUPT_VECTOR_CONFIGURATION = 0x09,
896 	NVME_FEAT_WRITE_ATOMICITY		= 0x0A,
897 	NVME_FEAT_ASYNC_EVENT_CONFIGURATION	= 0x0B,
898 	NVME_FEAT_AUTONOMOUS_POWER_STATE_TRANSITION = 0x0C,
899 	NVME_FEAT_HOST_MEMORY_BUFFER		= 0x0D,
900 	NVME_FEAT_TIMESTAMP			= 0x0E,
901 	NVME_FEAT_KEEP_ALIVE_TIMER		= 0x0F,
902 	NVME_FEAT_HOST_CONTROLLED_THERMAL_MGMT	= 0x10,
903 	NVME_FEAT_NON_OP_POWER_STATE_CONFIG	= 0x11,
904 	NVME_FEAT_READ_RECOVERY_LEVEL_CONFIG	= 0x12,
905 	NVME_FEAT_PREDICTABLE_LATENCY_MODE_CONFIG = 0x13,
906 	NVME_FEAT_PREDICTABLE_LATENCY_MODE_WINDOW = 0x14,
907 	NVME_FEAT_LBA_STATUS_INFORMATION_ATTRIBUTES = 0x15,
908 	NVME_FEAT_HOST_BEHAVIOR_SUPPORT		= 0x16,
909 	NVME_FEAT_SANITIZE_CONFIG		= 0x17,
910 	NVME_FEAT_ENDURANCE_GROUP_EVENT_CONFIGURATION = 0x18,
911 	/* 0x19-0x77 - reserved */
912 	/* 0x78-0x7f - NVMe Management Interface */
913 	NVME_FEAT_SOFTWARE_PROGRESS_MARKER	= 0x80,
914 	NVME_FEAT_HOST_IDENTIFIER		= 0x81,
915 	NVME_FEAT_RESERVATION_NOTIFICATION_MASK	= 0x82,
916 	NVME_FEAT_RESERVATION_PERSISTENCE	= 0x83,
917 	NVME_FEAT_NAMESPACE_WRITE_PROTECTION_CONFIG = 0x84,
918 	/* 0x85-0xBF - command set specific (reserved) */
919 	/* 0xC0-0xFF - vendor specific */
920 };
921 
922 enum nvme_dsm_attribute {
923 	NVME_DSM_ATTR_INTEGRAL_READ		= 0x1,
924 	NVME_DSM_ATTR_INTEGRAL_WRITE		= 0x2,
925 	NVME_DSM_ATTR_DEALLOCATE		= 0x4,
926 };
927 
928 enum nvme_activate_action {
929 	NVME_AA_REPLACE_NO_ACTIVATE		= 0x0,
930 	NVME_AA_REPLACE_ACTIVATE		= 0x1,
931 	NVME_AA_ACTIVATE			= 0x2,
932 };
933 
934 struct nvme_power_state {
935 	/** Maximum Power */
936 	uint16_t	mp;			/* Maximum Power */
937 	uint8_t		ps_rsvd1;
938 	uint8_t		mps_nops;		/* Max Power Scale, Non-Operational State */
939 
940 	uint32_t	enlat;			/* Entry Latency */
941 	uint32_t	exlat;			/* Exit Latency */
942 
943 	uint8_t		rrt;			/* Relative Read Throughput */
944 	uint8_t		rrl;			/* Relative Read Latency */
945 	uint8_t		rwt;			/* Relative Write Throughput */
946 	uint8_t		rwl;			/* Relative Write Latency */
947 
948 	uint16_t	idlp;			/* Idle Power */
949 	uint8_t		ips;			/* Idle Power Scale */
950 	uint8_t		ps_rsvd8;
951 
952 	uint16_t	actp;			/* Active Power */
953 	uint8_t		apw_aps;		/* Active Power Workload, Active Power Scale */
954 	uint8_t		ps_rsvd10[9];
955 } __packed;
956 
957 _Static_assert(sizeof(struct nvme_power_state) == 32, "bad size for nvme_power_state");
958 
959 #define NVME_SERIAL_NUMBER_LENGTH	20
960 #define NVME_MODEL_NUMBER_LENGTH	40
961 #define NVME_FIRMWARE_REVISION_LENGTH	8
962 
963 struct nvme_controller_data {
964 	/* bytes 0-255: controller capabilities and features */
965 
966 	/** pci vendor id */
967 	uint16_t		vid;
968 
969 	/** pci subsystem vendor id */
970 	uint16_t		ssvid;
971 
972 	/** serial number */
973 	uint8_t			sn[NVME_SERIAL_NUMBER_LENGTH];
974 
975 	/** model number */
976 	uint8_t			mn[NVME_MODEL_NUMBER_LENGTH];
977 
978 	/** firmware revision */
979 	uint8_t			fr[NVME_FIRMWARE_REVISION_LENGTH];
980 
981 	/** recommended arbitration burst */
982 	uint8_t			rab;
983 
984 	/** ieee oui identifier */
985 	uint8_t			ieee[3];
986 
987 	/** multi-interface capabilities */
988 	uint8_t			mic;
989 
990 	/** maximum data transfer size */
991 	uint8_t			mdts;
992 
993 	/** Controller ID */
994 	uint16_t		ctrlr_id;
995 
996 	/** Version */
997 	uint32_t		ver;
998 
999 	/** RTD3 Resume Latency */
1000 	uint32_t		rtd3r;
1001 
1002 	/** RTD3 Enter Latency */
1003 	uint32_t		rtd3e;
1004 
1005 	/** Optional Asynchronous Events Supported */
1006 	uint32_t		oaes;	/* bitfield really */
1007 
1008 	/** Controller Attributes */
1009 	uint32_t		ctratt;	/* bitfield really */
1010 
1011 	/** Read Recovery Levels Supported */
1012 	uint16_t		rrls;
1013 
1014 	uint8_t			reserved1[9];
1015 
1016 	/** Controller Type */
1017 	uint8_t			cntrltype;
1018 
1019 	/** FRU Globally Unique Identifier */
1020 	uint8_t			fguid[16];
1021 
1022 	/** Command Retry Delay Time 1 */
1023 	uint16_t		crdt1;
1024 
1025 	/** Command Retry Delay Time 2 */
1026 	uint16_t		crdt2;
1027 
1028 	/** Command Retry Delay Time 3 */
1029 	uint16_t		crdt3;
1030 
1031 	uint8_t			reserved2[122];
1032 
1033 	/* bytes 256-511: admin command set attributes */
1034 
1035 	/** optional admin command support */
1036 	uint16_t		oacs;
1037 
1038 	/** abort command limit */
1039 	uint8_t			acl;
1040 
1041 	/** asynchronous event request limit */
1042 	uint8_t			aerl;
1043 
1044 	/** firmware updates */
1045 	uint8_t			frmw;
1046 
1047 	/** log page attributes */
1048 	uint8_t			lpa;
1049 
1050 	/** error log page entries */
1051 	uint8_t			elpe;
1052 
1053 	/** number of power states supported */
1054 	uint8_t			npss;
1055 
1056 	/** admin vendor specific command configuration */
1057 	uint8_t			avscc;
1058 
1059 	/** Autonomous Power State Transition Attributes */
1060 	uint8_t			apsta;
1061 
1062 	/** Warning Composite Temperature Threshold */
1063 	uint16_t		wctemp;
1064 
1065 	/** Critical Composite Temperature Threshold */
1066 	uint16_t		cctemp;
1067 
1068 	/** Maximum Time for Firmware Activation */
1069 	uint16_t		mtfa;
1070 
1071 	/** Host Memory Buffer Preferred Size */
1072 	uint32_t		hmpre;
1073 
1074 	/** Host Memory Buffer Minimum Size */
1075 	uint32_t		hmmin;
1076 
1077 	/** Name space capabilities  */
1078 	struct {
1079 		/* if nsmgmt, report tnvmcap and unvmcap */
1080 		uint8_t    tnvmcap[16];
1081 		uint8_t    unvmcap[16];
1082 	} __packed untncap;
1083 
1084 	/** Replay Protected Memory Block Support */
1085 	uint32_t		rpmbs; /* Really a bitfield */
1086 
1087 	/** Extended Device Self-test Time */
1088 	uint16_t		edstt;
1089 
1090 	/** Device Self-test Options */
1091 	uint8_t			dsto; /* Really a bitfield */
1092 
1093 	/** Firmware Update Granularity */
1094 	uint8_t			fwug;
1095 
1096 	/** Keep Alive Support */
1097 	uint16_t		kas;
1098 
1099 	/** Host Controlled Thermal Management Attributes */
1100 	uint16_t		hctma; /* Really a bitfield */
1101 
1102 	/** Minimum Thermal Management Temperature */
1103 	uint16_t		mntmt;
1104 
1105 	/** Maximum Thermal Management Temperature */
1106 	uint16_t		mxtmt;
1107 
1108 	/** Sanitize Capabilities */
1109 	uint32_t		sanicap; /* Really a bitfield */
1110 
1111 	/** Host Memory Buffer Minimum Descriptor Entry Size */
1112 	uint32_t		hmminds;
1113 
1114 	/** Host Memory Maximum Descriptors Entries */
1115 	uint16_t		hmmaxd;
1116 
1117 	/** NVM Set Identifier Maximum */
1118 	uint16_t		nsetidmax;
1119 
1120 	/** Endurance Group Identifier Maximum */
1121 	uint16_t		endgidmax;
1122 
1123 	/** ANA Transition Time */
1124 	uint8_t			anatt;
1125 
1126 	/** Asymmetric Namespace Access Capabilities */
1127 	uint8_t			anacap;
1128 
1129 	/** ANA Group Identifier Maximum */
1130 	uint32_t		anagrpmax;
1131 
1132 	/** Number of ANA Group Identifiers */
1133 	uint32_t		nanagrpid;
1134 
1135 	/** Persistent Event Log Size */
1136 	uint32_t		pels;
1137 
1138 	uint8_t			reserved3[156];
1139 	/* bytes 512-703: nvm command set attributes */
1140 
1141 	/** submission queue entry size */
1142 	uint8_t			sqes;
1143 
1144 	/** completion queue entry size */
1145 	uint8_t			cqes;
1146 
1147 	/** Maximum Outstanding Commands */
1148 	uint16_t		maxcmd;
1149 
1150 	/** number of namespaces */
1151 	uint32_t		nn;
1152 
1153 	/** optional nvm command support */
1154 	uint16_t		oncs;
1155 
1156 	/** fused operation support */
1157 	uint16_t		fuses;
1158 
1159 	/** format nvm attributes */
1160 	uint8_t			fna;
1161 
1162 	/** volatile write cache */
1163 	uint8_t			vwc;
1164 
1165 	/** Atomic Write Unit Normal */
1166 	uint16_t		awun;
1167 
1168 	/** Atomic Write Unit Power Fail */
1169 	uint16_t		awupf;
1170 
1171 	/** NVM Vendor Specific Command Configuration */
1172 	uint8_t			nvscc;
1173 
1174 	/** Namespace Write Protection Capabilities */
1175 	uint8_t			nwpc;
1176 
1177 	/** Atomic Compare & Write Unit */
1178 	uint16_t		acwu;
1179 	uint16_t		reserved6;
1180 
1181 	/** SGL Support */
1182 	uint32_t		sgls;
1183 
1184 	/** Maximum Number of Allowed Namespaces */
1185 	uint32_t		mnan;
1186 
1187 	/* bytes 540-767: Reserved */
1188 	uint8_t			reserved7[224];
1189 
1190 	/** NVM Subsystem NVMe Qualified Name */
1191 	uint8_t			subnqn[256];
1192 
1193 	/* bytes 1024-1791: Reserved */
1194 	uint8_t			reserved8[768];
1195 
1196 	/* bytes 1792-2047: NVMe over Fabrics specification */
1197 	uint8_t			reserved9[256];
1198 
1199 	/* bytes 2048-3071: power state descriptors */
1200 	struct nvme_power_state power_state[32];
1201 
1202 	/* bytes 3072-4095: vendor specific */
1203 	uint8_t			vs[1024];
1204 } __packed __aligned(4);
1205 
1206 _Static_assert(sizeof(struct nvme_controller_data) == 4096, "bad size for nvme_controller_data");
1207 
1208 struct nvme_namespace_data {
1209 	/** namespace size */
1210 	uint64_t		nsze;
1211 
1212 	/** namespace capacity */
1213 	uint64_t		ncap;
1214 
1215 	/** namespace utilization */
1216 	uint64_t		nuse;
1217 
1218 	/** namespace features */
1219 	uint8_t			nsfeat;
1220 
1221 	/** number of lba formats */
1222 	uint8_t			nlbaf;
1223 
1224 	/** formatted lba size */
1225 	uint8_t			flbas;
1226 
1227 	/** metadata capabilities */
1228 	uint8_t			mc;
1229 
1230 	/** end-to-end data protection capabilities */
1231 	uint8_t			dpc;
1232 
1233 	/** end-to-end data protection type settings */
1234 	uint8_t			dps;
1235 
1236 	/** Namespace Multi-path I/O and Namespace Sharing Capabilities */
1237 	uint8_t			nmic;
1238 
1239 	/** Reservation Capabilities */
1240 	uint8_t			rescap;
1241 
1242 	/** Format Progress Indicator */
1243 	uint8_t			fpi;
1244 
1245 	/** Deallocate Logical Block Features */
1246 	uint8_t			dlfeat;
1247 
1248 	/** Namespace Atomic Write Unit Normal  */
1249 	uint16_t		nawun;
1250 
1251 	/** Namespace Atomic Write Unit Power Fail */
1252 	uint16_t		nawupf;
1253 
1254 	/** Namespace Atomic Compare & Write Unit */
1255 	uint16_t		nacwu;
1256 
1257 	/** Namespace Atomic Boundary Size Normal */
1258 	uint16_t		nabsn;
1259 
1260 	/** Namespace Atomic Boundary Offset */
1261 	uint16_t		nabo;
1262 
1263 	/** Namespace Atomic Boundary Size Power Fail */
1264 	uint16_t		nabspf;
1265 
1266 	/** Namespace Optimal IO Boundary */
1267 	uint16_t		noiob;
1268 
1269 	/** NVM Capacity */
1270 	uint8_t			nvmcap[16];
1271 
1272 	/** Namespace Preferred Write Granularity  */
1273 	uint16_t		npwg;
1274 
1275 	/** Namespace Preferred Write Alignment */
1276 	uint16_t		npwa;
1277 
1278 	/** Namespace Preferred Deallocate Granularity */
1279 	uint16_t		npdg;
1280 
1281 	/** Namespace Preferred Deallocate Alignment */
1282 	uint16_t		npda;
1283 
1284 	/** Namespace Optimal Write Size */
1285 	uint16_t		nows;
1286 
1287 	/* bytes 74-91: Reserved */
1288 	uint8_t			reserved5[18];
1289 
1290 	/** ANA Group Identifier */
1291 	uint32_t		anagrpid;
1292 
1293 	/* bytes 96-98: Reserved */
1294 	uint8_t			reserved6[3];
1295 
1296 	/** Namespace Attributes */
1297 	uint8_t			nsattr;
1298 
1299 	/** NVM Set Identifier */
1300 	uint16_t		nvmsetid;
1301 
1302 	/** Endurance Group Identifier */
1303 	uint16_t		endgid;
1304 
1305 	/** Namespace Globally Unique Identifier */
1306 	uint8_t			nguid[16];
1307 
1308 	/** IEEE Extended Unique Identifier */
1309 	uint8_t			eui64[8];
1310 
1311 	/** lba format support */
1312 	uint32_t		lbaf[16];
1313 
1314 	uint8_t			reserved7[192];
1315 
1316 	uint8_t			vendor_specific[3712];
1317 } __packed __aligned(4);
1318 
1319 _Static_assert(sizeof(struct nvme_namespace_data) == 4096, "bad size for nvme_namepsace_data");
1320 
1321 enum nvme_log_page {
1322 	/* 0x00 - reserved */
1323 	NVME_LOG_ERROR			= 0x01,
1324 	NVME_LOG_HEALTH_INFORMATION	= 0x02,
1325 	NVME_LOG_FIRMWARE_SLOT		= 0x03,
1326 	NVME_LOG_CHANGED_NAMESPACE	= 0x04,
1327 	NVME_LOG_COMMAND_EFFECT		= 0x05,
1328 	NVME_LOG_DEVICE_SELF_TEST	= 0x06,
1329 	NVME_LOG_TELEMETRY_HOST_INITIATED = 0x07,
1330 	NVME_LOG_TELEMETRY_CONTROLLER_INITIATED = 0x08,
1331 	NVME_LOG_ENDURANCE_GROUP_INFORMATION = 0x09,
1332 	NVME_LOG_PREDICTABLE_LATENCY_PER_NVM_SET = 0x0a,
1333 	NVME_LOG_PREDICTABLE_LATENCY_EVENT_AGGREGATE = 0x0b,
1334 	NVME_LOG_ASYMMETRIC_NAMESPACE_ACCESS = 0x0c,
1335 	NVME_LOG_PERSISTENT_EVENT_LOG	= 0x0d,
1336 	NVME_LOG_LBA_STATUS_INFORMATION	= 0x0e,
1337 	NVME_LOG_ENDURANCE_GROUP_EVENT_AGGREGATE = 0x0f,
1338 	/* 0x06-0x7F - reserved */
1339 	/* 0x80-0xBF - I/O command set specific */
1340 	NVME_LOG_RES_NOTIFICATION	= 0x80,
1341 	NVME_LOG_SANITIZE_STATUS	= 0x81,
1342 	/* 0x82-0xBF - reserved */
1343 	/* 0xC0-0xFF - vendor specific */
1344 
1345 	/*
1346 	 * The following are Intel Specific log pages, but they seem
1347 	 * to be widely implemented.
1348 	 */
1349 	INTEL_LOG_READ_LAT_LOG		= 0xc1,
1350 	INTEL_LOG_WRITE_LAT_LOG		= 0xc2,
1351 	INTEL_LOG_TEMP_STATS		= 0xc5,
1352 	INTEL_LOG_ADD_SMART		= 0xca,
1353 	INTEL_LOG_DRIVE_MKT_NAME	= 0xdd,
1354 
1355 	/*
1356 	 * HGST log page, with lots ofs sub pages.
1357 	 */
1358 	HGST_INFO_LOG			= 0xc1,
1359 };
1360 
1361 struct nvme_error_information_entry {
1362 	uint64_t		error_count;
1363 	uint16_t		sqid;
1364 	uint16_t		cid;
1365 	uint16_t		status;
1366 	uint16_t		error_location;
1367 	uint64_t		lba;
1368 	uint32_t		nsid;
1369 	uint8_t			vendor_specific;
1370 	uint8_t			trtype;
1371 	uint16_t		reserved30;
1372 	uint64_t		csi;
1373 	uint16_t		ttsi;
1374 	uint8_t			reserved[22];
1375 } __packed __aligned(4);
1376 
1377 _Static_assert(sizeof(struct nvme_error_information_entry) == 64, "bad size for nvme_error_information_entry");
1378 
1379 struct nvme_health_information_page {
1380 	uint8_t			critical_warning;
1381 	uint16_t		temperature;
1382 	uint8_t			available_spare;
1383 	uint8_t			available_spare_threshold;
1384 	uint8_t			percentage_used;
1385 
1386 	uint8_t			reserved[26];
1387 
1388 	/*
1389 	 * Note that the following are 128-bit values, but are
1390 	 *  defined as an array of 2 64-bit values.
1391 	 */
1392 	/* Data Units Read is always in 512-byte units. */
1393 	uint64_t		data_units_read[2];
1394 	/* Data Units Written is always in 512-byte units. */
1395 	uint64_t		data_units_written[2];
1396 	/* For NVM command set, this includes Compare commands. */
1397 	uint64_t		host_read_commands[2];
1398 	uint64_t		host_write_commands[2];
1399 	/* Controller Busy Time is reported in minutes. */
1400 	uint64_t		controller_busy_time[2];
1401 	uint64_t		power_cycles[2];
1402 	uint64_t		power_on_hours[2];
1403 	uint64_t		unsafe_shutdowns[2];
1404 	uint64_t		media_errors[2];
1405 	uint64_t		num_error_info_log_entries[2];
1406 	uint32_t		warning_temp_time;
1407 	uint32_t		error_temp_time;
1408 	uint16_t		temp_sensor[8];
1409 	/* Thermal Management Temperature 1 Transition Count */
1410 	uint32_t		tmt1tc;
1411 	/* Thermal Management Temperature 2 Transition Count */
1412 	uint32_t		tmt2tc;
1413 	/* Total Time For Thermal Management Temperature 1 */
1414 	uint32_t		ttftmt1;
1415 	/* Total Time For Thermal Management Temperature 2 */
1416 	uint32_t		ttftmt2;
1417 
1418 	uint8_t			reserved2[280];
1419 } __packed __aligned(4);
1420 
1421 /* Currently sparse/smatch incorrectly packs this struct in some situations. */
1422 #ifndef __CHECKER__
1423 _Static_assert(sizeof(struct nvme_health_information_page) == 512, "bad size for nvme_health_information_page");
1424 #endif
1425 
1426 struct nvme_firmware_page {
1427 	uint8_t			afi;
1428 	uint8_t			reserved[7];
1429 	uint64_t		revision[7]; /* revisions for 7 slots */
1430 	uint8_t			reserved2[448];
1431 } __packed __aligned(4);
1432 
1433 _Static_assert(sizeof(struct nvme_firmware_page) == 512, "bad size for nvme_firmware_page");
1434 
1435 struct nvme_ns_list {
1436 	uint32_t		ns[1024];
1437 } __packed __aligned(4);
1438 
1439 _Static_assert(sizeof(struct nvme_ns_list) == 4096, "bad size for nvme_ns_list");
1440 
1441 struct nvme_command_effects_page {
1442 	uint32_t		acs[256];
1443 	uint32_t		iocs[256];
1444 	uint8_t			reserved[2048];
1445 } __packed __aligned(4);
1446 
1447 _Static_assert(sizeof(struct nvme_command_effects_page) == 4096,
1448     "bad size for nvme_command_effects_page");
1449 
1450 struct nvme_device_self_test_page {
1451 	uint8_t			curr_operation;
1452 	uint8_t			curr_compl;
1453 	uint8_t			rsvd2[2];
1454 	struct {
1455 		uint8_t		status;
1456 		uint8_t		segment_num;
1457 		uint8_t		valid_diag_info;
1458 		uint8_t		rsvd3;
1459 		uint64_t	poh;
1460 		uint32_t	nsid;
1461 		/* Define as an array to simplify alignment issues */
1462 		uint8_t		failing_lba[8];
1463 		uint8_t		status_code_type;
1464 		uint8_t		status_code;
1465 		uint8_t		vendor_specific[2];
1466 	} __packed result[20];
1467 } __packed __aligned(4);
1468 
1469 /* Currently sparse/smatch incorrectly packs this struct in some situations. */
1470 #ifndef __CHECKER__
1471 _Static_assert(sizeof(struct nvme_device_self_test_page) == 564,
1472     "bad size for nvme_device_self_test_page");
1473 #endif
1474 
1475 struct nvme_res_notification_page {
1476 	uint64_t		log_page_count;
1477 	uint8_t			log_page_type;
1478 	uint8_t			available_log_pages;
1479 	uint8_t			reserved2;
1480 	uint32_t		nsid;
1481 	uint8_t			reserved[48];
1482 } __packed __aligned(4);
1483 
1484 _Static_assert(sizeof(struct nvme_res_notification_page) == 64,
1485     "bad size for nvme_res_notification_page");
1486 
1487 struct nvme_sanitize_status_page {
1488 	uint16_t		sprog;
1489 	uint16_t		sstat;
1490 	uint32_t		scdw10;
1491 	uint32_t		etfo;
1492 	uint32_t		etfbe;
1493 	uint32_t		etfce;
1494 	uint32_t		etfownd;
1495 	uint32_t		etfbewnd;
1496 	uint32_t		etfcewnd;
1497 	uint8_t			reserved[480];
1498 } __packed __aligned(4);
1499 
1500 _Static_assert(sizeof(struct nvme_sanitize_status_page) == 512,
1501     "bad size for nvme_sanitize_status_page");
1502 
1503 struct intel_log_temp_stats {
1504 	uint64_t	current;
1505 	uint64_t	overtemp_flag_last;
1506 	uint64_t	overtemp_flag_life;
1507 	uint64_t	max_temp;
1508 	uint64_t	min_temp;
1509 	uint64_t	_rsvd[5];
1510 	uint64_t	max_oper_temp;
1511 	uint64_t	min_oper_temp;
1512 	uint64_t	est_offset;
1513 } __packed __aligned(4);
1514 
1515 _Static_assert(sizeof(struct intel_log_temp_stats) == 13 * 8, "bad size for intel_log_temp_stats");
1516 
1517 struct nvme_resv_reg_ctrlr {
1518 	uint16_t		ctrlr_id;	/* Controller ID */
1519 	uint8_t			rcsts;		/* Reservation Status */
1520 	uint8_t			reserved3[5];
1521 	uint64_t		hostid;		/* Host Identifier */
1522 	uint64_t		rkey;		/* Reservation Key */
1523 } __packed __aligned(4);
1524 
1525 _Static_assert(sizeof(struct nvme_resv_reg_ctrlr) == 24, "bad size for nvme_resv_reg_ctrlr");
1526 
1527 struct nvme_resv_reg_ctrlr_ext {
1528 	uint16_t		ctrlr_id;	/* Controller ID */
1529 	uint8_t			rcsts;		/* Reservation Status */
1530 	uint8_t			reserved3[5];
1531 	uint64_t		rkey;		/* Reservation Key */
1532 	uint64_t		hostid[2];	/* Host Identifier */
1533 	uint8_t			reserved32[32];
1534 } __packed __aligned(4);
1535 
1536 _Static_assert(sizeof(struct nvme_resv_reg_ctrlr_ext) == 64, "bad size for nvme_resv_reg_ctrlr_ext");
1537 
1538 struct nvme_resv_status {
1539 	uint32_t		gen;		/* Generation */
1540 	uint8_t			rtype;		/* Reservation Type */
1541 	uint8_t			regctl[2];	/* Number of Registered Controllers */
1542 	uint8_t			reserved7[2];
1543 	uint8_t			ptpls;		/* Persist Through Power Loss State */
1544 	uint8_t			reserved10[14];
1545 	struct nvme_resv_reg_ctrlr	ctrlr[0];
1546 } __packed __aligned(4);
1547 
1548 _Static_assert(sizeof(struct nvme_resv_status) == 24, "bad size for nvme_resv_status");
1549 
1550 struct nvme_resv_status_ext {
1551 	uint32_t		gen;		/* Generation */
1552 	uint8_t			rtype;		/* Reservation Type */
1553 	uint8_t			regctl[2];	/* Number of Registered Controllers */
1554 	uint8_t			reserved7[2];
1555 	uint8_t			ptpls;		/* Persist Through Power Loss State */
1556 	uint8_t			reserved10[14];
1557 	uint8_t			reserved24[40];
1558 	struct nvme_resv_reg_ctrlr_ext	ctrlr[0];
1559 } __packed __aligned(4);
1560 
1561 _Static_assert(sizeof(struct nvme_resv_status_ext) == 64, "bad size for nvme_resv_status_ext");
1562 
1563 #define NVME_TEST_MAX_THREADS	128
1564 
1565 struct nvme_io_test {
1566 	enum nvme_nvm_opcode	opc;
1567 	uint32_t		size;
1568 	uint32_t		time;	/* in seconds */
1569 	uint32_t		num_threads;
1570 	uint32_t		flags;
1571 	uint64_t		io_completed[NVME_TEST_MAX_THREADS];
1572 };
1573 
1574 enum nvme_io_test_flags {
1575 	/*
1576 	 * Specifies whether dev_refthread/dev_relthread should be
1577 	 *  called during NVME_BIO_TEST.  Ignored for other test
1578 	 *  types.
1579 	 */
1580 	NVME_TEST_FLAG_REFTHREAD =	0x1,
1581 };
1582 
1583 struct nvme_pt_command {
1584 	/*
1585 	 * cmd is used to specify a passthrough command to a controller or
1586 	 *  namespace.
1587 	 *
1588 	 * The following fields from cmd may be specified by the caller:
1589 	 *	* opc  (opcode)
1590 	 *	* nsid (namespace id) - for admin commands only
1591 	 *	* cdw10-cdw15
1592 	 *
1593 	 * Remaining fields must be set to 0 by the caller.
1594 	 */
1595 	struct nvme_command	cmd;
1596 
1597 	/*
1598 	 * cpl returns completion status for the passthrough command
1599 	 *  specified by cmd.
1600 	 *
1601 	 * The following fields will be filled out by the driver, for
1602 	 *  consumption by the caller:
1603 	 *	* cdw0
1604 	 *	* status (except for phase)
1605 	 *
1606 	 * Remaining fields will be set to 0 by the driver.
1607 	 */
1608 	struct nvme_completion	cpl;
1609 
1610 	/* buf is the data buffer associated with this passthrough command. */
1611 	void *			buf;
1612 
1613 	/*
1614 	 * len is the length of the data buffer associated with this
1615 	 *  passthrough command.
1616 	 */
1617 	uint32_t		len;
1618 
1619 	/*
1620 	 * is_read = 1 if the passthrough command will read data into the
1621 	 *  supplied buffer from the controller.
1622 	 *
1623 	 * is_read = 0 if the passthrough command will write data from the
1624 	 *  supplied buffer to the controller.
1625 	 */
1626 	uint32_t		is_read;
1627 
1628 	/*
1629 	 * driver_lock is used by the driver only.  It must be set to 0
1630 	 *  by the caller.
1631 	 */
1632 	struct mtx *		driver_lock;
1633 };
1634 
1635 struct nvme_get_nsid {
1636 	char		cdev[SPECNAMELEN + 1];
1637 	uint32_t	nsid;
1638 };
1639 
1640 struct nvme_hmb_desc {
1641 	uint64_t	addr;
1642 	uint32_t	size;
1643 	uint32_t	reserved;
1644 };
1645 
1646 #define nvme_completion_is_error(cpl)					\
1647 	(NVME_STATUS_GET_SC((cpl)->status) != 0 || NVME_STATUS_GET_SCT((cpl)->status) != 0)
1648 
1649 void	nvme_strvis(uint8_t *dst, const uint8_t *src, int dstlen, int srclen);
1650 
1651 #ifdef _KERNEL
1652 
1653 struct bio;
1654 struct thread;
1655 
1656 struct nvme_namespace;
1657 struct nvme_controller;
1658 struct nvme_consumer;
1659 
1660 typedef void (*nvme_cb_fn_t)(void *, const struct nvme_completion *);
1661 
1662 typedef void *(*nvme_cons_ns_fn_t)(struct nvme_namespace *, void *);
1663 typedef void *(*nvme_cons_ctrlr_fn_t)(struct nvme_controller *);
1664 typedef void (*nvme_cons_async_fn_t)(void *, const struct nvme_completion *,
1665 				     uint32_t, void *, uint32_t);
1666 typedef void (*nvme_cons_fail_fn_t)(void *);
1667 
1668 enum nvme_namespace_flags {
1669 	NVME_NS_DEALLOCATE_SUPPORTED	= 0x1,
1670 	NVME_NS_FLUSH_SUPPORTED		= 0x2,
1671 };
1672 
1673 int	nvme_ctrlr_passthrough_cmd(struct nvme_controller *ctrlr,
1674 				   struct nvme_pt_command *pt,
1675 				   uint32_t nsid, int is_user_buffer,
1676 				   int is_admin_cmd);
1677 
1678 /* Admin functions */
1679 void	nvme_ctrlr_cmd_set_feature(struct nvme_controller *ctrlr,
1680 				   uint8_t feature, uint32_t cdw11,
1681 				   uint32_t cdw12, uint32_t cdw13,
1682 				   uint32_t cdw14, uint32_t cdw15,
1683 				   void *payload, uint32_t payload_size,
1684 				   nvme_cb_fn_t cb_fn, void *cb_arg);
1685 void	nvme_ctrlr_cmd_get_feature(struct nvme_controller *ctrlr,
1686 				   uint8_t feature, uint32_t cdw11,
1687 				   void *payload, uint32_t payload_size,
1688 				   nvme_cb_fn_t cb_fn, void *cb_arg);
1689 void	nvme_ctrlr_cmd_get_log_page(struct nvme_controller *ctrlr,
1690 				    uint8_t log_page, uint32_t nsid,
1691 				    void *payload, uint32_t payload_size,
1692 				    nvme_cb_fn_t cb_fn, void *cb_arg);
1693 
1694 /* NVM I/O functions */
1695 int	nvme_ns_cmd_write(struct nvme_namespace *ns, void *payload,
1696 			  uint64_t lba, uint32_t lba_count, nvme_cb_fn_t cb_fn,
1697 			  void *cb_arg);
1698 int	nvme_ns_cmd_write_bio(struct nvme_namespace *ns, struct bio *bp,
1699 			      nvme_cb_fn_t cb_fn, void *cb_arg);
1700 int	nvme_ns_cmd_read(struct nvme_namespace *ns, void *payload,
1701 			 uint64_t lba, uint32_t lba_count, nvme_cb_fn_t cb_fn,
1702 			 void *cb_arg);
1703 int	nvme_ns_cmd_read_bio(struct nvme_namespace *ns, struct bio *bp,
1704 			      nvme_cb_fn_t cb_fn, void *cb_arg);
1705 int	nvme_ns_cmd_deallocate(struct nvme_namespace *ns, void *payload,
1706 			       uint8_t num_ranges, nvme_cb_fn_t cb_fn,
1707 			       void *cb_arg);
1708 int	nvme_ns_cmd_flush(struct nvme_namespace *ns, nvme_cb_fn_t cb_fn,
1709 			  void *cb_arg);
1710 int	nvme_ns_dump(struct nvme_namespace *ns, void *virt, off_t offset,
1711 		     size_t len);
1712 
1713 /* Registration functions */
1714 struct nvme_consumer *	nvme_register_consumer(nvme_cons_ns_fn_t    ns_fn,
1715 					       nvme_cons_ctrlr_fn_t ctrlr_fn,
1716 					       nvme_cons_async_fn_t async_fn,
1717 					       nvme_cons_fail_fn_t  fail_fn);
1718 void		nvme_unregister_consumer(struct nvme_consumer *consumer);
1719 
1720 /* Controller helper functions */
1721 device_t	nvme_ctrlr_get_device(struct nvme_controller *ctrlr);
1722 const struct nvme_controller_data *
1723 		nvme_ctrlr_get_data(struct nvme_controller *ctrlr);
1724 static inline bool
1725 nvme_ctrlr_has_dataset_mgmt(const struct nvme_controller_data *cd)
1726 {
1727 	/* Assumes cd was byte swapped by nvme_controller_data_swapbytes() */
1728 	return ((cd->oncs >> NVME_CTRLR_DATA_ONCS_DSM_SHIFT) &
1729 		NVME_CTRLR_DATA_ONCS_DSM_MASK);
1730 }
1731 
1732 /* Namespace helper functions */
1733 uint32_t	nvme_ns_get_max_io_xfer_size(struct nvme_namespace *ns);
1734 uint32_t	nvme_ns_get_sector_size(struct nvme_namespace *ns);
1735 uint64_t	nvme_ns_get_num_sectors(struct nvme_namespace *ns);
1736 uint64_t	nvme_ns_get_size(struct nvme_namespace *ns);
1737 uint32_t	nvme_ns_get_flags(struct nvme_namespace *ns);
1738 const char *	nvme_ns_get_serial_number(struct nvme_namespace *ns);
1739 const char *	nvme_ns_get_model_number(struct nvme_namespace *ns);
1740 const struct nvme_namespace_data *
1741 		nvme_ns_get_data(struct nvme_namespace *ns);
1742 uint32_t	nvme_ns_get_stripesize(struct nvme_namespace *ns);
1743 
1744 int	nvme_ns_bio_process(struct nvme_namespace *ns, struct bio *bp,
1745 			    nvme_cb_fn_t cb_fn);
1746 int	nvme_ns_ioctl_process(struct nvme_namespace *ns, u_long cmd,
1747     caddr_t arg, int flag, struct thread *td);
1748 
1749 /*
1750  * Command building helper functions -- shared with CAM
1751  * These functions assume allocator zeros out cmd structure
1752  * CAM's xpt_get_ccb and the request allocator for nvme both
1753  * do zero'd allocations.
1754  */
1755 static inline
1756 void	nvme_ns_flush_cmd(struct nvme_command *cmd, uint32_t nsid)
1757 {
1758 
1759 	cmd->opc = NVME_OPC_FLUSH;
1760 	cmd->nsid = htole32(nsid);
1761 }
1762 
1763 static inline
1764 void	nvme_ns_rw_cmd(struct nvme_command *cmd, uint32_t rwcmd, uint32_t nsid,
1765     uint64_t lba, uint32_t count)
1766 {
1767 	cmd->opc = rwcmd;
1768 	cmd->nsid = htole32(nsid);
1769 	cmd->cdw10 = htole32(lba & 0xffffffffu);
1770 	cmd->cdw11 = htole32(lba >> 32);
1771 	cmd->cdw12 = htole32(count-1);
1772 }
1773 
1774 static inline
1775 void	nvme_ns_write_cmd(struct nvme_command *cmd, uint32_t nsid,
1776     uint64_t lba, uint32_t count)
1777 {
1778 	nvme_ns_rw_cmd(cmd, NVME_OPC_WRITE, nsid, lba, count);
1779 }
1780 
1781 static inline
1782 void	nvme_ns_read_cmd(struct nvme_command *cmd, uint32_t nsid,
1783     uint64_t lba, uint32_t count)
1784 {
1785 	nvme_ns_rw_cmd(cmd, NVME_OPC_READ, nsid, lba, count);
1786 }
1787 
1788 static inline
1789 void	nvme_ns_trim_cmd(struct nvme_command *cmd, uint32_t nsid,
1790     uint32_t num_ranges)
1791 {
1792 	cmd->opc = NVME_OPC_DATASET_MANAGEMENT;
1793 	cmd->nsid = htole32(nsid);
1794 	cmd->cdw10 = htole32(num_ranges - 1);
1795 	cmd->cdw11 = htole32(NVME_DSM_ATTR_DEALLOCATE);
1796 }
1797 
1798 extern int nvme_use_nvd;
1799 
1800 #endif /* _KERNEL */
1801 
1802 /* Endianess conversion functions for NVMe structs */
1803 static inline
1804 void	nvme_completion_swapbytes(struct nvme_completion *s __unused)
1805 {
1806 #ifndef _LITTLE_ENDIAN
1807 
1808 	s->cdw0 = le32toh(s->cdw0);
1809 	/* omit rsvd1 */
1810 	s->sqhd = le16toh(s->sqhd);
1811 	s->sqid = le16toh(s->sqid);
1812 	/* omit cid */
1813 	s->status = le16toh(s->status);
1814 #endif
1815 }
1816 
1817 static inline
1818 void	nvme_power_state_swapbytes(struct nvme_power_state *s __unused)
1819 {
1820 #ifndef _LITTLE_ENDIAN
1821 
1822 	s->mp = le16toh(s->mp);
1823 	s->enlat = le32toh(s->enlat);
1824 	s->exlat = le32toh(s->exlat);
1825 	s->idlp = le16toh(s->idlp);
1826 	s->actp = le16toh(s->actp);
1827 #endif
1828 }
1829 
1830 static inline
1831 void	nvme_controller_data_swapbytes(struct nvme_controller_data *s __unused)
1832 {
1833 #ifndef _LITTLE_ENDIAN
1834 	int i;
1835 
1836 	s->vid = le16toh(s->vid);
1837 	s->ssvid = le16toh(s->ssvid);
1838 	s->ctrlr_id = le16toh(s->ctrlr_id);
1839 	s->ver = le32toh(s->ver);
1840 	s->rtd3r = le32toh(s->rtd3r);
1841 	s->rtd3e = le32toh(s->rtd3e);
1842 	s->oaes = le32toh(s->oaes);
1843 	s->ctratt = le32toh(s->ctratt);
1844 	s->rrls = le16toh(s->rrls);
1845 	s->crdt1 = le16toh(s->crdt1);
1846 	s->crdt2 = le16toh(s->crdt2);
1847 	s->crdt3 = le16toh(s->crdt3);
1848 	s->oacs = le16toh(s->oacs);
1849 	s->wctemp = le16toh(s->wctemp);
1850 	s->cctemp = le16toh(s->cctemp);
1851 	s->mtfa = le16toh(s->mtfa);
1852 	s->hmpre = le32toh(s->hmpre);
1853 	s->hmmin = le32toh(s->hmmin);
1854 	s->rpmbs = le32toh(s->rpmbs);
1855 	s->edstt = le16toh(s->edstt);
1856 	s->kas = le16toh(s->kas);
1857 	s->hctma = le16toh(s->hctma);
1858 	s->mntmt = le16toh(s->mntmt);
1859 	s->mxtmt = le16toh(s->mxtmt);
1860 	s->sanicap = le32toh(s->sanicap);
1861 	s->hmminds = le32toh(s->hmminds);
1862 	s->hmmaxd = le16toh(s->hmmaxd);
1863 	s->nsetidmax = le16toh(s->nsetidmax);
1864 	s->endgidmax = le16toh(s->endgidmax);
1865 	s->anagrpmax = le32toh(s->anagrpmax);
1866 	s->nanagrpid = le32toh(s->nanagrpid);
1867 	s->pels = le32toh(s->pels);
1868 	s->maxcmd = le16toh(s->maxcmd);
1869 	s->nn = le32toh(s->nn);
1870 	s->oncs = le16toh(s->oncs);
1871 	s->fuses = le16toh(s->fuses);
1872 	s->awun = le16toh(s->awun);
1873 	s->awupf = le16toh(s->awupf);
1874 	s->acwu = le16toh(s->acwu);
1875 	s->sgls = le32toh(s->sgls);
1876 	s->mnan = le32toh(s->mnan);
1877 	for (i = 0; i < 32; i++)
1878 		nvme_power_state_swapbytes(&s->power_state[i]);
1879 #endif
1880 }
1881 
1882 static inline
1883 void	nvme_namespace_data_swapbytes(struct nvme_namespace_data *s __unused)
1884 {
1885 #ifndef _LITTLE_ENDIAN
1886 	int i;
1887 
1888 	s->nsze = le64toh(s->nsze);
1889 	s->ncap = le64toh(s->ncap);
1890 	s->nuse = le64toh(s->nuse);
1891 	s->nawun = le16toh(s->nawun);
1892 	s->nawupf = le16toh(s->nawupf);
1893 	s->nacwu = le16toh(s->nacwu);
1894 	s->nabsn = le16toh(s->nabsn);
1895 	s->nabo = le16toh(s->nabo);
1896 	s->nabspf = le16toh(s->nabspf);
1897 	s->noiob = le16toh(s->noiob);
1898 	s->npwg = le16toh(s->npwg);
1899 	s->npwa = le16toh(s->npwa);
1900 	s->npdg = le16toh(s->npdg);
1901 	s->npda = le16toh(s->npda);
1902 	s->nows = le16toh(s->nows);
1903 	s->anagrpid = le32toh(s->anagrpid);
1904 	s->nvmsetid = le16toh(s->nvmsetid);
1905 	s->endgid = le16toh(s->endgid);
1906 	for (i = 0; i < 16; i++)
1907 		s->lbaf[i] = le32toh(s->lbaf[i]);
1908 #endif
1909 }
1910 
1911 static inline
1912 void	nvme_error_information_entry_swapbytes(
1913     struct nvme_error_information_entry *s __unused)
1914 {
1915 #ifndef _LITTLE_ENDIAN
1916 
1917 	s->error_count = le64toh(s->error_count);
1918 	s->sqid = le16toh(s->sqid);
1919 	s->cid = le16toh(s->cid);
1920 	s->status = le16toh(s->status);
1921 	s->error_location = le16toh(s->error_location);
1922 	s->lba = le64toh(s->lba);
1923 	s->nsid = le32toh(s->nsid);
1924 	s->csi = le64toh(s->csi);
1925 	s->ttsi = le16toh(s->ttsi);
1926 #endif
1927 }
1928 
1929 static inline
1930 void	nvme_le128toh(void *p __unused)
1931 {
1932 #ifndef _LITTLE_ENDIAN
1933 	/* Swap 16 bytes in place */
1934 	char *tmp = (char*)p;
1935 	char b;
1936 	int i;
1937 	for (i = 0; i < 8; i++) {
1938 		b = tmp[i];
1939 		tmp[i] = tmp[15-i];
1940 		tmp[15-i] = b;
1941 	}
1942 #endif
1943 }
1944 
1945 static inline
1946 void	nvme_health_information_page_swapbytes(
1947     struct nvme_health_information_page *s __unused)
1948 {
1949 #ifndef _LITTLE_ENDIAN
1950 	int i;
1951 
1952 	s->temperature = le16toh(s->temperature);
1953 	nvme_le128toh((void *)s->data_units_read);
1954 	nvme_le128toh((void *)s->data_units_written);
1955 	nvme_le128toh((void *)s->host_read_commands);
1956 	nvme_le128toh((void *)s->host_write_commands);
1957 	nvme_le128toh((void *)s->controller_busy_time);
1958 	nvme_le128toh((void *)s->power_cycles);
1959 	nvme_le128toh((void *)s->power_on_hours);
1960 	nvme_le128toh((void *)s->unsafe_shutdowns);
1961 	nvme_le128toh((void *)s->media_errors);
1962 	nvme_le128toh((void *)s->num_error_info_log_entries);
1963 	s->warning_temp_time = le32toh(s->warning_temp_time);
1964 	s->error_temp_time = le32toh(s->error_temp_time);
1965 	for (i = 0; i < 8; i++)
1966 		s->temp_sensor[i] = le16toh(s->temp_sensor[i]);
1967 	s->tmt1tc = le32toh(s->tmt1tc);
1968 	s->tmt2tc = le32toh(s->tmt2tc);
1969 	s->ttftmt1 = le32toh(s->ttftmt1);
1970 	s->ttftmt2 = le32toh(s->ttftmt2);
1971 #endif
1972 }
1973 
1974 static inline
1975 void	nvme_firmware_page_swapbytes(struct nvme_firmware_page *s __unused)
1976 {
1977 #ifndef _LITTLE_ENDIAN
1978 	int i;
1979 
1980 	for (i = 0; i < 7; i++)
1981 		s->revision[i] = le64toh(s->revision[i]);
1982 #endif
1983 }
1984 
1985 static inline
1986 void	nvme_ns_list_swapbytes(struct nvme_ns_list *s __unused)
1987 {
1988 #ifndef _LITTLE_ENDIAN
1989 	int i;
1990 
1991 	for (i = 0; i < 1024; i++)
1992 		s->ns[i] = le32toh(s->ns[i]);
1993 #endif
1994 }
1995 
1996 static inline
1997 void	nvme_command_effects_page_swapbytes(
1998     struct nvme_command_effects_page *s __unused)
1999 {
2000 #ifndef _LITTLE_ENDIAN
2001 	int i;
2002 
2003 	for (i = 0; i < 256; i++)
2004 		s->acs[i] = le32toh(s->acs[i]);
2005 	for (i = 0; i < 256; i++)
2006 		s->iocs[i] = le32toh(s->iocs[i]);
2007 #endif
2008 }
2009 
2010 static inline
2011 void	nvme_res_notification_page_swapbytes(
2012     struct nvme_res_notification_page *s __unused)
2013 {
2014 #ifndef _LITTLE_ENDIAN
2015 	s->log_page_count = le64toh(s->log_page_count);
2016 	s->nsid = le32toh(s->nsid);
2017 #endif
2018 }
2019 
2020 static inline
2021 void	nvme_sanitize_status_page_swapbytes(
2022     struct nvme_sanitize_status_page *s __unused)
2023 {
2024 #ifndef _LITTLE_ENDIAN
2025 	s->sprog = le16toh(s->sprog);
2026 	s->sstat = le16toh(s->sstat);
2027 	s->scdw10 = le32toh(s->scdw10);
2028 	s->etfo = le32toh(s->etfo);
2029 	s->etfbe = le32toh(s->etfbe);
2030 	s->etfce = le32toh(s->etfce);
2031 	s->etfownd = le32toh(s->etfownd);
2032 	s->etfbewnd = le32toh(s->etfbewnd);
2033 	s->etfcewnd = le32toh(s->etfcewnd);
2034 #endif
2035 }
2036 
2037 static inline
2038 void	intel_log_temp_stats_swapbytes(struct intel_log_temp_stats *s __unused)
2039 {
2040 #ifndef _LITTLE_ENDIAN
2041 
2042 	s->current = le64toh(s->current);
2043 	s->overtemp_flag_last = le64toh(s->overtemp_flag_last);
2044 	s->overtemp_flag_life = le64toh(s->overtemp_flag_life);
2045 	s->max_temp = le64toh(s->max_temp);
2046 	s->min_temp = le64toh(s->min_temp);
2047 	/* omit _rsvd[] */
2048 	s->max_oper_temp = le64toh(s->max_oper_temp);
2049 	s->min_oper_temp = le64toh(s->min_oper_temp);
2050 	s->est_offset = le64toh(s->est_offset);
2051 #endif
2052 }
2053 
2054 static inline
2055 void	nvme_resv_status_swapbytes(struct nvme_resv_status *s __unused,
2056     size_t size __unused)
2057 {
2058 #ifndef _LITTLE_ENDIAN
2059 	u_int i, n;
2060 
2061 	s->gen = le32toh(s->gen);
2062 	n = (s->regctl[1] << 8) | s->regctl[0];
2063 	n = MIN(n, (size - sizeof(s)) / sizeof(s->ctrlr[0]));
2064 	for (i = 0; i < n; i++) {
2065 		s->ctrlr[i].ctrlr_id = le16toh(s->ctrlr[i].ctrlr_id);
2066 		s->ctrlr[i].hostid = le64toh(s->ctrlr[i].hostid);
2067 		s->ctrlr[i].rkey = le64toh(s->ctrlr[i].rkey);
2068 	}
2069 #endif
2070 }
2071 
2072 static inline
2073 void	nvme_resv_status_ext_swapbytes(struct nvme_resv_status_ext *s __unused,
2074     size_t size __unused)
2075 {
2076 #ifndef _LITTLE_ENDIAN
2077 	u_int i, n;
2078 
2079 	s->gen = le32toh(s->gen);
2080 	n = (s->regctl[1] << 8) | s->regctl[0];
2081 	n = MIN(n, (size - sizeof(s)) / sizeof(s->ctrlr[0]));
2082 	for (i = 0; i < n; i++) {
2083 		s->ctrlr[i].ctrlr_id = le16toh(s->ctrlr[i].ctrlr_id);
2084 		s->ctrlr[i].rkey = le64toh(s->ctrlr[i].rkey);
2085 		nvme_le128toh((void *)s->ctrlr[i].hostid);
2086 	}
2087 #endif
2088 }
2089 
2090 static inline void
2091 nvme_device_self_test_swapbytes(struct nvme_device_self_test_page *s __unused)
2092 {
2093 #ifndef _LITTLE_ENDIAN
2094 	uint8_t *tmp;
2095 	uint32_t r, i;
2096 	uint8_t b;
2097 
2098 	for (r = 0; r < 20; r++) {
2099 		s->result[r].poh = le64toh(s->result[r].poh);
2100 		s->result[r].nsid = le32toh(s->result[r].nsid);
2101 		/* Unaligned 64-bit loads fail on some architectures */
2102 		tmp = s->result[r].failing_lba;
2103 		for (i = 0; i < 4; i++) {
2104 			b = tmp[i];
2105 			tmp[i] = tmp[7-i];
2106 			tmp[7-i] = b;
2107 		}
2108 	}
2109 #endif
2110 }
2111 #endif /* __NVME_H__ */
2112