1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22/* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27#pragma dictionary "INTEL" 28 29/* 30 * Eversholt rules for the intel CPU/Memory 31 */ 32 33/* 34 * Ereports for Simple error codes. 35 */ 36 37#define SMPL_EVENT(leafclass, t) \ 38 event ereport.cpu.intel.leafclass@chip/core/strand { within(t) } 39 40SMPL_EVENT(unknown, 1s); 41SMPL_EVENT(unclassified, 1s); 42SMPL_EVENT(microcode_rom_parity, 1s); 43SMPL_EVENT(external, 1s); 44SMPL_EVENT(frc, 1s); 45SMPL_EVENT(internal_timer, 1s); 46SMPL_EVENT(internal_parity, 1s); 47SMPL_EVENT(internal_unclassified, 1s); 48 49/* 50 * Propogations for all but "external" and "unknown" simple errors. 51 * If the error is uncorrected we produce a fault immediately, otherwise 52 * we diagnose it to an upset and decalre a fault when the SERD engine 53 * trips. 54 */ 55 56engine serd.cpu.intel.simple@chip/core/strand, N=3, T=72h; 57event fault.cpu.intel.internal@chip/core/strand, 58 engine=serd.cpu.intel.simple@chip/core/strand; 59 60prop fault.cpu.intel.internal@chip/core/strand 61 { payloadprop("error_uncorrected") == 1 ? setserdincrement(4) : 1} (0)-> 62 ereport.cpu.intel.microcode_rom_parity@chip/core/strand, 63 ereport.cpu.intel.internal_timer@chip/core/strand, 64 ereport.cpu.intel.internal_parity@chip/core/strand, 65 ereport.cpu.intel.unclassified@chip/core/strand, 66 ereport.cpu.intel.internal_unclassified@chip/core/strand, 67 ereport.cpu.intel.frc@chip/core/strand; 68 69/* 70 * Ereports for Compound error codes. These are in pairs "foo" and "foo_uc" 71 * for the corrected and uncorrected version of each error type. All are 72 * detected at chip/core/strand. 73 */ 74 75#define CMPND_EVENT(leafclass, t) \ 76 event ereport.cpu.intel.leafclass@chip/core/strand { within(t) }; \ 77 event ereport.cpu.intel.leafclass/**/_uc@chip/core/strand { within(t) } 78 79/* 80 * Ereports for Compound error codes - intel errors 81 */ 82CMPND_EVENT(l0cache, 1s); 83CMPND_EVENT(l1cache, 1s); 84CMPND_EVENT(l2cache, 1s); 85CMPND_EVENT(cache, 1s); 86 87/* 88 * Ereports for Compound error codes - TLB errors 89 */ 90CMPND_EVENT(l0dtlb, 1s); 91CMPND_EVENT(l1dtlb, 1s); 92CMPND_EVENT(l2dtlb, 1s); 93CMPND_EVENT(dtlb, 1s); 94 95CMPND_EVENT(l0itlb, 1s); 96CMPND_EVENT(l1itlb, 1s); 97CMPND_EVENT(l2itlb, 1s); 98CMPND_EVENT(itlb, 1s); 99 100CMPND_EVENT(l0tlb, 1s); 101CMPND_EVENT(l1tlb, 1s); 102CMPND_EVENT(l2tlb, 1s); 103CMPND_EVENT(tlb, 1s); 104 105/* 106 * Ereports for Compound error codes - memory hierarchy errors 107 */ 108CMPND_EVENT(l0dcache, 1s); 109CMPND_EVENT(l1dcache, 1s); 110CMPND_EVENT(l2dcache, 1s); 111CMPND_EVENT(dcache, 1s); 112 113CMPND_EVENT(l0icache, 1s); 114CMPND_EVENT(l1icache, 1s); 115CMPND_EVENT(l2icache, 1s); 116CMPND_EVENT(icache, 1s); 117 118/* 119 * Ereports for Compound error codes - bus and interconnect errors 120 */ 121CMPND_EVENT(bus_interconnect, 1s); 122CMPND_EVENT(bus_interconnect_memory, 1s); 123CMPND_EVENT(bus_interconnect_io, 1s); 124 125/* 126 * Compound error propogations. 127 * 128 * We resist the temptation propogate, for example, a single dcache fault 129 * to all ereports mentioning dcache (l0dcache, l1dcache, l2dcache, dcache). 130 * Instead we will diagnose a distinct fault for each possible cache level, 131 * whether or not current chips have dcaches at all levels. 132 * 133 * Corrected errors are SERDed and produce a fault when the engine fires; 134 * the same fault is diagnosed immediately for a corresponding uncorrected 135 * error. 136 */ 137 138#define CMPND_FLT_PROP_1(erptleaf, fltleaf, n, t) \ 139 engine serd.cpu.intel.fltleaf@chip/core/strand, N=n, T=t; \ 140 event fault.cpu.intel.fltleaf@chip/core/strand, \ 141 engine=serd.cpu.intel.fltleaf@chip/core/strand; \ 142 \ 143 prop fault.cpu.intel.fltleaf@chip/core/strand (0)-> \ 144 ereport.cpu.intel.erptleaf@chip/core/strand; \ 145 \ 146 prop fault.cpu.intel.fltleaf@chip/core/strand \ 147 { setserdincrement(n + 1) } (0)-> \ 148 ereport.cpu.intel.erptleaf/**/_uc@chip/core/strand 149 150#define CMPND_FLT_PROP_2(erptleaf, fltleaf, n, t) \ 151 engine serd.cpu.intel.fltleaf@chip/core/strand, N=n, T=t; \ 152 event fault.cpu.intel.fltleaf@chip/core/strand, retire=0, response=0,\ 153 engine=serd.cpu.intel.fltleaf@chip/core/strand; \ 154 \ 155 prop fault.cpu.intel.fltleaf@chip/core/strand (0)-> \ 156 ereport.cpu.intel.erptleaf@chip/core/strand; \ 157 \ 158 prop fault.cpu.intel.fltleaf@chip/core/strand \ 159 { setserdincrement(n + 1) } (0)-> \ 160 ereport.cpu.intel.erptleaf/**/_uc@chip/core/strand 161 162CMPND_FLT_PROP_1(l0cache, l0cache, 3, 72h); 163CMPND_FLT_PROP_1(l1cache, l1cache, 3, 72h); 164CMPND_FLT_PROP_1(l2cache, l2cache, 3, 72h); 165CMPND_FLT_PROP_1(cache, cache, 12, 72h); 166 167CMPND_FLT_PROP_1(l0dtlb, l0dtlb, 3, 72h); 168CMPND_FLT_PROP_1(l1dtlb, l1dtlb, 3, 72h); 169CMPND_FLT_PROP_1(l2dtlb, l2dtlb, 3, 72h); 170CMPND_FLT_PROP_1(dtlb, dtlb, 12, 72h); 171 172CMPND_FLT_PROP_1(l0itlb, l0itlb, 3, 72h); 173CMPND_FLT_PROP_1(l1itlb, l1itlb, 3, 72h); 174CMPND_FLT_PROP_1(l2itlb, l2itlb, 3, 72h); 175CMPND_FLT_PROP_1(itlb, itlb, 12, 72h); 176 177CMPND_FLT_PROP_1(l0tlb, litlb, 3, 72h); 178CMPND_FLT_PROP_1(l1tlb, litlb, 3, 72h); 179CMPND_FLT_PROP_1(l2tlb, litlb, 3, 72h); 180CMPND_FLT_PROP_1(tlb, tlb, 12, 72h); 181 182CMPND_FLT_PROP_1(l0dcache, l0dcache, 3, 72h); 183CMPND_FLT_PROP_1(l1dcache, l1dcache, 3, 72h); 184CMPND_FLT_PROP_1(l2dcache, l2dcache, 3, 72h); 185CMPND_FLT_PROP_1(dcache, dcache, 12, 72h); 186 187CMPND_FLT_PROP_1(l0icache, l0icache, 3, 72h); 188CMPND_FLT_PROP_1(l1icache, l1icache, 3, 72h); 189CMPND_FLT_PROP_1(l2icache, l2icache, 3, 72h); 190CMPND_FLT_PROP_1(icache, icache, 12, 72h); 191 192CMPND_FLT_PROP_2(bus_interconnect, bus_interconnect, 10, 72h); 193CMPND_FLT_PROP_2(bus_interconnect_memory, bus_interconnect_memory, 10, 72h); 194CMPND_FLT_PROP_2(bus_interconnect_io, bus_interconnect_io, 10, 72h); 195 196event upset.discard@chip/core/strand; 197 198prop upset.discard@chip/core/strand (0)-> 199 ereport.cpu.intel.external@chip/core/strand, 200 ereport.cpu.intel.unknown@chip/core/strand; 201 202/* errors detected in northbridge */ 203 204 205/* 206 * SET_ADDR and SET_OFFSET are used to set a payload value in the fault that 207 * we diagnose for page faults, to record the physical address of the faulting 208 * page. 209 */ 210#define SET_ADDR (!payloadprop_defined("physaddr") || \ 211 setpayloadprop("asru-physaddr", payloadprop("physaddr"))) 212 213#define SET_OFFSET (!payloadprop_defined("offset") || \ 214 setpayloadprop("asru-offset", payloadprop("offset"))) 215 216#define EREPORT_BUS_ERROR \ 217 ereport.cpu.intel.bus_interconnect_memory_uc@chip/core/strand, \ 218 ereport.cpu.intel.bus_interconnect_uc@chip/core/strand, \ 219 ereport.cpu.intel.bus_interconnect_memory@chip/core/strand, \ 220 ereport.cpu.intel.bus_interconnect@chip/core/strand, \ 221 ereport.cpu.intel.external@chip/core/strand 222 223engine stat.ce_pgflt@memory-controller/dram-channel/dimm; 224 225event ereport.cpu.intel.nb.mem_ue@motherboard/memory-controller{within(12s)}; 226event ereport.cpu.intel.nb.fbd.ma@motherboard/memory-controller{within(12s)}; 227event fault.memory.intel.page_ue@ 228 motherboard/memory-controller/dram-channel/dimm/rank, 229 message=0, response=0; 230event fault.memory.intel.dimm_ue@ 231 motherboard/memory-controller/dram-channel/dimm/rank; 232 233prop fault.memory.intel.page_ue@ 234 motherboard/memory-controller/dram-channel/dimm/rank[rank_num] 235 { payloadprop_defined("rank") && rank_num == payloadprop("rank") && 236 (payloadprop_defined("physaddr") || payloadprop_defined("offset")) && 237 SET_ADDR && SET_OFFSET } (1)-> 238 ereport.cpu.intel.nb.mem_ue@motherboard/memory-controller, 239 ereport.cpu.intel.nb.fbd.ma@motherboard/memory-controller; 240 241prop fault.memory.intel.page_ue@ 242 motherboard/memory-controller/dram-channel/dimm/rank (1)-> 243 ereport.cpu.intel.nb.mem_ue@motherboard/memory-controller, 244 ereport.cpu.intel.nb.fbd.ma@motherboard/memory-controller; 245 246prop fault.memory.intel.page_ue@ 247 motherboard/memory-controller/dram-channel/dimm/rank (0)-> 248 EREPORT_BUS_ERROR; 249 250prop fault.memory.intel.dimm_ue@ 251 motherboard/memory-controller/dram-channel<channel_num>/dimm/rank[rank_num] 252 { payloadprop_defined("rank") && rank_num == payloadprop("rank") } (1)-> 253 ereport.cpu.intel.nb.mem_ue@motherboard/memory-controller, 254 ereport.cpu.intel.nb.fbd.ma@motherboard/memory-controller; 255 256prop fault.memory.intel.dimm_ue@ 257 motherboard/memory-controller/dram-channel/dimm/rank (1)-> 258 ereport.cpu.intel.nb.mem_ue@motherboard/memory-controller, 259 ereport.cpu.intel.nb.fbd.ma@motherboard/memory-controller; 260 261prop fault.memory.intel.dimm_ue@ 262 motherboard/memory-controller/dram-channel/dimm/rank (0)-> 263 EREPORT_BUS_ERROR; 264 265event upset.memory.intel.discard@motherboard/memory-controller{within(1s)}; 266 267prop upset.memory.intel.discard@motherboard/memory-controller 268 { !payloadprop_defined("rank") } (1)-> 269 ereport.cpu.intel.nb.mem_ue@motherboard/memory-controller, 270 ereport.cpu.intel.nb.fbd.ma@motherboard/memory-controller; 271 272prop upset.memory.intel.discard@motherboard/memory-controller (0)-> 273 EREPORT_BUS_ERROR; 274 275#define PAGE_CE_COUNT 2 276#define PAGE_CE_TIME 72h 277#define DIMM_CE_COUNT 10 278#define DIMM_CE_TIME 1week 279 280event ereport.cpu.intel.nb.mem_ce@dimm/rank{within(12s)}; 281 282engine serd.memory.intel.page_ce@dimm/rank, N=PAGE_CE_COUNT, T=PAGE_CE_TIME; 283event fault.memory.intel.page_ce@dimm/rank, message=0, response=0, 284 count=stat.ce_pgflt@dimm, engine=serd.memory.intel.page_ce@dimm/rank; 285prop fault.memory.intel.page_ce@dimm/rank 286 { (payloadprop_defined("physaddr") || payloadprop_defined("offset")) && 287 SET_ADDR && SET_OFFSET } (0)-> 288 ereport.cpu.intel.nb.mem_ce@dimm/rank; 289 290engine serd.memory.intel.dimm_ce@dimm/rank, N=DIMM_CE_COUNT, T=DIMM_CE_TIME; 291event fault.memory.intel.dimm_ce@dimm/rank, 292 engine=serd.memory.intel.dimm_ce@dimm/rank; 293event error.memory.intel.dimm_ce@dimm; 294prop fault.memory.intel.dimm_ce@dimm/rank (1)-> 295 ereport.cpu.intel.nb.mem_ce@dimm/rank; 296prop fault.memory.intel.dimm_ce@dimm/rank 297 { !confprop_defined(dimm, "dimm-size") } (1)-> 298 error.memory.intel.dimm_ce@dimm; 299prop error.memory.intel.dimm_ce@dimm 300 { !confprop_defined(dimm, "dimm-size") && 301 count(stat.ce_pgflt@dimm) > 512 } (1)-> 302 ereport.cpu.intel.nb.mem_ce@dimm/rank; 303 304#define DIMM_CE(dimm_size, n, t, fault_rate) \ 305 prop fault.memory.intel.dimm_ce@dimm/rank { \ 306 confprop(dimm, "dimm-size") == dimm_size && \ 307 setserdn(n) & setserdt(t) } (1)-> \ 308 error.memory.intel.dimm_ce@dimm; \ 309 prop error.memory.intel.dimm_ce@dimm { \ 310 confprop(dimm, "dimm-size") == dimm_size && \ 311 count(stat.ce_pgflt@dimm) > fault_rate } (1)-> \ 312 ereport.cpu.intel.nb.mem_ce@dimm/rank; 313 314DIMM_CE("8G", 8, 1week, 2000) 315DIMM_CE("4G", 4, 1week, 1500) 316DIMM_CE("2G", 4, 2week, 1000) 317DIMM_CE("1G", 4, 4week, 500) 318DIMM_CE("512M", 4, 8week, 250) 319DIMM_CE("256M", 4, 16week, 125) 320 321event ereport.cpu.intel.nb.fbd.alert@rank{within(12s)}; 322event fault.memory.intel.fbd.alert@rank, retire=0; 323 324prop fault.memory.intel.fbd.alert@rank (1)-> 325 ereport.cpu.intel.nb.fbd.alert@rank; 326 327prop fault.memory.intel.fbd.alert@rank (0)-> 328 EREPORT_BUS_ERROR; 329 330event ereport.cpu.intel.nb.fbd.crc@rank{within(12s)}; 331event fault.memory.intel.fbd.crc@rank, retire=0; 332 333prop fault.memory.intel.fbd.crc@rank (1)-> 334 ereport.cpu.intel.nb.fbd.crc@rank; 335 336prop fault.memory.intel.fbd.crc@rank (0)-> EREPORT_BUS_ERROR; 337 338event ereport.cpu.intel.nb.fbd.reset_timeout@memory-controller {within(12s)}; 339event fault.memory.intel.fbd.reset_timeout@memory-controller, retire=0; 340 341prop fault.memory.intel.fbd.reset_timeout@memory-controller (1)-> 342 ereport.cpu.intel.nb.fbd.reset_timeout@memory-controller; 343 344prop fault.memory.intel.fbd.reset_timeout@memory-controller (0)-> 345 EREPORT_BUS_ERROR; 346 347event ereport.cpu.intel.nb.fbd.ch@dram-channel {within(12s)}; 348engine serd.cpu.intel.nb.fbd.ch@dram-channel, N=2, T=1month; 349event fault.memory.intel.fbd.ch@dram-channel, retire=0, 350 engine=serd.cpu.intel.nb.fbd.ch@dram-channel; 351 352prop fault.memory.intel.fbd.ch@dram-channel (1)-> 353 ereport.cpu.intel.nb.fbd.ch@dram-channel; 354 355prop fault.memory.intel.fbd.ch@dram-channel (0)-> 356 EREPORT_BUS_ERROR; 357 358event ereport.cpu.intel.nb.fbd.otf@dram-channel {within(12s)}; 359engine serd.cpu.intel.nb.fbd_otf@dram-channel, N=2, T=1week; 360event fault.memory.intel.fbd.otf@dram-channel, retire=0, response=0, 361 engine=serd.cpu.intel.nb.fbd_otf@dram-channel; 362 363prop fault.memory.intel.fbd.otf@dram-channel (1)-> 364 ereport.cpu.intel.nb.fbd.otf@dram-channel; 365 366event ereport.cpu.intel.nb.otf@motherboard {within(12s)}; 367event fault.cpu.intel.nb.otf@motherboard, retire=0, response=0; 368 369prop fault.cpu.intel.nb.otf@motherboard (1)-> 370 ereport.cpu.intel.nb.otf@motherboard; 371 372event ereport.cpu.intel.nb.unknown@memory-controller {within(12s)}; 373event ereport.cpu.intel.nb.unknown@memory-controller/dram-channel {within(12s)}; 374event ereport.cpu.intel.nb.spd@memory-controller/dram-channel {within(12s)}; 375event upset.discard@memory-controller; 376 377prop upset.discard@memory-controller (0)-> 378 ereport.cpu.intel.nb.unknown@memory-controller, 379 ereport.cpu.intel.nb.unknown@memory-controller/dram-channel, 380 ereport.cpu.intel.nb.spd@memory-controller/dram-channel; 381 382event ereport.cpu.intel.nb.mem_ds@memory-controller{within(30s)}; 383event fault.memory.intel.fbd.mem_ds@memory-controller/dram-channel/dimm/rank, 384 retire=0; 385 386prop fault.memory.intel.fbd.mem_ds@ 387 memory-controller/dram-channel/dimm/rank[rank_num] 388 { payloadprop_defined("rank") && rank_num == payloadprop("rank") } (1)-> 389 ereport.cpu.intel.nb.mem_ds@memory-controller; 390 391event ereport.cpu.intel.nb.fsb@chip{within(12s)}; 392event fault.cpu.intel.nb.fsb@chip, retire=0; 393 394prop fault.cpu.intel.nb.fsb@chip (1)-> 395 ereport.cpu.intel.nb.fsb@chip; 396 397prop fault.cpu.intel.nb.fsb@chip (0)-> EREPORT_BUS_ERROR; 398 399event ereport.cpu.intel.nb.ie@motherboard{within(12s)}; 400event fault.cpu.intel.nb.ie@motherboard, retire=0; 401 402prop fault.cpu.intel.nb.ie@motherboard (1)-> 403 ereport.cpu.intel.nb.ie@motherboard; 404 405prop fault.cpu.intel.nb.ie@motherboard (0)-> EREPORT_BUS_ERROR; 406 407event ereport.cpu.intel.nb.dma@motherboard{within(12s)}; 408event fault.cpu.intel.nb.dma@motherboard, retire=0, response=0; 409 410prop fault.cpu.intel.nb.dma@motherboard (1)-> 411 ereport.cpu.intel.nb.dma@motherboard; 412 413prop fault.cpu.intel.nb.dma@motherboard (0)-> EREPORT_BUS_ERROR; 414 415event ereport.cpu.intel.nb.esi@motherboard{within(12s)}; 416event ereport.cpu.intel.nb.pex@hostbridge{within(12s)}; 417event upset.cpu.intel.nb.pex@hostbridge; 418 419prop upset.cpu.intel.nb.pex@hostbridge (1)-> 420 ereport.cpu.intel.nb.esi@motherboard, 421 ereport.cpu.intel.nb.pex@hostbridge; 422 423prop upset.cpu.intel.nb.pex@hostbridge (0)-> EREPORT_BUS_ERROR; 424 425event ereport.cpu.intel.nb.unknown@rank{within(12s)}; 426event upset.discard@rank; 427 428prop upset.discard@rank (1)-> 429 ereport.cpu.intel.nb.unknown@rank; 430 431prop upset.discard@rank (0)-> EREPORT_BUS_ERROR; 432 433/* 434 * CPU integrated memory controller 435 */ 436 437#define CONTAINS_RANK (payloadprop_contains("resource", \ 438 asru(motherboard/chip/memory-controller/dram-channel/dimm/rank)) || \ 439 payloadprop_contains("resource", \ 440 asru(motherboard/chip/memory-controller/dram-channel/dimm))) 441 442#define CPU_MEM_CE_PGFLTS \ 443 (count(stat.ce_pgflt@motherboard/chip/memory-controller/dram-channel/dimm)) 444 445engine stat.ce_pgflt@motherboard/chip/memory-controller/dram-channel/dimm; 446 447event ereport.cpu.intel.quickpath.mem_ue@motherboard/chip/memory-controller 448 {within(12s)}; 449 450event fault.memory.intel.page_ue@ 451 motherboard/chip/memory-controller/dram-channel/dimm/rank, 452 message=0, response=0; /* do not message individual pageflts */ 453 454prop fault.memory.intel.page_ue@ 455 motherboard/chip/memory-controller/dram-channel/dimm/rank 456 { CONTAINS_RANK && 457 (payloadprop_defined("physaddr") || payloadprop_defined("offset")) && 458 SET_ADDR && SET_OFFSET } (1)-> 459 ereport.cpu.intel.quickpath.mem_ue@motherboard/chip/memory-controller; 460 461event fault.memory.intel.dimm_ue@ 462 motherboard/chip/memory-controller/dram-channel/dimm/rank; 463 464prop fault.memory.intel.dimm_ue@ 465 motherboard/chip/memory-controller/dram-channel/dimm/rank 466 { CONTAINS_RANK } (1)-> 467 ereport.cpu.intel.quickpath.mem_ue@motherboard/chip/memory-controller; 468 469prop fault.memory.intel.dimm_ue@ 470 motherboard/chip/memory-controller/dram-channel/dimm/rank (0)-> 471 EREPORT_BUS_ERROR; 472 473event ereport.cpu.intel.quickpath.mem_ce@ 474 motherboard/chip/memory-controller{within(12s)}; 475 476engine serd.memory.intel.page_ce@ 477 motherboard/chip/memory-controller/dram-channel/dimm/rank, 478 N=PAGE_CE_COUNT, T=PAGE_CE_TIME; 479 480event fault.memory.intel.page_ce@ 481 motherboard/chip/memory-controller/dram-channel/dimm/rank, 482 message=0, response=0, 483 count=stat.ce_pgflt@motherboard/chip/memory-controller/dram-channel/dimm, 484 engine=serd.memory.intel.page_ce@ 485 motherboard/chip/memory-controller/dram-channel/dimm/rank; 486 487prop fault.memory.intel.page_ce@ 488 motherboard/chip/memory-controller/dram-channel/dimm/rank 489 { CONTAINS_RANK && 490 (payloadprop_defined("physaddr") || payloadprop_defined("offset")) && 491 SET_ADDR && SET_OFFSET } (1)-> 492 ereport.cpu.intel.quickpath.mem_ce@motherboard/chip/memory-controller; 493 494engine serd.memory.intel.dimm_ce@ 495 motherboard/chip/memory-controller/dram-channel/dimm, 496 N=PAGE_CE_COUNT, T=PAGE_CE_TIME; 497event fault.memory.intel.dimm_ce@ 498 motherboard/chip/memory-controller/dram-channel/dimm, 499 engine=serd.memory.intel.dimm_ce@ 500 motherboard/chip/memory-controller/dram-channel/dimm; 501event error.memory.intel.dimm_ce@ 502 motherboard/chip/memory-controller/dram-channel/dimm; 503prop fault.memory.intel.dimm_ce@ 504 motherboard/chip/memory-controller/dram-channel/dimm 505 { !confprop_defined(dimm, "dimm-size") } (1)-> 506 error.memory.intel.dimm_ce@ 507 motherboard/chip/memory-controller/dram-channel/dimm; 508prop error.memory.intel.dimm_ce@ 509 motherboard/chip/memory-controller/dram-channel/dimm 510 { !confprop_defined(dimm, "dimm-size") && 511 count(stat.ce_pgflt@dimm) > 512 } (1)-> 512 ereport.cpu.intel.quickpath.mem_ce@motherboard/chip/memory-controller; 513 514#define CPU_MEM_DIMM_CE(dimm_size, n, t, fault_rate) \ 515 prop fault.memory.intel.dimm_ce@ \ 516 motherboard/chip/memory-controller/dram-channel/dimm { \ 517 confprop(dimm, "dimm-size") == dimm_size && \ 518 setserdn(n) & setserdt(t) } (1)-> \ 519 error.memory.intel.dimm_ce@ \ 520 motherboard/chip/memory-controller/dram-channel/dimm; \ 521 prop error.memory.intel.dimm_ce@ \ 522 motherboard/chip/memory-controller/dram-channel/dimm { \ 523 confprop(dimm, "dimm-size") == dimm_size && \ 524 count(stat.ce_pgflt@dimm) > fault_rate } (1)-> \ 525 ereport.cpu.intel.quickpath.mem_ce@ \ 526 motherboard/chip/memory-controller; 527 528CPU_MEM_DIMM_CE("16G", 16, 1week, 2000) 529CPU_MEM_DIMM_CE("8G", 8, 1week, 2000) 530CPU_MEM_DIMM_CE("4G", 4, 1week, 1500) 531CPU_MEM_DIMM_CE("2G", 4, 2week, 1000) 532CPU_MEM_DIMM_CE("1G", 4, 4week, 500) 533CPU_MEM_DIMM_CE("512M", 4, 8week, 250) 534 535event ereport.cpu.intel.quickpath.mem_unknown@motherboard/chip/memory-controller {within(12s)}; 536event ereport.cpu.intel.quickpath.mem_unknown@motherboard/chip/memory-controller/dram-channel 537 {within(12s)}; 538event ereport.cpu.intel.quickpath.mem_unknown@ 539 motherboard/chip/memory-controller/dram-channel/dimm/rank{within(12s)}; 540event upset.discard@motherboard/chip/memory-controller; 541event upset.discard@motherboard/chip/memory-controller/dram-channel/dimm/rank; 542 543prop upset.discard@motherboard/chip/memory-controller (0)-> 544 ereport.cpu.intel.quickpath.mem_unknown@motherboard/chip/memory-controller, 545 ereport.cpu.intel.quickpath.mem_unknown@ 546 motherboard/chip/memory-controller/dram-channel; 547 548prop upset.discard@ 549 motherboard/chip/memory-controller/dram-channel/dimm/rank (1)-> 550 ereport.cpu.intel.quickpath.mem_unknown@ 551 motherboard/chip/memory-controller/dram-channel/dimm/rank; 552 553event ereport.cpu.intel.quickpath.mem_parity@motherboard/chip/memory-controller {within(1s)}; 554event fault.cpu.intel.quickpath.mem_parity@motherboard/chip/memory-controller; 555 556prop fault.cpu.intel.quickpath.mem_parity@motherboard/chip/memory-controller (1)-> 557 ereport.cpu.intel.quickpath.mem_parity@motherboard/chip/memory-controller; 558 559event ereport.cpu.intel.quickpath.mem_addr_parity@motherboard/chip/memory-controller {within(1s)}; 560event fault.cpu.intel.quickpath.mem_addr_parity@ 561 motherboard/chip/memory-controller/dram-channel/dimm; 562event fault.cpu.intel.quickpath.mem_addr_parity@ 563 motherboard/chip/memory-controller; 564 565prop fault.cpu.intel.quickpath.mem_addr_parity@ 566 motherboard/chip/memory-controller (1)-> 567 ereport.cpu.intel.quickpath.mem_addr_parity@motherboard/chip/memory-controller; 568 569prop fault.cpu.intel.quickpath.mem_addr_parity@ 570 motherboard/chip/memory-controller/dram-channel/dimm 571 { payloadprop_contains("resource", asru(motherboard/chip/memory-controller/dram-channel/dimm)) } (1)-> 572 ereport.cpu.intel.quickpath.mem_addr_parity@motherboard/chip/memory-controller; 573 574event ereport.cpu.intel.quickpath.mem_bad_addr@motherboard/chip/memory-controller {within(1s)}; 575event fault.cpu.intel.quickpath.mem_bad_addr@motherboard/chip/memory-controller; 576 577prop fault.cpu.intel.quickpath.mem_bad_addr@motherboard/chip/memory-controller (1)-> 578 ereport.cpu.intel.quickpath.mem_bad_addr@motherboard/chip/memory-controller; 579 580event ereport.cpu.intel.quickpath.mem_spare@motherboard/chip/memory-controller {within(1s)}; 581event fault.cpu.intel.quickpath.mem_spare@ 582 motherboard/chip/memory-controller/dram-channel/dimm; 583 584prop fault.cpu.intel.quickpath.mem_spare@ 585 motherboard/chip/memory-controller/dram-channel/dimm (1)-> 586 ereport.cpu.intel.quickpath.mem_spare@motherboard/chip/memory-controller; 587 588event ereport.cpu.intel.quickpath.mem_bad_id@motherboard/chip/memory-controller {within(1s)}; 589event fault.cpu.intel.quickpath.mem_bad_id@motherboard/chip/memory-controller; 590 591prop fault.cpu.intel.quickpath.mem_bad_id@motherboard/chip/memory-controller (1)-> 592 ereport.cpu.intel.quickpath.mem_bad_id@motherboard/chip/memory-controller; 593 594event ereport.cpu.intel.quickpath.mem_redundant@motherboard/chip/memory-controller {within(1s)}; 595engine serd.cpu.intel.quickpath.mem_redundant@motherboard/chip/memory-controller, 596 N=2, T=72h; 597event fault.cpu.intel.quickpath.mem_redundant@ 598 motherboard/chip/memory-controller/dram-channel/dimm, 599 engine=serd.cpu.intel.quickpath.mem_redundant@ 600 motherboard/chip/memory-controller; 601 602prop fault.cpu.intel.quickpath.mem_redundant@ 603 motherboard/chip/memory-controller/dram-channel/dimm (1)-> 604 ereport.cpu.intel.quickpath.mem_redundant@ 605 motherboard/chip/memory-controller; 606 607event ereport.cpu.intel.quickpath.interconnect@motherboard/chip 608 {within(1s)}; 609event upset.cpu.intel.quickpath.interconnect@motherboard/chip; 610/* Diagnose corrected events to upsets */ 611prop upset.cpu.intel.quickpath.interconnect@motherboard/chip 612 { !STATUS_UC } (1)-> 613 ereport.cpu.intel.quickpath.interconnect@motherboard/chip; 614 615 616engine serd.cpu.intel.quickpath.interconnect@motherboard/chip, 617 N=3, T=72h; 618event fault.cpu.intel.quickpath.interconnect@motherboard/chip, 619 engine=serd.cpu.intel.quickpath.interconnect@motherboard/chip; 620 621/* Diagnose uncorrected events to faults */ 622prop fault.cpu.intel.quickpath.interconnect@motherboard/chip 623 { STATUS_UC } (0)-> 624 ereport.cpu.intel.quickpath.interconnect@motherboard/chip; 625